moved
git-svn-id: http://moon:8086/svn/vhdl/trunk@1413 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1 @@
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work
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@@ -0,0 +1,7 @@
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vhdl work "../../../../lib/fixed/fixed_pkg_c.vhd"
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vhdl work "../../../../lib/filter/src/filter_pkg.vhd"
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vhdl work "../../../../lib/filter/src/fir_stage_pkg.vhd"
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vhdl work "../../../../lib/filter/src/fir_iterative_pkg.vhd"
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vhdl work "../../../../lib/filter/src/fir_stage.vhd"
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vhdl work "../../../../lib/filter/src/fir_iterative.vhd"
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vhdl work "../../src/syn_fir_bandpass.vhd"
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@@ -0,0 +1,59 @@
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set -tmpdir "./xst/projnav.tmp"
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set -xsthdpdir "./xst"
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run
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-ifn syn_fir_bandpass.prj
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-ifmt mixed
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-ofn syn_fir_bandpass
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-ofmt NGC
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-p xc4vsx35-10-ff668
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-top syn_fir_bandpass
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-opt_mode Speed
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-opt_level 1
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-power NO
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-iuc NO
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-lso syn_fir_bandpass.lso
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-keep_hierarchy YES
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-rtlview Yes
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-glob_opt AllClockNets
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-read_cores YES
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-write_timing_constraints NO
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-cross_clock_analysis NO
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-hierarchy_separator /
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-bus_delimiter <>
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-case maintain
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-slice_utilization_ratio 100
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-bram_utilization_ratio 100
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-dsp_utilization_ratio 100
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-verilog2001 YES
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-fsm_extract YES -fsm_encoding Auto
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-safe_implementation No
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-fsm_style lut
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-ram_extract Yes
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-ram_style Auto
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-rom_extract Yes
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-mux_style Auto
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-decoder_extract YES
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-priority_extract YES
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-shreg_extract YES
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-shift_extract YES
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-xor_collapse YES
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-rom_style Auto
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-auto_bram_packing NO
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-mux_extract YES
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-resource_sharing YES
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-async_to_sync NO
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-use_dsp48 auto
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-iobuf NO
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-max_fanout 500
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-bufg 32
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-bufr 24
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-register_duplication YES
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-register_balancing No
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-slice_packing YES
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-optimize_primitives NO
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-use_clock_enable Auto
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-use_sync_set Auto
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-use_sync_reset Auto
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-iob auto
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-equivalent_register_removal YES
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-slice_utilization_ratio_maxmargin 5
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@@ -0,0 +1,2 @@
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ieee_proposed
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work
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@@ -0,0 +1,11 @@
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vhdl ieee_proposed "../../../../lib/fixed/xilinx/math_utility_pkg.vhdl"
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vhdl ieee_proposed "../../../../lib/fixed/xilinx/fixed_pkg_c.vhdl"
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vhdl work "../../../../lib/fixed/fixed_util_pkg.vhd"
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vhdl work "../../../../lib/misc/utils_pkg.vhd"
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vhdl work "../../../../lib/filter/src/filter_pkg.vhd"
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vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
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vhdl work "../../../../lib/filter/src/fir_pkg.vhd"
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vhdl work "../../../../lib/filter/src/fir_stage_sys.vhd"
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vhdl work "../../../../lib/filter/src/delay_line.vhd"
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vhdl work "../../../../lib/filter/src/fir_semi_parallel.vhd"
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vhdl work "../../src/syn_fir_lowpass_sp.vhd"
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@@ -0,0 +1,60 @@
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set -tmpdir "W:/vhdl/projects/ac97_Controller/ise91/fir_lowpass/xst/projnav.tmp"
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set -xsthdpdir "W:/vhdl/projects/ac97_Controller/ise91/fir_lowpass/xst"
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run
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-ifn syn_fir_lowpass.prj
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-ifmt mixed
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-ofn syn_fir_lowpass
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-ofmt NGC
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-p xc4vsx35-10-ff668
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-top syn_fir_lowpass
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-opt_mode Speed
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-opt_level 1
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-power NO
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-iuc NO
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-lso syn_fir_lowpass.lso
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-keep_hierarchy YES
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-netlist_hierarchy as_optimized
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-rtlview Yes
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-glob_opt AllClockNets
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-read_cores YES
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-write_timing_constraints NO
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-cross_clock_analysis NO
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-hierarchy_separator /
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-bus_delimiter <>
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-case maintain
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-slice_utilization_ratio 100
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-bram_utilization_ratio 100
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-dsp_utilization_ratio 100
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-verilog2001 YES
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-fsm_extract YES -fsm_encoding Auto
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-safe_implementation No
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-fsm_style lut
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-ram_extract Yes
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-ram_style Auto
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-rom_extract Yes
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-mux_style Auto
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-decoder_extract YES
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-priority_extract YES
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-shreg_extract YES
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-shift_extract YES
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-xor_collapse YES
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-rom_style Auto
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-auto_bram_packing NO
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-mux_extract YES
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-resource_sharing YES
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-async_to_sync NO
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-use_dsp48 auto
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-iobuf NO
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-max_fanout 500
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-bufg 32
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-bufr 24
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-register_duplication YES
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-register_balancing No
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-slice_packing YES
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-optimize_primitives NO
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-use_clock_enable Auto
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-use_sync_set Auto
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-use_sync_reset Auto
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-iob auto
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-equivalent_register_removal YES
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-slice_utilization_ratio_maxmargin 5
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@@ -0,0 +1 @@
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work
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@@ -0,0 +1,6 @@
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vhdl work "../../../../lib/fixed/fixed_pkg_c.vhd"
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vhdl work "../../../../lib/radio/nco/src/nco_pkg.vhd"
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vhdl work "../../../../lib/radio/nco/src/waverom_dual.vhd"
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vhdl work "../../../../lib/radio/nco/src/wavelut.vhd"
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vhdl work "../../../../lib/radio/nco/src/nco.vhd"
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vhdl work "../../src/syn_nco.vhd"
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@@ -0,0 +1,59 @@
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set -tmpdir "./xst/projnav.tmp"
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set -xsthdpdir "./xst"
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run
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-ifn syn_nco.prj
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-ifmt mixed
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-ofn syn_nco
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-ofmt NGC
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-p xc4vsx35-10-ff668
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-top syn_nco
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-opt_mode Speed
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-opt_level 1
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-power NO
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-iuc NO
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-lso syn_nco.lso
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-keep_hierarchy YES
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-rtlview Yes
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-glob_opt AllClockNets
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-read_cores YES
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-write_timing_constraints NO
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-cross_clock_analysis NO
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-hierarchy_separator /
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-bus_delimiter <>
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-case maintain
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-slice_utilization_ratio 100
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-bram_utilization_ratio 100
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-dsp_utilization_ratio 100
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-verilog2001 YES
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-fsm_extract YES -fsm_encoding Auto
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-safe_implementation No
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-fsm_style lut
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-ram_extract Yes
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-ram_style Auto
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-rom_extract Yes
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-mux_style Auto
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-decoder_extract YES
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-priority_extract YES
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-shreg_extract YES
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-shift_extract YES
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-xor_collapse YES
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-rom_style Auto
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-auto_bram_packing NO
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-mux_extract YES
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-resource_sharing YES
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-async_to_sync NO
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-use_dsp48 auto
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-iobuf NO
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-max_fanout 500
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-bufg 32
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-bufr 24
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-register_duplication YES
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-register_balancing No
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-slice_packing YES
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-optimize_primitives NO
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-use_clock_enable Auto
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-use_sync_set Auto
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-use_sync_reset Auto
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-iob auto
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-equivalent_register_removal YES
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-slice_utilization_ratio_maxmargin 5
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@@ -0,0 +1,97 @@
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CONFIG STEPPING="ES";
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# Bus clock nets
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NET "sys_clk_in" TNM_NET = "sys_clk";
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NET "ac97_bit_clk" TNM_NET = "ac97_clk";
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TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
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TIMESPEC "TSBITCLK" = PERIOD "ac97_clk" 80 ns HIGH 50 %;
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NET sys_clk_in LOC = AE14;
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NET sys_clk_in IOSTANDARD = LVCMOS33;
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NET sys_rst_n_in LOC = D6;
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NET sys_rst_n_in PULLUP;
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NET sys_rst_n_in TIG;
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////////////////////////////////////////////////////////////////////////////
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// AC97 Sound Controller
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////////////////////////////////////////////////////////////////////////////
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NET ac97_bit_clk LOC = AE10;
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NET ac97_bit_clk IOSTANDARD = LVCMOS33;
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NET ac97_bit_clk PERIOD = 80;
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NET ac97_sdata_in LOC = AD16;
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NET ac97_sdata_in IOSTANDARD = LVCMOS33;
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NET ac97_reset_n LOC = AD10;
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NET ac97_reset_n IOSTANDARD = LVCMOS33;
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NET ac97_reset_n TIG;
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NET ac97_reset_n SLEW = SLOW;
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NET ac97_sdata_out LOC = C8;
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NET ac97_sdata_out SLEW = FAST;
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NET ac97_sync LOC = D9;
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NET ac97_sync SLEW = FAST;
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////////////////////////////////////////////////////////////////////////////
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// RS-232
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////////////////////////////////////////////////////////////////////////////
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NET sys_rx LOC = W2;
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NET sys_rx IOSTANDARD = LVCMOS33;
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NET sys_rx TIG;
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NET "sys_tx" LOC = "W1";
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NET sys_tx IOSTANDARD = LVCMOS33;
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NET "sys_tx" TIG;
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////////////////////////////////////////////////////////////////////////////
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// Buttons, LEDs, and DIP Switches
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////////////////////////////////////////////////////////////////////////////
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# GPLED 0-3
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NET "sys_led<0>" LOC = "G5"; #GPLED0
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NET "sys_led<1>" LOC = "G6"; #GPLED1
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NET "sys_led<2>" LOC = "A11"; #GPLED2
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NET "sys_led<3>" LOC = "A12"; #GPLED3
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# North-East-South-West-Center LEDs
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NET "sys_led<4>" LOC = "F9"; # W LED
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NET "sys_led<5>" LOC = "E2"; # N LED
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NET "sys_led<6>" LOC = "E10"; # E LED
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NET "sys_led<7>" LOC = "A5"; # S LED
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NET "sys_led<8>" LOC = "C6"; # C LED
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NET "sys_led<*>" TIG;
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NET "sys_led<*>" SLEW = SLOW;
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NET "sys_led<*>" DRIVE = 2;
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NET "sys_led<*>" TIG;
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# North-East-South-West-Center Buttons
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NET "sys_btn<0>" LOC = "E9"; # W Button
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NET "sys_btn<1>" LOC = "E7"; # N Button
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NET "sys_btn<2>" LOC = "F10"; # E Button
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NET "sys_btn<3>" LOC = "A6"; # S Button
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NET "sys_btn<4>" LOC = "B6"; # C Button
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NET "sys_btn<*>" TIG;
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# Dip Switches 1-8
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NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
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NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
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NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
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NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
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NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
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NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
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NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
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NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
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NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
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NET "sys_dip<*>" TIG;
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////////////////////////////////////////////////////////////////////////////
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// LCD
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////////////////////////////////////////////////////////////////////////////
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NET sys_lcd_e LOC = AE13; # LCD_E
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NET sys_lcd_e IOSTANDARD = LVCMOS33;
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NET sys_lcd_e TIG;
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NET sys_lcd_rs LOC = AC17; # LCD_RS
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NET sys_lcd_rs IOSTANDARD = LVCMOS33;
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NET sys_lcd_rs TIG;
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NET sys_lcd_rw LOC = AB17; # LCD_RW
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NET sys_lcd_rw IOSTANDARD = LVCMOS33;
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NET sys_lcd_rw TIG;
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NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
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NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
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NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
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NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
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NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
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NET sys_lcd_d<*> TIG;
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NET sys_lcd_d<*> PULLDOWN;
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@@ -0,0 +1 @@
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work
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@@ -0,0 +1,13 @@
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vhdl work "../../../../lib/fixed/fixed_pkg_c.vhd"
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vhdl work "../../../../lib/CPUs/JCpu/src/core/cpu_pkg.vhd"
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vhdl work "../../../../lib/radio/mix/src/mix_pkg.vhd"
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vhdl work "../../../../lib/misc/singleshot.vhd"
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vhdl work "../../src/test_irom_ld.vhdl"
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vhdl work "../../src/ac_out.vhd"
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vhdl work "../../src/ac_in.vhd"
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vhdl work "../../src/test_xrom_ld.vhdl"
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vhdl work "../../src/cpu_embedded.vhd"
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vhdl work "../../src/ac_io.vhd"
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vhdl work "../../../../lib/radio/mix/src/mix_cpx.vhd"
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vhdl work "../../../../lib/misc/lcd_port.vhd"
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vhdl work "../../src/ac97_test.vhd"
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@@ -0,0 +1,33 @@
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-w
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-g DebugBitstream:No
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-g Binary:no
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-g CRC:Enable
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-g ConfigRate:4
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-g CclkPin:PullUp
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-g M0Pin:PullUp
|
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-g M1Pin:PullUp
|
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-g M2Pin:PullUp
|
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-g ProgPin:PullUp
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-g DonePin:PullUp
|
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-g InitPin:Pullup
|
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-g CsPin:Pullup
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-g DinPin:Pullup
|
||||
-g BusyPin:Pullup
|
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-g RdWrPin:Pullup
|
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-g TckPin:PullUp
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-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
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||||
-g UnusedPin:PullDown
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-g UserID:0xFFFFFFFF
|
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-g DCIUpdateMode:AsRequired
|
||||
-g StartUpClk:JtagClk
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||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Match_cycle:Auto
|
||||
-g Security:None
|
||||
-g DonePipe:No
|
||||
-g DriveDone:No
|
||||
-g Encrypt:No
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||||
@@ -0,0 +1,59 @@
|
||||
set -tmpdir "./xst/projnav.tmp"
|
||||
set -xsthdpdir "./xst"
|
||||
run
|
||||
-ifn ac97_test.prj
|
||||
-ifmt mixed
|
||||
-ofn ac97_test
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top ac97_test
|
||||
-opt_mode Speed
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||||
-opt_level 2
|
||||
-power NO
|
||||
-iuc NO
|
||||
-lso ac97_test.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
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||||
-bus_delimiter <>
|
||||
-case maintain
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||||
-slice_utilization_ratio 100
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||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
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||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob true
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
Reference in New Issue
Block a user