moved
git-svn-id: http://moon:8086/svn/vhdl/trunk@1413 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,7 @@
|
||||
vhdl work "../../../../lib/fixed/fixed_pkg_c.vhd"
|
||||
vhdl work "../../../../lib/filter/src/filter_pkg.vhd"
|
||||
vhdl work "../../../../lib/filter/src/fir_stage_pkg.vhd"
|
||||
vhdl work "../../../../lib/filter/src/fir_iterative_pkg.vhd"
|
||||
vhdl work "../../../../lib/filter/src/fir_stage.vhd"
|
||||
vhdl work "../../../../lib/filter/src/fir_iterative.vhd"
|
||||
vhdl work "../../src/syn_fir_bandpass.vhd"
|
||||
@@ -0,0 +1,59 @@
|
||||
set -tmpdir "./xst/projnav.tmp"
|
||||
set -xsthdpdir "./xst"
|
||||
run
|
||||
-ifn syn_fir_bandpass.prj
|
||||
-ifmt mixed
|
||||
-ofn syn_fir_bandpass
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top syn_fir_bandpass
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-power NO
|
||||
-iuc NO
|
||||
-lso syn_fir_bandpass.lso
|
||||
-keep_hierarchy YES
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-use_dsp48 auto
|
||||
-iobuf NO
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1,2 @@
|
||||
ieee_proposed
|
||||
work
|
||||
@@ -0,0 +1,11 @@
|
||||
vhdl ieee_proposed "../../../../lib/fixed/xilinx/math_utility_pkg.vhdl"
|
||||
vhdl ieee_proposed "../../../../lib/fixed/xilinx/fixed_pkg_c.vhdl"
|
||||
vhdl work "../../../../lib/fixed/fixed_util_pkg.vhd"
|
||||
vhdl work "../../../../lib/misc/utils_pkg.vhd"
|
||||
vhdl work "../../../../lib/filter/src/filter_pkg.vhd"
|
||||
vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
|
||||
vhdl work "../../../../lib/filter/src/fir_pkg.vhd"
|
||||
vhdl work "../../../../lib/filter/src/fir_stage_sys.vhd"
|
||||
vhdl work "../../../../lib/filter/src/delay_line.vhd"
|
||||
vhdl work "../../../../lib/filter/src/fir_semi_parallel.vhd"
|
||||
vhdl work "../../src/syn_fir_lowpass_sp.vhd"
|
||||
@@ -0,0 +1,60 @@
|
||||
set -tmpdir "W:/vhdl/projects/ac97_Controller/ise91/fir_lowpass/xst/projnav.tmp"
|
||||
set -xsthdpdir "W:/vhdl/projects/ac97_Controller/ise91/fir_lowpass/xst"
|
||||
run
|
||||
-ifn syn_fir_lowpass.prj
|
||||
-ifmt mixed
|
||||
-ofn syn_fir_lowpass
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top syn_fir_lowpass
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-power NO
|
||||
-iuc NO
|
||||
-lso syn_fir_lowpass.lso
|
||||
-keep_hierarchy YES
|
||||
-netlist_hierarchy as_optimized
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-use_dsp48 auto
|
||||
-iobuf NO
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,6 @@
|
||||
vhdl work "../../../../lib/fixed/fixed_pkg_c.vhd"
|
||||
vhdl work "../../../../lib/radio/nco/src/nco_pkg.vhd"
|
||||
vhdl work "../../../../lib/radio/nco/src/waverom_dual.vhd"
|
||||
vhdl work "../../../../lib/radio/nco/src/wavelut.vhd"
|
||||
vhdl work "../../../../lib/radio/nco/src/nco.vhd"
|
||||
vhdl work "../../src/syn_nco.vhd"
|
||||
@@ -0,0 +1,59 @@
|
||||
set -tmpdir "./xst/projnav.tmp"
|
||||
set -xsthdpdir "./xst"
|
||||
run
|
||||
-ifn syn_nco.prj
|
||||
-ifmt mixed
|
||||
-ofn syn_nco
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top syn_nco
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-power NO
|
||||
-iuc NO
|
||||
-lso syn_nco.lso
|
||||
-keep_hierarchy YES
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-use_dsp48 auto
|
||||
-iobuf NO
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1,97 @@
|
||||
CONFIG STEPPING="ES";
|
||||
|
||||
# Bus clock nets
|
||||
NET "sys_clk_in" TNM_NET = "sys_clk";
|
||||
NET "ac97_bit_clk" TNM_NET = "ac97_clk";
|
||||
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
|
||||
TIMESPEC "TSBITCLK" = PERIOD "ac97_clk" 80 ns HIGH 50 %;
|
||||
|
||||
NET sys_clk_in LOC = AE14;
|
||||
NET sys_clk_in IOSTANDARD = LVCMOS33;
|
||||
NET sys_rst_n_in LOC = D6;
|
||||
NET sys_rst_n_in PULLUP;
|
||||
NET sys_rst_n_in TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// AC97 Sound Controller
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET ac97_bit_clk LOC = AE10;
|
||||
NET ac97_bit_clk IOSTANDARD = LVCMOS33;
|
||||
NET ac97_bit_clk PERIOD = 80;
|
||||
NET ac97_sdata_in LOC = AD16;
|
||||
NET ac97_sdata_in IOSTANDARD = LVCMOS33;
|
||||
NET ac97_reset_n LOC = AD10;
|
||||
NET ac97_reset_n IOSTANDARD = LVCMOS33;
|
||||
NET ac97_reset_n TIG;
|
||||
NET ac97_reset_n SLEW = SLOW;
|
||||
NET ac97_sdata_out LOC = C8;
|
||||
NET ac97_sdata_out SLEW = FAST;
|
||||
NET ac97_sync LOC = D9;
|
||||
NET ac97_sync SLEW = FAST;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// RS-232
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_rx LOC = W2;
|
||||
NET sys_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_rx TIG;
|
||||
NET "sys_tx" LOC = "W1";
|
||||
NET sys_tx IOSTANDARD = LVCMOS33;
|
||||
NET "sys_tx" TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Buttons, LEDs, and DIP Switches
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
# GPLED 0-3
|
||||
NET "sys_led<0>" LOC = "G5"; #GPLED0
|
||||
NET "sys_led<1>" LOC = "G6"; #GPLED1
|
||||
NET "sys_led<2>" LOC = "A11"; #GPLED2
|
||||
NET "sys_led<3>" LOC = "A12"; #GPLED3
|
||||
# North-East-South-West-Center LEDs
|
||||
NET "sys_led<4>" LOC = "F9"; # W LED
|
||||
NET "sys_led<5>" LOC = "E2"; # N LED
|
||||
NET "sys_led<6>" LOC = "E10"; # E LED
|
||||
NET "sys_led<7>" LOC = "A5"; # S LED
|
||||
NET "sys_led<8>" LOC = "C6"; # C LED
|
||||
NET "sys_led<*>" TIG;
|
||||
NET "sys_led<*>" SLEW = SLOW;
|
||||
NET "sys_led<*>" DRIVE = 2;
|
||||
NET "sys_led<*>" TIG;
|
||||
# North-East-South-West-Center Buttons
|
||||
NET "sys_btn<0>" LOC = "E9"; # W Button
|
||||
NET "sys_btn<1>" LOC = "E7"; # N Button
|
||||
NET "sys_btn<2>" LOC = "F10"; # E Button
|
||||
NET "sys_btn<3>" LOC = "A6"; # S Button
|
||||
NET "sys_btn<4>" LOC = "B6"; # C Button
|
||||
NET "sys_btn<*>" TIG;
|
||||
# Dip Switches 1-8
|
||||
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
|
||||
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
|
||||
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
|
||||
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
|
||||
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
|
||||
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
|
||||
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
|
||||
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
|
||||
NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
|
||||
NET "sys_dip<*>" TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// LCD
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_lcd_e LOC = AE13; # LCD_E
|
||||
NET sys_lcd_e IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_e TIG;
|
||||
NET sys_lcd_rs LOC = AC17; # LCD_RS
|
||||
NET sys_lcd_rs IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rs TIG;
|
||||
NET sys_lcd_rw LOC = AB17; # LCD_RW
|
||||
NET sys_lcd_rw IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rw TIG;
|
||||
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
|
||||
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
|
||||
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
|
||||
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
|
||||
NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_d<*> TIG;
|
||||
NET sys_lcd_d<*> PULLDOWN;
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,13 @@
|
||||
vhdl work "../../../../lib/fixed/fixed_pkg_c.vhd"
|
||||
vhdl work "../../../../lib/CPUs/JCpu/src/core/cpu_pkg.vhd"
|
||||
vhdl work "../../../../lib/radio/mix/src/mix_pkg.vhd"
|
||||
vhdl work "../../../../lib/misc/singleshot.vhd"
|
||||
vhdl work "../../src/test_irom_ld.vhdl"
|
||||
vhdl work "../../src/ac_out.vhd"
|
||||
vhdl work "../../src/ac_in.vhd"
|
||||
vhdl work "../../src/test_xrom_ld.vhdl"
|
||||
vhdl work "../../src/cpu_embedded.vhd"
|
||||
vhdl work "../../src/ac_io.vhd"
|
||||
vhdl work "../../../../lib/radio/mix/src/mix_cpx.vhd"
|
||||
vhdl work "../../../../lib/misc/lcd_port.vhd"
|
||||
vhdl work "../../src/ac97_test.vhd"
|
||||
@@ -0,0 +1,33 @@
|
||||
-w
|
||||
-g DebugBitstream:No
|
||||
-g Binary:no
|
||||
-g CRC:Enable
|
||||
-g ConfigRate:4
|
||||
-g CclkPin:PullUp
|
||||
-g M0Pin:PullUp
|
||||
-g M1Pin:PullUp
|
||||
-g M2Pin:PullUp
|
||||
-g ProgPin:PullUp
|
||||
-g DonePin:PullUp
|
||||
-g InitPin:Pullup
|
||||
-g CsPin:Pullup
|
||||
-g DinPin:Pullup
|
||||
-g BusyPin:Pullup
|
||||
-g RdWrPin:Pullup
|
||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullDown
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g DCIUpdateMode:AsRequired
|
||||
-g StartUpClk:JtagClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Match_cycle:Auto
|
||||
-g Security:None
|
||||
-g DonePipe:No
|
||||
-g DriveDone:No
|
||||
-g Encrypt:No
|
||||
@@ -0,0 +1,59 @@
|
||||
set -tmpdir "./xst/projnav.tmp"
|
||||
set -xsthdpdir "./xst"
|
||||
run
|
||||
-ifn ac97_test.prj
|
||||
-ifmt mixed
|
||||
-ofn ac97_test
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top ac97_test
|
||||
-opt_mode Speed
|
||||
-opt_level 2
|
||||
-power NO
|
||||
-iuc NO
|
||||
-lso ac97_test.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob true
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1,107 @@
|
||||
## Generated SDC file "syn_fir_lowpass.out.sdc"
|
||||
|
||||
## Copyright (C) 1991-2008 Altera Corporation
|
||||
## Your use of Altera Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Altera Program License
|
||||
## Subscription Agreement, Altera MegaCore Function License
|
||||
## Agreement, or other applicable license agreement, including,
|
||||
## without limitation, that your use is for the sole purpose of
|
||||
## programming logic devices manufactured by Altera and sold by
|
||||
## Altera or its authorized distributors. Please refer to the
|
||||
## applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus II"
|
||||
## VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition"
|
||||
|
||||
## DATE "Wed Dec 31 12:25:32 2008"
|
||||
|
||||
##
|
||||
## DEVICE "EP3C25F324C8"
|
||||
##
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {clkin} -period 7.500 [get_ports {clk}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
set_max_delay -from [all_inputs] -to [get_clocks clkin] 2.0
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
set_max_delay -from [all_outputs] -to [get_clocks clkin] 1.5
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
set_false_path -through [get_pins {rst}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
@@ -0,0 +1,107 @@
|
||||
## Generated SDC file "syn_fir_lowpass.out.sdc"
|
||||
|
||||
## Copyright (C) 1991-2008 Altera Corporation
|
||||
## Your use of Altera Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Altera Program License
|
||||
## Subscription Agreement, Altera MegaCore Function License
|
||||
## Agreement, or other applicable license agreement, including,
|
||||
## without limitation, that your use is for the sole purpose of
|
||||
## programming logic devices manufactured by Altera and sold by
|
||||
## Altera or its authorized distributors. Please refer to the
|
||||
## applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus II"
|
||||
## VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition"
|
||||
|
||||
## DATE "Wed Dec 31 12:25:32 2008"
|
||||
|
||||
##
|
||||
## DEVICE "EP3C25F324C8"
|
||||
##
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {clk166} -period 7.500 [get_ports {clk}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Create Generated Clock
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Latency
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Uncertainty
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
set_max_delay -from [all_inputs] -to [get_clocks clk166] 2.0
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
set_max_delay -from [all_outputs] -to [get_clocks clk166] 1.5
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Clock Groups
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set False Path
|
||||
#**************************************************************
|
||||
set_false_path -through [get_pins {rst}]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Minimum Delay
|
||||
#**************************************************************
|
||||
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Input Transition
|
||||
#**************************************************************
|
||||
|
||||
@@ -0,0 +1,23 @@
|
||||
# Copyright (C) 1991-2008 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
QUARTUS_VERSION = "8.1"
|
||||
DATE = "11:53:04 December 31, 2008"
|
||||
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "syn_fir_lowpass"
|
||||
@@ -0,0 +1,62 @@
|
||||
# Copyright (C) 1991-2008 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
# The default values for assignments are stored in the file
|
||||
# syn_fir_lowpass_assignment_defaults.qdf
|
||||
# If this file doesn't exist, and for assignments not listed, see file
|
||||
# assignment_defaults.qdf
|
||||
|
||||
# Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name DEVICE EP3C25F324C6
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY syn_fir_lowpass
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:53:04 DECEMBER 31, 2008"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 8.1
|
||||
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
|
||||
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
|
||||
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name DSP_BLOCK_BALANCING AUTO
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
|
||||
set_global_assignment -name SDC_FILE syn_fir_lowpass.out.sdc
|
||||
set_global_assignment -name VHDL_FILE ../../../../lib/misc/dpram_1w1r.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../../lib/filter/src/fir_semi_parallel.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../../lib/filter/src/delay_line.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../../lib/filter/src/fir_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../src/syn_fir_lowpass_sp.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../../lib/filter/src/fir_stage_sys.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../../lib/misc/utils_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../../lib/fixed/fixed_util_pkg.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../../lib/fixed/altera/math_utility_pkg.vhdl
|
||||
set_global_assignment -name VHDL_FILE ../../../../lib/fixed/altera/fixed_pkg_c.vhdl
|
||||
set_global_assignment -name VHDL_FILE ../../../../lib/filter/src/filter_pkg.vhd
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
@@ -0,0 +1,18 @@
|
||||
[ProjectWorkspace]
|
||||
ptn_Child1=Frames
|
||||
[ProjectWorkspace.Frames]
|
||||
ptn_Child1=ChildFrames
|
||||
[ProjectWorkspace.Frames.ChildFrames]
|
||||
ptn_Child1=Document-0
|
||||
ptn_Child2=Document-1
|
||||
ptn_Child3=Document-2
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-0]
|
||||
ptn_Child1=ViewFrame-0
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
|
||||
DocPathName=../../src/syn_fir_lowpass_sp.vhd
|
||||
DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2}
|
||||
IsChildFrameDetached=False
|
||||
IsActiveChildFrame=False
|
||||
ptn_Child1=StateMap
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap]
|
||||
AFC_IN_REPORT=False
|
||||
@@ -0,0 +1,56 @@
|
||||
###########################################################################
|
||||
#
|
||||
# Generated by : Version 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
#
|
||||
# Project : syn_fir_lowpass
|
||||
# Revision : syn_fir_lowpass
|
||||
#
|
||||
# Date : Wed Dec 31 12:24:38 Westeuropäische Normalzeit 2008
|
||||
#
|
||||
###########################################################################
|
||||
|
||||
|
||||
# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
|
||||
# In SDC, create_generated_clock auto-generates clock latency
|
||||
#
|
||||
# ------------------------------------------
|
||||
#
|
||||
# Create generated clocks based on PLLs
|
||||
derive_pll_clocks -use_tan_name
|
||||
#
|
||||
# ------------------------------------------
|
||||
|
||||
# ** Clock Latency
|
||||
# -------------
|
||||
|
||||
# ** Clock Uncertainty
|
||||
# -----------------
|
||||
|
||||
# ** Multicycles
|
||||
# -----------
|
||||
# ** Cuts
|
||||
# ----
|
||||
|
||||
# ** Input/Output Delays
|
||||
# -------------------
|
||||
|
||||
|
||||
|
||||
|
||||
# ** Tpd requirements
|
||||
# ----------------
|
||||
|
||||
# ** Setup/Hold Relationships
|
||||
# ------------------------
|
||||
|
||||
# ** Tsu/Th requirements
|
||||
# -------------------
|
||||
|
||||
|
||||
# ** Tco/MinTco requirements
|
||||
# -----------------------
|
||||
|
||||
|
||||
|
||||
# ---------------------------------------------
|
||||
|
||||
Reference in New Issue
Block a user