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- added performance values for different cache sizes

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git-svn-id: http://moon:8086/svn/vhdl/trunk@303 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-31 10:57:36 +00:00
parent cc122dd696
commit 30cfa326f2
1 changed files with 15 additions and 6 deletions
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lib/CPUs/MIPS/doc/J-MIPS.txt
+15 -6
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@@ -13,7 +13,7 @@ J-MIPS Features
- Direct-mapped Instruction Cache mit variabler Größe, 8-words per Line - Direct-mapped Instruction Cache mit variabler Größe, 8-words per Line
- Direct-mapped Data Cache mit variabler Größe, 8-words per Line - Direct-mapped Data Cache mit variabler Größe, 8-words per Line
- J-Bus kompatible Bus Interface Unit (J-Bus ist im wesentlichen FIFO interface mit 'wichtigen' Signalnamen) - J-Bus kompatible Bus Interface Unit (J-Bus ist im wesentlichen FIFO interface mit 'wichtigen' Signalnamen)
- 1,15 DMIPS/MHz mit 16Kbyte I/D-Cache (Dhrystone 2.1) - 1,15 DMIPS/MHz mit 16Kbyte I/D-Cache (Dhrystone 2.1, GCC 4.3)
----------------------------------------------------------------- -----------------------------------------------------------------
Known Limitations Known Limitations
@@ -27,7 +27,6 @@ Known Limitations
----------------------------------------------------------------- -----------------------------------------------------------------
Known Bugs Known Bugs
----------------------------------------------------------------- -----------------------------------------------------------------
- nicht alle Cache-Sizes funktionieren
- Umschaltung (RE) zwischen Little/Big-Endian fehlerhaft - Umschaltung (RE) zwischen Little/Big-Endian fehlerhaft
- es gibt bestimmt noch nicht entdeckte Bugs - es gibt bestimmt noch nicht entdeckte Bugs
@@ -55,10 +54,10 @@ Virtex-4 XC4VSX35-10
Config: 16Kbyte I/D-Cache Config: 16Kbyte I/D-Cache
Number of Slices 2387 15360 15% Number of Slices 2387 15360 15%
Number of Slice Flip Flops 1784 30720 5% Number of Slice Flip Flops 1784 30720 5%
Number of 4 input LUTs 3962 30720 12% Number of 4 input LUTs 3962 30720 12%
Number of FIFO16/RAMB16s 18 192 9% Number of FIFO16/RAMB16s 18 192 9%
Speed: 110MHz nach Synthesis Speed: 110MHz nach Synthesis
@@ -67,11 +66,21 @@ Virtex-1 XCV1000-4
Config: 4Kbyte I/D-Cache Config: 4Kbyte I/D-Cache
Number of Slices 2045 13824 16% Number of Slices 2045 13824 16%
Number of Slice Flip Flops 1783 27648 7% Number of Slice Flip Flops 1783 27648 7%
Number of 4 input LUTs 3923 27648 15% Number of 4 input LUTs 3923 27648 15%
Number of FIFO16/RAMB16s 20 32 62% Number of FIFO16/RAMB16s 20 32 62%
Speed: 30MHz nach Synthesis Speed: 30MHz nach Synthesis
----------------------------------------------------------------- -----------------------------------------------------------------
Performance bei 100MHz
-----------------------------------------------------------------
I/D-Cache Dhrystone-2.1 RipeMD-160 Whetstone Stanford Queens(12x12)
1k 32 DMIPS 5 Mbit/s 345 kwhets/s 47/767 2,135s
2k 51 DMIPS 5 Mbit/s 534 kwhets/s 38/561 2,134s
4k 72 DMIPS 5 Mbit/s 623 kwhets/s 36/259 2,121s
8k 98 DMIPS 10 Mbit/s 1149 kwhets/s 31/228 1,938s
16k 115 DMIPS 17 Mbit/s 1234 kwhets/s 23/225 1,938s
32k 115 DMIPS 17 Mbit/s 1285 kwhets/s 24/218 1,938s
64k 115 DMIPS 17 Mbit/s 1285 kwhets/s 20/221 1,938s