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- added 16-depth Bus input FIFO (2 cycles additional latency)

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git-svn-id: http://moon:8086/svn/vhdl/trunk@709 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-06 14:07:47 +00:00
parent 0b403e7a58
commit 2e3f14ea17
1 changed files with 47 additions and 13 deletions
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lib/CPUs/MIPS/src/core/mips_bui.vhd
+47 -13
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@@ -155,7 +155,9 @@ architecture behavior of biu is
signal dcache_en2 : std_logic;
signal dcache_en : std_logic;
signal uncached_access : std_logic;
signal ACK : std_logic;
signal DAT : unsigned(31 downto 0);
type timeout_cnt_t is range 0 to 1E5-1;
signal bus_timeout_cnt : timeout_cnt_t;
signal bus_timeout : std_logic;
@@ -168,6 +170,13 @@ architecture behavior of biu is
signal bout_fifo_empty : std_logic;
signal bout_rdy : std_logic;
signal bin_fifo_din : unsigned(31 downto 0);
signal bin_fifo_dout : unsigned(31 downto 0);
signal bin_fifo_re : std_logic;
signal bin_fifo_we : std_logic;
signal bin_fifo_full : std_logic;
signal bin_fifo_empty : std_logic;
alias bout_fifo_addr_in is bout_fifo_din(31 downto 0);
alias bout_fifo_data_in is bout_fifo_din(63 downto 32);
alias bout_fifo_sel_in is bout_fifo_din(67 downto 64);
@@ -196,9 +205,6 @@ architecture behavior of biu is
begin
MRDY_O <= '1';
read_cyc_register:
process(CLK_I)
begin
@@ -213,6 +219,7 @@ read_cyc_register:
end if;
end process;
MRDY_O <= not bin_fifo_full;
CYC_O <= not bout_fifo_empty or read_cycle;
STB_O <= not bout_fifo_empty;
ADDR_O <= bout_fifo_addr_out;
@@ -237,8 +244,8 @@ inst_icache : icache
STB_O => STB_O_icache,
CYC_O => CYC_O_icache,
ADDR_O => ADDR_O_icache,
DAT_I => DAT_I,
ACK_I => ACK_I,
DAT_I => DAT,
ACK_I => ACK,
SRDY_I => SRDY_I_icache,
ctrl => cop0_ctrl_in.icache,
cpu_en => cpu_imem_en,
@@ -262,8 +269,8 @@ inst_dcache : dcache
CYC_O => CYC_O_dcache,
STB_O => STB_O_dcache,
ADDR_O => ADDR_O_dcache,
DAT_I => DAT_I,
ACK_I => ACK_I,
DAT_I => DAT,
ACK_I => ACK,
SRDY_I => SRDY_I_dcache,
ctrl => cop0_ctrl_in.dcache,
cpu_en => dcache_en,
@@ -281,6 +288,33 @@ inst_dcache : dcache
cpu_dmem_din <= dcache_dout when uncached_access = '0' else DAT_I_dmem_rd;
dcache_en <= dcached and cpu_dmem_en and dcache_en2; -- or write_busy);
-- Instantiate synchronous FIFO
inst_bin_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => 4,
data_width => 32
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => bin_fifo_we,
re => bin_fifo_re,
fifo_full => bin_fifo_full,
fifo_empty => bin_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => bin_fifo_din,
data_r => bin_fifo_dout
);
bin_fifo_din <= DAT_I;
DAT <= bin_fifo_dout;
ACK <= not bin_fifo_empty;
bin_fifo_we <= ACK_I;
bin_fifo_re <= read_cycle;
-- Instantiate synchronous FIFO
inst_bout_fifo: entity work.fifo_sync
GENERIC MAP
@@ -359,7 +393,7 @@ dmem_rd_flags:
CYC_O_dmem_rd <= '0';
dcache_en2 <= '1';
else
if ACK_I = '1' and dmem_mem_rd_gnt = '1' then
if ACK = '1' and dmem_mem_rd_gnt = '1' then
uncached_access <= '1';
CYC_O_dmem_rd <= '0';
dcache_en2 <= '1';
@@ -380,8 +414,8 @@ dmem_rd_data:
if rising_edge(CLK_I) then
if RST_I = '1' then
DAT_I_dmem_rd <= (others => '0');
elsif ACK_I = '1' and CYC_O_dmem_rd = '1' then
DAT_I_dmem_rd <= DAT_I;
elsif ACK = '1' and CYC_O_dmem_rd = '1' then
DAT_I_dmem_rd <= DAT;
end if;
end if;
end process;
@@ -410,7 +444,7 @@ bus_state_next:
end process;
bus_state:
process(s, CYC_O_icache, CYC_O_dcache, CYC_O_dmem_wr, CYC_O_dmem_rd, bout_rdy, ACK_I)
process(s, CYC_O_icache, CYC_O_dcache, CYC_O_dmem_wr, CYC_O_dmem_rd, bout_rdy, ACK)
begin
icache_mem_gnt <= '0';
@@ -462,7 +496,7 @@ bus_state:
end if;
when read_finish =>
dmem_mem_rd_gnt <= '1';
if ACK_I = '1' then
if ACK = '1' then
sn <= ready;
end if;
when others =>