From 2dd7abc098cfb4e1386ec880a28a1c013bdd4b96 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Tue, 23 Mar 2021 21:28:49 +0000
Subject: [PATCH] - added ghdl tb

git-svn-id: http://moon:8086/svn/vhdl/trunk@1506 cc03376c-175c-47c8-b038-4cd826a8556b
---
 .../ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.gtkw   | 54 +++++++++++++++++++
 .../ghdl/tb_sdram_ctrl_frontend.make          | 33 ++++++++++++
 2 files changed, 87 insertions(+)
 create mode 100644 lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.gtkw
 create mode 100644 lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_sdram_ctrl_frontend.make

diff --git a/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.gtkw b/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.gtkw
new file mode 100644
index 0000000..295e402
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.gtkw
@@ -0,0 +1,54 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Tue Mar 23 21:27:53 2021
+[*]
+[dumpfile] "/home/jens/work/vhdl/trunk/lib/SDRAM/ddr_sdr_v1_5/ghdl/build/tb_ctrl_ddr_wb32/tb_ctrl_ddr_wb32.vcd"
+[dumpfile_mtime] "Tue Mar 23 21:25:18 2021"
+[dumpfile_size] 133040938
+[savefile] "/home/jens/work/vhdl/trunk/lib/SDRAM/ddr_sdr_v1_5/ghdl/build/tb_ctrl_ddr_wb32/tb_ctrl_ddr_wb32.gtkw"
+[timestart] 0
+[size] 1856 1136
+[pos] -51 -51
+*-34.834126 46500000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] tb_ctrl_ddr_wb32.
+[sst_width] 256
+[signals_width] 244
+[sst_expanded] 1
+[sst_vpaned_height] 331
+@28
+tb_ctrl_ddr_wb32.uut.clk_i
+tb_ctrl_ddr_wb32.uut.rst_i
+@22
+tb_ctrl_ddr_wb32.uut.sel_i[3:0]
+@28
+tb_ctrl_ddr_wb32.uut.stb_i
+tb_ctrl_ddr_wb32.uut.srdy_o
+tb_ctrl_ddr_wb32.uut.we_i
+tb_ctrl_ddr_wb32.uut.ack_o
+@22
+tb_ctrl_ddr_wb32.uut.addr_i[31:0]
+tb_ctrl_ddr_wb32.uut.dat_i[31:0]
+tb_ctrl_ddr_wb32.uut.dat_o[31:0]
+tb_ctrl_ddr_wb32.uut.sd_addr[12:0]
+@200
+-
+@28
+tb_ctrl_ddr_wb32.uut.sd_ba[1:0]
+tb_ctrl_ddr_wb32.uut.sd_cas_n
+tb_ctrl_ddr_wb32.uut.sd_cke
+tb_ctrl_ddr_wb32.uut.sd_clk_n
+tb_ctrl_ddr_wb32.uut.sd_clk_p
+tb_ctrl_ddr_wb32.uut.sd_cs_n
+@22
+tb_ctrl_ddr_wb32.uut.sd_data[31:0]
+tb_ctrl_ddr_wb32.uut.sd_dm[3:0]
+tb_ctrl_ddr_wb32.uut.sd_dqs[3:0]
+@28
+tb_ctrl_ddr_wb32.uut.sd_ras_n
+tb_ctrl_ddr_wb32.uut.sd_we_n
+tb_ctrl_ddr_wb32.uut.sdram_clk0
+tb_ctrl_ddr_wb32.uut.sdram_clk_fb_i
+tb_ctrl_ddr_wb32.uut.sdram_clk_i
+tb_ctrl_ddr_wb32.uut.sdram_rst0
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_sdram_ctrl_frontend.make b/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_sdram_ctrl_frontend.make
new file mode 100644
index 0000000..656e61f
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_sdram_ctrl_frontend.make
@@ -0,0 +1,33 @@
+include ../../../../lib/FIFO/ghdl/fifo_sync.inc
+include ../../../../lib/FIFO/ghdl/fifo_async.inc
+
+ROOT_PATH := ../../../..
+LIB_PATH := $(ROOT_PATH)/lib
+SRC_PATH := $(LIB_PATH)/SDRAM/ddr_sdr_v1_5
+
+SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
+SRCS += $(FIFO_SYNC_SRCS)
+SRCS += $(FIFO_ASYNC_SRCS)
+SRCS += $(SRC_PATH)/src/sdram_const.vhd
+SRCS += $(SRC_PATH)/src/sdram_config_mt46v16m16.vhd
+SRCS += $(SRC_PATH)/src/sdram_types.vhd
+SRCS += $(SRC_PATH)/src/sdram_cmd.vhd
+SRCS += $(SRC_PATH)/src/sdram_ctrl.vhd
+SRCS += $(SRC_PATH)/src/ddr_clk_virtex4.vhd
+SRCS += $(SRC_PATH)/src/ddr_phy_virtex4.vhd
+SRCS += $(SRC_PATH)/src/sdram_ctrl_top.vhd
+SRCS += $(SRC_PATH)/src/sdram_ctrl_frontend_wb32.vhd
+SRCS += $(SRC_PATH)/src/ctrl_ddr_wb32.vhd
+SRCS += $(SRC_PATH)/src/mt46v16m16.vhd
+SRCS += $(SRC_PATH)/src/tb_ctrl_ddr_wb32.vhd
+
+# Compile
+TARGET := tb_ctrl_ddr_wb32
+ENTITY := tb_ctrl_ddr_wb32
+WITH_VCD := y
+RUN_TIME := 200us
+
+GHDL_OPTS := -P$(ROOT_PATH)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit
+
+include $(ROOT_PATH)/Common/make/ghdl.mk
+