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- zero lead-in / lead-out,

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but added 4 cycles relelease necessary for writes. See tWR in datasheet)
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git-svn-id: http://moon:8086/svn/vhdl/trunk@568 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-10-30 13:55:06 +00:00
parent d37afef047
commit 2db39f4504
2 changed files with 4 additions and 4 deletions
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lib/CPUs/MIPS/src/async_defs.vhd
+1 -1
View File
@@ -35,7 +35,7 @@ package async_defs is
ncyc_pulse_rd => 12, ncyc_pulse_rd => 12,
ncyc_pulse_wr => 7, ncyc_pulse_wr => 7,
ncyc_leadout => 0, ncyc_leadout => 0,
ncyc_release => 0, ncyc_release => 4,
ncyc_pulse_rst => 8, ncyc_pulse_rst => 8,
can_page_rd => true, can_page_rd => true,
nbits_page_rd => 4, nbits_page_rd => 4,
projects/mips_sys/src/sys_types.vhd
+3 -3
View File
@@ -31,11 +31,11 @@ package async_defs is
constant ts_flash : async_timespec_t := constant ts_flash : async_timespec_t :=
( (
ncyc_leadin => 1, ncyc_leadin => 0,
ncyc_pulse_rd => 12, ncyc_pulse_rd => 12,
ncyc_pulse_wr => 7, ncyc_pulse_wr => 7,
ncyc_leadout => 1, ncyc_leadout => 0,
ncyc_release => 1, ncyc_release => 4,
ncyc_pulse_rst => 8, ncyc_pulse_rst => 8,
can_page_rd => true, can_page_rd => true,
nbits_page_rd => 4, nbits_page_rd => 4,