From 2c9f7472596a9df613f11a117d43cade86dc31f7 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 1 Mar 2009 18:13:20 +0000 Subject: [PATCH] Initial version Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@374 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/dist/tmpl/notes.txt | 35 +++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 lib/CPUs/MIPS/dist/tmpl/notes.txt diff --git a/lib/CPUs/MIPS/dist/tmpl/notes.txt b/lib/CPUs/MIPS/dist/tmpl/notes.txt new file mode 100644 index 0000000..6b37017 --- /dev/null +++ b/lib/CPUs/MIPS/dist/tmpl/notes.txt @@ -0,0 +1,35 @@ +----------------------------------------------------------------- +Changes in release 11 +----------------------------------------------------------------- +- bug-fix in mips_pipeline: pc_is_branch is now initialized at reset + (fixes CPU unrecoverable state after reset) +- reverted "optimization" in mips_dcache, which behaved buggy during exceptions +- new example source: test_exception +- minor changes in libsys +- added async_port_timing in doc + +----------------------------------------------------------------- +Changes in release 10b +----------------------------------------------------------------- +- fixed compiler bug (missing nop after lw) in bootloader, + which caused exception during boot + +----------------------------------------------------------------- +Changes in release 10a +----------------------------------------------------------------- +async_port_wb: +- added byte enable for async_port + +bootloader.c +- fixed compiler bug (missing nop after lw) + +mips-core +- SEL_O lines are also asserted correctly during reads + +tools/romgen +- TCL-Jtage now compatible with Chipscope 10.1 + +mips_sys.c +- use byte enable for sram and flash + +