diff --git a/lib/CPUs/MIPS/dist/tmpl/notes.txt b/lib/CPUs/MIPS/dist/tmpl/notes.txt
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+-----------------------------------------------------------------
+Changes in release 11
+-----------------------------------------------------------------
+- bug-fix in mips_pipeline: pc_is_branch is now initialized at reset
+  (fixes CPU unrecoverable state after reset)
+- reverted "optimization" in mips_dcache, which behaved buggy during exceptions
+- new example source: test_exception
+- minor changes in libsys
+- added async_port_timing in doc
+
+-----------------------------------------------------------------
+Changes in release 10b
+-----------------------------------------------------------------
+- fixed compiler bug (missing nop after lw) in bootloader,
+  which caused exception during boot
+
+-----------------------------------------------------------------
+Changes in release 10a
+-----------------------------------------------------------------
+async_port_wb:
+- added byte enable for async_port
+
+bootloader.c
+- fixed compiler bug (missing nop after lw)
+
+mips-core
+- SEL_O lines are also asserted correctly during reads
+
+tools/romgen
+- TCL-Jtage now compatible with Chipscope 10.1
+
+mips_sys.c
+- use byte enable for sram and flash
+
+