From 2b459949bb2bdff30eb0242fb53a2c7d0c7ef2e5 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 13 Jun 2015 11:37:26 +0000 Subject: [PATCH] - fixed pipelined access git-svn-id: http://moon:8086/svn/vhdl/trunk@1301 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/spi/src/spi_flash_wb.vhd | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/lib/spi/src/spi_flash_wb.vhd b/lib/spi/src/spi_flash_wb.vhd index b9a6cfa..b347296 100644 --- a/lib/spi/src/spi_flash_wb.vhd +++ b/lib/spi/src/spi_flash_wb.vhd @@ -65,6 +65,7 @@ ARCHITECTURE rtl OF spi_flash_wb IS signal state : state_t; signal state_next : state_t; + signal SRDY_mem : std_logic; signal ACK_mem : std_logic; signal ACK_reg : std_logic; signal DAT_mem : unsigned(31 downto 0); @@ -78,6 +79,7 @@ begin INT_O <= '0'; ACK_O <= ACK_mem or ACK_reg; DAT_O <= DAT_reg when ACK_reg = '1' else DAT_mem; + SRDY_O <= SRDY_mem; tag_match <= tag_valid when ADDR_I(tag_reg'range) = tag_reg else '0'; register_access <= ADDR_I(FLASH_ADDR_BITS); @@ -137,7 +139,7 @@ word_addr_register: process(CLK_I) begin if rising_edge(CLK_I) then - if (CYC_I and STB_I and not register_access and not WE_I) = '1' then + if (CYC_I and STB_I and SRDY_mem and not register_access and not WE_I) = '1' then word_addr_reg <= ADDR_I(CACHE_ADDR_BITS-1 downto 2); end if; end if; @@ -192,7 +194,7 @@ proc_fsm: process(state, CYC_I, STB_I, WE_I, tag_match, mst_cmd_rdy, mst_din_rdy, mst_status, register_access) begin state_next <= state; - SRDY_O <= CYC_I; + SRDY_mem <= '0'; mst_cmd_vld <= '0'; mst_din_vld <= '0'; tag_we <= '0'; @@ -202,6 +204,7 @@ begin state_next <= idle; when idle => + SRDY_mem <= CYC_I; if (CYC_I and STB_I and not WE_I and not register_access) = '1' then if tag_match = '0' then state_next <= spi_cmd;