From 2a0d20f4b2503d867fd779ef1c8d7526cb9e4790 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Thu, 9 Oct 2008 11:50:07 +0000
Subject: [PATCH] - Added Bus timeout detection - STB_O, ADDR_O registered to
 output when SRDY

git-svn-id: http://moon:8086/svn/vhdl/trunk@31 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/CPUs/MIPS/src/core/mips_bui.vhd | 66 +++++++++++++++++++++++++----
 1 file changed, 58 insertions(+), 8 deletions(-)

diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd
index e2f9842..463b52d 100644
--- a/lib/CPUs/MIPS/src/core/mips_bui.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_bui.vhd
@@ -43,10 +43,12 @@ entity bui is
 		CYC_O			: out STD_LOGIC;
 		STB_O			: out STD_LOGIC;
 		MRDY_O			: out STD_LOGIC;
+		cpu_imem_err	: out STD_LOGIC;
 		cpu_imem_rdy	: out STD_LOGIC;
 		cpu_imem_en		: in  STD_LOGIC;
 		cpu_imem_addr	: in  word_t;
 		cpu_imem_din	: out word_t;
+		cpu_dmem_err	: out STD_LOGIC;
 		cpu_dmem_rdy	: out STD_LOGIC;
 		cpu_dmem_en		: in  STD_LOGIC;
 		cpu_dmem_re		: in  STD_LOGIC;
@@ -139,6 +141,10 @@ architecture behavior of bui is
 	signal dcache_en		: std_logic;
 	signal uncached_access	: std_logic;
 	
+	type timeout_cnt_t is range 0 to 1E5-1;	
+	signal bus_timeout_cnt	: timeout_cnt_t;
+	signal bus_timeout		: std_logic;
+	
 begin
 
 bus_strobe:
@@ -149,9 +155,9 @@ bus_strobe:
 				STB_O	<= '0';
 			elsif dmem_mem_gnt = '1' then
 				STB_O	<= STB_O_dmem;
-			elsif dcache_mem_gnt = '1' then
+			elsif SRDY_I_dcache = '1' then
 				STB_O	<= STB_O_dcache;
-			elsif icache_mem_gnt = '1' then
+			elsif SRDY_I_icache = '1' then
 				STB_O	<= STB_O_icache;
 			elsif SRDY_I = '1' then
 				STB_O	<= '0';
@@ -159,27 +165,40 @@ bus_strobe:
 		end if;
 	end process;	
 
+bus_cycle:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			CYC_O		<= '0';
+			if dmem_mem_gnt = '1' then
+				CYC_O	<= CYC_O_dmem;
+			elsif dcache_mem_gnt = '1' then
+				CYC_O	<= CYC_O_dcache;
+			elsif icache_mem_gnt = '1' then
+				CYC_O	<= CYC_O_icache;
+			end if;	
+		end if;
+	end process;	
+
 bus_out:
 	process(CLK_I)
 	begin
 		if rising_edge(CLK_I) then
-			CYC_O		<= '0';
 			if RST_I = '1' then
 				ADDR_O		<= (others => '0');
 				DAT_O		<= (others => '0');
+				WE_O		<= '0';
+				SEL_O		<= (others => '0');
 			elsif dmem_mem_gnt = '1' then
-				CYC_O		<= CYC_O_dmem;
 				ADDR_O		<= ADDR_O_dmem;
 				DAT_O		<= DAT_O_dmem;
 				WE_O		<= WE_O_dmem;
 				SEL_O		<= SEL_O_dmem;
-			elsif dcache_mem_gnt = '1' then
-				CYC_O		<= CYC_O_dcache;
+			elsif SRDY_I_dcache = '1' then
 				ADDR_O		<= ADDR_O_dcache;
 				WE_O		<= '0';
 				SEL_O		<= (others => '0');
-			elsif icache_mem_gnt = '1' then
-				CYC_O		<= CYC_O_icache;
+			elsif SRDY_I_icache = '1' then
 				ADDR_O		<= ADDR_O_icache;
 				WE_O		<= '0';
 				SEL_O		<= (others => '0');
@@ -361,6 +380,37 @@ bus_state:
 				
 	end process;	
 
+bus_timeout_counter:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if (icache_mem_gnt or dcache_mem_gnt or dmem_mem_gnt) = '1' then
+				if bus_timeout_cnt /= 0 then
+					bus_timeout_cnt	<= bus_timeout_cnt - 1;
+				else
+					bus_timeout	<= '1';
+				end if;	
+			else
+				bus_timeout_cnt	<= timeout_cnt_t'high;
+				bus_timeout		<= '0';
+			end if;
+		end if;
+	end process;	
+
+bus_err:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				cpu_imem_err	<= '0';
+				cpu_dmem_err	<= '0';
+			elsif bus_timeout = '1' then
+				cpu_imem_err	<= icache_mem_gnt;
+				cpu_dmem_err	<= dcache_mem_gnt or dmem_mem_gnt;
+			end if;
+		end if;
+	end process;	
+	
 -------------------------------------------------------------------
 	
 end behavior;