From 29eb6a05c314529c9ac11550cee9e6784202f18f Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 25 Oct 2008 11:11:52 +0000 Subject: [PATCH] - Cleaned up git-svn-id: http://moon:8086/svn/vhdl/trunk@105 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/VGA_ctrl/src/dpram.vhd | 79 ---------------------- lib/VGA_ctrl/src/linefifo.vhd | 121 ---------------------------------- 2 files changed, 200 deletions(-) delete mode 100644 lib/VGA_ctrl/src/dpram.vhd delete mode 100644 lib/VGA_ctrl/src/linefifo.vhd diff --git a/lib/VGA_ctrl/src/dpram.vhd b/lib/VGA_ctrl/src/dpram.vhd deleted file mode 100644 index b6c5419..0000000 --- a/lib/VGA_ctrl/src/dpram.vhd +++ /dev/null @@ -1,79 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -entity dpram is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram; - -architecture Behavioral of dpram is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal RAM : RAMtype; - -begin - -process (clka) - begin - if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) <= din_a; - end if; - end if; - end if; -end process; - -process (clkb) - begin - if clkb'event and clkb = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); - end if; - end if; -end process; - - -end Behavioral; - diff --git a/lib/VGA_ctrl/src/linefifo.vhd b/lib/VGA_ctrl/src/linefifo.vhd deleted file mode 100644 index 4336ede..0000000 --- a/lib/VGA_ctrl/src/linefifo.vhd +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity linefifo is - Generic - ( - depth : natural := 64; - almost_full_thresh : natural := 60; - almost_empty_thresh : natural := 4 - ); - Port - ( - rst : in STD_LOGIC; - clk_w : in STD_LOGIC; - clk_r : in STD_LOGIC; - we_w : in STD_LOGIC; - re_r : in STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC; - color_w : in color_t; - color_r : out color_t - ); -end linefifo; - -architecture Behavioral of linefifo is - - constant data_width : integer := 8; - constant addr_width : integer := NextExpBaseTwo(depth); - - signal buf_we_w : STD_LOGIC; - signal ptr_w : unsigned (ADDR_WIDTH-1 downto 0); - signal ptr_r : unsigned (ADDR_WIDTH-1 downto 0); - signal full : STD_LOGIC; - signal empty : STD_LOGIC; - signal almost_full : STD_LOGIC; - signal almost_empty : STD_LOGIC; - -begin - - buf_we_w <= we_w; - fifo_full <= full; - fifo_empty <= empty; - fifo_afull <= almost_full; - fifo_aempty <= almost_empty; - -gen_line: - for c in color_range_t generate - begin - inst_dpram: entity work.dpram - GENERIC MAP - ( - addr_width => addr_width, - data_width => data_width - ) - PORT MAP( - clka => clk_w, - clkb => clk_r, - en_a => '1', - en_b => '1', - we_a => buf_we_w, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => color_w(c), - dout_b => color_r(c) - ); - end generate; - - inst_fifo_ctrl: entity work.async_fifo_ctrl - GENERIC MAP - ( - addr_width => ADDR_WIDTH, - almost_full_thresh => almost_full_thresh, - almost_empty_thresh => almost_empty_thresh - ) - PORT MAP - ( - rst => rst, - clk_w => clk_w, - clk_r => clk_r, - we => we_w, - re => re_r, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => full, - fifo_empty => empty, - fifo_afull => almost_full, - fifo_aempty => almost_empty - - ); - -end Behavioral; -