From 293699d051f43c8d35ba2c87e6e9178f6d577c90 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Thu, 11 Mar 2010 11:35:25 +0000
Subject: [PATCH] update Committed on the Free edition of March Hare Software
 CVSNT Server. Upgrade to CVS Suite for more features and support:
 http://march-hare.com/cvsnt/

git-svn-id: http://moon:8086/svn/vhdl/trunk@768 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/CPUs/MIPS/doc/J-MIPS.txt               | 2 ++
 lib/CPUs/MIPS/syn/ise101/mips_top.prj      | 5 ++++-
 lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj | 5 ++++-
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/lib/CPUs/MIPS/doc/J-MIPS.txt b/lib/CPUs/MIPS/doc/J-MIPS.txt
index 6f6dcb2..43448cb 100644
--- a/lib/CPUs/MIPS/doc/J-MIPS.txt
+++ b/lib/CPUs/MIPS/doc/J-MIPS.txt
@@ -14,6 +14,8 @@ J-MIPS Features
 - Direct-mapped Data Cache mit variabler Größe, 8-words per Line
 - J-Bus kompatible Bus Interface Unit (J-Bus ist im wesentlichen FIFO interface mit 'wichtigen' Signalnamen)
 - 1,2 DMIPS/MHz mit 16Kbyte I/D-Cache (Dhrystone 2.1, GCC 4.3)
+- Endianness umschaltbar zur Hard-reset Zeit
+- Unterschiedliche Frequenzen für CPU und BUS möglich
 
 -----------------------------------------------------------------
 Known Limitations
diff --git a/lib/CPUs/MIPS/syn/ise101/mips_top.prj b/lib/CPUs/MIPS/syn/ise101/mips_top.prj
index d7e78b5..ea45b69 100644
--- a/lib/CPUs/MIPS/syn/ise101/mips_top.prj
+++ b/lib/CPUs/MIPS/syn/ise101/mips_top.prj
@@ -1,9 +1,12 @@
+vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../../../FIFO/src/gray_counter.vhd"
 vhdl work "../../../../misc/dpram_2w2r.vhd"
 vhdl work "../../../../misc/dpram_1w1r.vhd"
 vhdl work "../../../../FIFO/src/fifo_sync_ctrl.vhd"
-vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../../../FIFO/src/fifo_async_ctrl.vhd"
 vhdl work "../../src/core/mips_types.vhd"
 vhdl work "../../../../FIFO/src/fifo_sync.vhd"
+vhdl work "../../../../FIFO/src/fifo_async.vhd"
 vhdl work "../../src/core/mips_shifter.vhd"
 vhdl work "../../src/core/mips_reg.vhd"
 vhdl work "../../src/core/mips_muldiv.vhd"
diff --git a/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj b/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
index ebe6b75..7676319 100644
--- a/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
+++ b/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
@@ -1,9 +1,12 @@
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
 vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd"
 vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
 vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
 vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
 vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"