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- uses now new generic DPRAMs

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git-svn-id: http://moon:8086/svn/vhdl/trunk@942 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-02-09 09:26:12 +00:00
parent bf4ba346c0
commit 280db0f521
3 changed files with 15 additions and 31 deletions
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lib/CPUs/MIPS/src/core/dcache.vhd
+3 -21
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@@ -58,26 +58,8 @@ END dcache;
ARCHITECTURE behavior OF dcache IS
COMPONENT dpram_1w1r
GENERIC
(
addr_width : integer := 3;
data_width : integer := 8
);
PORT (
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
en_a : in STD_LOGIC;
en_b : in STD_LOGIC;
we_a : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
END COMPONENT;
COMPONENT dpram_2w2r is
COMPONENT dpram_2w2r2c_ra is
GENERIC
(
addr_width : integer := 3;
@@ -276,7 +258,7 @@ instant_raw_logic:
end if;
end process;
inst_tag_ram : dpram_2w2r
inst_tag_ram : dpram_2w2r2c_ra
GENERIC MAP
(
addr_width => tag_ram_addr_width,
@@ -302,7 +284,7 @@ gen_data_ram:
for i in 0 to 3 generate
begin
inst_data_ram : dpram_2w2r
inst_data_ram : dpram_2w2r2c_ra
GENERIC MAP
(
addr_width => lg2(cache_size),