[UART]

- composed uart from uart_tx and uart_rx
- tb_uart tests uart

git-svn-id: http://moon:8086/svn/vhdl/trunk@1354 cc03376c-175c-47c8-b038-4cd826a8556b

lib/uart/tb_uart.vhd

@@ -25,6 +25,9 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.numeric_std.ALL;
 
+LIBRARY WORK;
+USE WORK.uart_types.all;
+
 entity tb_uart is
 end;
 
@@ -38,58 +41,42 @@ architecture behave of tb_uart is
 	signal rst				: std_logic := '1';  
 	signal clk				: std_logic := '1';  
 	signal en_16_x_baud		: std_logic := '1';  
+	signal ctrl				: ctrl_t;  
+	signal status			: status_t;  
 	
 	-- TX
 	signal tx_we			: std_logic := '0';  
-	signal ser_out			: std_logic;  
-	signal tx_full			: std_logic;  
-	signal tx_half_full		: std_logic;  
+	signal tx_ser			: std_logic;  
 	signal tx_din			: unsigned(7 downto 0) := (others => '0');
 
 	-- RX
-	signal ser_in			: std_logic := '1';  
-	signal rx_dout_vld		: std_logic;  
-	signal rx_full			: std_logic;  
-	signal rx_half_full		: std_logic;  
-	signal rx_dout			: unsigned(7 downto 0);
 	signal rx_re			: std_logic := '0';  
+	signal rx_ser			: std_logic := '1';  
+	signal rx_dout			: unsigned(7 downto 0);
 	
 	-- Others
-	signal baud_count		: unsigned(15 downto 0);
-	signal baud_reg			: unsigned(15 downto 0) := to_unsigned(BAUD_DIV-1, baud_count'length);
 	signal data_rx			: unsigned(7 downto 0);
 	signal data_tx			: unsigned(7 downto 0);
 	signal count_rx			: natural;
 
 begin
 
-	ser_in	<= ser_out;
+	rx_ser			<= tx_ser;
+	ctrl.baudrate	<= to_unsigned(BAUD_DIV-1, ctrl.baudrate'length);
 	
-inst_uart_tx : entity work.uart_tx
+dut : entity work.uart
 	PORT MAP
 	(
 		rst					=> rst,
 		clk					=> clk,
 		we					=> tx_we,
-		din					=> tx_din,
-		en_16_x_baud		=> en_16_x_baud,
-		full				=> tx_full,
-		half_full			=> tx_half_full,
-		ser_out				=> ser_out
-	);
-
-inst_uart_rx : entity work.uart_rx
-	PORT MAP
-	(
-		rst					=> rst,
-		clk					=> clk,
-		en_16_x_baud		=> en_16_x_baud,
-		dout_vld			=> rx_dout_vld,
-		dout				=> rx_dout,
 		re					=> rx_re,
-		full				=> rx_full,
-		half_full			=> rx_half_full,
-		ser_in				=> ser_in
+		din					=> tx_din,
+		dout				=> rx_dout,
+		ser_tx				=> tx_ser,
+		ser_rx				=> rx_ser,
+		ctrl				=> ctrl,
+		status				=> status
 	);
 
 CLK_GEN: process
@@ -104,7 +91,7 @@ PROC_DATAREG_RX:
 		if rising_edge(clk) then
 			if rst = '1' then
 				count_rx <= 0;
-			elsif rx_dout_vld = '1' and rx_re = '1' then
+			elsif status.rx_present = '1' and rx_re = '1' then
 --				assert rx_dout = count_rx report "Data mismatch" severity failure;
 				data_rx 	<= rx_dout;
 				count_rx	<= count_rx + 1;
@@ -115,7 +102,7 @@ PROC_DATAREG_RX:
 PROC_RX_RE: process
 	begin
 		wait for 10 us;
-		rx_re	<= rx_dout_vld;
+		rx_re	<= status.rx_present;
 	end process;
 
 PROC_DATAREG_TX: process
@@ -124,22 +111,6 @@ PROC_DATAREG_TX: process
 		data_tx <= tx_din;
 	end process;
 
-baud_timer:
-process(clk)
-begin
-	if rising_edge(clk) then
-		en_16_x_baud <= '0';
-		if rst = '1' then
-			baud_count <= (others => '0');
-		elsif baud_count = baud_reg then
-			baud_count <= (others => '0');
-			en_16_x_baud <= '1';
-		else
-			baud_count <= baud_count + 1;
-		end if;
-	end if;
-end process;
-
 ------------------------------------------------------------------------------------------
 
 STIMULUS: process
@@ -156,7 +127,7 @@ STIMULUS: process
 			wait until rising_edge(clk);
 			tx_din <= to_unsigned(i, 8);
 			tx_we <= '1';
-			wait until rising_edge(clk) and tx_full = '0';
+			wait until rising_edge(clk) and status.tx_full = '0';
 			tx_we <= '0';
 		end loop;
 		wait;