From 26a0a30fdcb0d1640fef5e859580647dd66bb09d Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 15 May 2010 23:43:34 +0000 Subject: [PATCH] - fixed bus-timeout for nx=0 and ny /= 0 Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@915 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/VGA_ctrl/src/vga_frontend64.vhd | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/lib/VGA_ctrl/src/vga_frontend64.vhd b/lib/VGA_ctrl/src/vga_frontend64.vhd index 5a68669..e12d774 100644 --- a/lib/VGA_ctrl/src/vga_frontend64.vhd +++ b/lib/VGA_ctrl/src/vga_frontend64.vhd @@ -671,12 +671,12 @@ proc_blit_src_counter: blit_src_first <= '0'; if blit_src_row_cnt /= blit_nx then blit_src_row_cnt <= blit_src_row_cnt + 1; - if blit_src_unaligned = '1' then - blit_src_do_extra2 <= '1'; - end if; elsif blit_src_do_extra2 = '1' then blit_src_do_extra2 <= '0'; else + if blit_src_unaligned = '1' then + blit_src_do_extra2 <= '1'; + end if; blit_src_row_cnt <= (others => '0'); blit_src_first <= blit_src_unaligned; end if; @@ -725,16 +725,19 @@ proc_blit_addr_src: blit_src_off_y <= blit_dimx_src_0; blit_src_finish <= '0'; blit_src_do_extra <= '0'; + if blit_src_addr (2 downto 0) /= "000" then + blit_src_do_extra <= not blit_const_color_en; + end if; elsif blit_src_finish = '0' and ((STB_O_blit_src = '1' and bus_fifo_rdy = '1') or (blit_const_color_en = '1' and blitfifo_src_full = '0')) then blit_src_offset <= blit_src_offset + 8; if blit_src_cnt_x /= blit_nx then blit_src_cnt_x <= blit_src_cnt_x + 1; - if blit_src_unaligned = '1' then - blit_src_do_extra <= '1'; - end if; elsif blit_src_do_extra = '1' then blit_src_do_extra <= '0'; else + if blit_src_unaligned = '1' then + blit_src_do_extra <= '1'; + end if; if blit_src_cnt_y /= blit_ny then blit_src_cnt_x <= (others => '0'); blit_src_offset <= blit_src_off_y; @@ -797,7 +800,8 @@ proc_blit_addr_dst: blit_dst_last <= '0'; blit_dst_unaligned <= '0'; if blit_addr_dst (2 downto 0) /= "000" then - blit_dst_unaligned <= '1'; + blit_dst_unaligned <= '1'; + blit_dst_do_extra <= '1'; end if; elsif blit_dst_finish = '0' and (STB_O_blit_dst = '1' and bus_fifo_rdy = '1') then blit_dst_first <= blit_dst_last; @@ -805,13 +809,13 @@ proc_blit_addr_dst: blit_dst_offset <= blit_dst_offset + 8; if blit_dst_cnt_x /= blit_nx then blit_dst_cnt_x <= blit_dst_cnt_x + 1; - if blit_dst_unaligned = '1' then - blit_dst_do_extra <= '1'; - end if; elsif blit_dst_do_extra = '1' then blit_dst_do_extra <= '0'; blit_dst_last <= '1'; else + if blit_dst_unaligned = '1' then + blit_dst_do_extra <= '1'; + end if; if blit_dst_cnt_y /= blit_ny then blit_dst_cnt_x <= (others => '0'); blit_dst_offset <= blit_dst_off_y;