diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo
index ad0a7dd..a7a3287 100644
--- a/lib/CPUs/MIPS/sim/tb_mips_top.wdo
+++ b/lib/CPUs/MIPS/sim/tb_mips_top.wdo
@@ -97,6 +97,8 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_reg_en
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/was_miss
 add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count
 add wave -noupdate -divider D-Cache
 add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/s
 add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr
@@ -128,7 +130,7 @@ add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/was_miss
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we
 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {2158634 ps} 0}
+WaveRestoreCursors {{Cursor 1} {2127774 ps} 0}
 configure wave -namecolwidth 188
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -142,4 +144,4 @@ configure wave -gridperiod 100
 configure wave -griddelta 40
 configure wave -timeline 1
 update
-WaveRestoreZoom {2118570 ps} {2318226 ps}
+WaveRestoreZoom {0 ps} {5031559 ps}