diff --git a/lib/filter/src/fir_stage_sys.vhd b/lib/filter/src/fir_stage_sys.vhd
index 75a9a1a..7a3b240 100644
--- a/lib/filter/src/fir_stage_sys.vhd
+++ b/lib/filter/src/fir_stage_sys.vhd
@@ -138,8 +138,10 @@ begin
 	variable yout : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
 	begin
 		if rising_edge(clk) then
-			yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate);
-			y_out <= yout;
+			if ce = '1' then
+				yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate);
+				y_out <= yout;
+			end if;	
 		end	if;
 	end process;