diff --git a/projects/vga_ctrl/src/tb_vga_ctrl.vhd b/projects/vga_ctrl/src/tb_vga_ctrl.vhd
index 107729d..704980a 100644
--- a/projects/vga_ctrl/src/tb_vga_ctrl.vhd
+++ b/projects/vga_ctrl/src/tb_vga_ctrl.vhd
@@ -45,51 +45,51 @@ ARCHITECTURE behavior OF tb_vga_ctrl IS
 	);
 	PORT
 	(
-		sys_rst_in : IN std_logic;
-		sys_clk_in : IN std_logic;    
+		rst_in : IN std_logic;
+		clk_in : IN std_logic;    
 		      
 		-- VGA signals
-		sys_vga_clk_in : IN std_logic;
-		sys_vga_clk_ce : IN std_logic;
-		sys_vga_red : OUT unsigned(7 downto 0);
-		sys_vga_green : OUT unsigned(7 downto 0);
-		sys_vga_blue : OUT unsigned(7 downto 0);
-		sys_vga_blank_n : OUT std_logic;
-		sys_vga_sync_n : OUT std_logic;
-		sys_vga_hsync : OUT std_logic;
-		sys_vga_vsync : OUT std_logic;
+		vga_clk_in : IN std_logic;
+		vga_clk_ce : IN std_logic;
+		vga_red : OUT unsigned(7 downto 0);
+		vga_green : OUT unsigned(7 downto 0);
+		vga_blue : OUT unsigned(7 downto 0);
+		vga_blank_n : OUT std_logic;
+		vga_sync_n : OUT std_logic;
+		vga_hsync : OUT std_logic;
+		vga_vsync : OUT std_logic;
 		
 		-- Buttons and LEDs
-		sys_dip : in unsigned(7 downto 0);
-		sys_btn : in unsigned(4 downto 0);
-		sys_led : out unsigned(8 downto 0)
+		dip : in unsigned(7 downto 0);
+		btn : in unsigned(4 downto 0);
+		led : out unsigned(8 downto 0)
 	);
 	END COMPONENT;
 
 	--Constants
 	constant tsvga			: vga_timespec_t := ts_vga_testbench;
 	constant PERIOD : time := 10 ns;
-	constant SYS_CLK_PERIOD		: time := 10 ns;
+	constant CLK_PERIOD		: time := 10 ns;
 	constant VGA_CLK_PERIOD	: time := (integer(1E9) / tsvga.f_pxl_clk) * 1 ns;
 
 	--Inputs
-	SIGNAL sys_rst_in :  std_logic := '1';
-	SIGNAL sys_clk_in :  std_logic := '0';
-	SIGNAL sys_color_en :  unsigned(2 downto 0) := (others => '0');
-	SIGNAL sys_dip :  unsigned(7 downto 0) := (others => '0');
-	SIGNAL sys_btn :  unsigned(4 downto 0) := (others => '0');
+	SIGNAL rst_in :  std_logic := '1';
+	SIGNAL clk_in :  std_logic := '0';
+	SIGNAL color_en :  unsigned(2 downto 0) := (others => '0');
+	SIGNAL dip :  unsigned(7 downto 0) := (others => '0');
+	SIGNAL btn :  unsigned(4 downto 0) := (others => '0');
 
 	--Outputs
-	SIGNAL sys_vga_clk_ce :  std_logic := '1';
-	SIGNAL sys_vga_clk_in :  std_logic := '0';
-	SIGNAL sys_vga_red :  unsigned(7 downto 0);
-	SIGNAL sys_vga_green :  unsigned(7 downto 0);
-	SIGNAL sys_vga_blue :  unsigned(7 downto 0);
-	SIGNAL sys_vga_blank_n :  std_logic;
-	SIGNAL sys_vga_sync_n :  std_logic;
-	SIGNAL sys_vga_hsync :  std_logic;
-	SIGNAL sys_vga_vsync :  std_logic;
-	SIGNAL sys_led :  unsigned(8 downto 0);
+	SIGNAL vga_clk_ce :  std_logic := '1';
+	SIGNAL vga_clk_in :  std_logic := '0';
+	SIGNAL vga_red :  unsigned(7 downto 0);
+	SIGNAL vga_green :  unsigned(7 downto 0);
+	SIGNAL vga_blue :  unsigned(7 downto 0);
+	SIGNAL vga_blank_n :  std_logic;
+	SIGNAL vga_sync_n :  std_logic;
+	SIGNAL vga_hsync :  std_logic;
+	SIGNAL vga_vsync :  std_logic;
+	SIGNAL led :  unsigned(8 downto 0);
 	constant f_sys : real := 100.0;
 	constant f_vga : real := 130.0;
 --	SIGNAL test_M : natural := VGA_FREQ_M(f_sys, f_vga);
@@ -105,33 +105,33 @@ BEGIN
 	)
 	PORT MAP
 	(
-		sys_rst_in => sys_rst_in,
-		sys_clk_in => sys_clk_in,
+		rst_in => rst_in,
+		clk_in => clk_in,
 
-		sys_vga_clk_in => sys_vga_clk_in,
-		sys_vga_clk_ce => sys_vga_clk_ce,
-		sys_vga_red => sys_vga_red,
-		sys_vga_green => sys_vga_green,
-		sys_vga_blue => sys_vga_blue,
-		sys_vga_blank_n => sys_vga_blank_n,
-		sys_vga_sync_n => sys_vga_sync_n,
-		sys_vga_hsync => sys_vga_hsync,
-		sys_vga_vsync => sys_vga_vsync,
+		vga_clk_in => vga_clk_in,
+		vga_clk_ce => vga_clk_ce,
+		vga_red => vga_red,
+		vga_green => vga_green,
+		vga_blue => vga_blue,
+		vga_blank_n => vga_blank_n,
+		vga_sync_n => vga_sync_n,
+		vga_hsync => vga_hsync,
+		vga_vsync => vga_vsync,
 		
-		sys_dip => sys_dip,
-		sys_btn => sys_btn,
-		sys_led => sys_led
+		dip => dip,
+		btn => btn,
+		led => led
 	);
 
- 	sys_clk : PROCESS
+ 	clk : PROCESS
 	BEGIN
-		sys_clk_in <= not sys_clk_in;
-		wait for SYS_CLK_PERIOD/2;
+		clk_in <= not clk_in;
+		wait for CLK_PERIOD/2;
 	END PROCESS;
 
  	vga_clk : PROCESS
 	BEGIN
-		sys_vga_clk_in <= not sys_vga_clk_in;
+		vga_clk_in <= not vga_clk_in;
 		wait for VGA_CLK_PERIOD/2;
 	END PROCESS;
 
@@ -139,17 +139,17 @@ BEGIN
 	BEGIN
 
 		-- Wait 100 ns for global reset to finish
-		wait for 100*SYS_CLK_PERIOD;
-		sys_rst_in <= '0';
+		wait for 100*CLK_PERIOD;
+		rst_in <= '0';
 
-		wait for SYS_CLK_PERIOD;
-		sys_dip <= X"AA";
+		wait for CLK_PERIOD;
+		dip <= X"AA";
 
-		wait for SYS_CLK_PERIOD;
-		sys_color_en <= "100";
+		wait for CLK_PERIOD;
+		color_en <= "100";
 
-		wait for 10*SYS_CLK_PERIOD;
-		sys_color_en <= "000";
+		wait for 10*CLK_PERIOD;
+		color_en <= "000";
 
 		-- Wait 100 ns for global reset to finish
 		wait for 100 ns;
diff --git a/projects/vga_ctrl/src/vga_ctrl_top.vhd b/projects/vga_ctrl/src/vga_ctrl_top.vhd
index 06576a7..235f439 100644
--- a/projects/vga_ctrl/src/vga_ctrl_top.vhd
+++ b/projects/vga_ctrl/src/vga_ctrl_top.vhd
@@ -31,24 +31,24 @@ entity vga_ctrl_top is
 	);
 	Port
 	(
-		sys_rst_in		: in std_logic;
-		sys_clk_in		: in std_logic;
+		rst_in		: in std_logic;
+		clk_in		: in std_logic;
 		
 		-- VGA signals
-		sys_vga_clk_in	: in  std_logic;
-		sys_vga_clk_ce	: in  std_logic;
-		sys_vga_red		: out unsigned(7 downto 0);
-		sys_vga_green	: out unsigned(7 downto 0);
-		sys_vga_blue	: out unsigned(7 downto 0);
-		sys_vga_blank_n	: out std_logic;
-		sys_vga_sync_n	: out std_logic;
-		sys_vga_hsync	: out std_logic;
-		sys_vga_vsync	: out std_logic;
+		vga_clk_in	: in  std_logic;
+		vga_clk_ce	: in  std_logic;
+		vga_red		: out unsigned(7 downto 0);
+		vga_green	: out unsigned(7 downto 0);
+		vga_blue	: out unsigned(7 downto 0);
+		vga_blank_n	: out std_logic;
+		vga_sync_n	: out std_logic;
+		vga_hsync	: out std_logic;
+		vga_vsync	: out std_logic;
 		
 		-- Buttons and LEDs
-		sys_btn			: in unsigned(4 downto 0);
-		sys_dip			: in unsigned(7 downto 0);
-		sys_led			: out unsigned(8 downto 0)
+		btn			: in unsigned(4 downto 0);
+		dip			: in unsigned(7 downto 0);
+		led			: out unsigned(8 downto 0)
 	);
 end vga_ctrl_top;
 
@@ -126,8 +126,8 @@ inst_vga_backend : entity work.vga_backend
 	PORT MAP
 	(
 		-- System signals
-		sys_rst			=> rst,
-		sys_clk			=> clk,
+		sys_rst			=> rst_in,
+		sys_clk			=> clk_in,
 		
 		-- Color channels
 		color_in		=> color_in,
@@ -150,18 +150,18 @@ inst_vga_backend : entity work.vga_backend
 		stat_vpos		=> stat_vpos,
 		
 		-- VGA domain signals
-		vga_clk_in		=> sys_vga_clk_in,
-		vga_clk_ce		=> sys_vga_clk_ce,
-		vga_red			=> sys_vga_red,
-		vga_green		=> sys_vga_green,
-		vga_blue		=> sys_vga_blue,
-		vga_blank_n		=> sys_vga_blank_n,
-		vga_sync_n		=> sys_vga_sync_n,
-		vga_hsync		=> sys_vga_hsync,
-		vga_vsync		=> sys_vga_vsync
+		vga_clk_in		=> vga_clk_in,
+		vga_clk_ce		=> vga_clk_ce,
+		vga_red			=> vga_red,
+		vga_green		=> vga_green,
+		vga_blue		=> vga_blue,
+		vga_blank_n		=> vga_blank_n,
+		vga_sync_n		=> vga_sync_n,
+		vga_hsync		=> vga_hsync,
+		vga_vsync		=> vga_vsync
 	);
 
-	vga_clk			<= sys_vga_clk_in;
+	vga_clk			<= vga_clk_in;
 	ctrl_scan_en	<= '1';
 	color_en(0)		<= '1';
 	color_en(1)		<= cg_draw;
@@ -186,8 +186,8 @@ inst_vga_backend : entity work.vga_backend
 	)		
 	PORT MAP
 	(
-	    rst				=> rst,
-	    sys_clk			=> clk,
+	    rst				=> rst_in,
+	    sys_clk			=> clk_in,
 	    vga_clk			=> vga_clk,
 	    ce				=> cg_en,
 	    frame_pulse		=> scan_rdy,
@@ -232,8 +232,8 @@ inst_vga_backend : entity work.vga_backend
 	);
 
 	---------------------------------------------------------------------------------------------
-	rst             <= sys_rst_in and stat_vga_rdy;
-	clk				<= sys_clk_in;
+	rst             <= rst_in and stat_vga_rdy;
+	clk				<= clk_in;
 
 	scan_rdy		<= stat_hready and stat_vready;
 
@@ -245,7 +245,7 @@ inst_vga_backend : entity work.vga_backend
 led_out: process (clk)
 	begin
 		if rising_edge(clk) then
-			sys_led	<= '0' & cpu_led;
+			led	<= '0' & cpu_led;
 		end if;
 	end process;
 
@@ -258,11 +258,11 @@ cpu_reg_read:
 		if rising_edge(clk) then
 			case cpu_addr is
 			when X"00" =>	-- 00
-				reg := "000" & unsigned(sys_btn(4 downto 0));
+				reg := "000" & unsigned(btn(4 downto 0));
 			when X"01" =>	-- 01 
 				reg := cpu_led;
 			when X"05" =>	-- 05 
-				reg := unsigned(sys_dip);
+				reg := unsigned(dip);
 			when X"0B" =>
 				reg := "000000" & cg_rdy & stat_vga_rdy;
 			when others => null;