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git-svn-id: http://moon:8086/svn/vhdl/trunk@802 cc03376c-175c-47c8-b038-4cd826a8556b

lib/emac/src/sipo.vhd

@@ -0,0 +1,110 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+use work.utils_pkg.all; --  Imports the standard textio package.
+
+ENTITY sipo IS
+	Generic
+	(
+		data_width_in	: natural := 8;
+		data_width_out	: natural := 32;
+		msb_first		: boolean := false
+	);
+	Port
+	(
+		rst			: in  STD_LOGIC;
+		clk			: in  STD_LOGIC;
+		enable		: in  STD_LOGIC;
+		din_en		: in  STD_LOGIC;
+		din			: in  unsigned(data_width_in-1 downto 0);
+		dout_en		: out STD_LOGIC;
+		dout_be		: out unsigned(data_width_out/data_width_in-1 downto 0);
+		dout		: out unsigned(data_width_out-1 downto 0)
+		
+	);
+END sipo;
+
+ARCHITECTURE behavior OF sipo IS
+
+	constant num_shifts		: natural := data_width_out/data_width_in;
+	signal idle				: STD_LOGIC;
+	signal pre_fin			: STD_LOGIC;
+	signal shift_cnt_pipe	: unsigned(num_shifts-1 downto 0);
+	signal vld_pipe			: unsigned(num_shifts-1 downto 0);
+	signal shift_pipe		: unsigned(data_width_out-1 downto 0);
+	
+--------------------------------------------------------------------------
+begin
+
+	pre_fin		<= shift_cnt_pipe(shift_cnt_pipe'left);
+	
+--------------------------------------------------------------------------
+process(clk)
+begin
+	if rising_edge(clk) then
+		dout_en		<= pre_fin;
+		if rst = '1' then
+			dout_be	<= (others => '0');
+		elsif pre_fin = '1' then
+			dout_be		<= vld_pipe;
+			dout		<= shift_pipe;
+		end if;
+	end if;
+end process;
+
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' or enable = '0' then
+			idle	<= '1';
+		elsif din_en = '1' then
+			idle	<= '0';
+		end if;
+	end if;
+end process;
+
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' or pre_fin = '1' or enable = '0' then
+			shift_cnt_pipe	<= (num_shifts-1 downto 1 => '0') & '1';
+		elsif idle = '0' then
+			shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & '1';
+		end if;
+	end if;
+end process;
+
+process(clk)
+begin
+	if rising_edge(clk) then
+		if (msb_first) then
+			shift_pipe		<= shift_pipe(shift_pipe'left-data_width_in downto 0) & din;
+		else
+			shift_pipe		<= din & shift_pipe(shift_pipe'left downto data_width_in);
+		end if;
+	end if;
+end process;
+
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' or enable = '0' or pre_fin = '1' then
+			if (msb_first) then
+				vld_pipe		<= (num_shifts-1 downto 1 => '0') & din_en;
+			else
+				vld_pipe		<= din_en & (num_shifts-2 downto 0 => '0');
+			end if;
+		else
+			if (msb_first) then
+				vld_pipe		<= vld_pipe(shift_cnt_pipe'left-1 downto 0) & din_en;
+			else
+				vld_pipe		<= din_en & vld_pipe(shift_cnt_pipe'left downto 1);
+			end if;
+		end if;
+	end if;
+end process;
+
+--------------------------------------------------------------------------
+end behavior;