From 1e0d84d98960e03f1e3034dcbdfe14c3d6e8d83d Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 23 Aug 2008 08:20:31 +0000 Subject: [PATCH] This commit was manufactured by cvs2svn to create branch 'BRANCH_TEST'. git-svn-id: http://moon:8086/svn/vhdl/branches/BRANCH_TEST@6 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/JCpu/asm/dctest.jsm | 56 - lib/CPUs/JCpu/asm/dctest.tcl | 212 - lib/CPUs/JCpu/asm/itest.jsm | 858 -- lib/CPUs/JCpu/asm/itest.tcl | 3407 ------- lib/CPUs/JCpu/asm/make | 50 - lib/CPUs/JCpu/asm/mul8x8.jsm | 29 - lib/CPUs/JCpu/asm/mul8x8.tcl | 154 - lib/CPUs/JCpu/asm/reti_issue.jsm | 50 - lib/CPUs/JCpu/asm/reti_issue.tcl | 157 - lib/CPUs/JCpu/doc/block_diagram.png | Bin 8026 -> 0 bytes lib/CPUs/JCpu/doc/memory_map.png | Bin 3545 -> 0 bytes lib/CPUs/JCpu/gpl-3.0.txt | 674 -- lib/CPUs/JCpu/sim/tb_cpu.fdo | 22 - lib/CPUs/JCpu/sim/tb_cpu.wdo | 107 - lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo | 21 - lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo | 26 - 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------------------------------------------------- - xmem - org 4 -konst: dc 0x01, 0x12,"A" -gap1: db 16 -mesg: dc "Hallo", 13,0x0A, 0 -name: dc "Jens",0 -msg1: dc "Welcome to JASM CPU",0 -msg2: dc "Ready",0 -msg3: dc "Testing",0 -msg4: dc "Passed",0 -msg5: dc "Error",0 -crlf: dc 0x0D, 0x0A - - org 0x00 -shit: db 4 - - cmem 0 - org 8 -cram1: db 16 -cram2: db 6 -cram3: db 4 - - cmem 1 -cram4: db 8 -cram5: db 8 - org 0x20 -cram6: db 8 -cram7: db 4 - -reg_revision: equ 0x00 -reg_testid: equ 0x01 - -; ------------------------------------------------- - code - org 0x000 -reset: jmp start - -; ------------------------------------------------- - org 0x001 -int_vec: jmp isr - -; ------------------------------------------------- - org 0x010 - -start: jmp start - -; ------------------------------------------------- -isr: reti - diff --git a/lib/CPUs/JCpu/asm/dctest.tcl b/lib/CPUs/JCpu/asm/dctest.tcl deleted file mode 100644 index ca88834..0000000 --- a/lib/CPUs/JCpu/asm/dctest.tcl +++ /dev/null @@ -1,212 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE -# Assembled from dctest.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA -# User 1 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"] - -# 0x000: JMP 0x010 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030010" - -# 0x001: JMP 0x011 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00130011" - -# 0x002: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00200000" - -# 0x003: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00300000" - -# 0x004: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00400000" - -# 0x005: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000" - -# 0x006: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00600000" - -# 0x007: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000" - -# 0x008: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00800000" - -# 0x009: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000" - -# 0x00A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A00000" - -# 0x00B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000" - -# 0x00C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C00000" - -# 0x00D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000" - -# 0x00E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E00000" - -# 0x00F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000" - -# 0x010: JMP 0x010 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01030010" - -# 0x011: RETI -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0113F000" - -# Assembled from dctest.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA -# User 2 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"] - -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0401" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0512" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0641" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1748" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1861" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "196C" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A6C" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B6F" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C0D" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D0A" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F4A" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2065" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "216E" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2273" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2457" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2565" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "266C" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2763" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "286F" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "296D" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A65" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B20" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C74" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D6F" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E20" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F4A" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3041" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3153" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "324D" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3320" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3443" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3550" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3655" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3852" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3965" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3A61" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3B64" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3C79" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3E54" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3F65" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4073" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4174" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4269" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "436E" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4467" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4650" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4761" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4873" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4973" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4A65" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4B64" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4D45" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4E72" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4F72" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "506F" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5172" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "530D" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "540A" - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/JCpu/asm/itest.jsm b/lib/CPUs/JCpu/asm/itest.jsm deleted file mode 100644 index 9666253..0000000 --- a/lib/CPUs/JCpu/asm/itest.jsm +++ /dev/null @@ -1,858 +0,0 @@ -; ------------------------------------------------- -; PROJECT "itest" -; ------------------------------------------------- - -include "../../../jasm/cregs.inc.jsm" - -; ------------------------------------------------- - xmem -msg: dc "Hallo", 0 -xram: db 256 - - cmem 0 -cram: db 256 - -reg_revision: equ 0x00 -reg_testid: equ 0x01 - -; ------------------------------------------------- - code - org 0x000 -reset: jmp start - -; ------------------------------------------------- - org 0x001 -int_vec: jmp isr - -; ------------------------------------------------- - org 0x010 - -start: call init - cin R0, (cpu_revision) - xout (reg_revision), R0 - - ; Test 0 - call test0 - - ; Test 1 - mov R0, 1 - xout (reg_testid), R0 - call test1 - - ; Test 2 - mov R0, 2 - xout (reg_testid), R0 - call test2 - - ; Test 3 - mov R0, 3 - xout (reg_testid), R0 - call test3 - - ; Test 4 - mov R0, 4 - xout (reg_testid), R0 - call test4 - - ; Test 5 - mov R0, 5 - xout (reg_testid), R0 - call test5 - - ; Test 6 - mov R0, 6 - xout (reg_testid), R0 - call test6 - - ; Test 7 - mov R0, 7 - xout (reg_testid), R0 - call test7 - - ; Test 8 - mov R0, 8 - xout (reg_testid), R0 - call test8 - - ; Test 9 - mov R0, 9 - xout (reg_testid), R0 - call test9 - - ; Test 10 - mov R0, 10 - xout (reg_testid), R0 - call test10 - - ; Test 11 - mov R0, 11 - xout (reg_testid), R0 - call test11 - - ; Test 12 - mov R0, 12 - xout (reg_testid), R0 - call test12 - - ; End of test - mov R0, 0xFF - xout (reg_testid), R0 - - jmp ok - -; ------------------------------------------------- -init: mov R0, 0 - mov R1, 0 - mov R2, 0 - mov R3, 0 - mov R4, 0 - mov R5, 0 - mov R6, 0 - mov R7, 0 - mov R8, 0 - mov R9, 0 - mov R10, 0 - mov R11, 0 - mov R12, 0 - mov R13, 0 - mov R14, 0 - mov R15, 0 - ret - -; ------------------------------------------------- -; MOV|R|K -; MOV|R|R -test0: mov R0, 0x10 - cmp R0, 0x10 - jne error - add R0, 1 - - mov R1, R0 - cmp R1, 0x11 - jne error - add R1, 1 - - mov R2, R1 - cmp R2, 0x12 - jne error - add R2, 1 - - mov R3, R2 - cmp R3, 0x13 - jne error - add R3, 1 - - mov R4, R3 - cmp R4, 0x14 - jne error - add R4, 1 - - mov R5, R4 - cmp R5, 0x15 - jne error - add R5, 1 - - mov R6, R5 - cmp R6, 0x16 - jne error - add R6, 1 - - mov R7, R6 - cmp R7, 0x17 - jne error - add R7, 1 - - mov R8, R7 - cmp R8, 0x18 - jne error - add R8, 1 - - mov R9, R8 - cmp R9, 0x19 - jne error - add R9, 1 - - mov R10, R9 - cmp R10, 0x1A - jne error - add R10, 1 - - mov R11, R10 - cmp R11, 0x1B - jne error - add R11, 1 - - mov R12, R11 - cmp R12, 0x1C - jne error - add R12, 1 - - mov R13, R12 - cmp R13, 0x1D - jne error - add R13, 1 - - mov R14, R13 - cmp R14, 0x1E - jne error - add R14, 1 - - mov R15, R14 - cmp R15, 0x1F - jne error - add R15, 1 - - ret - -; ------------------------------------------------- -; Instruction test -; TST|R -; CMP|R|K -; JNZ|K -; JC|K -; JNE|K -; JLT|K -; JGT|K -; JLE|K -; JGE|K -; JMP|K -test1: mov R0, 0 ; R0 <= 0 - tst R0 - jnz error - jc error - cmp R0, 0 - jne error - jlt error - jgt error - jle t1_ok10 - jmp error - -t1_ok10: jeq t1_ok20 - jmp error - -t1_ok20: jge t1_ok30 - jmp error - -t1_ok30: cmp R0, 0x55 - jeq error - jlt t1_ok40 - jmp error - -t1_ok40: jle t1_ok50 - jmp error - -t1_ok50: jge error - jgt error - - mov R0, 0x55 ; R0 <= 0xAA - tst R0 - jz error - jc error - - cmp R0, 0xAA - jeq error - jne t1_ok60 - jmp error - -t1_ok60: jlt t1_ok70 - jmp error - -t1_ok70: jle t1_ok80 - jmp error - -t1_ok80: jgt error - - cmp R0, 0x55 - jeq t1_ok90 - jmp error - -t1_ok90: jne error - jlt error - - jle t1_ok100 - jmp error - -t1_ok100: jgt error - jge t1_ok110 - jmp error - -t1_ok110: mov R0, 0xAA ; R0 <= 0x55 - tst R0 - jz error - jc error - - cmp R0, 0x55 - jeq error - jne t1_ok120 - jmp error - -t1_ok120: jgt t1_ok130 - jmp error - -t1_ok130: jge t1_ok140 - jmp error - -t1_ok140: jlt error - jle error - - ret - -; ------------------------------------------------- -; ADD|R|K -; ADDC|R|K -; ToDo: ADD|R|R -; ToDo: ADDC|R|R -; CMP|R|R -test2: mov R0, 0 - mov R1, 0 - mov R2, R0 - mov R3, R1 - -t2_loop: add R0, 0x01 - addc R1, 0x00 - add R2, 1 - cmp R2, 0 - jne t2_L1 - add R3, 1 - cmp R3, 0x02 -t2_L1: jne t2_loop - cmp R0, R2 - jne error - cmp R1, R3 - jne error - mov R0, 0 - - ret - -; ------------------------------------------------- -; SUB|R|K -; SUBC|R|K -; ToDo: SUB|R|R -; ToDo: SUBC|R|R -; CMP|R|R -test3: mov R0, 0x00 - mov R1, 0x03 - mov R2, R0 - mov R3, R1 - -t3_loop: sub R0, 0x01 - subc R1, 0x00 - sub R2, 1 - cmp R2, 0xFF - jne t3_L1 - sub R3, 1 - cmp R3, 0x00 -t3_L1: jne t3_loop - cmp R0, R2 - jne error - cmp R1, R3 - jne error - mov R0, 0 - - ret -; ------------------------------------------------- -; SUB|K|R -; SUB|R|R -; SUBC|R|R -; SUBC|K|R -; CMP|R|R -test4: mov R0, 0x03 - mov R1, 0x05 - sub 0x05, R0 - sub R1, 0x03 - cmp R0, R1 - jne error - mov R0, 0x03 - mov R1, 0x05 - sub R0, R1 - subc 0, R0 - cmp R0, 0x01 - jne error - add R0, 0 - subc R1, R0 - cmp R1, 0x04 - jne error - mov R0, 0 - - ret - -; ------------------------------------------------- -; MOVC|R|Ri -; MOVC|R|Ki -; MOVC|Ri|R -; MOVC|Ri|K -; MOVC|Ki|R -test5: mov R0, 1 - movc (cram+0x5A), R0 - dec R0 - movc (cram+0), R0 - movc R1, (cram+0x5A) - movc (R1), 0xA5 - movc R0, (R1) - movc R1, (R1) - add R1, 0xFF-0xA5 - movc R0, (R1) -t5_loop1: movc (R0), R0 - movc R2, (R0) - cmp R2, R0 - jne error - movc (R2), R1 - movc R2, (R2) - cmp R2, R1 - jne error - dec R1 - inc R0 - jnz t5_loop1 - - ret - -; ------------------------------------------------- -; MOVX|R|Ri -; MOVX|R|Ki -; MOVX|Ri|R -; MOVX|Ri|K -; MOVX|Ki|R -test6: mov R0, 1 - movx (xram+0x5A), R0 - dec R0 - movx (xram+0), R0 - movx R1, (xram+0x5A) - movx (R1), 0xA5 - movx R0, (R1) - movx R1, (R1) - add R1, 0xFF-0xA5 - movx R0, (R1) -t6_loop1: movx (R0), R0 - movx R2, (R0) - cmp R2, R0 - jne error - movx (R2), R1 - movx R2, (R2) - cmp R2, R1 - jne error - dec R1 - inc R0 - jnz t6_loop1 - - ret - -; ------------------------------------------------- -; PUSH|R -; POP|R -test7: mov R0, 0xAA - mov R1, 0 -t7_loop1: push R0 - inc R0 - dec R1 - jnz t7_loop1 -t7_loop2: pop R0 - dec R1 - jnz t7_loop2 - cmp R0, 0xAA - jne error - - ret - -; ------------------------------------------------- -; JMP|K -; CALL|K -; RET -test8: mov R0, 0x55 - push R0 - mov R0, 0 - mov R1, 0xFF - call t8_rec - pop R0 - cmp R0, 0x55 - jne error - - ; Stack manipulations 1 - mov R0, return1'high - mov R1, return1'low - cout (cpu_stack_high), R0 - push R1 - - mov R0, init'high - mov R1, init'low - cout (cpu_stack_high), R0 - push R1 - ret - - ; Stack manipulations 2 -return1: mov R0, return2'high - mov R1, return2'low - cout (cpu_stack_high), R0 - push R1 - - mov R0, init'high - mov R1, init'low - cout (cpu_stack_high), R0 - push R1 -return2: ret - -t8_rec: cmp R0, R1 - jeq ex_t8_rec - inc R0 - jmp t8_rstub -ex_t8_rec: dec R0 - dec R1 - ret - -t8_rstub: call t8_rec - jmp ex_t8_rec - -; ------------------------------------------------- -; SWAP|R -; SHL|R -; SHR|R -; ROL|R -; ROR|R -; ROLC|R -; RORC|R -test9: mov R0, 0xA5 ; SWAP test - mov R1, 0x5A - swap R0 - cmp R0, 0x5A - jne error - swap R0 - cmp R0, 0xA5 - jne error - mov R0, 0xD2 - swap R0 - cmp R0, 0x2D - jne error - swap R1 - cmp R0, 0x2D - jne error - cmp R1, 0xA5 - jne error - - mov R0, 0x2D - shl R0 ; SHL test - cmp R0, 0x5A - jne error - shl R0 - cmp R0, 0xB4 - jne error - shl R0 - cmp R0, 0x68 - jne error - shl R0 - cmp R0, 0xD0 - jne error - shl R0 - cmp R0, 0xA0 - jne error - shl R0 - cmp R0, 0x40 - jne error - shl R0 - cmp R0, 0x80 - jne error - shl R0 - cmp R0, 0x00 - jne error - - mov R1, 0x84 - shr R1 ; SHR test - cmp R1, 0x42 - jne error - shr R1 - cmp R1, 0x21 - jne error - shr R1 - cmp R1, 0x10 - jne error - shr R1 - cmp R1, 0x08 - jne error - shr R1 - cmp R1, 0x04 - jne error - shr R1 - cmp R1, 0x02 - jne error - shr R1 - cmp R1, 0x01 - jne error - shr R1 - cmp R1, 0x00 - jne error - - mov R0, 0xC5 ; ROL test - rol R0 - cmp R0, 0x8B - jne error - rol R0 - cmp R0, 0x17 - jne error - rol R0 - cmp R0, 0x2E - jne error - rol R0 - cmp R0, 0x5C - jne error - rol R0 - cmp R0, 0xB8 - jne error - rol R0 - cmp R0, 0x71 - jne error - rol R0 - cmp R0, 0xE2 - jne error - rol R0 - cmp R0, 0xC5 - jne error - - mov R1, 0x63 ; ROR test - ror R1 - cmp R1, 0xB1 - jne error - ror R1 - cmp R1, 0xD8 - jne error - ror R1 - cmp R1, 0x6C - jne error - ror R1 - cmp R1, 0x36 - jne error - ror R1 - cmp R1, 0x1B - jne error - ror R1 - cmp R1, 0x8D - jne error - ror R1 - cmp R1, 0xC6 - jne error - ror R1 - cmp R1, 0x63 - jne error - - - xor R0, R0 ; ROLC generate - mov R0, 0xC5 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - - cmp R0, 0xC5 ; ROLC verify - jne error - pop R0 - cmp R0, 0x62 - jne error - pop R0 - cmp R0, 0xB1 - jne error - pop R0 - cmp R0, 0x58 - jne error - pop R0 - cmp R0, 0xAC - jne error - pop R0 - cmp R0, 0x56 - jne error - pop R0 - cmp R0, 0x2B - jne error - pop R0 - cmp R0, 0x15 - jne error - pop R0 - cmp R0, 0x8A - jne error - - xor R1, R1 ; RORC generate - mov R1, 0x63 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - - cmp R1, 0x63 ; RORC verify - jne error - pop R1 - cmp R1, 0xC6 - jne error - pop R1 - cmp R1, 0x8C - jne error - pop R1 - cmp R1, 0x19 - jne error - pop R1 - cmp R1, 0x33 - jne error - pop R1 - cmp R1, 0x66 - jne error - pop R1 - cmp R1, 0xCC - jne error - pop R1 - cmp R1, 0x98 - jne error - pop R1 - cmp R1, 0x31 - jne error - - ret - -; ------------------------------------------------- -; AND|R|R -; AND|R|K -; OR|R|R -; OR|R|K -; XOR|R|R -; XOR|R|K -test10: mov R0, 0xA5 ; AND - swap R0 - push R0 - and R0, 0x0F - cmp R0, 0x0A - jne error - pop R0 - push R0 - and R0, 0x0F - cmp R0, 0x0A - pop R1 - jne error - swap R1 - mov R2, 0x0F - and R1, R2 - cmp R1, 0x05 - jne error - - mov R0, 0x05 ; OR - mov R2, 0xA0 - swap R0 - or R2, R0 - cmp R2, 0xF0 - jne error - swap R0 - or R0, 0x50 - cmp R0, 0x55 - jne error - - mov R1, 0x01 - mov R0, 0x01 - xor R0, 0x01 - jnz error - xor R0, R1 - cmp R0, 0x01 - jne error - - ret - -; ------------------------------------------------- -test11: - mov R0, 0x03 - cout (cpu_int_ctrl), R0 - - xin R0, (2) - or R0, 1 - xout (2), R0 - nop - nop - nop - nop - nop - nop - xin R0, (2) - and R0, 0xFE - xout (2), R0 - nop - nop - nop - nop - - cin R0, (cpu_int_ctrl) - or R0, 0x80 - cout (cpu_int_ctrl), R0 - nop - cin R0, (cpu_int_ctrl) - or R0, 0x80 - cout (cpu_int_ctrl), R0 - nop - cin R0, (cpu_int_ctrl) - or R0, 0x80 - cout (cpu_int_ctrl), R0 - nop - cin R0, (cpu_int_ctrl) - or R0, 0x80 - cout (cpu_int_ctrl), R0 - nop - nop - nop - nop - nop - nop - nop - nop - nop - ret - -; ------------------------------------------------- -; Tests clrc, setc -test12: sub R0, 0 - jc error - setc - jnc error - nop - sub R0, 0 - jc error - - mov R0, 0 - clrc - jc error - setc - jnc error - nop - clrc - jc error - ret - -; ------------------------------------------------- -isr: inc R14 - reti - -; ------------------------------------------------- - org 0x3FF -error: jmp error - -; ------------------------------------------------- - org 0x2FF -ok: jmp ok - -; ------------------------------------------------- - \ No newline at end of file diff --git a/lib/CPUs/JCpu/asm/itest.tcl b/lib/CPUs/JCpu/asm/itest.tcl deleted file mode 100644 index 3724ca6..0000000 --- a/lib/CPUs/JCpu/asm/itest.tcl +++ /dev/null @@ -1,3407 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE -# Assembled from itest.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA -# User 1 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"] - -# 0x000: JMP 0x010 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030010" - -# 0x001: JMP 0x288 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00130288" - -# 0x002: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00200000" - -# 0x003: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00300000" - -# 0x004: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00400000" - -# 0x005: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000" - -# 0x006: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00600000" - -# 0x007: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000" - -# 0x008: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00800000" - -# 0x009: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000" - -# 0x00A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A00000" - -# 0x00B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000" - -# 0x00C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C00000" - -# 0x00D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000" - -# 0x00E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E00000" - -# 0x00F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000" - -# 0x010: CALL 0x03B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0103B03B" - -# 0x011: CIN R00, (0x00) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01129000" - -# 0x012: XOUT (0x00), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01224000" - -# 0x013: CALL 0x04C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0133B04C" - -# 0x014: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01403010" - -# 0x015: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01524010" - -# 0x016: CALL 0x08D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0163B08D" - -# 0x017: MOV R00, 0x02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01703020" - -# 0x018: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01824010" - -# 0x019: CALL 0x0C9 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0193B0C9" - -# 0x01A: MOV R00, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A03030" - -# 0x01B: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B24010" - -# 0x01C: CALL 0x0DB -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01C3B0DB" - -# 0x01D: MOV R00, 0x04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01D03040" - -# 0x01E: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01E24010" - -# 0x01F: CALL 0x0ED -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01F3B0ED" - -# 0x020: MOV R00, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02003050" - -# 0x021: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02124010" - -# 0x022: CALL 0x0FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0223B0FF" - -# 0x023: MOV R00, 0x06 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02303060" - -# 0x024: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02424010" - -# 0x025: CALL 0x115 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0253B115" - -# 0x026: MOV R00, 0x07 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02603070" - -# 0x027: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02724010" - -# 0x028: CALL 0x12B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0283B12B" - -# 0x029: MOV R00, 0x08 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02903080" - -# 0x02A: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02A24010" - -# 0x02B: CALL 0x137 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02B3B137" - -# 0x02C: MOV R00, 0x09 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02C03090" - -# 0x02D: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02D24010" - -# 0x02E: CALL 0x15A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02E3B15A" - -# 0x02F: MOV R00, 0x0A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02F030A0" - -# 0x030: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03024010" - -# 0x031: CALL 0x22A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0313B22A" - -# 0x032: MOV R00, 0x0B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "032030B0" - -# 0x033: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03324010" - -# 0x034: CALL 0x24D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0343B24D" - -# 0x035: MOV R00, 0x0C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "035030C0" - -# 0x036: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03624010" - -# 0x037: CALL 0x278 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0373B278" - -# 0x038: MOV R00, 0xFF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03803FF0" - -# 0x039: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03924010" - -# 0x03A: JMP 0x2FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03A302FF" - -# 0x03B: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03B03000" - -# 0x03C: MOV R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03C03001" - -# 0x03D: MOV R02, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03D03002" - -# 0x03E: MOV R03, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03E03003" - -# 0x03F: MOV R04, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03F03004" - -# 0x040: MOV R05, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04003005" - -# 0x041: MOV R06, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04103006" - -# 0x042: MOV R07, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04203007" - -# 0x043: MOV R08, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04303008" - -# 0x044: MOV R09, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04403009" - -# 0x045: MOV R10, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0450300A" - -# 0x046: MOV R11, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0460300B" - -# 0x047: MOV R12, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0470300C" - -# 0x048: MOV R13, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0480300D" - -# 0x049: MOV R14, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0490300E" - -# 0x04A: MOV R15, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04A0300F" - -# 0x04B: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04B3E000" - -# 0x04C: MOV R00, 0x10 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04C03100" - -# 0x04D: CMP R00, 0x10 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04D0F100" - -# 0x04E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04E3A3FF" - -# 0x04F: ADD R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04F11010" - -# 0x050: MOV R01, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05002001" - -# 0x051: CMP R01, 0x11 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0510F111" - -# 0x052: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0523A3FF" - -# 0x053: ADD R01, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05311011" - -# 0x054: MOV R02, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05402012" - -# 0x055: CMP R02, 0x12 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0550F122" - -# 0x056: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0563A3FF" - -# 0x057: ADD R02, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05711012" - -# 0x058: MOV R03, R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05802023" - -# 0x059: CMP R03, 0x13 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0590F133" - -# 0x05A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05A3A3FF" - -# 0x05B: ADD R03, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05B11013" - -# 0x05C: MOV R04, R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05C02034" - -# 0x05D: CMP R04, 0x14 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05D0F144" - -# 0x05E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05E3A3FF" - -# 0x05F: ADD R04, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05F11014" - -# 0x060: MOV R05, R04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06002045" - -# 0x061: CMP R05, 0x15 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0610F155" - -# 0x062: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0623A3FF" - -# 0x063: ADD R05, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06311015" - -# 0x064: MOV R06, R05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06402056" - -# 0x065: CMP R06, 0x16 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0650F166" - -# 0x066: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0663A3FF" - -# 0x067: ADD R06, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06711016" - -# 0x068: MOV R07, R06 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06802067" - -# 0x069: CMP R07, 0x17 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0690F177" - -# 0x06A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06A3A3FF" - -# 0x06B: ADD R07, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06B11017" - -# 0x06C: MOV R08, R07 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06C02078" - -# 0x06D: CMP R08, 0x18 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06D0F188" - -# 0x06E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06E3A3FF" - -# 0x06F: ADD R08, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06F11018" - -# 0x070: MOV R09, R08 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07002089" - -# 0x071: CMP R09, 0x19 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0710F199" - -# 0x072: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0723A3FF" - -# 0x073: ADD R09, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07311019" - -# 0x074: MOV R10, R09 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0740209A" - -# 0x075: CMP R10, 0x1A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0750F1AA" - -# 0x076: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0763A3FF" - -# 0x077: ADD R10, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0771101A" - -# 0x078: MOV R11, R10 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "078020AB" - -# 0x079: CMP R11, 0x1B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0790F1BB" - -# 0x07A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07A3A3FF" - -# 0x07B: ADD R11, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07B1101B" - -# 0x07C: MOV R12, R11 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07C020BC" - -# 0x07D: CMP R12, 0x1C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07D0F1CC" - -# 0x07E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07E3A3FF" - -# 0x07F: ADD R12, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07F1101C" - -# 0x080: MOV R13, R12 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "080020CD" - -# 0x081: CMP R13, 0x1D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0810F1DD" - -# 0x082: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0823A3FF" - -# 0x083: ADD R13, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0831101D" - -# 0x084: MOV R14, R13 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "084020DE" - -# 0x085: CMP R14, 0x1E -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0850F1EE" - -# 0x086: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0863A3FF" - -# 0x087: ADD R14, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0871101E" - -# 0x088: MOV R15, R14 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "088020EF" - -# 0x089: CMP R15, 0x1F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0890F1FF" - -# 0x08A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08A3A3FF" - -# 0x08B: ADD R15, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08B1101F" - -# 0x08C: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08C3E000" - -# 0x08D: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08D03000" - -# 0x08E: TST R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08E0F000" - -# 0x08F: JNZ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08F323FF" - -# 0x090: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "090333FF" - -# 0x091: CMP R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0910F000" - -# 0x092: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0923A3FF" - -# 0x093: JLT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "093353FF" - -# 0x094: JGT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "094363FF" - -# 0x095: JLE 0x097 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09537097" - -# 0x096: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "096303FF" - -# 0x097: JEQ 0x099 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09739099" - -# 0x098: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "098303FF" - -# 0x099: JGE 0x09B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0993809B" - -# 0x09A: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09A303FF" - -# 0x09B: CMP R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09B0F550" - -# 0x09C: JEQ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09C393FF" - -# 0x09D: JLT 0x09F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09D3509F" - -# 0x09E: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09E303FF" - -# 0x09F: JLE 0x0A1 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09F370A1" - -# 0x0A0: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A0303FF" - -# 0x0A1: JGE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A1383FF" - -# 0x0A2: JGT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A2363FF" - -# 0x0A3: MOV R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A303550" - -# 0x0A4: TST R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A40F000" - -# 0x0A5: JZ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A5313FF" - -# 0x0A6: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A6333FF" - -# 0x0A7: CMP R00, 0xAA -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A70FAA0" - -# 0x0A8: JEQ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A8393FF" - -# 0x0A9: JNE 0x0AB -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A93A0AB" - -# 0x0AA: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AA303FF" - -# 0x0AB: JLT 0x0AD -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AB350AD" - -# 0x0AC: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AC303FF" - -# 0x0AD: JLE 0x0AF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AD370AF" - -# 0x0AE: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AE303FF" - -# 0x0AF: JGT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AF363FF" - -# 0x0B0: CMP R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B00F550" - -# 0x0B1: JEQ 0x0B3 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B1390B3" - -# 0x0B2: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B2303FF" - -# 0x0B3: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B33A3FF" - -# 0x0B4: JLT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B4353FF" - -# 0x0B5: JLE 0x0B7 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B5370B7" - -# 0x0B6: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B6303FF" - -# 0x0B7: JGT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B7363FF" - -# 0x0B8: JGE 0x0BA -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B8380BA" - -# 0x0B9: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B9303FF" - -# 0x0BA: MOV R00, 0xAA -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BA03AA0" - -# 0x0BB: TST R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BB0F000" - -# 0x0BC: JZ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BC313FF" - -# 0x0BD: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BD333FF" - -# 0x0BE: CMP R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BE0F550" - -# 0x0BF: JEQ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BF393FF" - -# 0x0C0: JNE 0x0C2 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C03A0C2" - -# 0x0C1: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C1303FF" - -# 0x0C2: JGT 0x0C4 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C2360C4" - -# 0x0C3: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C3303FF" - -# 0x0C4: JGE 0x0C6 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C4380C6" - -# 0x0C5: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C5303FF" - -# 0x0C6: JLT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C6353FF" - -# 0x0C7: JLE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C7373FF" - -# 0x0C8: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C83E000" - -# 0x0C9: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C903000" - -# 0x0CA: MOV R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CA03001" - -# 0x0CB: MOV R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CB02002" - -# 0x0CC: MOV R03, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CC02013" - -# 0x0CD: ADD R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CD11010" - -# 0x0CE: ADDC R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CE13001" - -# 0x0CF: ADD R02, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CF11012" - -# 0x0D0: CMP R02, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D00F002" - -# 0x0D1: JNE 0x0D4 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D13A0D4" - -# 0x0D2: ADD R03, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D211013" - -# 0x0D3: CMP R03, 0x02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D30F023" - -# 0x0D4: JNE 0x0CD -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D43A0CD" - -# 0x0D5: CMP R00, R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D50E020" - -# 0x0D6: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D63A3FF" - -# 0x0D7: CMP R01, R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D70E031" - -# 0x0D8: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D83A3FF" - -# 0x0D9: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D903000" - -# 0x0DA: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DA3E000" - -# 0x0DB: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DB03000" - -# 0x0DC: MOV R01, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DC03031" - -# 0x0DD: MOV R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DD02002" - -# 0x0DE: MOV R03, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DE02013" - -# 0x0DF: SUB R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DF15010" - -# 0x0E0: SUBC R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E017001" - -# 0x0E1: SUB R02, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E115012" - -# 0x0E2: CMP R02, 0xFF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E20FFF2" - -# 0x0E3: JNE 0x0E6 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E33A0E6" - -# 0x0E4: SUB R03, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E415013" - -# 0x0E5: CMP R03, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E50F003" - -# 0x0E6: JNE 0x0DF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E63A0DF" - -# 0x0E7: CMP R00, R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E70E020" - -# 0x0E8: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E83A3FF" - -# 0x0E9: CMP R01, R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E90E031" - -# 0x0EA: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EA3A3FF" - -# 0x0EB: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EB03000" - -# 0x0EC: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EC3E000" - -# 0x0ED: MOV R00, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0ED03030" - -# 0x0EE: MOV R01, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EE03051" - -# 0x0EF: SUB 0x05, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EF2E050" - -# 0x0F0: SUB R01, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F015031" - -# 0x0F1: CMP R00, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F10E010" - -# 0x0F2: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F23A3FF" - -# 0x0F3: MOV R00, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F303030" - -# 0x0F4: MOV R01, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F403051" - -# 0x0F5: SUB R00, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F514010" - -# 0x0F6: SUBC 0x00, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F62F000" - -# 0x0F7: CMP R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F70F010" - -# 0x0F8: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F83A3FF" - -# 0x0F9: ADD R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F911000" - -# 0x0FA: SUBC R01, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FA16001" - -# 0x0FB: CMP R01, 0x04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FB0F041" - -# 0x0FC: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FC3A3FF" - -# 0x0FD: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FD03000" - -# 0x0FE: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FE3E000" - -# 0x0FF: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FF03010" - -# 0x100: MOVC (0x5A), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1000D5A0" - -# 0x101: DEC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10115010" - -# 0x102: MOVC (0x00), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1020D000" - -# 0x103: MOVC R01, (0x5A) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1030A5A1" - -# 0x104: MOVC (R01), 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1040CA51" - -# 0x105: MOVC R00, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10509010" - -# 0x106: MOVC R01, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10609011" - -# 0x107: ADD R01, 0x5A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "107115A1" - -# 0x108: MOVC R00, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10809010" - -# 0x109: MOVC (R00), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1090B000" - -# 0x10A: MOVC R02, (R00) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10A09002" - -# 0x10B: CMP R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10B0E002" - -# 0x10C: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10C3A3FF" - -# 0x10D: MOVC (R01), R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10D0B021" - -# 0x10E: MOVC R02, (R02) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10E09022" - -# 0x10F: CMP R02, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10F0E012" - -# 0x110: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1103A3FF" - -# 0x111: DEC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11115011" - -# 0x112: INC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11211010" - -# 0x113: JNZ 0x109 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11332109" - -# 0x114: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1143E000" - -# 0x115: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11503010" - -# 0x116: MOVX (0x60), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11608600" - -# 0x117: DEC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11715010" - -# 0x118: MOVX (0x06), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11808060" - -# 0x119: MOVX R01, (0x60) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11905601" - -# 0x11A: MOVX (R01), 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11A07A51" - -# 0x11B: MOVX R00, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11B04010" - -# 0x11C: MOVX R01, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11C04011" - -# 0x11D: ADD R01, 0x5A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11D115A1" - -# 0x11E: MOVX R00, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11E04010" - -# 0x11F: MOVX (R00), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11F06000" - -# 0x120: MOVX R02, (R00) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12004002" - -# 0x121: CMP R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1210E002" - -# 0x122: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1223A3FF" - -# 0x123: MOVX (R01), R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12306021" - -# 0x124: MOVX R02, (R02) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12404022" - -# 0x125: CMP R02, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1250E012" - -# 0x126: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1263A3FF" - -# 0x127: DEC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12715011" - -# 0x128: INC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12811010" - -# 0x129: JNZ 0x11F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1293211F" - -# 0x12A: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12A3E000" - -# 0x12B: MOV R00, 0xAA -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12B03AA0" - -# 0x12C: MOV R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12C03001" - -# 0x12D: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12D3C000" - -# 0x12E: INC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12E11010" - -# 0x12F: DEC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12F15011" - -# 0x130: JNZ 0x12D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1303212D" - -# 0x131: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1313D000" - -# 0x132: DEC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13215011" - -# 0x133: JNZ 0x131 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13332131" - -# 0x134: CMP R00, 0xAA -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1340FAA0" - -# 0x135: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1353A3FF" - -# 0x136: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1363E000" - -# 0x137: MOV R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13703550" - -# 0x138: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1383C000" - -# 0x139: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13903000" - -# 0x13A: MOV R01, 0xFF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13A03FF1" - -# 0x13B: CALL 0x151 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13B3B151" - -# 0x13C: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13C3D000" - -# 0x13D: CMP R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13D0F550" - -# 0x13E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13E3A3FF" - -# 0x13F: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13F03010" - -# 0x140: MOV R01, 0x48 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14003481" - -# 0x141: COUT (0x05), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14126050" - -# 0x142: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1423C001" - -# 0x143: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14303000" - -# 0x144: MOV R01, 0x3B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "144033B1" - -# 0x145: COUT (0x05), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14526050" - -# 0x146: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1463C001" - -# 0x147: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1473E000" - -# 0x148: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14803010" - -# 0x149: MOV R01, 0x50 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14903501" - -# 0x14A: COUT (0x05), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14A26050" - -# 0x14B: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14B3C001" - -# 0x14C: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14C03000" - -# 0x14D: MOV R01, 0x3B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14D033B1" - -# 0x14E: COUT (0x05), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14E26050" - -# 0x14F: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14F3C001" - -# 0x150: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1503E000" - -# 0x151: CMP R00, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1510E010" - -# 0x152: JEQ 0x155 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15239155" - -# 0x153: INC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15311010" - -# 0x154: JMP 0x158 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15430158" - -# 0x155: DEC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15515010" - -# 0x156: DEC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15615011" - -# 0x157: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1573E000" - -# 0x158: CALL 0x151 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1583B151" - -# 0x159: JMP 0x155 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15930155" - -# 0x15A: MOV R00, 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15A03A50" - -# 0x15B: MOV R01, 0x5A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15B035A1" - -# 0x15C: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15C2A000" - -# 0x15D: CMP R00, 0x5A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15D0F5A0" - -# 0x15E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15E3A3FF" - -# 0x15F: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15F2A000" - -# 0x160: CMP R00, 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1600FA50" - -# 0x161: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1613A3FF" - -# 0x162: MOV R00, 0xD2 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16203D20" - -# 0x163: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1632A000" - -# 0x164: CMP R00, 0x2D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1640F2D0" - -# 0x165: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1653A3FF" - -# 0x166: SWAP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1662A001" - -# 0x167: CMP R00, 0x2D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1670F2D0" - -# 0x168: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1683A3FF" - -# 0x169: CMP R01, 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1690FA51" - -# 0x16A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16A3A3FF" - -# 0x16B: MOV R00, 0x2D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16B032D0" - -# 0x16C: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16C1E000" - -# 0x16D: CMP R00, 0x5A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16D0F5A0" - -# 0x16E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16E3A3FF" - -# 0x16F: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16F1E000" - -# 0x170: CMP R00, 0xB4 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1700FB40" - -# 0x171: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1713A3FF" - -# 0x172: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1721E000" - -# 0x173: CMP R00, 0x68 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1730F680" - -# 0x174: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1743A3FF" - -# 0x175: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1751E000" - -# 0x176: CMP R00, 0xD0 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1760FD00" - -# 0x177: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1773A3FF" - -# 0x178: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1781E000" - -# 0x179: CMP R00, 0xA0 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1790FA00" - -# 0x17A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17A3A3FF" - -# 0x17B: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17B1E000" - -# 0x17C: CMP R00, 0x40 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17C0F400" - -# 0x17D: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17D3A3FF" - -# 0x17E: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17E1E000" - -# 0x17F: CMP R00, 0x80 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17F0F800" - -# 0x180: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1803A3FF" - -# 0x181: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1811E000" - -# 0x182: CMP R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1820F000" - -# 0x183: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1833A3FF" - -# 0x184: MOV R01, 0x84 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18403841" - -# 0x185: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1851F001" - -# 0x186: CMP R01, 0x42 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1860F421" - -# 0x187: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1873A3FF" - -# 0x188: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1881F001" - -# 0x189: CMP R01, 0x21 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1890F211" - -# 0x18A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18A3A3FF" - -# 0x18B: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18B1F001" - -# 0x18C: CMP R01, 0x10 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18C0F101" - -# 0x18D: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18D3A3FF" - -# 0x18E: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18E1F001" - -# 0x18F: CMP R01, 0x08 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18F0F081" - -# 0x190: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1903A3FF" - -# 0x191: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1911F001" - -# 0x192: CMP R01, 0x04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1920F041" - -# 0x193: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1933A3FF" - -# 0x194: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1941F001" - -# 0x195: CMP R01, 0x02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1950F021" - -# 0x196: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1963A3FF" - -# 0x197: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1971F001" - -# 0x198: CMP R01, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1980F011" - -# 0x199: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1993A3FF" - -# 0x19A: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19A1F001" - -# 0x19B: CMP R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19B0F001" - -# 0x19C: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19C3A3FF" - -# 0x19D: MOV R00, 0xC5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19D03C50" - -# 0x19E: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19E20000" - -# 0x19F: CMP R00, 0x8B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19F0F8B0" - -# 0x1A0: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A03A3FF" - -# 0x1A1: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A120000" - -# 0x1A2: CMP R00, 0x17 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A20F170" - -# 0x1A3: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A33A3FF" - -# 0x1A4: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A420000" - -# 0x1A5: CMP R00, 0x2E -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A50F2E0" - -# 0x1A6: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A63A3FF" - -# 0x1A7: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A720000" - -# 0x1A8: CMP R00, 0x5C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A80F5C0" - -# 0x1A9: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A93A3FF" - -# 0x1AA: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AA20000" - -# 0x1AB: CMP R00, 0xB8 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AB0FB80" - -# 0x1AC: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AC3A3FF" - -# 0x1AD: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AD20000" - -# 0x1AE: CMP R00, 0x71 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AE0F710" - -# 0x1AF: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AF3A3FF" - -# 0x1B0: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B020000" - -# 0x1B1: CMP R00, 0xE2 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B10FE20" - -# 0x1B2: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B23A3FF" - -# 0x1B3: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B320000" - -# 0x1B4: CMP R00, 0xC5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B40FC50" - -# 0x1B5: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B53A3FF" - -# 0x1B6: MOV R01, 0x63 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B603631" - -# 0x1B7: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B721001" - -# 0x1B8: CMP R01, 0xB1 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B80FB11" - -# 0x1B9: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B93A3FF" - -# 0x1BA: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BA21001" - -# 0x1BB: CMP R01, 0xD8 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BB0FD81" - -# 0x1BC: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BC3A3FF" - -# 0x1BD: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BD21001" - -# 0x1BE: CMP R01, 0x6C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BE0F6C1" - -# 0x1BF: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BF3A3FF" - -# 0x1C0: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C021001" - -# 0x1C1: CMP R01, 0x36 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C10F361" - -# 0x1C2: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C23A3FF" - -# 0x1C3: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C321001" - -# 0x1C4: CMP R01, 0x1B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C40F1B1" - -# 0x1C5: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C53A3FF" - -# 0x1C6: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C621001" - -# 0x1C7: CMP R01, 0x8D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C70F8D1" - -# 0x1C8: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C83A3FF" - -# 0x1C9: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C921001" - -# 0x1CA: CMP R01, 0xC6 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CA0FC61" - -# 0x1CB: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CB3A3FF" - -# 0x1CC: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CC21001" - -# 0x1CD: CMP R01, 0x63 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CD0F631" - -# 0x1CE: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CE3A3FF" - -# 0x1CF: XOR R00, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CF1C000" - -# 0x1D0: MOV R00, 0xC5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D003C50" - -# 0x1D1: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D122000" - -# 0x1D2: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D23C000" - -# 0x1D3: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D322000" - -# 0x1D4: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D43C000" - -# 0x1D5: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D522000" - -# 0x1D6: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D63C000" - -# 0x1D7: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D722000" - -# 0x1D8: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D83C000" - -# 0x1D9: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D922000" - -# 0x1DA: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DA3C000" - -# 0x1DB: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DB22000" - -# 0x1DC: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DC3C000" - -# 0x1DD: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DD22000" - -# 0x1DE: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DE3C000" - -# 0x1DF: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DF22000" - -# 0x1E0: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E03C000" - -# 0x1E1: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E122000" - -# 0x1E2: CMP R00, 0xC5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E20FC50" - -# 0x1E3: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E33A3FF" - -# 0x1E4: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E43D000" - -# 0x1E5: CMP R00, 0x62 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E50F620" - -# 0x1E6: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E63A3FF" - -# 0x1E7: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E73D000" - -# 0x1E8: CMP R00, 0xB1 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E80FB10" - -# 0x1E9: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E93A3FF" - -# 0x1EA: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EA3D000" - -# 0x1EB: CMP R00, 0x58 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EB0F580" - -# 0x1EC: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EC3A3FF" - -# 0x1ED: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1ED3D000" - -# 0x1EE: CMP R00, 0xAC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EE0FAC0" - -# 0x1EF: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EF3A3FF" - -# 0x1F0: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F03D000" - -# 0x1F1: CMP R00, 0x56 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F10F560" - -# 0x1F2: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F23A3FF" - -# 0x1F3: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F33D000" - -# 0x1F4: CMP R00, 0x2B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F40F2B0" - -# 0x1F5: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F53A3FF" - -# 0x1F6: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F63D000" - -# 0x1F7: CMP R00, 0x15 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F70F150" - -# 0x1F8: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F83A3FF" - -# 0x1F9: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F93D000" - -# 0x1FA: CMP R00, 0x8A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FA0F8A0" - -# 0x1FB: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FB3A3FF" - -# 0x1FC: XOR R01, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FC1C011" - -# 0x1FD: MOV R01, 0x63 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FD03631" - -# 0x1FE: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FE23001" - -# 0x1FF: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FF3C001" - -# 0x200: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20023001" - -# 0x201: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2013C001" - -# 0x202: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20223001" - -# 0x203: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2033C001" - -# 0x204: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20423001" - -# 0x205: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2053C001" - -# 0x206: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20623001" - -# 0x207: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2073C001" - -# 0x208: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20823001" - -# 0x209: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2093C001" - -# 0x20A: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20A23001" - -# 0x20B: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20B3C001" - -# 0x20C: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20C23001" - -# 0x20D: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20D3C001" - -# 0x20E: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20E23001" - -# 0x20F: CMP R01, 0x63 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20F0F631" - -# 0x210: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2103A3FF" - -# 0x211: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2113D001" - -# 0x212: CMP R01, 0xC6 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2120FC61" - -# 0x213: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2133A3FF" - -# 0x214: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2143D001" - -# 0x215: CMP R01, 0x8C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2150F8C1" - -# 0x216: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2163A3FF" - -# 0x217: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2173D001" - -# 0x218: CMP R01, 0x19 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2180F191" - -# 0x219: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2193A3FF" - -# 0x21A: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21A3D001" - -# 0x21B: CMP R01, 0x33 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21B0F331" - -# 0x21C: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21C3A3FF" - -# 0x21D: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21D3D001" - -# 0x21E: CMP R01, 0x66 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21E0F661" - -# 0x21F: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21F3A3FF" - -# 0x220: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2203D001" - -# 0x221: CMP R01, 0xCC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2210FCC1" - -# 0x222: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2223A3FF" - -# 0x223: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2233D001" - -# 0x224: CMP R01, 0x98 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2240F981" - -# 0x225: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2253A3FF" - -# 0x226: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2263D001" - -# 0x227: CMP R01, 0x31 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2270F311" - -# 0x228: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2283A3FF" - -# 0x229: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2293E000" - -# 0x22A: MOV R00, 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22A03A50" - -# 0x22B: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22B2A000" - -# 0x22C: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22C3C000" - -# 0x22D: AND R00, 0x0F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22D190F0" - -# 0x22E: CMP R00, 0x0A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22E0F0A0" - -# 0x22F: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22F3A3FF" - -# 0x230: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2303D000" - -# 0x231: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2313C000" - -# 0x232: AND R00, 0x0F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "232190F0" - -# 0x233: CMP R00, 0x0A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2330F0A0" - -# 0x234: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2343D001" - -# 0x235: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2353A3FF" - -# 0x236: SWAP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2362A001" - -# 0x237: MOV R02, 0x0F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "237030F2" - -# 0x238: AND R01, R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23818021" - -# 0x239: CMP R01, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2390F051" - -# 0x23A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23A3A3FF" - -# 0x23B: MOV R00, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23B03050" - -# 0x23C: MOV R02, 0xA0 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23C03A02" - -# 0x23D: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23D2A000" - -# 0x23E: OR R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23E1A002" - -# 0x23F: CMP R02, 0xF0 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23F0FF02" - -# 0x240: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2403A3FF" - -# 0x241: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2412A000" - -# 0x242: OR R00, 0x50 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2421B500" - -# 0x243: CMP R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2430F550" - -# 0x244: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2443A3FF" - -# 0x245: MOV R01, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24503011" - -# 0x246: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24603010" - -# 0x247: XOR R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2471D010" - -# 0x248: JNZ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "248323FF" - -# 0x249: XOR R00, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2491C010" - -# 0x24A: CMP R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24A0F010" - -# 0x24B: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24B3A3FF" - -# 0x24C: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24C3E000" - -# 0x24D: MOV R00, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24D03030" - -# 0x24E: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24E26030" - -# 0x24F: XIN R00, (0x02) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24F28020" - -# 0x250: OR R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2501B010" - -# 0x251: XOUT (0x02), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25124020" - -# 0x252: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25200000" - -# 0x253: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25300000" - -# 0x254: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25400000" - -# 0x255: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25500000" - -# 0x256: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25600000" - -# 0x257: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25700000" - -# 0x258: XIN R00, (0x02) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25828020" - -# 0x259: AND R00, 0xFE -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25919FE0" - -# 0x25A: XOUT (0x02), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25A24020" - -# 0x25B: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25B00000" - -# 0x25C: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25C00000" - -# 0x25D: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25D00000" - -# 0x25E: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25E00000" - -# 0x25F: CIN R00, (0x03) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25F29030" - -# 0x260: OR R00, 0x80 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2601B800" - -# 0x261: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26126030" - -# 0x262: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26200000" - -# 0x263: CIN R00, (0x03) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26329030" - -# 0x264: OR R00, 0x80 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2641B800" - -# 0x265: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26526030" - -# 0x266: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26600000" - -# 0x267: CIN R00, (0x03) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26729030" - -# 0x268: OR R00, 0x80 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2681B800" - -# 0x269: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26926030" - -# 0x26A: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26A00000" - -# 0x26B: CIN R00, (0x03) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26B29030" - -# 0x26C: OR R00, 0x80 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26C1B800" - -# 0x26D: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26D26030" - -# 0x26E: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26E00000" - -# 0x26F: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26F00000" - -# 0x270: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27000000" - -# 0x271: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27100000" - -# 0x272: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27200000" - -# 0x273: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27300000" - -# 0x274: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27400000" - -# 0x275: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27500000" - -# 0x276: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27600000" - -# 0x277: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2773E000" - -# 0x278: SUB R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27815000" - -# 0x279: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "279333FF" - -# 0x27A: SETC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27A2B000" - -# 0x27B: JNC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27B343FF" - -# 0x27C: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27C00000" - -# 0x27D: SUB R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27D15000" - -# 0x27E: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27E333FF" - -# 0x27F: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27F03000" - -# 0x280: CLRC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28015000" - -# 0x281: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "281333FF" - -# 0x282: SETC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2822B000" - -# 0x283: JNC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "283343FF" - -# 0x284: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28400000" - -# 0x285: CLRC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28515000" - -# 0x286: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "286333FF" - -# 0x287: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2873E000" - -# 0x288: INC R14 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2881101E" - -# 0x289: RETI -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2893F000" - -# 0x28A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28A00000" - -# 0x28B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28B00000" - -# 0x28C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28C00000" - -# 0x28D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28D00000" - -# 0x28E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28E00000" - -# 0x28F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28F00000" - -# 0x290: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29000000" - -# 0x291: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29100000" - -# 0x292: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29200000" - -# 0x293: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29300000" - -# 0x294: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29400000" - -# 0x295: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29500000" - -# 0x296: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29600000" - -# 0x297: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29700000" - -# 0x298: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29800000" - -# 0x299: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29900000" - -# 0x29A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29A00000" - -# 0x29B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29B00000" - -# 0x29C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29C00000" - -# 0x29D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29D00000" - -# 0x29E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29E00000" - -# 0x29F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29F00000" - -# 0x2A0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A000000" - -# 0x2A1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A100000" - -# 0x2A2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A200000" - -# 0x2A3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A300000" - -# 0x2A4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A400000" - -# 0x2A5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A500000" - -# 0x2A6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A600000" - -# 0x2A7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A700000" - -# 0x2A8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A800000" - -# 0x2A9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A900000" - -# 0x2AA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AA00000" - -# 0x2AB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AB00000" - -# 0x2AC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AC00000" - -# 0x2AD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AD00000" - -# 0x2AE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AE00000" - -# 0x2AF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AF00000" - -# 0x2B0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B000000" - -# 0x2B1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B100000" - -# 0x2B2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B200000" - -# 0x2B3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B300000" - -# 0x2B4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B400000" - -# 0x2B5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B500000" - -# 0x2B6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B600000" - -# 0x2B7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B700000" - -# 0x2B8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B800000" - -# 0x2B9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B900000" - -# 0x2BA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BA00000" - -# 0x2BB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BB00000" - -# 0x2BC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BC00000" - -# 0x2BD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BD00000" - -# 0x2BE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BE00000" - -# 0x2BF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BF00000" - -# 0x2C0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C000000" - -# 0x2C1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C100000" - -# 0x2C2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C200000" - -# 0x2C3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C300000" - -# 0x2C4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C400000" - -# 0x2C5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C500000" - -# 0x2C6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C600000" - -# 0x2C7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C700000" - -# 0x2C8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C800000" - -# 0x2C9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C900000" - -# 0x2CA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CA00000" - -# 0x2CB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CB00000" - -# 0x2CC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CC00000" - -# 0x2CD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CD00000" - -# 0x2CE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CE00000" - -# 0x2CF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CF00000" - -# 0x2D0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D000000" - -# 0x2D1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D100000" - -# 0x2D2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D200000" - -# 0x2D3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D300000" - -# 0x2D4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D400000" - -# 0x2D5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D500000" - -# 0x2D6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D600000" - -# 0x2D7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D700000" - -# 0x2D8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D800000" - -# 0x2D9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D900000" - -# 0x2DA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DA00000" - -# 0x2DB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DB00000" - -# 0x2DC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DC00000" - -# 0x2DD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DD00000" - -# 0x2DE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DE00000" - -# 0x2DF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DF00000" - -# 0x2E0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E000000" - -# 0x2E1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E100000" - -# 0x2E2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E200000" - -# 0x2E3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E300000" - -# 0x2E4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E400000" - -# 0x2E5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E500000" - -# 0x2E6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E600000" - -# 0x2E7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E700000" - -# 0x2E8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E800000" - -# 0x2E9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E900000" - -# 0x2EA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EA00000" - -# 0x2EB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EB00000" - -# 0x2EC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EC00000" - -# 0x2ED: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2ED00000" - -# 0x2EE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EE00000" - -# 0x2EF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EF00000" - -# 0x2F0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F000000" - -# 0x2F1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F100000" - -# 0x2F2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F200000" - -# 0x2F3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F300000" - -# 0x2F4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F400000" - -# 0x2F5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F500000" - -# 0x2F6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F600000" - -# 0x2F7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F700000" - -# 0x2F8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F800000" - -# 0x2F9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F900000" - -# 0x2FA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FA00000" - -# 0x2FB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FB00000" - -# 0x2FC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FC00000" - -# 0x2FD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FD00000" - -# 0x2FE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FE00000" - -# 0x2FF: JMP 0x2FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FF302FF" - -# 0x300: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30000000" - -# 0x301: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30100000" - -# 0x302: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30200000" - -# 0x303: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30300000" - -# 0x304: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30400000" - -# 0x305: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30500000" - -# 0x306: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30600000" - -# 0x307: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30700000" - -# 0x308: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30800000" - -# 0x309: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30900000" - -# 0x30A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30A00000" - -# 0x30B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30B00000" - -# 0x30C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30C00000" - -# 0x30D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30D00000" - -# 0x30E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30E00000" - -# 0x30F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30F00000" - -# 0x310: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31000000" - -# 0x311: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31100000" - -# 0x312: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31200000" - -# 0x313: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31300000" - -# 0x314: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31400000" - -# 0x315: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31500000" - -# 0x316: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31600000" - -# 0x317: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31700000" - -# 0x318: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31800000" - -# 0x319: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31900000" - -# 0x31A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31A00000" - -# 0x31B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31B00000" - -# 0x31C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31C00000" - -# 0x31D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31D00000" - -# 0x31E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31E00000" - -# 0x31F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31F00000" - -# 0x320: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32000000" - -# 0x321: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32100000" - -# 0x322: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32200000" - -# 0x323: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32300000" - -# 0x324: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32400000" - -# 0x325: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32500000" - -# 0x326: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32600000" - -# 0x327: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32700000" - -# 0x328: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32800000" - -# 0x329: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32900000" - -# 0x32A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32A00000" - -# 0x32B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32B00000" - -# 0x32C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32C00000" - -# 0x32D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32D00000" - -# 0x32E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32E00000" - -# 0x32F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32F00000" - -# 0x330: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33000000" - -# 0x331: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33100000" - -# 0x332: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33200000" - -# 0x333: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33300000" - -# 0x334: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33400000" - -# 0x335: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33500000" - -# 0x336: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33600000" - -# 0x337: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33700000" - -# 0x338: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33800000" - -# 0x339: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33900000" - -# 0x33A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33A00000" - -# 0x33B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33B00000" - -# 0x33C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33C00000" - -# 0x33D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33D00000" - -# 0x33E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33E00000" - -# 0x33F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33F00000" - -# 0x340: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34000000" - -# 0x341: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34100000" - -# 0x342: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34200000" - -# 0x343: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34300000" - -# 0x344: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34400000" - -# 0x345: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34500000" - -# 0x346: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34600000" - -# 0x347: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34700000" - -# 0x348: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34800000" - -# 0x349: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34900000" - -# 0x34A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34A00000" - -# 0x34B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34B00000" - -# 0x34C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34C00000" - -# 0x34D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34D00000" - -# 0x34E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34E00000" - -# 0x34F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34F00000" - -# 0x350: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35000000" - -# 0x351: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35100000" - -# 0x352: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35200000" - -# 0x353: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35300000" - -# 0x354: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35400000" - -# 0x355: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35500000" - -# 0x356: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35600000" - -# 0x357: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35700000" - -# 0x358: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35800000" - -# 0x359: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35900000" - -# 0x35A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35A00000" - -# 0x35B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35B00000" - -# 0x35C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35C00000" - -# 0x35D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35D00000" - -# 0x35E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35E00000" - -# 0x35F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35F00000" - -# 0x360: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36000000" - -# 0x361: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36100000" - -# 0x362: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36200000" - -# 0x363: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36300000" - -# 0x364: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36400000" - -# 0x365: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36500000" - -# 0x366: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36600000" - -# 0x367: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36700000" - -# 0x368: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36800000" - -# 0x369: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36900000" - -# 0x36A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36A00000" - -# 0x36B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36B00000" - -# 0x36C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36C00000" - -# 0x36D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36D00000" - -# 0x36E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36E00000" - -# 0x36F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36F00000" - -# 0x370: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37000000" - -# 0x371: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37100000" - -# 0x372: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37200000" - -# 0x373: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37300000" - -# 0x374: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37400000" - -# 0x375: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37500000" - -# 0x376: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37600000" - -# 0x377: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37700000" - -# 0x378: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37800000" - -# 0x379: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37900000" - -# 0x37A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37A00000" - -# 0x37B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37B00000" - -# 0x37C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37C00000" - -# 0x37D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37D00000" - -# 0x37E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37E00000" - -# 0x37F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37F00000" - -# 0x380: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38000000" - -# 0x381: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38100000" - -# 0x382: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38200000" - -# 0x383: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38300000" - -# 0x384: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38400000" - -# 0x385: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38500000" - -# 0x386: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38600000" - -# 0x387: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38700000" - -# 0x388: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38800000" - -# 0x389: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38900000" - -# 0x38A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38A00000" - -# 0x38B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38B00000" - -# 0x38C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38C00000" - -# 0x38D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38D00000" - -# 0x38E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38E00000" - -# 0x38F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38F00000" - -# 0x390: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39000000" - -# 0x391: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39100000" - -# 0x392: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39200000" - -# 0x393: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39300000" - -# 0x394: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39400000" - -# 0x395: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39500000" - -# 0x396: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39600000" - -# 0x397: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39700000" - -# 0x398: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39800000" - -# 0x399: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39900000" - -# 0x39A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39A00000" - -# 0x39B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39B00000" - -# 0x39C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39C00000" - -# 0x39D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39D00000" - -# 0x39E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39E00000" - -# 0x39F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39F00000" - -# 0x3A0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A000000" - -# 0x3A1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A100000" - -# 0x3A2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A200000" - -# 0x3A3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A300000" - -# 0x3A4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A400000" - -# 0x3A5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A500000" - -# 0x3A6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A600000" - -# 0x3A7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A700000" - -# 0x3A8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A800000" - -# 0x3A9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A900000" - -# 0x3AA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AA00000" - -# 0x3AB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AB00000" - -# 0x3AC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AC00000" - -# 0x3AD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AD00000" - -# 0x3AE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AE00000" - -# 0x3AF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AF00000" - -# 0x3B0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B000000" - -# 0x3B1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B100000" - -# 0x3B2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B200000" - -# 0x3B3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B300000" - -# 0x3B4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B400000" - -# 0x3B5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B500000" - -# 0x3B6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B600000" - -# 0x3B7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B700000" - -# 0x3B8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B800000" - -# 0x3B9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B900000" - -# 0x3BA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BA00000" - -# 0x3BB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BB00000" - -# 0x3BC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BC00000" - -# 0x3BD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BD00000" - -# 0x3BE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BE00000" - -# 0x3BF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BF00000" - -# 0x3C0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C000000" - -# 0x3C1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C100000" - -# 0x3C2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C200000" - -# 0x3C3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C300000" - -# 0x3C4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C400000" - -# 0x3C5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C500000" - -# 0x3C6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C600000" - -# 0x3C7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C700000" - -# 0x3C8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C800000" - -# 0x3C9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C900000" - -# 0x3CA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CA00000" - -# 0x3CB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CB00000" - -# 0x3CC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CC00000" - -# 0x3CD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CD00000" - -# 0x3CE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CE00000" - -# 0x3CF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CF00000" - -# 0x3D0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D000000" - -# 0x3D1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D100000" - -# 0x3D2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D200000" - -# 0x3D3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D300000" - -# 0x3D4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D400000" - -# 0x3D5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D500000" - -# 0x3D6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D600000" - -# 0x3D7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D700000" - -# 0x3D8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D800000" - -# 0x3D9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D900000" - -# 0x3DA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DA00000" - -# 0x3DB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DB00000" - -# 0x3DC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DC00000" - -# 0x3DD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DD00000" - -# 0x3DE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DE00000" - -# 0x3DF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DF00000" - -# 0x3E0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E000000" - -# 0x3E1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E100000" - -# 0x3E2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E200000" - -# 0x3E3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E300000" - -# 0x3E4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E400000" - -# 0x3E5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E500000" - -# 0x3E6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E600000" - -# 0x3E7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E700000" - -# 0x3E8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E800000" - -# 0x3E9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E900000" - -# 0x3EA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EA00000" - -# 0x3EB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EB00000" - -# 0x3EC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EC00000" - -# 0x3ED: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3ED00000" - -# 0x3EE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EE00000" - -# 0x3EF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EF00000" - -# 0x3F0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F000000" - -# 0x3F1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F100000" - -# 0x3F2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F200000" - -# 0x3F3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F300000" - -# 0x3F4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F400000" - -# 0x3F5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F500000" - -# 0x3F6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F600000" - -# 0x3F7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F700000" - -# 0x3F8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F800000" - -# 0x3F9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F900000" - -# 0x3FA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FA00000" - -# 0x3FB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FB00000" - -# 0x3FC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FC00000" - -# 0x3FD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FD00000" - -# 0x3FE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FE00000" - -# 0x3FF: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FF303FF" - -# Assembled from itest.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA -# User 2 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"] - -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0048" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0161" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "026C" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "036C" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "046F" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "6F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "7F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "8F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "9F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "A900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AD00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "AF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "B900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BD00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "BF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CD00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DD00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "ED00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FD00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10500" - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/JCpu/asm/make b/lib/CPUs/JCpu/asm/make deleted file mode 100644 index e7f598f..0000000 --- a/lib/CPUs/JCpu/asm/make +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/sh - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: rom-file generation for cpu_core -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -TARGET=$2 -DSTDIR=$1 - -JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools - -$JASM_HOME/jasm.rb $TARGET.jsm - -irom_tcl_snippet="$TARGET.irom.tcl.snip" -irom_vhdl_snippet="$TARGET.irom.vhdl.snip" -irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip" -xrom_tcl_snippet="$TARGET.xrom.tcl.snip" -xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip" -xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip" - -$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl -$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl - -$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl -$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl - -cat $irom_tcl_snippet > $TARGET.tcl.snip.snip -cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip -$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl - -rm -f *.snip diff --git a/lib/CPUs/JCpu/asm/mul8x8.jsm b/lib/CPUs/JCpu/asm/mul8x8.jsm deleted file mode 100644 index c9b6c3b..0000000 --- a/lib/CPUs/JCpu/asm/mul8x8.jsm +++ /dev/null @@ -1,29 +0,0 @@ -; ------------------------------------------------- -; Constants -; ------------------------------------------------- - -; Chip register -include "../../../jasm/cregs.inc.jsm" - -; ------------------------------------------------- -; Program -; ------------------------------------------------- - code - org 0x000 -reset: jmp init - -; ------------------------------------------------- -; Main -; ------------------------------------------------- -init: mov R0, 0x45 - mov R1, 0xF5 - - call mul8x8 -stop: jmp stop - - -; ------------------------------------------------- -include "../../../jasm/mul8x8.inc.jsm" - - - \ No newline at end of file diff --git a/lib/CPUs/JCpu/asm/mul8x8.tcl b/lib/CPUs/JCpu/asm/mul8x8.tcl deleted file mode 100644 index 6bec87e..0000000 --- a/lib/CPUs/JCpu/asm/mul8x8.tcl +++ /dev/null @@ -1,154 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE -# Assembled from mul8x8.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA -# User 1 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"] - -# 0x000: JMP 0x001 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030001" - -# 0x001: MOV R00, 0x45 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00103450" - -# 0x002: MOV R01, 0xF5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203F51" - -# 0x003: CALL 0x005 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0033B005" - -# 0x004: JMP 0x004 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00430004" - -# 0x005: PUSH R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0053C002" - -# 0x006: PUSH R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0063C003" - -# 0x007: PUSH R04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0073C004" - -# 0x008: MOV R04, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00802014" - -# 0x009: MOV R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00903001" - -# 0x00A: MOV R02, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A03002" - -# 0x00B: MOV R03, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B03003" - -# 0x00C: CMP R04, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C0F014" - -# 0x00D: JEQ 0x015 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D39015" - -# 0x00E: SHR R04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E1F004" - -# 0x00F: JNC 0x012 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F34012" - -# 0x010: ADD R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01010002" - -# 0x011: ADDC R03, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01112013" - -# 0x012: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0121E000" - -# 0x013: ROLC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01322001" - -# 0x014: JMP 0x00C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143000C" - -# 0x015: ADD R00, R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01510020" - -# 0x016: ADDC R01, R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01612031" - -# 0x017: POP R04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0173D004" - -# 0x018: POP R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003" - -# 0x019: POP R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0193D002" - -# 0x01A: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A3E000" - -# Assembled from mul8x8.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA -# User 2 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"] - - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/JCpu/asm/reti_issue.jsm b/lib/CPUs/JCpu/asm/reti_issue.jsm deleted file mode 100644 index 78edc49..0000000 --- a/lib/CPUs/JCpu/asm/reti_issue.jsm +++ /dev/null @@ -1,50 +0,0 @@ -; ------------------------------------------------- -; Constants -; ------------------------------------------------- - -; Chip register -cpu_revision: equ 0x00 ; RO -cpu_control: equ 0x01 ; R/W -cpu_status: equ 0x02 ; RO -cpu_int_ctrl: equ 0x03 ; R/W - -; ------------------------------------------------- -; Program -; ------------------------------------------------- - code -reset: jmp init - - org 0x001 -; nop - reti - -; ------------------------------------------------- -; Main -; ------------------------------------------------- -init: mov R0, 0x05 - cout (cpu_int_ctrl), R0 - mov R0, 0x00 -loop: nop - inc R0 - nop - call subr - nop - push R3 - nop - push R2 - nop - push R1 - nop - push R0 - nop - pop R0 - nop - pop R1 - nop - pop R2 - nop - pop R3 - nop - jmp loop - -subr: ret diff --git a/lib/CPUs/JCpu/asm/reti_issue.tcl b/lib/CPUs/JCpu/asm/reti_issue.tcl deleted file mode 100644 index 5da9c56..0000000 --- a/lib/CPUs/JCpu/asm/reti_issue.tcl +++ /dev/null @@ -1,157 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE -# Assembled from reti_issue.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA -# User 1 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"] - -# 0x000: JMP 0x002 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030002" - -# 0x001: RETI -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0013F000" - -# 0x002: MOV R00, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203050" - -# 0x003: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00326030" - -# 0x004: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00403000" - -# 0x005: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000" - -# 0x006: INC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00611010" - -# 0x007: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000" - -# 0x008: CALL 0x01B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0083B01B" - -# 0x009: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000" - -# 0x00A: PUSH R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A3C003" - -# 0x00B: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000" - -# 0x00C: PUSH R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C3C002" - -# 0x00D: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000" - -# 0x00E: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E3C001" - -# 0x00F: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000" - -# 0x010: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0103C000" - -# 0x011: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01100000" - -# 0x012: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0123D000" - -# 0x013: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01300000" - -# 0x014: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143D001" - -# 0x015: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01500000" - -# 0x016: POP R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0163D002" - -# 0x017: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01700000" - -# 0x018: POP R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003" - -# 0x019: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01900000" - -# 0x01A: JMP 0x005 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A30005" - -# 0x01B: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B3E000" - -# Assembled from reti_issue.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA -# User 2 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"] - - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/JCpu/doc/block_diagram.png b/lib/CPUs/JCpu/doc/block_diagram.png deleted file mode 100644 index 14bbb546864ab27695f53a12755b96921ad898a9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8026 zcmZ8m2UJtf(g*)4N>ve2M3LST1qCBj2t~S7fk+gjOMpa$NQnwk1%Z%61VKb8(xeH2 z0Mb(^g3_BxE)i*RQ7{nT!}s3z&Ue0ZX7A4K&g{;5yuXkGqgG`+< zTwH=}e+ze4VBsw;uG0%w;Fs+~#}+300#6RV;0jW@)4sPjl>fWChlo0ae{LYka*y+g zyJ~{AH~jTaBJb0R99vyTr>l$G>f`2fOFqzZ<7^LK3q8~_(R`!92dcAI*7MlixFZ>D zr}yMJTm3thfAaFme&{A_%I6mOFBE5MFT(Z4BN4fH}k3+M4*JN4WIaUIvT zUEP5mxuX7ok|VCO``iKXB5?V*?M&8MuDumtuPcDP`HW&%LP@I1lD3}`hXj6Ap632} z9+vn<{A>)ulba_*%wYYi>SF)vlt8gkhW@NOa!1QZm2{$!qGdLv$Z~+6UdBD-{Sw2; zHAqX$N2CoqeH~a(o~&f*u@6x+L&^>ok3rS{0rjr$W07Zk03&Htb?GaK%0cJs-ZQjU z`AgC<`PxGgCkfMAdv3qm?5CGLNt0{-nu0?N0~c0(Dv{f_PL))tr_vkd+68=9j)fjf zMM8?b>Eu^o=!(ir?vp=0AHl?*@hoE=bNbMH5s1B)QH4U^^COdq%@@6&8yDA6ns_z5 zkTtFyvBf|7Cn)`vEf2ZJBIkJP7=w9)#Qce3c{MkwrAV82$1=6SGRktfL@j`V{qoK4 z-J;#JUUHo6eE2R5mxIm?dMo}-G1d?W$O6PG(45(SZD2AO#OSGs>*-+=cX%q$=sZBn zeHRVitWUb>e=*4;i2g_5UqYmR1j{F~kgx}5;+;^C2iiB8vmX%4Evj6DGPlXB+0VE5 z_^>>WPDpF=4BZz3mF)M81oib48F*Z?6U*0LQ`XVsQFGN{%S*f^+?mkPEO4B%Jnb+t zV+uG{vhMyJ47bk4<`XgIOJvw@XkzQv9!}(I^k{l>32Rmyd^%tMFD2r$wj3F6DMI2o zEs6UK$!5e5uq$6f37!A*C=8X%NA5q@YERE^=6w|E zCTuY~(@u2YNp;syaEdiVQ#7B#ds#aOWo31ra*vAkLX*j7fqe%?XuxbM!CI|NBtJ{q zQFj!p@Ye%kRrKT>w@(p1`Q-K+0OxysCCmVOt2l~&Nmd^C4&buIUIgJhbl(yCsQjo` zqymvb=1n^po5-c2O2+xbvp0@ix{rO!3G)moJt1wK9a;05*1QOLD^=7TID4K#qx9)$SbCPVyagXoP2e*GUsxcBFXO> z?J^hkpW4Hs>)#mubu`HePb=ULy+hNKfDg@&qf4hvt0SMwS~sCM3i34k^chFpiWl%} z?hK0l?JUt(zOHgX%J9$G|MhQ^Go*44ner3f00NM5dhEK97~*}{!Ba?@eYopBO;$q) zTevo>=kVqco)fkDv&X?M@}qq7rLGmBK#WvAxIWE{d^b=n)up)em8FtH|FGLP=()tB zsY1rMs9YaaXRfKp#gjN*37haja;YvJvRaSmaCQrZV(gOrGlqXWt!u3J&q|yZx#u57 zRQ@)q^h&4y;bx25xD?X+U7Bd)=0~yE>^`aTb$KVNu7tmFVE1hq+@Ay$M1xYxuW$qW z5KxPBuYKU-VUk^>&`EY5#{bCjCHh@b`HbD{>i9tZe0S^h$Tol0=0_l7A}zgKVCP8i zJaKr3mFk;lBF*Z8t{z}|LvNeQ;({Uk@vBiE0bMW5+Ty%qfVm8surivhcXA-x#C5h{ zGFxcQaE0guTMp)%1@}~dN)@1-Dn^V2jT{FBp4hsb4kc=I+iuZz5;DX$h`3WP5Q|hG ze5b1H!y*hP4UsfpyUJ_wbbd)hC<))t5KZM=m@`M&M6Ovp$S@i~*EFazNf6I%W_I%^ zBA7}{v4gID?Qc!i#pm455-QET5LX^f8AU{cAIPw7Amx9f=zqiM|7F7C5KKgEd8=F5 zJ(;23%E3QL&9c{v^sb~S;I6wMzQ(Jpk~+qhQE9Tvv$Ix1?Hnp-iotjonLF%Ah&l*t zmAKLI3OQ33cAgL%bBb{7_g|%Gix+xm;#Y zvgQ}2?o7Y=8Jkn(soTLGdlTe`)@mat3Q}9bX%XI3<*<5AwyO856jvcic-rCpOh44L z(&}rw$PDkQWHk~?3g5hRO!e(4)rkk;*7)^rh)Yl2#Y{O*3Qu3I%~x3cLUAyhk0||i z|MBEF?!m$(?fU2=SlRw_U%;kbc4 z73dgywvIb6-%ek=&U@k!vopHgL)1Kto+U%ZcvB1Z(q8OtqfE#W|CO`}vbxL_G;1jU zPUCB*7q`~K2tECe=xwHW5&G=4KlZww z*yUTEY1J1s`A+`XDL77BZKwY}dlhyB;4ebIWGos9z-hv-=?>Q+a#zy3t`HdYl+F}| z97zYr577M)9Q(u`))Mir!0I8}CstK^@gchRqWrL=onU-=RMV;mld6^cssKF84A|5* z&$fq|9+6x2ig~N%3!)<5IP=xZ-VztZ-iz*0ktR4bT(#p9Q#ES`4Qli0?R0Kmbnj9s z*iM&pMt|J-=NxE-`)bGj3{*~5yo;ulwk|z68q+)@&NDzjbY z7Q0LVNve@fjje?(HV%BQE8MGQZxtr>7t4Q>1SaTJnx@=(-l z(&snp+;JXY?mK`h-x-m!>UDXedRPvs2kX+yn0C8FZm5S7Io9FNS)bH5(v!YP9=E#sqPC&zQZIx&_G_P6J zr+M(l?+Rvj9cX3m*?Y*FAW`lHen&(aQS!o|(x9%$3z3tDUamFL-=?K3VZL0pu$ z3h}ch=|H{a+y;^A_4*lnXS~J1CDuq*7AMZ`W!k#a`ypL)lb?d=C1y91fhb%KRBqT_ zb66jXoU|;fEEJb1I8*-9*E2-*SdS_!Tf1ywD&92vxOJ~mLq;5PCD`wK!fDlz1L=t_ z0tCA?h3}!)ES1y>suQ$Kiw~R%;H%WCjT3)sjcS*DI{04ulvJ(W=`rQF85(zGlijIe z9lhgHwcbZf!+awW;?rTrHIToS3?E7lApl-A^XOjdbE(1R)0z9z8HUWpi?_rvlkrJ) zY0|WYavGKqR)xFsj%s1mq@FC!pSpe;-jy_t$LpOk5sZbKFPF#n@|oi^V>OHkPS%Q; zXCeL{g=nINEk>Ya3wrtqu;WaY+R@OWySahNKZN))?|9M+L zz}D4hM6M=4(!T7FGKu^Nn5`%O(>;cPVe2OlnogZ10ja_TjGns~UKDsj0_`y=?ueeb zzna5N$()}(`!@H&YBV^9j+jLJBTp`5M0~dKn9O>BN9Y}0?^hC=pIr-1z-%3w$&+_4 z(E4^szd@@ReWt3P!N{XEhT#qkDTD;he|o%%uwkbhCOtpkJ5kw%gs?`g&}VXK~m zB?%2WA@&v^2kC1mV$9%4B$Iez9N<`d(M;g+!x_#EUY)Cv(b)>2;|7l=8g+7FD9fF^ z?+%_cuyz~nD^W-bgk?2NM6|zA+#5?tlZS5`dtx`|7L<$M1eim*x72ZzoiCjGlSqLi zi>6S_`p~i(z?<`)`KAxbY69#|CMu6mCuhP}Ck{vex8u>^$skO6!kECeF!3^Dzc4UdIxp+nO?4)rViUEJQ)(cd8SW@RIKNIvnl=!Cw&Upzn_SGXo}S-&BjrUl}!8# z7c>(4nH>*rzNb{Y=8WqB6{(3R47a83PvG;RZgqOzdfEupAB9XQrSY5wZa{Ju%9z2# zu1UZQrHF>P7+xQWI^Nj4n$QtYSoz~ZY0T7>Bl64FTTPxLaQe-*cAav)5sXsvKl}UQ zq`<9GawYYf9Mstxo*@a+XDpmM%DU%?+Pe0ULWbl?PXWB%wP$7Fuf>$si58(<*liDf z;HC0TMlB^vuia*9up91d*p((9Lv2pT(P=((T|mUc+e5wMI7`y{+qf|8oScT;YD!c~ zG5lw0am6hS$bFi~lP*=_gibGauQcS4N8-UzL%|hNAAhRme&CfWO5vB|xz54kcb{qN zDU_36$OuGCxKn4Qz@}o?b7|hW&-Ml{i;aaC1^0P(v4hjW=vqXpV^g_h_?JWELoX;Z zhP|N-Tw*ClAF2O-#@R4uM|ujR6mUlEZUd@SPuJ7*CR?jxyfz^gCvNuz6UHA;{wmB3 zilNJkvw9vr{V30KP6{~Wfi2!NY%vr(w`eF*0<`%Ra;~n+C!c4}8v&;egvg1k678lL-%~)0tlM zML24Gqg2#FFo>vWi4-=$vd)v6_9a4`z;|PKTxvT4vUX4P6B7%E+?ag-EYP=R4$R|^ zqAD{~&Vdu2)!n5X0wY5<@UpCi1bSZ|UOGq57@)N8v1M-cSHhogt{UqzV;K=>SiHZ$ z;&Qx8M8DL$clht+LffR4ux5mw)Jc3JXcVh>-0DCuoj27ptW)yv z(&`0M z%;zY~IvR$VbT_!QLRHw2hUWl*Ez5fw-zc5`QV>X;x90jv8~i;!{#@IOzH@OMHK3^J zV&vgEW9jstMehB!0GW2HL-L7akCkvQUL&}BwI~}eNw92N9Wm5q|=noQ;jqZr7i6lRwShr~( zaS>=lkEdw<>B@35{DkTss9=q6fr4tnfv~iLp8`dabU&w*kE#0}c|>7<2&9SNcA_3@596eJ>E5YKE$^qP5p)k7c5?#_D)nYA9SLXNWAEJD z%kJkDa-_pnswcmWW>3^HIVNj-o}(>dyhjj$oy_!cleebz3u~sJ<#o4TtEvZxh(X+r zmX_-9maVrP>h5{<(_qO=TtJnY4>y4QZ2@D=kLRnBH)qcfwdb>D=H~3+f+^CE-OwV( z`F`#h`q&}jrlZ30Fg|EH+Jj+ z9kwWeW5%scIrEwK+K0{A6^QE$=mdT|9K~4l5m3nSWzZ5CIIYZ)M>}(J-kFWTxpq@J zds6OE1dQ=rHv`?iJ7xPQKa$h?R@MSVFz=OLJQE^b0XSBjw_QdG$yvWAluv1`FZM?W z9=mpae1K4UUp{?n4N{iQoovlYp7D0Rk1@`juI=?zE{!E~I=>gu)e_*3Pq?)^T%^PGP66<%q)u7C)zbr7KtIZO>Be zk}Y0rGO30!ZDR9Jq+?r{0A2!@Tbsb7&C56c`39elpYT`cM0aK2l!V^IG@U{Jz3cL* zA)<$DOvjInDP00SxZF0qQT$!Ct1*Dq*(?u^Jt0xzR2F;W3<`5Q;AhC+70V?-_iFU8 zm{MmWQ>wChc;iv`9KCe8@|Q9xg64mbF6@Rr;jG~kae4NRf8jHJ8K($ZhYwJ8!QPX? zRH{^PzSVYIx$+_NgPq_Z@{_!YDtUuuj=i8q`_G$P++B?x(hbXV|Ih~$ui!u*ze2KjB8K1;{S{oi;Dfk&EEQ21(-jq5MzoG6eipMZ zlHUOb+Ay3G@0FdFc~X!_W*H(urI$heyg#RsfoP1QLbIgwG9MPz8~~s&W>p*lX0&}v zq}Nyx=Zc>WVz(0BzRk8Zv_`enZUP0}v-yWry~bZPMN?Z8OWl<`=y^rCp4(qLBOlcO z-bo=}!+*oa6U7^jF2*r*xd&{fho<)hJ>0M53Y(Ib`Z~2j3My zUaNPP>OL&0M-um#c=es7P2U)2)sRxfZqg-QoG>pF7q80a>}Jv`In+2JCD>u-fM*l3 zipeKBBS}r&RU;yjm$xz|)xU9EfHuWp8zJ_Z0XqHtV;V0Jk&WN|ARwSUOz#l_`<7O< zF}^(c0{=S7X8f3WcH~_d_GPyl9vdPJPs@waWF9N$XfinYs!;U7=?nH7zjH=w?_wj# zU@nPs&2~_cdNK-}U(pXpR2&{VR(>%jd4e~oXA#yA!^_vz1b{6oSp%>Awx2}#A(9Dc;PFv&6BVl4!bF-hq-@EGjdx<%t-S9Q#WI&==EH!^mHdsHdUCoqhM&I)S!7g8W)O*(1 zuc|yc*fvWDnL66{><<%ISiIhgv0^GtPg^X6c5kg~dS~de?--MBFSZ;2&7>D)%g;Zl z3jHLZTscsXMN5E|!7bxf^QP%%0!7`L#;JTs9d)q?t?FZD0ufoKEwjgd zrWdrPdJjuHwK06$Sy>y--WhLb9)6#6k?V^hWQ$u8!j!$4k1{U2xzJMKc3bWhQAebe z^A7h?_D$qnTAR2_P(oG4WgqolM=pEqD4P2f&O^TF?PXSKPeDwmZoB%rVzo6m!6_`-SIU52*&3wA1}5oSH_;k_tXgxq9PQg3iZjgH1#pSQm-cWI_r)ZJZ{R8d2jr=hV#6Nlg~mM<4)4$lwFXq_0)v4 zb+G+Yy*!x03eJuTmCBLJv6h3XH!LyDzA#aFvY}wBwg|dwmB>))`bG8h0|pXrcpLGs zH7^s)XT17^*i!~OYOSr#$@0aR=S=7$8NEz>2=0wTBsZI5OJ8wFS3cA12UZm;#FiXj zi-Rz#r1HRXSC!`62fVN$dCyBHFFkp5%y0WNQVFnK-?67%JsQ$Xcz%hz_EA}4FFRV* zexT`Uwi$V?E}74O?~SIiTSj;!jLA!lc#7HQqOd!g0jdHotwEYUpGh!VvHY`iop}3& zhHHLla=pXi&O-b~6|%wgkm?y881?dL74ksN?Zo$&3a%}ARNq0049dL_Q(jJS6&Sm7 zPXjz90hp4M%a~i4G8&+hF1=xXx9>OiU-@#S8{x*ypv9t61a8} z%dlo=Zu^C!;>9!@qdp1~Hj7tw^Hv{>w;y-v9_`tOivLmBa@c>kw0tY7CcJusZ<`05 z(x*^9C4OSXkz6*L=U#cso;n-!9fmed#<$eLVbBhL+1?CKc}vYF}*s3&Y<=eJTIhOZI(}= zWou+u)`v%e-|qUeLxkeB{dDzvR41uwcoLPRcPpLa^U>k$dC$M87J!Lc(^%c>=IHUmGL~>8y=ZR)!Z-G z_6K==`(D3`+b7_eL<-)WcKR_DPz1ESKN$$cx+>_FjMskDm>Dqu9v(BZa`p<$b?B8+ zj#;@nA9PXqo8fOMIL){xw#a#f_&)DcEiGZ4x_ux)?>H?%$kdVl1fVa$i%y9WXZ{7< z7e8OnZ%@w|P=0zVGo8NE)O^`DE2l)fUlHeQp6^T8Jfvz0{l*t-i3#md(Tn$2{WanN zBj26YwZ@jqkF6Lcd*h|S^URVb6+Xl&EEHJAteD(pJ@ZUdIHl@nH5!0YBBu?%{UEcO zyTSMvmMob=Yhgl6lNBwY(ayG8GBT>shUH>3rajoY#EW5lsW^&rQ$)vTPtbZ2AHOJZ z$>#x;r0qvTGHM!2KQ;Ds4`|Kac_ zCh*E{vr@eii4JzvCEo4Asmh-4QDK<$XS_^r$EQYbzpV0upJ<5{2Fx$c$?;D21lV4; zFahN?h%tM{FPUD_047PE7B|wPTI8G{jeGYrM!Pz1mS~fk?(lbb^cRYi?r9{Q)2E^d zvirJ@Z1`5V&>JW6=P%iZDZjLu5jju&TDFgRS@6HW{67}?ENdzlQ?2qHH+gG60x42w R_xBh16(cKnnZb=m{{zZ`SOEY4 diff --git a/lib/CPUs/JCpu/doc/memory_map.png b/lib/CPUs/JCpu/doc/memory_map.png deleted file mode 100644 index 30a22a08a2c6fb8ce339c3d68920919a94977aed..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3545 zcmbtXc{CJm+a61{Y}tvjjK)5iELqDwV~CiEv4$B!Qj%hV<`!re!uUW_mA(7?>+DPoO9pLb3fdyQySeyIAfw5P669ks=|58T|8; zaYzSRztfQ-tPT&ByjTWCJ6egr+|8yAj0g-*U&dX0V+X_XL^rFOWZ* z2koZun&b8Eq-fF#SMpq;J1ROmU2HQA53{Im*^&Z~s^X2%QD1cYD}t3X(Q7zq9Zdos zoE}+0FK1MJDJVCoI){PqSc{AsU1_Lnz;E5^Nq8zcxBE;%4mFiwDgXoG{;fofkl_qm zdsI0k`vxx&h-Pa19fqD4W@ztEgq??UV%+5{wy6R7lHyaMbT~!y?HjypZ z?w#MU`zC_wKvJHk2ki7<{Xb~`4f#Kb(`<3I`Ot~}>LZj3?p@THHFt3R0C^FjX(%4L z<5D8eVNn!@h``Z0CV8QkR-7_uY-KU%Ds}Nt@X7m~IIrBMW`+x`_D6h%eQXG5fyL@G zxnpa=eT`kU0$fwm*B!Cb+XJ3Z(R=EyhY7y-8R@j0n5{B%2DY%&(*jChez(a>_a z4yi=MrL5EB936TVP>9q=KkA?UnF25;9Iwvn8xxHiK4a1}bWoZ+Gd3o=%*_o8+cSF5 zuFeO@c)VXyZp=8}`>!i8XBIB%UQic5#|6>nbe$Aqx7nEkTp;Yvf9$nun0_+*t{}=C z)pb`ze@dLGm}|Z0Tb>@Y;Jz%+U!~AYVq^Y&O=C7W9zWcC?;cxoz#5aBUc>umQPau+ zANY^SWp;&ZS4tmyF>Z^7eW}dQciiLnuC;B?R98pV3BdIpGN!bZ#l(s8=zaw3 z;pyC|*XFq@Goo?@XBdNIihae&ViQ!w5%t}P&5j8qZ^r6=-zAU@tP-ns-G?Zi*B;R| zy4_NY8(_~Z2z%_mw_CJc{5ymrO{HBsQjLOfhcn^%;8R!i+gR`q-((hSMO4>iEQC6& z(;GjizKZcLuDZi9Qzi}wLY*4ud{s^-d~zjoMO&~M!rSE-7iUkD23w!6p8&`Ybk&D4 z5j3{Ez9*+AcsoK)%-gZzRT6e*(^)TEBP^6NgD53yCZ7{N^vWEEzY`e%9p02^z{YqN z3p2!VS@rxVUV(!&j!&;eWtEPBRerwd9;8To*)zOr9ooq0?j)#KS|P z^Ug^6X6Fn>3-Kk+^xRpSV@$m}oE2tOe%gJ@MJ-rgezz1#M;ywiY3J$QPDzqQwzz)^ z0&1$h!Qqip1%ASWB>&T-YGv*3+rzb7sL#D@dQ%j}@J3XGv3m}e#@Xz&dK|rUZhyxV zq#x$fHHr^Z&z!JbM8=-X^&Eoq6k!gr<`p#Je4YnV)t9HdVwA#m_!t>Wdsf%)L#-P) z3S>j@WIsj*{#Kh^Z|d`-BnUoh2{;Jcx?<9oWoUp(S$4ai>*s?Tj&x(`RS1Br2XDyY zC->DX4mFpBlPBly73NH|vn^JV2G_pdK>rj_CWR7A7E+ggEzoyL%XXVSB+jCN{tE2>EBn;{Hgj|^{O)Ca4qj(c`A=Tp|s+60j?L*dK8 z##=>Ph-u=MuYrw^mH>s*#^on3_TtDrkniSxkUZ)Hnyx*_U6@yWuKj%qG05)-nc!UB z#jc#cB7^JmG}bd(rCZ%zh(IGUzb=`IQd%a1un=C8uen7P18af~-j6v8vp+1V`y&iT zH~V#r{5MxXW9zMQsqIpm&hugQdy)ge?jTJf|K+E?J0ojEc12X#)0UsBb?Ue6wH}wc zVC@>bIt=t=%@avY?(naiUZ(c)2AJ9qd5r%f6(`Y_)rX&rBp%=4d~2N84FW2uonaSj zT$#3@0q=lUodPt9!@6a8%(OJMgRHFdJHp(tc2F?{_j~lr%Q}g(TdZ&bKBpwet_B`; z<1`#*laIJ5AF<};TXRaE3ctPYv2e{aNSE+rEloguI7FKoQ2f9958&$(@? za!9X;PxJ5%*x;7Fx#SS7MJjP~WcF;qocWdF?Av;Dl?4n))UDVhN78l4(UPxiPP$dO ze{J_T$PN5|MU(0@qP>@s9uSNx(x-~Oh_Zd4q50z&_99wkpx~+${q`a}77~Vq$aJC09r0krx>> z#p^^N+cA0R!y7n1x#PLv=3JF!gTPO|z7KXz&xH@PVa-j~BQNDzLdfYQ$DUU)(!z;q zFZY&~^WU}G;Fo%8k2_a5Qrd0t&v93!f*c&I!hd`mtMRw8k9}<@Oxdnr76^T|#rz|D z9-%DRvgBc~)3YKV*CHf%D!FG{@T8lAG!^g!1a?DY0mV@LcbBIgh&FAjps6;yr?eX4 z{oss^7b_5Y*>!ZDUvu`o-`?u|mg~_s{1ho8d@M%h43_n-5uu&@m|{&@`k*RLE@lw& z5`l6W$h<*-%=<^qPm+>b zG~`g6;iqwu=W-+Ca~E8wQQm)Z;=Z}%M0FVt@B1nzNC55+DMqWJwEuoAlZ%b$$*=61 z*-5JppKdnxD4NYlqJb;ynkN;GDDj{(z`JIb>aA;pZnexbNbeIXw`NoQHJ`{rb&eK; z#oK1tN`MOtRy8#&tjGQC%{Vk~q>gDSB~3wb+7&CAq*Uz##_yWOmFPTQx&dYR4dW-q z(2c@oKz*4QR%t^k*LmWVo7yq11=*b$@F?xc!G=U3t&#wnFk!Z)ZJ7hthV3o?$6lvw{OQAn(=+b_~*@#EK zjH+P=>kiiMkha3GnZyY;*Bc`R6rb=styjh8frn+TDXp$Ap`(i-{#(U=mFF6`&Rx5a zRI7B2&)uX7&wtsx!-`BT2D0?dK>Zmui9nAbFGpU=VJ=J6b)#)y=tsIEAse5pM^s}U`VrU U+3VN3fBt7MvrDG6##iJ12RA=#&;S4c diff --git a/lib/CPUs/JCpu/gpl-3.0.txt b/lib/CPUs/JCpu/gpl-3.0.txt deleted file mode 100644 index 94a9ed0..0000000 --- a/lib/CPUs/JCpu/gpl-3.0.txt +++ /dev/null @@ -1,674 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 3, 29 June 2007 - - Copyright (C) 2007 Free Software Foundation, Inc. - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The GNU General Public License is a free, copyleft license for -software and other kinds of works. - - The licenses for most software and other practical works are designed -to take away your freedom to share and change the works. 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If your program is a subroutine library, you -may consider it more useful to permit linking proprietary applications with -the library. If this is what you want to do, use the GNU Lesser General -Public License instead of this License. But first, please read -. diff --git a/lib/CPUs/JCpu/sim/tb_cpu.fdo b/lib/CPUs/JCpu/sim/tb_cpu.fdo deleted file mode 100644 index 36b8dc0..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu.fdo +++ /dev/null @@ -1,22 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/cpu_pkg.vhd" -vcom -explicit -93 "../src/core/stack_ctrl.vhd" -vcom -explicit -93 "../src/core/reg_dual.vhd" -vcom -explicit -93 "../src/core/chipram.vhd" -vcom -explicit -93 "../src/core/chipreg.vhd" -vcom -explicit -93 "../src/core/pc.vhd" -vcom -explicit -93 "../src/core/dpath_ctrl.vhd" -vcom -explicit -93 "../src/core/int_ctrl.vhd" -vcom -explicit -93 "../src/core/alu.vhd" -vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/test_irom.vhdl" -vcom -explicit -93 "../src/core/tb_cpu.vhd" -vsim -t 1ps -lib work tb_cpu -do {tb_cpu.wdo} -view wave -view structure -view signals -run 50us diff --git a/lib/CPUs/JCpu/sim/tb_cpu.wdo b/lib/CPUs/JCpu/sim/tb_cpu.wdo deleted file mode 100644 index 2ef036e..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu.wdo +++ /dev/null @@ -1,107 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cpu/rst -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -format Logic /tb_cpu/ce -add wave -noupdate -format Logic /tb_cpu/uut/cpu_active -add wave -noupdate -format Logic /tb_cpu/int_in -add wave -noupdate -format Logic /tb_cpu/int_ack -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr -add wave -noupdate -format Logic /tb_cpu/xmem_we -add wave -noupdate -format Logic /tb_cpu/xmem_re -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram -add wave -noupdate -format Logic /tb_cpu/uut/io_sel -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -divider CPU -add wave -noupdate -format Literal /tb_cpu/reg -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Literal /tb_cpu/uut/cpu_status -add wave -noupdate -format Literal /tb_cpu/uut/status_reg -add wave -noupdate -format Literal /tb_cpu/uut/ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result -add wave -noupdate -format Literal /tb_cpu/uut/alu_status -add wave -noupdate -format Logic /tb_cpu/uut/pc_inc -add wave -noupdate -format Logic /tb_cpu/uut/pc_load -add wave -noupdate -format Logic /tb_cpu/uut/stk_we -add wave -noupdate -format Logic /tb_cpu/uut/cmem_we -add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase -add wave -noupdate -format Logic /tb_cpu/uut/was_pcld -add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc -add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load -add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push -add wave -noupdate -format Logic /tb_cpu/uut/stk_push -add wave -noupdate -format Logic /tb_cpu/uut/stk_pop -add wave -noupdate -format Logic /tb_cpu/uut/status_save -add wave -noupdate -format Logic /tb_cpu/uut/status_restore -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr -add wave -noupdate -divider Stack -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we -add wave -noupdate -divider Chipram -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b -add wave -noupdate -divider Sequencer -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem -add wave -noupdate -divider {Chip register} -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout -add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {136355 ps} 0} -configure wave -namecolwidth 166 -configure wave -valuecolwidth 101 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {93532 ps} {206468 ps} diff --git a/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo b/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo deleted file mode 100644 index dd965ec..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo +++ /dev/null @@ -1,21 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/core/cpu_pkg.vhd" -vcom -explicit -93 "../src/core/stack_ctrl.vhd" -vcom -explicit -93 "../src/core/reg_dual.vhd" -vcom -explicit -93 "../src/core/chipram.vhd" -vcom -explicit -93 "../src/core/pc.vhd" -vcom -explicit -93 "../src/core/dpath_ctrl.vhd" -vcom -explicit -93 "../src/core/int_ctrl.vhd" -vcom -explicit -93 "../src/core/alu.vhd" -vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/cpu_embedded.vhd" -vcom -explicit -93 "../src/tb_cpu_embedded.vhd" -vcom -explicit -93 "../src/test_irom.vhdl" -vsim -t 1ps -lib work tb_cpu_embedded -do {tb_cpu_embedded.wdo} -view wave -view structure -view signals -run 10us diff --git a/lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo b/lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo deleted file mode 100644 index caec2d7..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo +++ /dev/null @@ -1,26 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cpu_embedded/rst -add wave -noupdate -format Logic /tb_cpu_embedded/clk -add wave -noupdate -format Logic /tb_cpu_embedded/ce -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/sram -add wave -noupdate -format Logic /tb_cpu_embedded/int_in -add wave -noupdate -format Logic /tb_cpu_embedded/int_ack -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_data -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {2168142 ps} 0} -configure wave -namecolwidth 143 -configure wave -valuecolwidth 101 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {10500 ns} diff --git a/lib/CPUs/JCpu/sim/tb_cpu_itest.fdo b/lib/CPUs/JCpu/sim/tb_cpu_itest.fdo deleted file mode 100644 index 77ca67d..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_itest.fdo +++ /dev/null @@ -1,22 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/cpu_pkg.vhd" -vcom -explicit -93 "../src/core/stack_ctrl.vhd" -vcom -explicit -93 "../src/core/reg_dual.vhd" -vcom -explicit -93 "../src/core/chipram.vhd" -vcom -explicit -93 "../src/core/chipreg.vhd" -vcom -explicit -93 "../src/core/pc.vhd" -vcom -explicit -93 "../src/core/dpath_ctrl.vhd" -vcom -explicit -93 "../src/core/int_ctrl.vhd" -vcom -explicit -93 "../src/core/alu.vhd" -vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/itest_irom.vhdl" -vcom -explicit -93 "../src/tb_cpu_itest.vhd" -vsim -t 1ps -lib work tb_cpu -do {tb_cpu_itest.wdo} -view wave -view structure -view signals -run 400us diff --git a/lib/CPUs/JCpu/sim/tb_cpu_itest.wdo b/lib/CPUs/JCpu/sim/tb_cpu_itest.wdo deleted file mode 100644 index 747f9d3..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_itest.wdo +++ /dev/null @@ -1,123 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cpu/rst -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -format Logic /tb_cpu/ce -add wave -noupdate -format Logic /tb_cpu/int_in -add wave -noupdate -format Logic /tb_cpu/int_ack -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr -add wave -noupdate -format Logic /tb_cpu/xmem_we -add wave -noupdate -format Logic /tb_cpu/xmem_re -add wave -noupdate -format Logic /tb_cpu/xmem_wait -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/reg -add wave -noupdate -format Logic /tb_cpu/uut/io_sel -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_data -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_addr -add wave -noupdate -divider CPU -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Literal /tb_cpu/uut/cpu_status -add wave -noupdate -format Literal /tb_cpu/uut/status_reg -add wave -noupdate -format Literal /tb_cpu/uut/ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result -add wave -noupdate -format Literal /tb_cpu/uut/alu_status -add wave -noupdate -format Logic /tb_cpu/uut/pc_inc -add wave -noupdate -format Logic /tb_cpu/uut/pc_load -add wave -noupdate -format Logic /tb_cpu/uut/cpu_active -add wave -noupdate -format Logic /tb_cpu/uut/stk_we -add wave -noupdate -format Logic /tb_cpu/uut/cmem_we -add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase -add wave -noupdate -format Logic /tb_cpu/uut/was_pcld -add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc -add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load -add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push -add wave -noupdate -format Logic /tb_cpu/uut/stk_push -add wave -noupdate -format Logic /tb_cpu/uut/stk_pop -add wave -noupdate -format Logic /tb_cpu/uut/status_save -add wave -noupdate -format Logic /tb_cpu/uut/status_restore -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr -add wave -noupdate -divider Stack -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we -add wave -noupdate -divider Chipram -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b -add wave -noupdate -divider Sequencer -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/reg -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem -add wave -noupdate -divider {Chip register} -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout -add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -divider {Interrup Ctrl.} -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in -add wave -noupdate -format Literal -expand /tb_cpu/uut/inst_int_ctrl/ctrl_in -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_sampled -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {53866171 ps} 0} -configure wave -namecolwidth 166 -configure wave -valuecolwidth 101 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {420 us} diff --git a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo deleted file mode 100644 index f83b9b4..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo +++ /dev/null @@ -1,22 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/cpu_pkg.vhd" -vcom -explicit -93 "../src/core/stack_ctrl.vhd" -vcom -explicit -93 "../src/core/reg_dual.vhd" -vcom -explicit -93 "../src/core/chipram.vhd" -vcom -explicit -93 "../src/core/chipreg.vhd" -vcom -explicit -93 "../src/core/pc.vhd" -vcom -explicit -93 "../src/core/dpath_ctrl.vhd" -vcom -explicit -93 "../src/core/int_ctrl.vhd" -vcom -explicit -93 "../src/core/alu.vhd" -vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/irom_reti_issue.vhdl" -vcom -explicit -93 "../src/core/tb_cpu.vhd" -vsim -t 1ps -lib work tb_cpu -do {tb_cpu_reti_issue.wdo} -view wave -view structure -view signals -run 50us diff --git a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo deleted file mode 100644 index 1e67acb..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo +++ /dev/null @@ -1,82 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines -add wave -noupdate -divider {Chip RAM} -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clka -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clkb -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_a -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_b -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b -add wave -noupdate -divider {Interrupt controller} -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/rst -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/clk -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/ctrl_in -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_reg -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request_clr -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/iphase_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_int_ctrl/pc_addr_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state_next -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out -add wave -noupdate -divider PC -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/rst -add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/clk -add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/inc -add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/load -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_next -add wave -noupdate -divider {Stack controller} -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/rst -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/clk -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {8115990 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {8048536 ps} {8340629 ps} diff --git a/lib/CPUs/JCpu/sim/tb_mul8x8.fdo b/lib/CPUs/JCpu/sim/tb_mul8x8.fdo deleted file mode 100644 index f727dff..0000000 --- a/lib/CPUs/JCpu/sim/tb_mul8x8.fdo +++ /dev/null @@ -1,21 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/core/cpu_pkg.vhd" -vcom -explicit -93 "../src/core/stack_ctrl.vhd" -vcom -explicit -93 "../src/core/reg_dual.vhd" -vcom -explicit -93 "../src/core/chipram.vhd" -vcom -explicit -93 "../src/core/pc.vhd" -vcom -explicit -93 "../src/core/dpath_ctrl.vhd" -vcom -explicit -93 "../src/core/int_ctrl.vhd" -vcom -explicit -93 "../src/core/alu.vhd" -vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/cpu_embedded.vhd" -vcom -explicit -93 "../src/tb_cpu_embedded.vhd" -vcom -explicit -93 "../src/mul8x8_irom.vhdl" -vsim -t 1ps -lib work tb_cpu_embedded -do {tb_mul8x8.wdo} -view wave -view structure -view signals -run 10us diff --git a/lib/CPUs/JCpu/sim/tb_mul8x8.wdo b/lib/CPUs/JCpu/sim/tb_mul8x8.wdo deleted file mode 100644 index 355e0a4..0000000 --- a/lib/CPUs/JCpu/sim/tb_mul8x8.wdo +++ /dev/null @@ -1,31 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/rst -add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/clk -add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/ce -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_addr -add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/cpu_status -add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/status_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_result -add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/alu_status -add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/mem -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {529679 ps} 0} -configure wave -namecolwidth 143 -configure wave -valuecolwidth 101 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {9002500 ps} {10052500 ps} diff --git a/lib/CPUs/JCpu/src/core/alu.vhd b/lib/CPUs/JCpu/src/core/alu.vhd deleted file mode 100644 index 19b3478..0000000 --- a/lib/CPUs/JCpu/src/core/alu.vhd +++ /dev/null @@ -1,236 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity alu is - Generic ( - data_width : integer := 8 - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - op_en : in STD_LOGIC; - cy_in : in STD_LOGIC; - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - opsel : in alu_op_t; - res_out : out unsigned (data_width-1 downto 0); - stat_load : in STD_LOGIC; - stat_in : in alu_status_t; - stat_out : out alu_status_t - ); -end alu; - -architecture Behavioral of alu is - - signal sum_cy, sh_cy, sum_cy_in, sh_cy_in, left_shift, add_subn : STD_LOGIC; - signal result, sum_res, lf_res, sh_res, res_reg : unsigned (data_width-1 downto 0); - signal status, stat_reg : alu_status_t; - - -------------------------------------------------------------------------- - function test_zero(arg : unsigned) return STD_LOGIC is - variable result : STD_LOGIC; - begin - result := '0'; - for i in arg'range loop - result := result or To_X01(arg(i)); - end loop; - - return not result; - end test_zero; - --------------------------------------------------------------------------- -begin - --------------------------------------------------------------------------- -proc_logic_func: - process (op1_in, op2_in, opsel) - begin - - case opsel is - when op1_and_op2 => - lf_res <= op1_in and op2_in; - when op1_or_op2 => - lf_res <= op1_in or op2_in; - when op1_xor_op2 => - lf_res <= op1_in xor op2_in; - when others => - lf_res <= (others => '-'); - end case; - - end process; - --------------------------------------------------------------------------- -proc_shift_func: - process (op1_in, left_shift, sh_cy_in) - begin - if left_shift = '1' then - sh_res <= op1_in(op1_in'left-1 downto op1_in'right) & sh_cy_in; - sh_cy <= op1_in(op1_in'left); - else - sh_res <= sh_cy_in & op1_in(op1_in'left downto op1_in'right+1); - sh_cy <= op1_in(op1_in'right); - end if; - - end process; - --------------------------------------------------------------------------- -proc_alu_out: - process(opsel, op1_in, op2_in, res_reg, stat_reg, lf_res, sum_res, sh_res, sum_cy, sh_cy, cy_in) - - begin - - case opsel is - - when op1_add_op2 | op1_sub_op2 | op1_addc_op2 | op1_subc_op2 => - status.zero <= test_zero(res_reg); - status.carry <= sum_cy; - result <= sum_res; - when op1_and_op2 | op1_or_op2 | op1_xor_op2 => - status.zero <= test_zero(res_reg); - status.carry <= stat_reg.carry; - result <= lf_res; - when shl_op | shr_op | rol_op | ror_op | rolc_op | rorc_op => - status.zero <= test_zero(res_reg); - status.carry <= sh_cy; - result <= sh_res; - when swap_op => - result <= op1_in(op1_in'left-op1_in'length/2 downto op1_in'right) & op1_in(op1_in'left downto op1_in'right+op1_in'length/2); - status <= stat_reg; - when others => - result <= op2_in; - status.zero <= stat_reg.zero; - status.carry <= stat_reg.carry or cy_in; - end case; - - end process; - --------------------------------------------------------------------------- -proc_alu_in: - process(opsel, op1_in, stat_reg) - - begin - - add_subn <= '-'; - sum_cy_in <= '-'; - sh_cy_in <= '-'; - left_shift <= '-'; - - case opsel is - - when op1_add_op2 => - sum_cy_in <= '0'; - add_subn <= '1'; - - when op1_sub_op2 => - sum_cy_in <= '0'; - add_subn <= '0'; - - when op1_addc_op2 => - sum_cy_in <= stat_reg.carry; - add_subn <= '1'; - - when op1_subc_op2 => - sum_cy_in <= stat_reg.carry; - add_subn <= '0'; - - when shl_op => - sh_cy_in <= '0'; - left_shift <= '1'; - - when shr_op => - sh_cy_in <= '0'; - left_shift <= '0'; - - when rol_op => - sh_cy_in <= op1_in(op1_in'left); - left_shift <= '1'; - - when ror_op => - sh_cy_in <= op1_in(op1_in'right); - left_shift <= '0'; - - when rolc_op => - sh_cy_in <= stat_reg.carry; - left_shift <= '1'; - - when rorc_op => - sh_cy_in <= stat_reg.carry; - left_shift <= '0'; - - when others => null; - - end case; - - end process; - --------------------------------------------------------------------------- -proc_res_reg: - process(clk, rst, op_en, stat_load, res_reg, stat_reg) - begin - if rst = '1' then - res_reg <= (others => '0'); - stat_reg <= (others => '0'); - elsif rising_edge(clk) then - if op_en = '1' then - res_reg <= result; - stat_reg <= status; - elsif stat_load = '1' then - stat_reg <= stat_in; - end if; - end if; - res_out <= res_reg; - stat_out <= stat_reg; - - end process; - --------------------------------------------------------------------------- -alu_addsub: - process(op1_in, op2_in, sum_cy_in, add_subn) - variable sum : unsigned(data_width+1 downto 0); - variable op1, op2 : unsigned(data_width+1 downto 0); - begin - if add_subn = '1' then - op1 := '0' & op1_in & '1'; - op2 := '0' & op2_in & sum_cy_in; - sum := op1 + op2; - else - op1 := '0' & op1_in & not sum_cy_in; - op2 := '0' & op2_in & '1'; - sum := op1 - op2; - end if; - - -- Form sum + carry - sum_res <= sum(data_width downto 1); - sum_cy <= sum(sum'left); - - end process; - --------------------------------------------------------------------------- -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/chipram.vhd b/lib/CPUs/JCpu/src/core/chipram.vhd deleted file mode 100644 index a954a77..0000000 --- a/lib/CPUs/JCpu/src/core/chipram.vhd +++ /dev/null @@ -1,85 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: On-chip RAM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity chipram is - Generic ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end chipram; - -architecture Behavioral of chipram is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - shared variable RAM : RAMtype; - -begin - -process (clka) -begin -if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) := din_a; - end if; - dout_a <= RAM(to_integer(addr_a)); - end if; -end if; -end process; - -process (clkb) -begin -if clkb'event and clkb = '1' then - if en_b = '1' then - if we_b = '1' then - RAM(to_integer(addr_b)) := din_b; - end if; - dout_b <= RAM(to_integer(addr_b)); - end if; -end if; -end process; - - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/chipreg.vhd b/lib/CPUs/JCpu/src/core/chipreg.vhd deleted file mode 100644 index 483c627..0000000 --- a/lib/CPUs/JCpu/src/core/chipreg.vhd +++ /dev/null @@ -1,123 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: On-Chip registers --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity chipreg is - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - addr : in dmem_addr_t; - din : in dmem_data_t; - dout : out dmem_data_t; - ctrl_in : in creg_ctrl_in_t; - ctrl_out : out creg_ctrl_out_t - ); -end chipreg; - -architecture Behavioral of chipreg is - - signal reg_page_sel : page_sel_t; - signal reg_int_ctrl : int_ctrl_in_t; - signal reg_stk_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - signal reg_cmem_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - -begin - -proc_assign_ctrl_lines: - process (clk) - begin - if rising_edge(clk) then - ctrl_out.page_sel <= reg_page_sel; - ctrl_out.int_ctrl <= reg_int_ctrl; - ctrl_out.stk_high <= reg_stk_high; - ctrl_out.cmem_high <= reg_cmem_high; - end if; - end process; - -proc_reg_write: - process (rst, clk) - begin - if rst = '1' then - reg_stk_high <= (others => '0'); - reg_cmem_high <= (others => '0'); - reg_page_sel <= (others => '0'); - reg_int_ctrl.enable <= '0'; - reg_int_ctrl.polarity <= '1'; - reg_int_ctrl.edge_sens <= '1'; - elsif rising_edge(clk) then - reg_int_ctrl.request <= '0'; - if we = '1' then - case addr is - when X"01" => - reg_page_sel(page_sel_t'range) <= din(page_sel_t'range); - when X"03" => - reg_int_ctrl.enable <= din(0); - reg_int_ctrl.polarity <= din(1); - reg_int_ctrl.edge_sens <= din(2); - reg_int_ctrl.request <= din(7); - when X"04" => - reg_cmem_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - when X"05" => - reg_stk_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - when others => null; - end case; - end if; - end if; - end process; - -proc_reg_read: - process (clk) - begin - if rising_edge(clk) then - case addr is - when X"00" => -- Revison - dout <= to_unsigned(REVISION, dmem_data_t'length); - when X"01" => -- Control 0 - dout <= (7 downto page_sel_t'length => '0') & reg_page_sel; - when X"02" => -- CPU status - dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero; - when X"03" => -- Interrupt control - dout <= "00000" & reg_int_ctrl.edge_sens & reg_int_ctrl.polarity & reg_int_ctrl.enable; - when X"04" => -- Upper stack bits out - dout <= "0000" & reg_cmem_high; - when X"05" => -- Upper cmem bits out - dout <= "0000" & reg_stk_high; - when others => - if addr(0) = '0' then - dout <= X"DE"; - else - dout <= X"AD"; - end if; - end case; - - end if; - end process; - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/cpu.vhd b/lib/CPUs/JCpu/src/core/cpu.vhd deleted file mode 100644 index 1184806..0000000 --- a/lib/CPUs/JCpu/src/core/cpu.vhd +++ /dev/null @@ -1,566 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: JCPU top file --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity cpu is - Generic ( - use_instr_register : boolean := false; - use_ctrl_rom : boolean := true - - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_wait : in STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0); - instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0); - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0); - io_sel : out std_logic - ); -end cpu; - -architecture rtl of cpu is - - COMPONENT stack_ctrl - GENERIC ( - addr_width : integer - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - push : in STD_LOGIC; - pop : in STD_LOGIC; - din : in inst_addr_t; - dout : out inst_addr_t; - mem_we : out STD_LOGIC; - ptr_out : out unsigned (addr_width-1 downto 0) - ); - END COMPONENT; - - COMPONENT pc - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - inc : in STD_LOGIC; - load : in STD_LOGIC; - pc_in : in inst_addr_t; - pc_out : out inst_addr_t; - pc_next : out inst_addr_t - ); - END COMPONENT; - - COMPONENT dpath_ctrl - GENERIC ( - use_rom : boolean - ); - Port ( - inst_in : in inst_t; - iphase_in : in iphase_t; - status_in : in cpu_status_t; - ctrl_out : out dpath_ctrl_out_t; - idout : out inst_addr_t; - ddout : out dmem_data_t - ); - END COMPONENT; - - COMPONENT int_ctrl - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ctrl_in : in int_ctrl_in_t; - int_in : in STD_LOGIC; - int_exit : in STD_LOGIC; - iphase_in : in iphase_t; - int_ack_out : out STD_LOGIC; - stat_save_out : out STD_LOGIC; - stat_rest_out : out STD_LOGIC; - pc_addr_out : out inst_addr_t; - pc_load_out : out STD_LOGIC; - stk_push_out : out STD_LOGIC; - stk_pop_out : out STD_LOGIC - ); - END COMPONENT; - - COMPONENT reg_dual - GENERIC ( - addr_width : integer; - data_width : integer - ); - Port ( - clk : in STD_LOGIC; - we_a : in STD_LOGIC; - ptr_a : in reg_ptr_t; - ptr_b : in reg_ptr_t; - din_a : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - - COMPONENT chipram - GENERIC ( - addr_width : integer; - data_width : integer - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - - COMPONENT chipreg - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - addr : in dmem_addr_t; - din : in dmem_data_t; - dout : out dmem_data_t; - ctrl_in : in creg_ctrl_in_t; - ctrl_out : out creg_ctrl_out_t - ); - END COMPONENT; - - COMPONENT alu - GENERIC ( - data_width : integer := 8 - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - op_en : in STD_LOGIC; - cy_in : in STD_LOGIC; - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - opsel : in alu_op_t; - res_out : out unsigned (data_width-1 downto 0); - stat_load : in STD_LOGIC; - stat_in : in alu_status_t; - stat_out : out alu_status_t - ); - END COMPONENT; - - signal cpu_status, status_reg : cpu_status_t; -- := cpu_status_t(others => '0'); - signal ctrl : dpath_ctrl_out_t; - signal stk_out : inst_addr_t; - signal stk_in : inst_addr_t; - signal stk_reg : inst_addr_t; - signal pc_in, pc_out, pc_next, idata, int_pc_addr : inst_addr_t; - signal iphase : iphase_t; - signal const_data, reg_a_dout, reg_b_dout : dmem_data_t; - signal reg_din : dmem_data_t; - signal alu_op1, alu_op2, alu_result : dmem_data_t; - signal alu_status : alu_status_t; - signal pc_inc, pc_load, cpu_active, stk_we, cmem_we, creg_we : STD_LOGIC; - signal ctrl_inst : inst_t; - signal ctrl_iphase : iphase_t; - signal was_pcld, was_pop2pc, int_pc_load, int_stk_push, int_stk_pop, stk_push, stk_pop : STD_LOGIC; - signal status_save, status_restore : STD_LOGIC; - signal creg_dout : dmem_data_t; - signal cmem_din, cmem_dout : inst_addr_t; - signal stk_addr, cmem_addr : unsigned(CHIPRAM_SIZE_BITS-1 downto 0); - signal stk_ptr : unsigned(STACK_SIZE_BITS-1 downto 0); - signal creg_ctrl_out : creg_ctrl_out_t; - signal creg_ctrl_in : creg_ctrl_in_t; - signal irq_out : std_logic; - signal xio_sel, cio_sel : std_logic; - signal mem_data : dmem_data_t; - signal mem_addr : dmem_data_t; - -begin - io_sel <= xio_sel; - instr_addr <= pc_out; - pc_inc <= cpu_active and ctrl.lines.pc_inc; - stk_addr <= '0' & stk_ptr; - cpu_status.alu <= alu_status; - cpu_status.xmem_wait <= xmem_wait; - creg_ctrl_in.alu <= alu_status; - - xmem_dout <= mem_data; - xmem_addr <= mem_addr; - cmem_din <= creg_ctrl_out.cmem_high & mem_data; - cmem_addr <= '1' & creg_ctrl_out.page_sel & mem_addr(MIN(cmem_addr'length-creg_ctrl_out.page_sel'length-1, mem_addr'length)-1 downto 0); - --------------------------------------------------------------------- -mem_ctrl_lines: - process(ctrl.lines) - begin - xio_sel <= '0'; - xmem_re <= '0'; - xmem_we <= '0'; - cio_sel <= '0'; - cmem_we <= '0'; - creg_we <= '0'; - - case ctrl.lines.mem_access is - when xmem_access => - xmem_re <= ctrl.lines.mem_read; - xmem_we <= ctrl.lines.mem_write; - when xio_access => - xio_sel <= '1'; - xmem_re <= ctrl.lines.mem_read; - xmem_we <= ctrl.lines.mem_write; - when cmem_access => - cmem_we <= ctrl.lines.mem_write; - when cio_access => - cio_sel <= '1'; - creg_we <= ctrl.lines.mem_write; - when others => null; - end case; - end process; - -iphase_counter: - process(rst, clk, ce) - variable pos : integer; - begin - if rst = '1' then - iphase <= iphase_t'low; - cpu_active <= '0'; - elsif rising_edge(clk) then - cpu_active <= '0'; - if ce = '1' then - cpu_active <= '1'; - if iphase = iphase_t'high then - iphase <= iphase_t'low; - else - iphase <= iphase + 1; - end if; - end if; - end if; - end process; - -gen_instr_reg: -if use_instr_register = true generate - -instr_reg: - process (rst, clk, ce) - begin - if rst = '1' then - ctrl_inst <= (others => '0'); - ctrl_iphase <= 0; - elsif rising_edge(clk) and ce = '1' then - ctrl_inst <= instr_din; - ctrl_iphase <= iphase; - end if; - end process; - -end generate; - -gen_instr_direct: -if use_instr_register = false generate - - ctrl_inst <= instr_din; - ctrl_iphase <= iphase; - -end generate; - -status_register: - process(clk, status_save) - begin - if rising_edge(clk) and status_save = '1' then - status_reg.alu <= alu_status; - end if; - end process; - -pc_pushpop: - process(ctrl.lines, int_pc_load, int_stk_push, int_stk_pop, was_pop2pc) - begin - pc_load <= ctrl.lines.pc_load or int_pc_load; - stk_push <= (ctrl.lines.stk_pushd or ctrl.lines.stk_push) or (int_stk_push and not was_pop2pc); - stk_pop <= ctrl.lines.stk_popd or int_stk_pop or (ctrl.lines.stk_pop and not int_pc_load); - end process; - -lines_delay: - process(clk) - begin - if rising_edge(clk) then - was_pcld <= ctrl.lines.pc_load; - was_pop2pc <= ctrl.lines.stk_pop and ctrl.lines.pc_load; - end if; - end process; - -stk_mux: - process(ctrl.lines, was_pcld, int_stk_push, pc_next, idata, reg_a_dout, creg_ctrl_out) - begin - if was_pcld = '1' and int_stk_push = '1' then - stk_in <= idata; - elsif ctrl.lines.stk_pushd = '1' then - stk_in <= creg_ctrl_out.stk_high & reg_a_dout; - else - stk_in <= pc_next; - end if; - - end process; - -pc_mux: - process(ctrl.lines, int_pc_load, int_stk_pop, idata, int_pc_addr, stk_out) - begin - - pc_in <= stk_out; - if int_pc_load = '1' then - if int_stk_pop = '0' then - pc_in <= int_pc_addr; - end if; - elsif ctrl.lines.pc_load = '1' then - if ctrl.lines.stk_pop = '0' then - pc_in <= idata; - end if; - end if; - - end process; - -mem_data_mux: - process(ctrl.lines.ddata_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out) - begin - case ctrl.lines.ddata_src_sel is - when reg_a => - mem_data <= reg_a_dout; - when reg_b => - mem_data <= reg_b_dout; - when const => - mem_data <= const_data; - when others => - mem_data <= const_data; - end case; - - end process; - -mem_addr_mux: - process(ctrl.lines.daddr_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out.page_sel) - begin - case ctrl.lines.daddr_src_sel is - when reg_a => - mem_addr <= reg_a_dout; - when reg_b => - mem_addr <= reg_b_dout; - when const => - mem_addr <= const_data; - when others => - mem_addr <= const_data; - end case; - - end process; - -reg_in_mux: - process(ctrl.lines.reg_src_sel, cio_sel, xmem_din, alu_result, stk_out, cmem_dout, creg_dout) - variable data : dmem_data_t; - begin - case ctrl.lines.reg_src_sel is - when xmem_src => - data := xmem_din; - when cmem_src => - if cio_sel = '0' then - data := cmem_dout(dmem_data_t'range); - else - data := creg_dout(dmem_data_t'range); - end if; - when stk_src => - data := stk_out(dmem_data_t'range); - when others => - data := alu_result; - end case; - - reg_din <= data; - - end process; - -alu_op1_mux: - process(ctrl.lines.alu_op1_src_sel, reg_a_dout, reg_b_dout, const_data) - variable data : dmem_data_t; - begin - case ctrl.lines.alu_op1_src_sel is - when reg_a => - data := reg_a_dout; - when reg_b => - data := reg_b_dout; - when others => - data := const_data; - end case; - - alu_op1 <= data; - - end process; - -alu_op2_mux: - process(ctrl.lines.alu_op2_src_sel, reg_a_dout, reg_b_dout, const_data) - variable data : dmem_data_t; - begin - case ctrl.lines.alu_op2_src_sel is - when reg_a => - data := reg_a_dout; - when reg_b => - data := reg_b_dout; - when others => - data := const_data; - end case; - - alu_op2 <= data; - - end process; - --------------------------------------------------------------------- - inst_stack_ctrl: stack_ctrl - GENERIC MAP ( - addr_width => STACK_SIZE_BITS - ) - PORT MAP( - rst => rst, - clk => clk, - push => stk_push, - pop => stk_pop, - dout => stk_reg, - din => stk_in, - ptr_out => stk_ptr, - mem_we => stk_we - ); - - inst_pc: pc - PORT MAP( - rst => rst, - clk => clk, - inc => pc_inc, - load => pc_load, - pc_in => pc_in, - pc_out => pc_out, - pc_next => pc_next - ); - - inst_dpath_ctrl: dpath_ctrl - GENERIC MAP ( - use_rom => use_ctrl_rom - ) - PORT MAP( - inst_in => ctrl_inst, - iphase_in => ctrl_iphase, - status_in => cpu_status, - ctrl_out => ctrl, - ddout => const_data, - idout => idata - ); - - inst_int_ctrl: int_ctrl - PORT MAP( - rst => rst, - clk => clk, - ctrl_in => creg_ctrl_out.int_ctrl, - int_in => int_in, - int_ack_out => int_ack, - int_exit => ctrl.lines.int_exit, - iphase_in => ctrl_iphase, - stat_save_out => status_save, - stat_rest_out => status_restore, - pc_addr_out => int_pc_addr, - pc_load_out => int_pc_load, - stk_push_out => int_stk_push, - stk_pop_out => int_stk_pop - - ); - - inst_reg_ab: reg_dual - GENERIC MAP ( - addr_width => REG_SIZE_BITS, - data_width => DMEM_DATA_WIDTH - ) - PORT MAP( - clk => clk, - we_a => ctrl.lines.reg_we, - ptr_a => ctrl.reg_a_ptr, - ptr_b => ctrl.reg_b_ptr, - din_a => reg_din, - dout_a => reg_a_dout, - dout_b => reg_b_dout - ); - - inst_chipram: chipram - GENERIC MAP ( - addr_width => CHIPRAM_SIZE_BITS, - data_width => IMEM_ADDR_WIDTH - ) - PORT MAP( - clka => clk, - clkb => clk, - en_a => cpu_active, - en_b => cpu_active, - we_a => stk_we, - we_b => cmem_we, - addr_a => stk_addr, - addr_b => cmem_addr, - din_a => stk_reg, - din_b => cmem_din, - dout_a => stk_out, - dout_b => cmem_dout - ); - - inst_chipreg: chipreg - PORT MAP( - rst => rst, - clk => clk, - we => creg_we, - addr => mem_addr, - din => mem_data, - dout => creg_dout, - ctrl_in => creg_ctrl_in, - ctrl_out => creg_ctrl_out - ); - - inst_alu: alu - GENERIC MAP ( - data_width => DMEM_DATA_WIDTH - ) - PORT MAP( - rst => rst, - clk => clk, - op_en => ctrl.lines.alu_load, - cy_in => ctrl.lines.alu_cy_in, - op1_in => alu_op1, - op2_in => alu_op2, - opsel => ctrl.lines.alu_opsel, - res_out => alu_result, - stat_load => status_restore, - stat_in => status_reg.alu, - stat_out => alu_status - ); - -end rtl; diff --git a/lib/CPUs/JCpu/src/core/cpu_pkg.vhd b/lib/CPUs/JCpu/src/core/cpu_pkg.vhd deleted file mode 100644 index 4c4d56c..0000000 --- a/lib/CPUs/JCpu/src/core/cpu_pkg.vhd +++ /dev/null @@ -1,904 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Types, constants and functions for JCPU --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - - -package cpu_pkg is - - -- Revision of the CPU - constant REVISION : integer := 4; - - -- Chipram depth (valid values 9..floor(log2(BlockRamBytes))) - constant CHIPRAM_SIZE_BITS : integer := 10; - - -- Chipregister file depth - constant CHIPREG_SIZE_BITS : integer := 8; - - -- Number of registers (16 registers fixed) - constant REG_SIZE_BITS : integer := 4; - - -- Instruction memory - constant IMEM_ADDR_WIDTH : integer := 12; - - -- Data memory - constant DMEM_DATA_WIDTH : integer := 8; - constant DMEM_ADDR_WIDTH : integer := 8; - - -- Instruction format - constant INST_OPCODE_WIDTH : integer := 6; - constant IMEM_DATA_WIDTH : integer := INST_OPCODE_WIDTH + DMEM_DATA_WIDTH + REG_SIZE_BITS; - - -- Microcode ROM - constant MUCODE_ADDR_WIDTH : integer := 10; - - -- Stack depth (uses lower half of CHIPRAM) - constant STACK_SIZE_BITS : integer := CHIPRAM_SIZE_BITS-1; - - --Types - subtype iphase_t is integer range 0 to 1; - type mem_access_t is (cmem_access, xmem_access, cio_access, xio_access); - type reg_src_t is (alu_src, stk_src, cmem_src, xmem_src); - type alu_src_t is (reg_a, reg_b, const); - type ddata_src_t is (reg_a, reg_b, const); - type daddr_src_t is (reg_a, reg_b, const); - subtype instr_name_t is string(1 to 12); - type instr_name_array_t is array (0 to 63) of instr_name_t; - subtype opcode_t is unsigned (INST_OPCODE_WIDTH-1 downto 0); - subtype inst_data_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0); - subtype inst_addr_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0); - subtype inst_t is unsigned (IMEM_DATA_WIDTH-1 downto 0); - subtype dmem_data_t is unsigned (DMEM_DATA_WIDTH-1 downto 0); - subtype dmem_addr_t is unsigned (DMEM_DATA_WIDTH-1 downto 0); - subtype reg_ptr_t is unsigned (3 downto 0); - type dmem_array_t is array (natural range <>) of dmem_data_t; - type instr_addr_array is array (integer range <>) of inst_addr_t; - subtype page_sel_t is unsigned (CHIPRAM_SIZE_BITS-DMEM_DATA_WIDTH-2 downto 0); - - type alu_op_t is - ( - pass_op2, - op1_add_op2, - op1_sub_op2, - op1_addc_op2, - op1_subc_op2, - op1_and_op2, - op1_or_op2, - op1_xor_op2, - swap_op, - shl_op, - shr_op, - rol_op, - ror_op, - rolc_op, - rorc_op - ); - - type alu_status_t is record - zero : STD_LOGIC; - carry : STD_LOGIC; - end record; - - type cpu_status_t is record - alu : alu_status_t; - xmem_wait : STD_LOGIC; - end record; - - type ctrl_lines_t is record - reg_we : STD_LOGIC; - reg_src_sel : reg_src_t; - alu_op1_src_sel : alu_src_t; - alu_op2_src_sel : alu_src_t; - alu_opsel : alu_op_t; - alu_load : STD_LOGIC; - alu_cy_in : STD_LOGIC; - ddata_src_sel : ddata_src_t; - daddr_src_sel : daddr_src_t; - pc_load : STD_LOGIC; - pc_inc : STD_LOGIC; - stk_push : STD_LOGIC; - stk_pop : STD_LOGIC; - stk_pushd : STD_LOGIC; - stk_popd : STD_LOGIC; - mem_access : mem_access_t; - mem_read : STD_LOGIC; - mem_write : STD_LOGIC; - int_exit : STD_LOGIC; - end record; - - type dpath_ctrl_out_t is record - lines : ctrl_lines_t; - reg_a_ptr : reg_ptr_t; - reg_b_ptr : reg_ptr_t; - end record; - - type int_ctrl_in_t is record - enable : std_logic; - polarity : std_logic; - edge_sens : std_logic; - request : std_logic; - end record; - - type creg_ctrl_out_t is record - page_sel : page_sel_t; - int_ctrl : int_ctrl_in_t; - stk_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - cmem_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - end record; - - type creg_ctrl_in_t is record - alu : alu_status_t; - end record; - - - type murom_t is array (0 to integer(2**MUCODE_ADDR_WIDTH)-1) of ctrl_lines_t; - - constant instr_name_array : instr_name_array_t := - ( - "NOP ", -- 00 - "HALT ", -- 01 - "MOV|R|R ", -- 02 - "MOV|R|K ", -- 03 - "MOVX|R|Ri ", -- 04 - "MOVX|R|Ki ", -- 05 - "MOVX|Ri|R ", -- 06 - "MOVX|Ri|K ", -- 07 - "MOVX|Ki|R ", -- 08 - "MOVC|R|Ri ", -- 09 - "MOVC|R|Ki ", -- 0A - "MOVC|Ri|R ", -- 0B - "MOVC|Ri|K ", -- 0C - "MOVC|Ki|R ", -- 0D - "CMP|R|R ", -- 0E - "CMP|R|K ", -- 0F - "ADD|R|R ", -- 10 - "ADD|R|K ", -- 11 - "ADDC|R|R ", -- 12 - "ADDC|R|K ", -- 13 - "SUB|R|R ", -- 14 - "SUB|R|K ", -- 15 - "SUBC|R|R ", -- 16 - "SUBC|R|K ", -- 17 - "AND|R|R ", -- 18 - "AND|R|K ", -- 19 - "OR|R|R ", -- 1A - "OR|R|K ", -- 1B - "XOR|R|R ", -- 1C - "XOR|R|K ", -- 1D - "SHL|R ", -- 1E - "SHR|R ", -- 1F - "ROL|R ", -- 20 - "ROR|R ", -- 21 - "ROLC|R ", -- 22 - "RORC|R ", -- 23 - "XOUT|Ki|R ", -- 24 - "XOUT|Ri|K ", -- 25 - "COUT|Ki|R ", -- 26 - "COUT|Ri|K ", -- 27 - "XIN|R|Ki ", -- 28 - "CIN|R|Ki ", -- 29 - "SWAP|R ", -- 2A - "SETC ", -- 2B - "UNDEF ", -- 2C - "UNDEF ", -- 2D - "SUB|K|R ", -- 2E - "SUBC|K|R ", -- 2F - "JMP|K ", -- 30 - "JZ|K ", -- 31 - "JNZ|K ", -- 32 - "JC|K ", -- 33 - "JNC|K ", -- 34 - "JLT|K ", -- 35 - "JGT|K ", -- 36 - "JLE|K ", -- 37 - "JGE|K ", -- 38 - "JEQ|K ", -- 39 - "JNE|K ", -- 3A - "CALL|K ", -- 3B - "PUSH|R ", -- 3C - "POP|R ", -- 3D - "RET ", -- 3E - "RETI " -- 3F - ); - -- Functions - function Instr(opcode : opcode_t) return inst_t; - function Instr(opcode : opcode_t; data : inst_data_t) return inst_t; - function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t; - function Instr(opcode : opcode_t; reg_a : integer) return inst_t; - function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t; - function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t; - function ctrl_lines_default return ctrl_lines_t; - function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t; - function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t; - function gen_murom return murom_t; - function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned; - function MIN (X, Y: INTEGER) return INTEGER; - function MAX (X, Y: INTEGER) return INTEGER; - -end cpu_pkg; - -package body cpu_pkg is - - function Instr(opcode : opcode_t) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - return inst; - - end Instr; - - function Instr(opcode : opcode_t; data : inst_data_t) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_addr_t'length) := data; - return inst; - - end Instr; - - function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_data_t'length) := data; - inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg, reg_ptr_t'length)); - - return inst; - - end Instr; - - function Instr(opcode : opcode_t; reg_a : integer) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length)); - - return inst; - - end Instr; - - function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length)); - inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length)); - - return inst; - - end Instr; - - function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - inst(3*(reg_ptr_t'length)-1 downto 2*reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_c, reg_ptr_t'length)); - inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length)); - inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length)); - - return inst; - - end Instr; - - function ctrl_lines_default return ctrl_lines_t is - variable result : ctrl_lines_t; - begin - result.pc_load := '0'; - result.pc_inc := '0'; - result.stk_push := '0'; - result.stk_pop := '0'; - result.stk_pushd := '0'; - result.stk_popd := '0'; - result.reg_we := '0'; - result.reg_src_sel := alu_src; - result.ddata_src_sel := reg_a; - result.daddr_src_sel := reg_b; - result.alu_opsel := pass_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.alu_load := '0'; - result.alu_cy_in := '0'; - result.mem_access := cmem_access; - result.mem_read := '0'; - result.mem_write := '0'; - result.int_exit := '0'; - return result; - - end ctrl_lines_default; - - function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is - variable instr_name : instr_name_t; - begin - instr_name := instr_name_array(to_integer(opcode)); - return idecoder(instr_name, iphase, status); - end idecoder; - - function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is - variable result : ctrl_lines_t; - variable ze, cy, xmem_wait : STD_LOGIC; - - begin - ze := status.alu.zero; - cy := status.alu.carry; - xmem_wait := status.xmem_wait; - - result := ctrl_lines_default; - if iphase = 0 then - result.pc_inc := '1'; - end if; - - case instr_name is - - when "HALT " => - result.pc_inc := '0'; - when "SETC " => -- carry <= 1 - result.reg_src_sel := alu_src; - result.alu_opsel := pass_op2; - result.alu_op2_src_sel := reg_b; - result.alu_load := '1'; - result.alu_cy_in := '1'; - when "MOV|R|R " => -- R(a) <= R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := pass_op2; - result.alu_op2_src_sel := reg_b; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "MOV|R|K " => -- R(a) <= #kk - result.reg_src_sel := alu_src; - result.alu_opsel := pass_op2; - result.alu_op2_src_sel := const; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "MOVC|Ri|R " => -- [R(b)] <= R(a) - result.mem_access := cmem_access; - result.daddr_src_sel := reg_b; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "MOVC|Ri|K " => -- [R(a)] <= kk - result.mem_access := cmem_access; - result.daddr_src_sel := reg_a; - result.ddata_src_sel := const; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "COUT|Ri|K " => -- [R(a)] <= kk - result.mem_access := cio_access; - result.daddr_src_sel := reg_a; - result.ddata_src_sel := const; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "MOVC|R|Ri " => -- R(a) <= [R(b)] - result.mem_access := cmem_access; - result.reg_src_sel := cmem_src; - result.daddr_src_sel := reg_b; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "MOVC|R|Ki " => -- R(a) <= [#addr] - result.mem_access := cmem_access; - result.reg_src_sel := cmem_src; - result.daddr_src_sel := const; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "CIN|R|Ki " => -- R(a) <= [#addr] - result.mem_access := cio_access; - result.reg_src_sel := cmem_src; - result.daddr_src_sel := const; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "MOVC|Ki|R " => -- [#addr] <= R(a) - result.mem_access := cmem_access; - result.daddr_src_sel := const; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "COUT|Ki|R " => -- [#addr] <= R(a) - result.mem_access := cio_access; - result.daddr_src_sel := const; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "MOVX|Ri|R " => -- [R(b)] <= R(a) - result.mem_access := xmem_access; - result.daddr_src_sel := reg_b; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - if xmem_wait = '1' then - result.mem_write := '1'; - result.pc_inc := '0'; - end if; - when "MOVX|Ri|K " => -- [R(a)] <= kk - result.mem_access := xmem_access; - result.daddr_src_sel := reg_a; - result.ddata_src_sel := const; - if iphase = 0 then - result.mem_write := '1'; - end if; - if xmem_wait = '1' then - result.mem_write := '1'; - result.pc_inc := '0'; - end if; - when "XOUT|Ri|K " => -- [R(a)] <= kk - result.mem_access := xio_access; - result.daddr_src_sel := reg_a; - result.ddata_src_sel := const; - if iphase = 0 then - result.mem_write := '1'; - end if; - if xmem_wait = '1' then - result.pc_inc := '0'; - result.mem_write := '1'; - end if; - when "MOVX|R|Ri " => -- R(a) <= [R(b)] - result.mem_access := xmem_access; - result.reg_src_sel := xmem_src; - result.daddr_src_sel := reg_b; - if iphase = 0 then - result.mem_read := '1'; - end if; - if xmem_wait = '0' then - if iphase = 1 then - result.reg_we := '1'; - end if; - else - result.pc_inc := '0'; - result.mem_read := '1'; - end if; - when "MOVX|R|Ki " => -- R(a) <= [#addr] - result.mem_access := xmem_access; - result.reg_src_sel := xmem_src; - result.daddr_src_sel := const; - if iphase = 0 then - result.mem_read := '1'; - end if; - if xmem_wait = '0' then - if iphase = 1 then - result.reg_we := '1'; - end if; - else - result.pc_inc := '0'; - result.mem_read := '1'; - end if; - when "XIN|R|Ki " => -- R(a) <= [#addr] - result.mem_access := xio_access; - result.reg_src_sel := xmem_src; - result.daddr_src_sel := const; - if iphase = 0 then - result.mem_read := '1'; - end if; - if xmem_wait = '0' then - if iphase = 1 then - result.reg_we := '1'; - end if; - else - result.pc_inc := '0'; - result.mem_read := '1'; - end if; - when "MOVX|Ki|R " => -- [#addr] <= R(a) - result.mem_access := xmem_access; - result.daddr_src_sel := const; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - if xmem_wait = '1' then - result.pc_inc := '0'; - result.mem_write := '1'; - end if; - when "XOUT|Ki|R " => -- [#addr] <= R(a) - result.mem_access := xio_access; - result.daddr_src_sel := const; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - if xmem_wait = '1' then - result.pc_inc := '0'; - result.mem_write := '1'; - end if; - when "ADD|R|R " => -- R(a) <= R(a) + R(b) - result.alu_opsel := op1_add_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ADD|R|K " => -- R(a) <= R(a) + k - result.alu_opsel := op1_add_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ADDC|R|R " => -- R(a) <= R(a) + R(b) - result.alu_opsel := op1_addc_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ADDC|R|K " => -- R(a) <= R(a) + k - result.alu_opsel := op1_addc_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUB|R|R " => -- R(a) <= R(a) + R(b) - result.alu_opsel := op1_sub_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUB|R|K " => -- R(a) <= R(a) + k - result.alu_opsel := op1_sub_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUB|K|R " => -- R(a) <= k - R(a) - result.alu_opsel := op1_sub_op2; - result.alu_op1_src_sel := const; - result.alu_op2_src_sel := reg_a; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUBC|R|R " => -- R(a) <= R(a) + R(b) - result.alu_opsel := op1_subc_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUBC|R|K " => -- R(a) <= R(a) + k - result.alu_opsel := op1_subc_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUBC|K|R " => -- R(a) <= K - R(a) - result.alu_opsel := op1_subc_op2; - result.alu_op1_src_sel := const; - result.alu_op2_src_sel := reg_a; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "AND|R|R " => -- R(a) <= R(a) and R(b) - result.alu_opsel := op1_and_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "AND|R|K " => -- R(a) <= R(a) and k - result.alu_opsel := op1_and_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "OR|R|R " => -- R(a) <= R(a) or R(b) - result.alu_opsel := op1_or_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "OR|R|K " => -- R(a) <= R(a) or R(b) - result.alu_opsel := op1_or_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "XOR|R|R " => -- R(a) <= R(a) xor R(b) - result.alu_opsel := op1_xor_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "XOR|R|K " => -- R(a) <= R(a) xor R(b) - result.alu_opsel := op1_xor_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SWAP|R " => -- R(a) <= R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := swap_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SHL|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := shl_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SHR|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := shr_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ROL|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := rol_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ROR|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := ror_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ROLC|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := rolc_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "RORC|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := rorc_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "CMP|R|R " => -- - result.alu_opsel := op1_sub_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.alu_load := '1'; - when "CMP|R|K " => -- - result.alu_opsel := op1_sub_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.alu_load := '1'; - when "JMP|K " => -- PC <= #addr - if iphase = 0 then - result.pc_load := '1'; - end if; - when "JZ|K " => -- PC <= #addr, zero - if iphase = 0 then - if ze = '1' then - result.pc_load := '1'; - end if; - end if; - when "JNZ|K " => -- PC <= #addr, !zero - if iphase = 0 then - if ze = '0' then - result.pc_load := '1'; - end if; - end if; - when "JC|K " => -- PC <= #addr, carry - if iphase = 0 then - if cy = '1' then - result.pc_load := '1'; - end if; - end if; - when "JNC|K " => -- PC <= #addr, !carry - if iphase = 0 then - if cy = '0' then - result.pc_load := '1'; - end if; - end if; - when "JLT|K " => -- PC <= #addr, !carry - if iphase = 0 then - if cy = '1' then - result.pc_load := '1'; - end if; - end if; - when "JGT|K " => -- - if iphase = 0 then - if (cy or ze) = '0' then - result.pc_load := '1'; - end if; - end if; - when "JLE|K " => -- - if iphase = 0 then - if (cy xor ze) = '1' then - result.pc_load := '1'; - end if; - end if; - when "JGE|K " => -- - if iphase = 0 then - if (not cy or ze) = '1' then - result.pc_load := '1'; - end if; - end if; - when "JEQ|K " => -- - if iphase = 0 then - if ze = '1' then - result.pc_load := '1'; - end if; - end if; - when "JNE|K " => -- - if iphase = 0 then - if ze = '0' then - result.pc_load := '1'; - end if; - end if; - when "PUSH|R " => -- push - if iphase = 0 then - result.stk_pushd := '1'; - end if; - when "POP|R " => -- pop - result.reg_src_sel := stk_src; - if iphase = 0 then - result.stk_popd := '1'; - elsif iphase = 1 then - result.reg_we := '1'; - end if; - when "CALL|K " => -- call - if iphase = 0 then - result.pc_load := '1'; - result.stk_push := '1'; - end if; - when "RET " => -- return - if iphase = 0 then - result.pc_load := '1'; - result.stk_pop := '1'; - end if; - when "RETI " => -- return - result.pc_inc := '0'; - result.int_exit := '1'; - - when others => null; -- nop - end case; - - return result; - - end idecoder; - - function gen_murom return murom_t is - variable result : murom_t; - variable opcode : opcode_t; - variable iphase : iphase_t; - variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0); - variable status : cpu_status_t; - variable pos : integer := 0; - - begin - for i in 0 to 2**addr'length-1 loop - addr := to_unsigned(i, addr'length); - opcode := addr(opcode'length-1 downto 0); - pos := opcode'length; - iphase := 0; - if addr(pos) = '1' then - iphase := 1; - end if; - pos := pos + 1; - status.alu.zero := addr(pos); - pos := pos + 1; - status.alu.carry := addr(pos); - pos := pos + 1; - status.xmem_wait := addr(pos); - - result(i) := idecoder(opcode, iphase, status); - end loop; - - return result; - end gen_murom; - - function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned is - variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0); - begin - addr := status.xmem_wait & status.alu.carry & status.alu.zero & to_unsigned(iphase, 1) & opcode; - return addr; - - end get_muromaddr; - - ------------------------------------------------------------- - function MIN (X, Y: INTEGER) return INTEGER is - variable res : integer := X; - begin - if Y < X then - res := Y; - end if; - - return res; - - end MIN; - - ------------------------------------------------------------- - function MAX (X, Y: INTEGER) return INTEGER is - variable res : integer := X; - begin - if Y > X then - res := Y; - end if; - - return res; - - end MAX; - - -end cpu_pkg; - diff --git a/lib/CPUs/JCpu/src/core/dpath_ctrl.vhd b/lib/CPUs/JCpu/src/core/dpath_ctrl.vhd deleted file mode 100644 index 1610d00..0000000 --- a/lib/CPUs/JCpu/src/core/dpath_ctrl.vhd +++ /dev/null @@ -1,87 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The datapath controller --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity dpath_ctrl is - Generic ( - use_rom : boolean := true - ); - Port ( - inst_in : in inst_t; - iphase_in : in iphase_t; - status_in : in cpu_status_t; - ctrl_out : out dpath_ctrl_out_t; - idout : out inst_addr_t; - ddout : out dmem_data_t - ); -end dpath_ctrl; - -architecture Behavioral of dpath_ctrl is - - signal opcode : opcode_t; - signal ctrl_lines : ctrl_lines_t; - signal dbg_iname : instr_name_t; - -begin - - idout <= inst_in(IMEM_ADDR_WIDTH-1 downto 0); - ddout <= inst_in(REG_SIZE_BITS+DMEM_DATA_WIDTH-1 downto REG_SIZE_BITS); - opcode <= inst_in(IMEM_DATA_WIDTH-1 downto IMEM_DATA_WIDTH-INST_OPCODE_WIDTH); - - ctrl_out.reg_a_ptr <= inst_in(reg_ptr_t'length-1 downto 0); - ctrl_out.reg_b_ptr <= inst_in(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length); - ctrl_out.lines <= ctrl_lines; - - -- pragma translate_off - dbg_iname <= instr_name_array(to_integer(opcode)); - -- pragma translate_on - -gen_ctrl_rom: -if use_rom = true generate - - i_dec: - process(opcode, iphase_in, status_in) - constant rom_data : murom_t := gen_murom; - variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0); - begin - addr := get_muromaddr(opcode, iphase_in, status_in); - ctrl_lines <= rom_data(to_integer(addr)); - end process; -end generate; - -gen_ctrl: -if use_rom = false generate - i_dec: - process (opcode, iphase_in, status_in) - begin - ctrl_lines <= idecoder(opcode, iphase_in, status_in); - end process; -end generate; - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/int_ctrl.vhd b/lib/CPUs/JCpu/src/core/int_ctrl.vhd deleted file mode 100644 index 2e54d67..0000000 --- a/lib/CPUs/JCpu/src/core/int_ctrl.vhd +++ /dev/null @@ -1,177 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Interrupt controller --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity int_ctrl is - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ctrl_in : in int_ctrl_in_t; - int_in : in STD_LOGIC; - int_exit : in STD_LOGIC; - iphase_in : in iphase_t; - pc_addr_out : out inst_addr_t; - int_ack_out : out STD_LOGIC; - stat_save_out : out STD_LOGIC; - stat_rest_out : out STD_LOGIC; - pc_load_out : out STD_LOGIC; - stk_push_out : out STD_LOGIC; - stk_pop_out : out STD_LOGIC - ); -end int_ctrl; - -architecture Behavioral of int_ctrl is - - type int_state_t is (int_idle, int_inject, int_active, int_release); - type pin_state_t is (pin_s0, pin_s1, pin_s2); - - signal int_state, int_state_next : int_state_t; - signal pin_state, pin_state_next : pin_state_t; - signal pc_load, int_ack, stk_push, stk_pop : STD_LOGIC; - signal int_request : std_logic; - signal int_sampled : std_logic; - -begin - - int_ack_out <= int_ack; - pc_load_out <= pc_load; - stk_push_out <= stk_push; - stk_pop_out <= stk_pop; - ------------------------------------------------------------------------ -irg_ctrl_fsm: - process (int_state, iphase_in, int_request, int_exit) - begin - - pc_addr_out <= to_unsigned(1, inst_addr_t'length); - int_state_next <= int_state; - int_ack <= '0'; - pc_load <= '0'; - stk_push <= '0'; - stk_pop <= '0'; - - case int_state is - - when int_idle => - if int_request = '1' and iphase_in = 1 then - int_state_next <= int_inject; - end if; - when int_inject => - if iphase_in = 0 then - int_ack <= '1'; - pc_load <= '1'; - elsif iphase_in = 1 then - stk_push <= '1'; - int_state_next <= int_active; - end if; - when int_active => - if int_exit = '1' and iphase_in = 1 then - int_state_next <= int_release; - end if; - when int_release => - if iphase_in = 0 then - stk_pop <= '1'; - pc_load <= '1'; - elsif iphase_in = 1 then - int_state_next <= int_idle; - end if; - when others => - int_state_next <= int_idle; - end case; - - end process; - -irq_ctrl_states: - process (rst, clk, int_state_next) - begin - if rst = '1' then - int_state <= int_idle; - elsif rising_edge(clk) then - int_state <= int_state_next; - end if; - end process; - ------------------------------------------------------------------------ -pin_sample: - process (clk) - begin - if rising_edge(clk) then - int_sampled <= int_in xor (not ctrl_in.polarity); - end if; - end process; - ------------------------------------------------------------------------ -pin_fsm: - process (pin_state, int_sampled, int_ack, ctrl_in) - begin - int_request <= '0'; - pin_state_next <= pin_state; - case pin_state is - when pin_s0 => - if int_sampled = '1' or ctrl_in.request = '1' then - if ctrl_in.enable = '1' then - pin_state_next <= pin_s1; - end if; - end if; - when pin_s1 => - int_request <= '1'; - if int_ack = '1' then - pin_state_next <= pin_s2; - end if; - when pin_s2 => - if ctrl_in.edge_sens = '0' then - pin_state_next <= pin_s0; - elsif int_sampled = '0' then - pin_state_next <= pin_s0; - end if; - when others => - pin_state_next <= pin_s0; - end case; - end process; - -pin_states: - process (rst, clk, pin_state_next) - begin - if rst = '1' then - pin_state <= pin_s0; - elsif rising_edge(clk) then - pin_state <= pin_state_next; - end if; - end process; - ------------------------------------------------------------------------ -stat_save_restore: - process (clk, stk_push, stk_pop) - begin - if rising_edge(clk) then - stat_save_out <= stk_push; - stat_rest_out <= stk_pop; - end if; - end process; - -end Behavioral; diff --git a/lib/CPUs/JCpu/src/core/pc.vhd b/lib/CPUs/JCpu/src/core/pc.vhd deleted file mode 100644 index 6b1d575..0000000 --- a/lib/CPUs/JCpu/src/core/pc.vhd +++ /dev/null @@ -1,70 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Programm counter --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity pc is - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - inc : in STD_LOGIC; - load : in STD_LOGIC; - pc_in : in inst_addr_t; - pc_out : out inst_addr_t; - pc_next : out inst_addr_t - ); -end pc; - -architecture Behavioral of pc is - -begin - -proc_pc: - process(rst, clk, inc, load, pc_in) - variable vpc, vpc_reg: inst_addr_t; - begin - if rst = '1' then - vpc_reg := (others => '0'); - elsif rising_edge(clk) then - if inc = '1' or load = '1' then - vpc_reg := vpc; - elsif inc = '0' then - pc_next <= vpc; - end if; - end if; - - if load = '1' then - vpc := pc_in; - else - vpc := vpc_reg + 1; - end if; - pc_out <= vpc_reg; - - end process; - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/reg_dual.vhd b/lib/CPUs/JCpu/src/core/reg_dual.vhd deleted file mode 100644 index 6b7e4d8..0000000 --- a/lib/CPUs/JCpu/src/core/reg_dual.vhd +++ /dev/null @@ -1,81 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: On-Chip work registers --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity reg_dual is - Generic ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clk : in STD_LOGIC; - we_a : in STD_LOGIC; - ptr_a : in reg_ptr_t; - ptr_b : in reg_ptr_t; - din_a : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end reg_dual; - -architecture Behavioral of reg_dual is - - constant depth : integer := 2**addr_width; - type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal addr_a, addr_b : unsigned (addr_width-1 downto 0) := (others => '0'); - - signal mem : mem_t; -begin - - addr_a <= TO_01(ptr_a(addr_width-1 downto 0)); - addr_b <= TO_01(ptr_b(addr_width-1 downto 0)); - -reg_in_ab: - process(clk) - begin - if rising_edge(clk) then - if we_a = '1' then - mem(to_integer(addr_a)) <= din_a; - end if; - end if; - end process; - -reg_out_a: - process(mem, addr_a) - begin - dout_a <= TO_01(mem(to_integer(addr_a))); - end process; - -reg_out_b: - process(mem, addr_b) - begin - dout_b <= TO_01(mem(to_integer(addr_b))); - end process; - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/stack_ctrl.vhd b/lib/CPUs/JCpu/src/core/stack_ctrl.vhd deleted file mode 100644 index 7eccae3..0000000 --- a/lib/CPUs/JCpu/src/core/stack_ctrl.vhd +++ /dev/null @@ -1,73 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The call/return/data stack --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity stack_ctrl is -Generic ( - addr_width : integer := 3 -); -Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - push : in STD_LOGIC; - pop : in STD_LOGIC; - ptr_out : out unsigned (addr_width-1 downto 0); - din : in inst_addr_t; - dout : out inst_addr_t; - mem_we : out STD_LOGIC - ); -end stack_ctrl; - -architecture Behavioral of stack_ctrl is - - signal ptr : unsigned (addr_width-1 downto 0); - -begin - - ptr_out <= ptr; - -stk_ptr: - process(rst, clk, ptr, push, pop) - begin - if rst = '1' then - ptr <= (others => '0'); - dout <= (others => '0'); - mem_we <= '0'; - elsif rising_edge(clk) then - mem_we <= push; - if push = '1' then - ptr <= ptr + 1; - dout <= din; - elsif pop = '1' then - ptr <= ptr - 1; - end if; - end if; - end process; - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/cpu_embedded.vhd b/lib/CPUs/JCpu/src/cpu_embedded.vhd deleted file mode 100644 index 1990170..0000000 --- a/lib/CPUs/JCpu/src/cpu_embedded.vhd +++ /dev/null @@ -1,109 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity cpu_embedded is - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_wait : in STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0); - io_sel : out STD_LOGIC - ); -end cpu_embedded; - -architecture rtl of cpu_embedded is - - signal irom_data : unsigned (IMEM_DATA_WIDTH-1 downto 0); - signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0); - - COMPONENT cpu - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_wait : in STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0); - instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0); - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - io_sel : out STD_LOGIC - ); - END COMPONENT; - - - COMPONENT irom - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - END COMPONENT; - -begin - -inst_cpu: cpu - PORT MAP( - rst => rst, - clk => clk, - ce => ce, - int_in => int_in, - int_ack => int_ack, - xmem_wait => xmem_wait, - xmem_we => xmem_we, - xmem_re => xmem_re, - instr_din => irom_data, - instr_addr => irom_addr, - xmem_din => xmem_din, - xmem_dout => xmem_dout, - xmem_addr => xmem_addr, - io_sel => io_sel - ); - -inst_irom: irom - PORT MAP( - clk => clk, - ce => ce, - addr => irom_addr, - dout => irom_data - ); - -end rtl; diff --git a/lib/CPUs/JCpu/src/dctest_irom.vhdl b/lib/CPUs/JCpu/src/dctest_irom.vhdl deleted file mode 100644 index 7987a15..0000000 --- a/lib/CPUs/JCpu/src/dctest_irom.vhdl +++ /dev/null @@ -1,79 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); -END irom; - -ARCHITECTURE dctest OF irom IS - - type imem_rom_t is array (0 to 17) of inst_t; - - -- Assembled from dctest.jsm - constant imem_rom : imem_rom_t := - ( - "110000" & X"010", -- 0x000: JMP 0x010 - "110000" & X"011", -- 0x001: JMP 0x011 - "000000" & X"000", -- 0x002: - "000000" & X"000", -- 0x003: - "000000" & X"000", -- 0x004: - "000000" & X"000", -- 0x005: - "000000" & X"000", -- 0x006: - "000000" & X"000", -- 0x007: - "000000" & X"000", -- 0x008: - "000000" & X"000", -- 0x009: - "000000" & X"000", -- 0x00A: - "000000" & X"000", -- 0x00B: - "000000" & X"000", -- 0x00C: - "000000" & X"000", -- 0x00D: - "000000" & X"000", -- 0x00E: - "000000" & X"000", -- 0x00F: - "110000" & X"010", -- 0x010: JMP 0x010 - "111111" & X"000" -- 0x011: RETI - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -end dctest; - diff --git a/lib/CPUs/JCpu/src/dctest_irom_ld.vhdl b/lib/CPUs/JCpu/src/dctest_irom_ld.vhdl deleted file mode 100644 index 223dd46..0000000 --- a/lib/CPUs/JCpu/src/dctest_irom_ld.vhdl +++ /dev/null @@ -1,1181 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from dctest.jsm - type imem_rom_t is array (0 to 1023) of inst_t; - signal imem_rom : imem_rom_t := - ( - "110000" & X"010", -- 0x000: JMP 0x010 - "110000" & X"011", -- 0x001: JMP 0x011 - "000000" & X"000", -- 0x002: - "000000" & X"000", -- 0x003: - "000000" & X"000", -- 0x004: - "000000" & X"000", -- 0x005: - "000000" & X"000", -- 0x006: - "000000" & X"000", -- 0x007: - "000000" & X"000", -- 0x008: - "000000" & X"000", -- 0x009: - "000000" & X"000", -- 0x00A: - "000000" & X"000", -- 0x00B: - "000000" & X"000", -- 0x00C: - "000000" & X"000", -- 0x00D: - "000000" & X"000", -- 0x00E: - "000000" & X"000", -- 0x00F: - "110000" & X"010", -- 0x010: JMP 0x010 - "111111" & X"000", -- 0x011: RETI - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000" - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : inst_addr_t; - signal jtag_ld_dout : inst_t; - signal jtag_ld_din : inst_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (31 downto 0); - constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1); - jtag_ld_din <= user_regi(inst_t'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/dctest_xrom.vhdl b/lib/CPUs/JCpu/src/dctest_xrom.vhdl deleted file mode 100644 index 24fe36c..0000000 --- a/lib/CPUs/JCpu/src/dctest_xrom.vhdl +++ /dev/null @@ -1,317 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); -END xrom; - -ARCHITECTURE dctest OF xrom IS - - type xmem_rom_t is array (0 to 255) of dmem_data_t; - - -- Assembled from dctest.jsm - constant xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"01", -- 0x04 - X"12", -- 0x05 - X"41", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"48", -- 0x17 - X"61", -- 0x18 - X"6C", -- 0x19 - X"6C", -- 0x1A - X"6F", -- 0x1B - X"0D", -- 0x1C - X"0A", -- 0x1D - X"00", -- 0x1E - X"4A", -- 0x1F - X"65", -- 0x20 - X"6E", -- 0x21 - X"73", -- 0x22 - X"00", -- 0x23 - X"57", -- 0x24 - X"65", -- 0x25 - X"6C", -- 0x26 - X"63", -- 0x27 - X"6F", -- 0x28 - X"6D", -- 0x29 - X"65", -- 0x2A - X"20", -- 0x2B - X"74", -- 0x2C - X"6F", -- 0x2D - X"20", -- 0x2E - X"4A", -- 0x2F - X"41", -- 0x30 - X"53", -- 0x31 - X"4D", -- 0x32 - X"20", -- 0x33 - X"43", -- 0x34 - X"50", -- 0x35 - X"55", -- 0x36 - X"00", -- 0x37 - X"52", -- 0x38 - X"65", -- 0x39 - X"61", -- 0x3A - X"64", -- 0x3B - X"79", -- 0x3C - X"00", -- 0x3D - X"54", -- 0x3E - X"65", -- 0x3F - X"73", -- 0x40 - X"74", -- 0x41 - X"69", -- 0x42 - X"6E", -- 0x43 - X"67", -- 0x44 - X"00", -- 0x45 - X"50", -- 0x46 - X"61", -- 0x47 - X"73", -- 0x48 - X"73", -- 0x49 - X"65", -- 0x4A - X"64", -- 0x4B - X"00", -- 0x4C - X"45", -- 0x4D - X"72", -- 0x4E - X"72", -- 0x4F - X"6F", -- 0x50 - X"72", -- 0x51 - X"00", -- 0x52 - X"0D", -- 0x53 - X"0A", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -end dctest; - diff --git a/lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl b/lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl deleted file mode 100644 index 802ba50..0000000 --- a/lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl +++ /dev/null @@ -1,413 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); - -END xrom; - -ARCHITECTURE loadable OF xrom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from dctest.jsm - type xmem_rom_t is array (0 to 255) of dmem_data_t; - signal xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"01", -- 0x04 - X"12", -- 0x05 - X"41", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"48", -- 0x17 - X"61", -- 0x18 - X"6C", -- 0x19 - X"6C", -- 0x1A - X"6F", -- 0x1B - X"0D", -- 0x1C - X"0A", -- 0x1D - X"00", -- 0x1E - X"4A", -- 0x1F - X"65", -- 0x20 - X"6E", -- 0x21 - X"73", -- 0x22 - X"00", -- 0x23 - X"57", -- 0x24 - X"65", -- 0x25 - X"6C", -- 0x26 - X"63", -- 0x27 - X"6F", -- 0x28 - X"6D", -- 0x29 - X"65", -- 0x2A - X"20", -- 0x2B - X"74", -- 0x2C - X"6F", -- 0x2D - X"20", -- 0x2E - X"4A", -- 0x2F - X"41", -- 0x30 - X"53", -- 0x31 - X"4D", -- 0x32 - X"20", -- 0x33 - X"43", -- 0x34 - X"50", -- 0x35 - X"55", -- 0x36 - X"00", -- 0x37 - X"52", -- 0x38 - X"65", -- 0x39 - X"61", -- 0x3A - X"64", -- 0x3B - X"79", -- 0x3C - X"00", -- 0x3D - X"54", -- 0x3E - X"65", -- 0x3F - X"73", -- 0x40 - X"74", -- 0x41 - X"69", -- 0x42 - X"6E", -- 0x43 - X"67", -- 0x44 - X"00", -- 0x45 - X"50", -- 0x46 - X"61", -- 0x47 - X"73", -- 0x48 - X"73", -- 0x49 - X"65", -- 0x4A - X"64", -- 0x4B - X"00", -- 0x4C - X"45", -- 0x4D - X"72", -- 0x4E - X"72", -- 0x4F - X"6F", -- 0x50 - X"72", -- 0x51 - X"00", -- 0x52 - X"0D", -- 0x53 - X"0A", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : dmem_addr_t; - signal jtag_ld_dout : dmem_data_t; - signal jtag_ld_din : dmem_data_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (15 downto 0); - constant id : unsigned (15 downto 0) := X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1); - jtag_ld_din <= user_regi(dmem_data_t'left downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/itest_irom.vhdl b/lib/CPUs/JCpu/src/itest_irom.vhdl deleted file mode 100644 index 94609a3..0000000 --- a/lib/CPUs/JCpu/src/itest_irom.vhdl +++ /dev/null @@ -1,1089 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.types_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY irom IS - Generic - ( - depth : integer := 4 - ); - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in addr_t; - dout : out word_t - ); -END irom; - -ARCHITECTURE itest OF irom IS - - type imem_rom_t is array (0 to depth-1) of word_t; - - -- Assembled from itest.jsm - constant imem_rom : imem_rom_t := - ( - "110000" & X"010", -- 0x000: JMP 0x010 - "110000" & X"288", -- 0x001: JMP 0x288 - "000000" & X"000", -- 0x002: - "000000" & X"000", -- 0x003: - "000000" & X"000", -- 0x004: - "000000" & X"000", -- 0x005: - "000000" & X"000", -- 0x006: - "000000" & X"000", -- 0x007: - "000000" & X"000", -- 0x008: - "000000" & X"000", -- 0x009: - "000000" & X"000", -- 0x00A: - "000000" & X"000", -- 0x00B: - "000000" & X"000", -- 0x00C: - "000000" & X"000", -- 0x00D: - "000000" & X"000", -- 0x00E: - "000000" & X"000", -- 0x00F: - "111011" & X"03B", -- 0x010: CALL 0x03B - "101001" & X"000", -- 0x011: CIN R00, (0x00) - "100100" & X"000", -- 0x012: XOUT (0x00), R00 - "111011" & X"04C", -- 0x013: CALL 0x04C - "000011" & X"010", -- 0x014: MOV R00, 0x01 - "100100" & X"010", -- 0x015: XOUT (0x01), R00 - "111011" & X"08D", -- 0x016: CALL 0x08D - "000011" & X"020", -- 0x017: MOV R00, 0x02 - "100100" & X"010", -- 0x018: XOUT (0x01), R00 - "111011" & X"0C9", -- 0x019: CALL 0x0C9 - "000011" & X"030", -- 0x01A: MOV R00, 0x03 - "100100" & X"010", -- 0x01B: XOUT (0x01), R00 - "111011" & X"0DB", -- 0x01C: CALL 0x0DB - "000011" & X"040", -- 0x01D: MOV R00, 0x04 - "100100" & X"010", -- 0x01E: XOUT (0x01), R00 - "111011" & X"0ED", -- 0x01F: CALL 0x0ED - "000011" & X"050", -- 0x020: MOV R00, 0x05 - "100100" & X"010", -- 0x021: XOUT (0x01), R00 - "111011" & X"0FF", -- 0x022: CALL 0x0FF - "000011" & X"060", -- 0x023: MOV R00, 0x06 - "100100" & X"010", -- 0x024: XOUT (0x01), R00 - "111011" & X"115", -- 0x025: CALL 0x115 - "000011" & X"070", -- 0x026: MOV R00, 0x07 - "100100" & X"010", -- 0x027: XOUT (0x01), R00 - "111011" & X"12B", -- 0x028: CALL 0x12B - "000011" & X"080", -- 0x029: MOV R00, 0x08 - "100100" & X"010", -- 0x02A: XOUT (0x01), R00 - "111011" & X"137", -- 0x02B: CALL 0x137 - "000011" & X"090", -- 0x02C: MOV R00, 0x09 - "100100" & X"010", -- 0x02D: XOUT (0x01), R00 - "111011" & X"15A", -- 0x02E: CALL 0x15A - "000011" & X"0A0", -- 0x02F: MOV R00, 0x0A - "100100" & X"010", -- 0x030: XOUT (0x01), R00 - "111011" & X"22A", -- 0x031: CALL 0x22A - "000011" & X"0B0", -- 0x032: MOV R00, 0x0B - "100100" & X"010", -- 0x033: XOUT (0x01), R00 - "111011" & X"24D", -- 0x034: CALL 0x24D - "000011" & X"0C0", -- 0x035: MOV R00, 0x0C - "100100" & X"010", -- 0x036: XOUT (0x01), R00 - "111011" & X"278", -- 0x037: CALL 0x278 - "000011" & X"FF0", -- 0x038: MOV R00, 0xFF - "100100" & X"010", -- 0x039: XOUT (0x01), R00 - "110000" & X"2FF", -- 0x03A: JMP 0x2FF - "000011" & X"000", -- 0x03B: MOV R00, 0x00 - "000011" & X"001", -- 0x03C: MOV R01, 0x00 - "000011" & X"002", -- 0x03D: MOV R02, 0x00 - "000011" & X"003", -- 0x03E: MOV R03, 0x00 - "000011" & X"004", -- 0x03F: MOV R04, 0x00 - "000011" & X"005", -- 0x040: MOV R05, 0x00 - "000011" & X"006", -- 0x041: MOV R06, 0x00 - "000011" & X"007", -- 0x042: MOV R07, 0x00 - "000011" & X"008", -- 0x043: MOV R08, 0x00 - "000011" & X"009", -- 0x044: MOV R09, 0x00 - "000011" & X"00A", -- 0x045: MOV R10, 0x00 - "000011" & X"00B", -- 0x046: MOV R11, 0x00 - "000011" & X"00C", -- 0x047: MOV R12, 0x00 - "000011" & X"00D", -- 0x048: MOV R13, 0x00 - "000011" & X"00E", -- 0x049: MOV R14, 0x00 - "000011" & X"00F", -- 0x04A: MOV R15, 0x00 - "111110" & X"000", -- 0x04B: RET - "000011" & X"100", -- 0x04C: MOV R00, 0x10 - "001111" & X"100", -- 0x04D: CMP R00, 0x10 - "111010" & X"3FF", -- 0x04E: JNE 0x3FF - "010001" & X"010", -- 0x04F: ADD R00, 0x01 - "000010" & X"001", -- 0x050: MOV R01, R00 - "001111" & X"111", -- 0x051: CMP R01, 0x11 - "111010" & X"3FF", -- 0x052: JNE 0x3FF - "010001" & X"011", -- 0x053: ADD R01, 0x01 - "000010" & X"012", -- 0x054: MOV R02, R01 - "001111" & X"122", -- 0x055: CMP R02, 0x12 - "111010" & X"3FF", -- 0x056: JNE 0x3FF - "010001" & X"012", -- 0x057: ADD R02, 0x01 - "000010" & X"023", -- 0x058: MOV R03, R02 - "001111" & X"133", -- 0x059: CMP R03, 0x13 - "111010" & X"3FF", -- 0x05A: JNE 0x3FF - "010001" & X"013", -- 0x05B: ADD R03, 0x01 - "000010" & X"034", -- 0x05C: MOV R04, R03 - "001111" & X"144", -- 0x05D: CMP R04, 0x14 - "111010" & X"3FF", -- 0x05E: JNE 0x3FF - "010001" & X"014", -- 0x05F: ADD R04, 0x01 - "000010" & X"045", -- 0x060: MOV R05, R04 - "001111" & X"155", -- 0x061: CMP R05, 0x15 - "111010" & X"3FF", -- 0x062: JNE 0x3FF - "010001" & X"015", -- 0x063: ADD R05, 0x01 - "000010" & X"056", -- 0x064: MOV R06, R05 - "001111" & X"166", -- 0x065: CMP R06, 0x16 - "111010" & X"3FF", -- 0x066: JNE 0x3FF - "010001" & X"016", -- 0x067: ADD R06, 0x01 - "000010" & X"067", -- 0x068: MOV R07, R06 - "001111" & X"177", -- 0x069: CMP R07, 0x17 - "111010" & X"3FF", -- 0x06A: JNE 0x3FF - "010001" & X"017", -- 0x06B: ADD R07, 0x01 - "000010" & X"078", -- 0x06C: MOV R08, R07 - "001111" & X"188", -- 0x06D: CMP R08, 0x18 - "111010" & X"3FF", -- 0x06E: JNE 0x3FF - "010001" & X"018", -- 0x06F: ADD R08, 0x01 - "000010" & X"089", -- 0x070: MOV R09, R08 - "001111" & X"199", -- 0x071: CMP R09, 0x19 - "111010" & X"3FF", -- 0x072: JNE 0x3FF - "010001" & X"019", -- 0x073: ADD R09, 0x01 - "000010" & X"09A", -- 0x074: MOV R10, R09 - "001111" & X"1AA", -- 0x075: CMP R10, 0x1A - "111010" & X"3FF", -- 0x076: JNE 0x3FF - "010001" & X"01A", -- 0x077: ADD R10, 0x01 - "000010" & X"0AB", -- 0x078: MOV R11, R10 - "001111" & X"1BB", -- 0x079: CMP R11, 0x1B - "111010" & X"3FF", -- 0x07A: JNE 0x3FF - "010001" & X"01B", -- 0x07B: ADD R11, 0x01 - "000010" & X"0BC", -- 0x07C: MOV R12, R11 - "001111" & X"1CC", -- 0x07D: CMP R12, 0x1C - "111010" & X"3FF", -- 0x07E: JNE 0x3FF - "010001" & X"01C", -- 0x07F: ADD R12, 0x01 - "000010" & X"0CD", -- 0x080: MOV R13, R12 - "001111" & X"1DD", -- 0x081: CMP R13, 0x1D - "111010" & X"3FF", -- 0x082: JNE 0x3FF - "010001" & X"01D", -- 0x083: ADD R13, 0x01 - "000010" & X"0DE", -- 0x084: MOV R14, R13 - "001111" & X"1EE", -- 0x085: CMP R14, 0x1E - "111010" & X"3FF", -- 0x086: JNE 0x3FF - "010001" & X"01E", -- 0x087: ADD R14, 0x01 - "000010" & X"0EF", -- 0x088: MOV R15, R14 - "001111" & X"1FF", -- 0x089: CMP R15, 0x1F - "111010" & X"3FF", -- 0x08A: JNE 0x3FF - "010001" & X"01F", -- 0x08B: ADD R15, 0x01 - "111110" & X"000", -- 0x08C: RET - "000011" & X"000", -- 0x08D: MOV R00, 0x00 - "001111" & X"000", -- 0x08E: TST R00 - "110010" & X"3FF", -- 0x08F: JNZ 0x3FF - "110011" & X"3FF", -- 0x090: JC 0x3FF - "001111" & X"000", -- 0x091: CMP R00, 0x00 - "111010" & X"3FF", -- 0x092: JNE 0x3FF - "110101" & X"3FF", -- 0x093: JLT 0x3FF - "110110" & X"3FF", -- 0x094: JGT 0x3FF - "110111" & X"097", -- 0x095: JLE 0x097 - "110000" & X"3FF", -- 0x096: JMP 0x3FF - "111001" & X"099", -- 0x097: JEQ 0x099 - "110000" & X"3FF", -- 0x098: JMP 0x3FF - "111000" & X"09B", -- 0x099: JGE 0x09B - "110000" & X"3FF", -- 0x09A: JMP 0x3FF - "001111" & X"550", -- 0x09B: CMP R00, 0x55 - "111001" & X"3FF", -- 0x09C: JEQ 0x3FF - "110101" & X"09F", -- 0x09D: JLT 0x09F - "110000" & X"3FF", -- 0x09E: JMP 0x3FF - "110111" & X"0A1", -- 0x09F: JLE 0x0A1 - "110000" & X"3FF", -- 0x0A0: JMP 0x3FF - "111000" & X"3FF", -- 0x0A1: JGE 0x3FF - "110110" & X"3FF", -- 0x0A2: JGT 0x3FF - "000011" & X"550", -- 0x0A3: MOV R00, 0x55 - "001111" & X"000", -- 0x0A4: TST R00 - "110001" & X"3FF", -- 0x0A5: JZ 0x3FF - "110011" & X"3FF", -- 0x0A6: JC 0x3FF - "001111" & X"AA0", -- 0x0A7: CMP R00, 0xAA - "111001" & X"3FF", -- 0x0A8: JEQ 0x3FF - "111010" & X"0AB", -- 0x0A9: JNE 0x0AB - "110000" & X"3FF", -- 0x0AA: JMP 0x3FF - "110101" & X"0AD", -- 0x0AB: JLT 0x0AD - "110000" & X"3FF", -- 0x0AC: JMP 0x3FF - "110111" & X"0AF", -- 0x0AD: JLE 0x0AF - "110000" & X"3FF", -- 0x0AE: JMP 0x3FF - "110110" & X"3FF", -- 0x0AF: JGT 0x3FF - "001111" & X"550", -- 0x0B0: CMP R00, 0x55 - "111001" & X"0B3", -- 0x0B1: JEQ 0x0B3 - "110000" & X"3FF", -- 0x0B2: JMP 0x3FF - "111010" & X"3FF", -- 0x0B3: JNE 0x3FF - "110101" & X"3FF", -- 0x0B4: JLT 0x3FF - "110111" & X"0B7", -- 0x0B5: JLE 0x0B7 - "110000" & X"3FF", -- 0x0B6: JMP 0x3FF - "110110" & X"3FF", -- 0x0B7: JGT 0x3FF - "111000" & X"0BA", -- 0x0B8: JGE 0x0BA - "110000" & X"3FF", -- 0x0B9: JMP 0x3FF - "000011" & X"AA0", -- 0x0BA: MOV R00, 0xAA - "001111" & X"000", -- 0x0BB: TST R00 - "110001" & X"3FF", -- 0x0BC: JZ 0x3FF - "110011" & X"3FF", -- 0x0BD: JC 0x3FF - "001111" & X"550", -- 0x0BE: CMP R00, 0x55 - "111001" & X"3FF", -- 0x0BF: JEQ 0x3FF - "111010" & X"0C2", -- 0x0C0: JNE 0x0C2 - "110000" & X"3FF", -- 0x0C1: JMP 0x3FF - "110110" & X"0C4", -- 0x0C2: JGT 0x0C4 - "110000" & X"3FF", -- 0x0C3: JMP 0x3FF - "111000" & X"0C6", -- 0x0C4: JGE 0x0C6 - "110000" & X"3FF", -- 0x0C5: JMP 0x3FF - "110101" & X"3FF", -- 0x0C6: JLT 0x3FF - "110111" & X"3FF", -- 0x0C7: JLE 0x3FF - "111110" & X"000", -- 0x0C8: RET - "000011" & X"000", -- 0x0C9: MOV R00, 0x00 - "000011" & X"001", -- 0x0CA: MOV R01, 0x00 - "000010" & X"002", -- 0x0CB: MOV R02, R00 - "000010" & X"013", -- 0x0CC: MOV R03, R01 - "010001" & X"010", -- 0x0CD: ADD R00, 0x01 - "010011" & X"001", -- 0x0CE: ADDC R01, 0x00 - "010001" & X"012", -- 0x0CF: ADD R02, 0x01 - "001111" & X"002", -- 0x0D0: CMP R02, 0x00 - "111010" & X"0D4", -- 0x0D1: JNE 0x0D4 - "010001" & X"013", -- 0x0D2: ADD R03, 0x01 - "001111" & X"023", -- 0x0D3: CMP R03, 0x02 - "111010" & X"0CD", -- 0x0D4: JNE 0x0CD - "001110" & X"020", -- 0x0D5: CMP R00, R02 - "111010" & X"3FF", -- 0x0D6: JNE 0x3FF - "001110" & X"031", -- 0x0D7: CMP R01, R03 - "111010" & X"3FF", -- 0x0D8: JNE 0x3FF - "000011" & X"000", -- 0x0D9: MOV R00, 0x00 - "111110" & X"000", -- 0x0DA: RET - "000011" & X"000", -- 0x0DB: MOV R00, 0x00 - "000011" & X"031", -- 0x0DC: MOV R01, 0x03 - "000010" & X"002", -- 0x0DD: MOV R02, R00 - "000010" & X"013", -- 0x0DE: MOV R03, R01 - "010101" & X"010", -- 0x0DF: SUB R00, 0x01 - "010111" & X"001", -- 0x0E0: SUBC R01, 0x00 - "010101" & X"012", -- 0x0E1: SUB R02, 0x01 - "001111" & X"FF2", -- 0x0E2: CMP R02, 0xFF - "111010" & X"0E6", -- 0x0E3: JNE 0x0E6 - "010101" & X"013", -- 0x0E4: SUB R03, 0x01 - "001111" & X"003", -- 0x0E5: CMP R03, 0x00 - "111010" & X"0DF", -- 0x0E6: JNE 0x0DF - "001110" & X"020", -- 0x0E7: CMP R00, R02 - "111010" & X"3FF", -- 0x0E8: JNE 0x3FF - "001110" & X"031", -- 0x0E9: CMP R01, R03 - "111010" & X"3FF", -- 0x0EA: JNE 0x3FF - "000011" & X"000", -- 0x0EB: MOV R00, 0x00 - "111110" & X"000", -- 0x0EC: RET - "000011" & X"030", -- 0x0ED: MOV R00, 0x03 - "000011" & X"051", -- 0x0EE: MOV R01, 0x05 - "101110" & X"050", -- 0x0EF: SUB 0x05, R00 - "010101" & X"031", -- 0x0F0: SUB R01, 0x03 - "001110" & X"010", -- 0x0F1: CMP R00, R01 - "111010" & X"3FF", -- 0x0F2: JNE 0x3FF - "000011" & X"030", -- 0x0F3: MOV R00, 0x03 - "000011" & X"051", -- 0x0F4: MOV R01, 0x05 - "010100" & X"010", -- 0x0F5: SUB R00, R01 - "101111" & X"000", -- 0x0F6: SUBC 0x00, R00 - "001111" & X"010", -- 0x0F7: CMP R00, 0x01 - "111010" & X"3FF", -- 0x0F8: JNE 0x3FF - "010001" & X"000", -- 0x0F9: ADD R00, 0x00 - "010110" & X"001", -- 0x0FA: SUBC R01, R00 - "001111" & X"041", -- 0x0FB: CMP R01, 0x04 - "111010" & X"3FF", -- 0x0FC: JNE 0x3FF - "000011" & X"000", -- 0x0FD: MOV R00, 0x00 - "111110" & X"000", -- 0x0FE: RET - "000011" & X"010", -- 0x0FF: MOV R00, 0x01 - "001101" & X"5A0", -- 0x100: MOVC (0x5A), R00 - "010101" & X"010", -- 0x101: DEC R00 - "001101" & X"000", -- 0x102: MOVC (0x00), R00 - "001010" & X"5A1", -- 0x103: MOVC R01, (0x5A) - "001100" & X"A51", -- 0x104: MOVC (R01), 0xA5 - "001001" & X"010", -- 0x105: MOVC R00, (R01) - "001001" & X"011", -- 0x106: MOVC R01, (R01) - "010001" & X"5A1", -- 0x107: ADD R01, 0x5A - "001001" & X"010", -- 0x108: MOVC R00, (R01) - "001011" & X"000", -- 0x109: MOVC (R00), R00 - "001001" & X"002", -- 0x10A: MOVC R02, (R00) - "001110" & X"002", -- 0x10B: CMP R02, R00 - "111010" & X"3FF", -- 0x10C: JNE 0x3FF - "001011" & X"021", -- 0x10D: MOVC (R01), R02 - "001001" & X"022", -- 0x10E: MOVC R02, (R02) - "001110" & X"012", -- 0x10F: CMP R02, R01 - "111010" & X"3FF", -- 0x110: JNE 0x3FF - "010101" & X"011", -- 0x111: DEC R01 - "010001" & X"010", -- 0x112: INC R00 - "110010" & X"109", -- 0x113: JNZ 0x109 - "111110" & X"000", -- 0x114: RET - "000011" & X"010", -- 0x115: MOV R00, 0x01 - "001000" & X"600", -- 0x116: MOVX (0x60), R00 - "010101" & X"010", -- 0x117: DEC R00 - "001000" & X"060", -- 0x118: MOVX (0x06), R00 - "000101" & X"601", -- 0x119: MOVX R01, (0x60) - "000111" & X"A51", -- 0x11A: MOVX (R01), 0xA5 - "000100" & X"010", -- 0x11B: MOVX R00, (R01) - "000100" & X"011", -- 0x11C: MOVX R01, (R01) - "010001" & X"5A1", -- 0x11D: ADD R01, 0x5A - "000100" & X"010", -- 0x11E: MOVX R00, (R01) - "000110" & X"000", -- 0x11F: MOVX (R00), R00 - "000100" & X"002", -- 0x120: MOVX R02, (R00) - "001110" & X"002", -- 0x121: CMP R02, R00 - "111010" & X"3FF", -- 0x122: JNE 0x3FF - "000110" & X"021", -- 0x123: MOVX (R01), R02 - "000100" & X"022", -- 0x124: MOVX R02, (R02) - "001110" & X"012", -- 0x125: CMP R02, R01 - "111010" & X"3FF", -- 0x126: JNE 0x3FF - "010101" & X"011", -- 0x127: DEC R01 - "010001" & X"010", -- 0x128: INC R00 - "110010" & X"11F", -- 0x129: JNZ 0x11F - "111110" & X"000", -- 0x12A: RET - "000011" & X"AA0", -- 0x12B: MOV R00, 0xAA - "000011" & X"001", -- 0x12C: MOV R01, 0x00 - "111100" & X"000", -- 0x12D: PUSH R00 - "010001" & X"010", -- 0x12E: INC R00 - "010101" & X"011", -- 0x12F: DEC R01 - "110010" & X"12D", -- 0x130: JNZ 0x12D - "111101" & X"000", -- 0x131: POP R00 - "010101" & X"011", -- 0x132: DEC R01 - "110010" & X"131", -- 0x133: JNZ 0x131 - "001111" & X"AA0", -- 0x134: CMP R00, 0xAA - "111010" & X"3FF", -- 0x135: JNE 0x3FF - "111110" & X"000", -- 0x136: RET - "000011" & X"550", -- 0x137: MOV R00, 0x55 - "111100" & X"000", -- 0x138: PUSH R00 - "000011" & X"000", -- 0x139: MOV R00, 0x00 - "000011" & X"FF1", -- 0x13A: MOV R01, 0xFF - "111011" & X"151", -- 0x13B: CALL 0x151 - "111101" & X"000", -- 0x13C: POP R00 - "001111" & X"550", -- 0x13D: CMP R00, 0x55 - "111010" & X"3FF", -- 0x13E: JNE 0x3FF - "000011" & X"010", -- 0x13F: MOV R00, 0x01 - "000011" & X"481", -- 0x140: MOV R01, 0x48 - "100110" & X"050", -- 0x141: COUT (0x05), R00 - "111100" & X"001", -- 0x142: PUSH R01 - "000011" & X"000", -- 0x143: MOV R00, 0x00 - "000011" & X"3B1", -- 0x144: MOV R01, 0x3B - "100110" & X"050", -- 0x145: COUT (0x05), R00 - "111100" & X"001", -- 0x146: PUSH R01 - "111110" & X"000", -- 0x147: RET - "000011" & X"010", -- 0x148: MOV R00, 0x01 - "000011" & X"501", -- 0x149: MOV R01, 0x50 - "100110" & X"050", -- 0x14A: COUT (0x05), R00 - "111100" & X"001", -- 0x14B: PUSH R01 - "000011" & X"000", -- 0x14C: MOV R00, 0x00 - "000011" & X"3B1", -- 0x14D: MOV R01, 0x3B - "100110" & X"050", -- 0x14E: COUT (0x05), R00 - "111100" & X"001", -- 0x14F: PUSH R01 - "111110" & X"000", -- 0x150: RET - "001110" & X"010", -- 0x151: CMP R00, R01 - "111001" & X"155", -- 0x152: JEQ 0x155 - "010001" & X"010", -- 0x153: INC R00 - "110000" & X"158", -- 0x154: JMP 0x158 - "010101" & X"010", -- 0x155: DEC R00 - "010101" & X"011", -- 0x156: DEC R01 - "111110" & X"000", -- 0x157: RET - "111011" & X"151", -- 0x158: CALL 0x151 - "110000" & X"155", -- 0x159: JMP 0x155 - "000011" & X"A50", -- 0x15A: MOV R00, 0xA5 - "000011" & X"5A1", -- 0x15B: MOV R01, 0x5A - "101010" & X"000", -- 0x15C: SWAP R00 - "001111" & X"5A0", -- 0x15D: CMP R00, 0x5A - "111010" & X"3FF", -- 0x15E: JNE 0x3FF - "101010" & X"000", -- 0x15F: SWAP R00 - "001111" & X"A50", -- 0x160: CMP R00, 0xA5 - "111010" & X"3FF", -- 0x161: JNE 0x3FF - "000011" & X"D20", -- 0x162: MOV R00, 0xD2 - "101010" & X"000", -- 0x163: SWAP R00 - "001111" & X"2D0", -- 0x164: CMP R00, 0x2D - "111010" & X"3FF", -- 0x165: JNE 0x3FF - "101010" & X"001", -- 0x166: SWAP R01 - "001111" & X"2D0", -- 0x167: CMP R00, 0x2D - "111010" & X"3FF", -- 0x168: JNE 0x3FF - "001111" & X"A51", -- 0x169: CMP R01, 0xA5 - "111010" & X"3FF", -- 0x16A: JNE 0x3FF - "000011" & X"2D0", -- 0x16B: MOV R00, 0x2D - "011110" & X"000", -- 0x16C: SHL R00 - "001111" & X"5A0", -- 0x16D: CMP R00, 0x5A - "111010" & X"3FF", -- 0x16E: JNE 0x3FF - "011110" & X"000", -- 0x16F: SHL R00 - "001111" & X"B40", -- 0x170: CMP R00, 0xB4 - "111010" & X"3FF", -- 0x171: JNE 0x3FF - "011110" & X"000", -- 0x172: SHL R00 - "001111" & X"680", -- 0x173: CMP R00, 0x68 - "111010" & X"3FF", -- 0x174: JNE 0x3FF - "011110" & X"000", -- 0x175: SHL R00 - "001111" & X"D00", -- 0x176: CMP R00, 0xD0 - "111010" & X"3FF", -- 0x177: JNE 0x3FF - "011110" & X"000", -- 0x178: SHL R00 - "001111" & X"A00", -- 0x179: CMP R00, 0xA0 - "111010" & X"3FF", -- 0x17A: JNE 0x3FF - "011110" & X"000", -- 0x17B: SHL R00 - "001111" & X"400", -- 0x17C: CMP R00, 0x40 - "111010" & X"3FF", -- 0x17D: JNE 0x3FF - "011110" & X"000", -- 0x17E: SHL R00 - "001111" & X"800", -- 0x17F: CMP R00, 0x80 - "111010" & X"3FF", -- 0x180: JNE 0x3FF - "011110" & X"000", -- 0x181: SHL R00 - "001111" & X"000", -- 0x182: CMP R00, 0x00 - "111010" & X"3FF", -- 0x183: JNE 0x3FF - "000011" & X"841", -- 0x184: MOV R01, 0x84 - "011111" & X"001", -- 0x185: SHR R01 - "001111" & X"421", -- 0x186: CMP R01, 0x42 - "111010" & X"3FF", -- 0x187: JNE 0x3FF - "011111" & X"001", -- 0x188: SHR R01 - "001111" & X"211", -- 0x189: CMP R01, 0x21 - "111010" & X"3FF", -- 0x18A: JNE 0x3FF - "011111" & X"001", -- 0x18B: SHR R01 - "001111" & X"101", -- 0x18C: CMP R01, 0x10 - "111010" & X"3FF", -- 0x18D: JNE 0x3FF - "011111" & X"001", -- 0x18E: SHR R01 - "001111" & X"081", -- 0x18F: CMP R01, 0x08 - "111010" & X"3FF", -- 0x190: JNE 0x3FF - "011111" & X"001", -- 0x191: SHR R01 - "001111" & X"041", -- 0x192: CMP R01, 0x04 - "111010" & X"3FF", -- 0x193: JNE 0x3FF - "011111" & X"001", -- 0x194: SHR R01 - "001111" & X"021", -- 0x195: CMP R01, 0x02 - "111010" & X"3FF", -- 0x196: JNE 0x3FF - "011111" & X"001", -- 0x197: SHR R01 - "001111" & X"011", -- 0x198: CMP R01, 0x01 - "111010" & X"3FF", -- 0x199: JNE 0x3FF - "011111" & X"001", -- 0x19A: SHR R01 - "001111" & X"001", -- 0x19B: CMP R01, 0x00 - "111010" & X"3FF", -- 0x19C: JNE 0x3FF - "000011" & X"C50", -- 0x19D: MOV R00, 0xC5 - "100000" & X"000", -- 0x19E: ROL R00 - "001111" & X"8B0", -- 0x19F: CMP R00, 0x8B - "111010" & X"3FF", -- 0x1A0: JNE 0x3FF - "100000" & X"000", -- 0x1A1: ROL R00 - "001111" & X"170", -- 0x1A2: CMP R00, 0x17 - "111010" & X"3FF", -- 0x1A3: JNE 0x3FF - "100000" & X"000", -- 0x1A4: ROL R00 - "001111" & X"2E0", -- 0x1A5: CMP R00, 0x2E - "111010" & X"3FF", -- 0x1A6: JNE 0x3FF - "100000" & X"000", -- 0x1A7: ROL R00 - "001111" & X"5C0", -- 0x1A8: CMP R00, 0x5C - "111010" & X"3FF", -- 0x1A9: JNE 0x3FF - "100000" & X"000", -- 0x1AA: ROL R00 - "001111" & X"B80", -- 0x1AB: CMP R00, 0xB8 - "111010" & X"3FF", -- 0x1AC: JNE 0x3FF - "100000" & X"000", -- 0x1AD: ROL R00 - "001111" & X"710", -- 0x1AE: CMP R00, 0x71 - "111010" & X"3FF", -- 0x1AF: JNE 0x3FF - "100000" & X"000", -- 0x1B0: ROL R00 - "001111" & X"E20", -- 0x1B1: CMP R00, 0xE2 - "111010" & X"3FF", -- 0x1B2: JNE 0x3FF - "100000" & X"000", -- 0x1B3: ROL R00 - "001111" & X"C50", -- 0x1B4: CMP R00, 0xC5 - "111010" & X"3FF", -- 0x1B5: JNE 0x3FF - "000011" & X"631", -- 0x1B6: MOV R01, 0x63 - "100001" & X"001", -- 0x1B7: ROR R01 - "001111" & X"B11", -- 0x1B8: CMP R01, 0xB1 - "111010" & X"3FF", -- 0x1B9: JNE 0x3FF - "100001" & X"001", -- 0x1BA: ROR R01 - "001111" & X"D81", -- 0x1BB: CMP R01, 0xD8 - "111010" & X"3FF", -- 0x1BC: JNE 0x3FF - "100001" & X"001", -- 0x1BD: ROR R01 - "001111" & X"6C1", -- 0x1BE: CMP R01, 0x6C - "111010" & X"3FF", -- 0x1BF: JNE 0x3FF - "100001" & X"001", -- 0x1C0: ROR R01 - "001111" & X"361", -- 0x1C1: CMP R01, 0x36 - "111010" & X"3FF", -- 0x1C2: JNE 0x3FF - "100001" & X"001", -- 0x1C3: ROR R01 - "001111" & X"1B1", -- 0x1C4: CMP R01, 0x1B - "111010" & X"3FF", -- 0x1C5: JNE 0x3FF - "100001" & X"001", -- 0x1C6: ROR R01 - "001111" & X"8D1", -- 0x1C7: CMP R01, 0x8D - "111010" & X"3FF", -- 0x1C8: JNE 0x3FF - "100001" & X"001", -- 0x1C9: ROR R01 - "001111" & X"C61", -- 0x1CA: CMP R01, 0xC6 - "111010" & X"3FF", -- 0x1CB: JNE 0x3FF - "100001" & X"001", -- 0x1CC: ROR R01 - "001111" & X"631", -- 0x1CD: CMP R01, 0x63 - "111010" & X"3FF", -- 0x1CE: JNE 0x3FF - "011100" & X"000", -- 0x1CF: XOR R00, R00 - "000011" & X"C50", -- 0x1D0: MOV R00, 0xC5 - "100010" & X"000", -- 0x1D1: ROLC R00 - "111100" & X"000", -- 0x1D2: PUSH R00 - "100010" & X"000", -- 0x1D3: ROLC R00 - "111100" & X"000", -- 0x1D4: PUSH R00 - "100010" & X"000", -- 0x1D5: ROLC R00 - "111100" & X"000", -- 0x1D6: PUSH R00 - "100010" & X"000", -- 0x1D7: ROLC R00 - "111100" & X"000", -- 0x1D8: PUSH R00 - "100010" & X"000", -- 0x1D9: ROLC R00 - "111100" & X"000", -- 0x1DA: PUSH R00 - "100010" & X"000", -- 0x1DB: ROLC R00 - "111100" & X"000", -- 0x1DC: PUSH R00 - "100010" & X"000", -- 0x1DD: ROLC R00 - "111100" & X"000", -- 0x1DE: PUSH R00 - "100010" & X"000", -- 0x1DF: ROLC R00 - "111100" & X"000", -- 0x1E0: PUSH R00 - "100010" & X"000", -- 0x1E1: ROLC R00 - "001111" & X"C50", -- 0x1E2: CMP R00, 0xC5 - "111010" & X"3FF", -- 0x1E3: JNE 0x3FF - "111101" & X"000", -- 0x1E4: POP R00 - "001111" & X"620", -- 0x1E5: CMP R00, 0x62 - "111010" & X"3FF", -- 0x1E6: JNE 0x3FF - "111101" & X"000", -- 0x1E7: POP R00 - "001111" & X"B10", -- 0x1E8: CMP R00, 0xB1 - "111010" & X"3FF", -- 0x1E9: JNE 0x3FF - "111101" & X"000", -- 0x1EA: POP R00 - "001111" & X"580", -- 0x1EB: CMP R00, 0x58 - "111010" & X"3FF", -- 0x1EC: JNE 0x3FF - "111101" & X"000", -- 0x1ED: POP R00 - "001111" & X"AC0", -- 0x1EE: CMP R00, 0xAC - "111010" & X"3FF", -- 0x1EF: JNE 0x3FF - "111101" & X"000", -- 0x1F0: POP R00 - "001111" & X"560", -- 0x1F1: CMP R00, 0x56 - "111010" & X"3FF", -- 0x1F2: JNE 0x3FF - "111101" & X"000", -- 0x1F3: POP R00 - "001111" & X"2B0", -- 0x1F4: CMP R00, 0x2B - "111010" & X"3FF", -- 0x1F5: JNE 0x3FF - "111101" & X"000", -- 0x1F6: POP R00 - "001111" & X"150", -- 0x1F7: CMP R00, 0x15 - "111010" & X"3FF", -- 0x1F8: JNE 0x3FF - "111101" & X"000", -- 0x1F9: POP R00 - "001111" & X"8A0", -- 0x1FA: CMP R00, 0x8A - "111010" & X"3FF", -- 0x1FB: JNE 0x3FF - "011100" & X"011", -- 0x1FC: XOR R01, R01 - "000011" & X"631", -- 0x1FD: MOV R01, 0x63 - "100011" & X"001", -- 0x1FE: RORC R01 - "111100" & X"001", -- 0x1FF: PUSH R01 - "100011" & X"001", -- 0x200: RORC R01 - "111100" & X"001", -- 0x201: PUSH R01 - "100011" & X"001", -- 0x202: RORC R01 - "111100" & X"001", -- 0x203: PUSH R01 - "100011" & X"001", -- 0x204: RORC R01 - "111100" & X"001", -- 0x205: PUSH R01 - "100011" & X"001", -- 0x206: RORC R01 - "111100" & X"001", -- 0x207: PUSH R01 - "100011" & X"001", -- 0x208: RORC R01 - "111100" & X"001", -- 0x209: PUSH R01 - "100011" & X"001", -- 0x20A: RORC R01 - "111100" & X"001", -- 0x20B: PUSH R01 - "100011" & X"001", -- 0x20C: RORC R01 - "111100" & X"001", -- 0x20D: PUSH R01 - "100011" & X"001", -- 0x20E: RORC R01 - "001111" & X"631", -- 0x20F: CMP R01, 0x63 - "111010" & X"3FF", -- 0x210: JNE 0x3FF - "111101" & X"001", -- 0x211: POP R01 - "001111" & X"C61", -- 0x212: CMP R01, 0xC6 - "111010" & X"3FF", -- 0x213: JNE 0x3FF - "111101" & X"001", -- 0x214: POP R01 - "001111" & X"8C1", -- 0x215: CMP R01, 0x8C - "111010" & X"3FF", -- 0x216: JNE 0x3FF - "111101" & X"001", -- 0x217: POP R01 - "001111" & X"191", -- 0x218: CMP R01, 0x19 - "111010" & X"3FF", -- 0x219: JNE 0x3FF - "111101" & X"001", -- 0x21A: POP R01 - "001111" & X"331", -- 0x21B: CMP R01, 0x33 - "111010" & X"3FF", -- 0x21C: JNE 0x3FF - "111101" & X"001", -- 0x21D: POP R01 - "001111" & X"661", -- 0x21E: CMP R01, 0x66 - "111010" & X"3FF", -- 0x21F: JNE 0x3FF - "111101" & X"001", -- 0x220: POP R01 - "001111" & X"CC1", -- 0x221: CMP R01, 0xCC - "111010" & X"3FF", -- 0x222: JNE 0x3FF - "111101" & X"001", -- 0x223: POP R01 - "001111" & X"981", -- 0x224: CMP R01, 0x98 - "111010" & X"3FF", -- 0x225: JNE 0x3FF - "111101" & X"001", -- 0x226: POP R01 - "001111" & X"311", -- 0x227: CMP R01, 0x31 - "111010" & X"3FF", -- 0x228: JNE 0x3FF - "111110" & X"000", -- 0x229: RET - "000011" & X"A50", -- 0x22A: MOV R00, 0xA5 - "101010" & X"000", -- 0x22B: SWAP R00 - "111100" & X"000", -- 0x22C: PUSH R00 - "011001" & X"0F0", -- 0x22D: AND R00, 0x0F - "001111" & X"0A0", -- 0x22E: CMP R00, 0x0A - "111010" & X"3FF", -- 0x22F: JNE 0x3FF - "111101" & X"000", -- 0x230: POP R00 - "111100" & X"000", -- 0x231: PUSH R00 - "011001" & X"0F0", -- 0x232: AND R00, 0x0F - "001111" & X"0A0", -- 0x233: CMP R00, 0x0A - "111101" & X"001", -- 0x234: POP R01 - "111010" & X"3FF", -- 0x235: JNE 0x3FF - "101010" & X"001", -- 0x236: SWAP R01 - "000011" & X"0F2", -- 0x237: MOV R02, 0x0F - "011000" & X"021", -- 0x238: AND R01, R02 - "001111" & X"051", -- 0x239: CMP R01, 0x05 - "111010" & X"3FF", -- 0x23A: JNE 0x3FF - "000011" & X"050", -- 0x23B: MOV R00, 0x05 - "000011" & X"A02", -- 0x23C: MOV R02, 0xA0 - "101010" & X"000", -- 0x23D: SWAP R00 - "011010" & X"002", -- 0x23E: OR R02, R00 - "001111" & X"F02", -- 0x23F: CMP R02, 0xF0 - "111010" & X"3FF", -- 0x240: JNE 0x3FF - "101010" & X"000", -- 0x241: SWAP R00 - "011011" & X"500", -- 0x242: OR R00, 0x50 - "001111" & X"550", -- 0x243: CMP R00, 0x55 - "111010" & X"3FF", -- 0x244: JNE 0x3FF - "000011" & X"011", -- 0x245: MOV R01, 0x01 - "000011" & X"010", -- 0x246: MOV R00, 0x01 - "011101" & X"010", -- 0x247: XOR R00, 0x01 - "110010" & X"3FF", -- 0x248: JNZ 0x3FF - "011100" & X"010", -- 0x249: XOR R00, R01 - "001111" & X"010", -- 0x24A: CMP R00, 0x01 - "111010" & X"3FF", -- 0x24B: JNE 0x3FF - "111110" & X"000", -- 0x24C: RET - "000011" & X"030", -- 0x24D: MOV R00, 0x03 - "100110" & X"030", -- 0x24E: COUT (0x03), R00 - "101000" & X"020", -- 0x24F: XIN R00, (0x02) - "011011" & X"010", -- 0x250: OR R00, 0x01 - "100100" & X"020", -- 0x251: XOUT (0x02), R00 - "000000" & X"000", -- 0x252: NOP - "000000" & X"000", -- 0x253: NOP - "000000" & X"000", -- 0x254: NOP - "000000" & X"000", -- 0x255: NOP - "000000" & X"000", -- 0x256: NOP - "000000" & X"000", -- 0x257: NOP - "101000" & X"020", -- 0x258: XIN R00, (0x02) - "011001" & X"FE0", -- 0x259: AND R00, 0xFE - "100100" & X"020", -- 0x25A: XOUT (0x02), R00 - "000000" & X"000", -- 0x25B: NOP - "000000" & X"000", -- 0x25C: NOP - "000000" & X"000", -- 0x25D: NOP - "000000" & X"000", -- 0x25E: NOP - "101001" & X"030", -- 0x25F: CIN R00, (0x03) - "011011" & X"800", -- 0x260: OR R00, 0x80 - "100110" & X"030", -- 0x261: COUT (0x03), R00 - "000000" & X"000", -- 0x262: NOP - "101001" & X"030", -- 0x263: CIN R00, (0x03) - "011011" & X"800", -- 0x264: OR R00, 0x80 - "100110" & X"030", -- 0x265: COUT (0x03), R00 - "000000" & X"000", -- 0x266: NOP - "101001" & X"030", -- 0x267: CIN R00, (0x03) - "011011" & X"800", -- 0x268: OR R00, 0x80 - "100110" & X"030", -- 0x269: COUT (0x03), R00 - "000000" & X"000", -- 0x26A: NOP - "101001" & X"030", -- 0x26B: CIN R00, (0x03) - "011011" & X"800", -- 0x26C: OR R00, 0x80 - "100110" & X"030", -- 0x26D: COUT (0x03), R00 - "000000" & X"000", -- 0x26E: NOP - "000000" & X"000", -- 0x26F: NOP - "000000" & X"000", -- 0x270: NOP - "000000" & X"000", -- 0x271: NOP - "000000" & X"000", -- 0x272: NOP - "000000" & X"000", -- 0x273: NOP - "000000" & X"000", -- 0x274: NOP - "000000" & X"000", -- 0x275: NOP - "000000" & X"000", -- 0x276: NOP - "111110" & X"000", -- 0x277: RET - "010101" & X"000", -- 0x278: SUB R00, 0x00 - "110011" & X"3FF", -- 0x279: JC 0x3FF - "101011" & X"000", -- 0x27A: SETC - "110100" & X"3FF", -- 0x27B: JNC 0x3FF - "000000" & X"000", -- 0x27C: NOP - "010101" & X"000", -- 0x27D: SUB R00, 0x00 - "110011" & X"3FF", -- 0x27E: JC 0x3FF - "000011" & X"000", -- 0x27F: MOV R00, 0x00 - "010101" & X"000", -- 0x280: CLRC - "110011" & X"3FF", -- 0x281: JC 0x3FF - "101011" & X"000", -- 0x282: SETC - "110100" & X"3FF", -- 0x283: JNC 0x3FF - "000000" & X"000", -- 0x284: NOP - "010101" & X"000", -- 0x285: CLRC - "110011" & X"3FF", -- 0x286: JC 0x3FF - "111110" & X"000", -- 0x287: RET - "010001" & X"01E", -- 0x288: INC R14 - "111111" & X"000", -- 0x289: RETI - "000000" & X"000", -- 0x28A: - "000000" & X"000", -- 0x28B: - "000000" & X"000", -- 0x28C: - "000000" & X"000", -- 0x28D: - "000000" & X"000", -- 0x28E: - "000000" & X"000", -- 0x28F: - "000000" & X"000", -- 0x290: - "000000" & X"000", -- 0x291: - "000000" & X"000", -- 0x292: - "000000" & X"000", -- 0x293: - "000000" & X"000", -- 0x294: - "000000" & X"000", -- 0x295: - "000000" & X"000", -- 0x296: - "000000" & X"000", -- 0x297: - "000000" & X"000", -- 0x298: - "000000" & X"000", -- 0x299: - "000000" & X"000", -- 0x29A: - "000000" & X"000", -- 0x29B: - "000000" & X"000", -- 0x29C: - "000000" & X"000", -- 0x29D: - "000000" & X"000", -- 0x29E: - "000000" & X"000", -- 0x29F: - "000000" & X"000", -- 0x2A0: - "000000" & X"000", -- 0x2A1: - "000000" & X"000", -- 0x2A2: - "000000" & X"000", -- 0x2A3: - "000000" & X"000", -- 0x2A4: - "000000" & X"000", -- 0x2A5: - "000000" & X"000", -- 0x2A6: - "000000" & X"000", -- 0x2A7: - "000000" & X"000", -- 0x2A8: - "000000" & X"000", -- 0x2A9: - "000000" & X"000", -- 0x2AA: - "000000" & X"000", -- 0x2AB: - "000000" & X"000", -- 0x2AC: - "000000" & X"000", -- 0x2AD: - "000000" & X"000", -- 0x2AE: - "000000" & X"000", -- 0x2AF: - "000000" & X"000", -- 0x2B0: - "000000" & X"000", -- 0x2B1: - "000000" & X"000", -- 0x2B2: - "000000" & X"000", -- 0x2B3: - "000000" & X"000", -- 0x2B4: - "000000" & X"000", -- 0x2B5: - "000000" & X"000", -- 0x2B6: - "000000" & X"000", -- 0x2B7: - "000000" & X"000", -- 0x2B8: - "000000" & X"000", -- 0x2B9: - "000000" & X"000", -- 0x2BA: - "000000" & X"000", -- 0x2BB: - "000000" & X"000", -- 0x2BC: - "000000" & X"000", -- 0x2BD: - "000000" & X"000", -- 0x2BE: - "000000" & X"000", -- 0x2BF: - "000000" & X"000", -- 0x2C0: - "000000" & X"000", -- 0x2C1: - "000000" & X"000", -- 0x2C2: - "000000" & X"000", -- 0x2C3: - "000000" & X"000", -- 0x2C4: - "000000" & X"000", -- 0x2C5: - "000000" & X"000", -- 0x2C6: - "000000" & X"000", -- 0x2C7: - "000000" & X"000", -- 0x2C8: - "000000" & X"000", -- 0x2C9: - "000000" & X"000", -- 0x2CA: - "000000" & X"000", -- 0x2CB: - "000000" & X"000", -- 0x2CC: - "000000" & X"000", -- 0x2CD: - "000000" & X"000", -- 0x2CE: - "000000" & X"000", -- 0x2CF: - "000000" & X"000", -- 0x2D0: - "000000" & X"000", -- 0x2D1: - "000000" & X"000", -- 0x2D2: - "000000" & X"000", -- 0x2D3: - "000000" & X"000", -- 0x2D4: - "000000" & X"000", -- 0x2D5: - "000000" & X"000", -- 0x2D6: - "000000" & X"000", -- 0x2D7: - "000000" & X"000", -- 0x2D8: - "000000" & X"000", -- 0x2D9: - "000000" & X"000", -- 0x2DA: - "000000" & X"000", -- 0x2DB: - "000000" & X"000", -- 0x2DC: - "000000" & X"000", -- 0x2DD: - "000000" & X"000", -- 0x2DE: - "000000" & X"000", -- 0x2DF: - "000000" & X"000", -- 0x2E0: - "000000" & X"000", -- 0x2E1: - "000000" & X"000", -- 0x2E2: - "000000" & X"000", -- 0x2E3: - "000000" & X"000", -- 0x2E4: - "000000" & X"000", -- 0x2E5: - "000000" & X"000", -- 0x2E6: - "000000" & X"000", -- 0x2E7: - "000000" & X"000", -- 0x2E8: - "000000" & X"000", -- 0x2E9: - "000000" & X"000", -- 0x2EA: - "000000" & X"000", -- 0x2EB: - "000000" & X"000", -- 0x2EC: - "000000" & X"000", -- 0x2ED: - "000000" & X"000", -- 0x2EE: - "000000" & X"000", -- 0x2EF: - "000000" & X"000", -- 0x2F0: - "000000" & X"000", -- 0x2F1: - "000000" & X"000", -- 0x2F2: - "000000" & X"000", -- 0x2F3: - "000000" & X"000", -- 0x2F4: - "000000" & X"000", -- 0x2F5: - "000000" & X"000", -- 0x2F6: - "000000" & X"000", -- 0x2F7: - "000000" & X"000", -- 0x2F8: - "000000" & X"000", -- 0x2F9: - "000000" & X"000", -- 0x2FA: - "000000" & X"000", -- 0x2FB: - "000000" & X"000", -- 0x2FC: - "000000" & X"000", -- 0x2FD: - "000000" & X"000", -- 0x2FE: - "110000" & X"2FF", -- 0x2FF: JMP 0x2FF - "000000" & X"000", -- 0x300: - "000000" & X"000", -- 0x301: - "000000" & X"000", -- 0x302: - "000000" & X"000", -- 0x303: - "000000" & X"000", -- 0x304: - "000000" & X"000", -- 0x305: - "000000" & X"000", -- 0x306: - "000000" & X"000", -- 0x307: - "000000" & X"000", -- 0x308: - "000000" & X"000", -- 0x309: - "000000" & X"000", -- 0x30A: - "000000" & X"000", -- 0x30B: - "000000" & X"000", -- 0x30C: - "000000" & X"000", -- 0x30D: - "000000" & X"000", -- 0x30E: - "000000" & X"000", -- 0x30F: - "000000" & X"000", -- 0x310: - "000000" & X"000", -- 0x311: - "000000" & X"000", -- 0x312: - "000000" & X"000", -- 0x313: - "000000" & X"000", -- 0x314: - "000000" & X"000", -- 0x315: - "000000" & X"000", -- 0x316: - "000000" & X"000", -- 0x317: - "000000" & X"000", -- 0x318: - "000000" & X"000", -- 0x319: - "000000" & X"000", -- 0x31A: - "000000" & X"000", -- 0x31B: - "000000" & X"000", -- 0x31C: - "000000" & X"000", -- 0x31D: - "000000" & X"000", -- 0x31E: - "000000" & X"000", -- 0x31F: - "000000" & X"000", -- 0x320: - "000000" & X"000", -- 0x321: - "000000" & X"000", -- 0x322: - "000000" & X"000", -- 0x323: - "000000" & X"000", -- 0x324: - "000000" & X"000", -- 0x325: - "000000" & X"000", -- 0x326: - "000000" & X"000", -- 0x327: - "000000" & X"000", -- 0x328: - "000000" & X"000", -- 0x329: - "000000" & X"000", -- 0x32A: - "000000" & X"000", -- 0x32B: - "000000" & X"000", -- 0x32C: - "000000" & X"000", -- 0x32D: - "000000" & X"000", -- 0x32E: - "000000" & X"000", -- 0x32F: - "000000" & X"000", -- 0x330: - "000000" & X"000", -- 0x331: - "000000" & X"000", -- 0x332: - "000000" & X"000", -- 0x333: - "000000" & X"000", -- 0x334: - "000000" & X"000", -- 0x335: - "000000" & X"000", -- 0x336: - "000000" & X"000", -- 0x337: - "000000" & X"000", -- 0x338: - "000000" & X"000", -- 0x339: - "000000" & X"000", -- 0x33A: - "000000" & X"000", -- 0x33B: - "000000" & X"000", -- 0x33C: - "000000" & X"000", -- 0x33D: - "000000" & X"000", -- 0x33E: - "000000" & X"000", -- 0x33F: - "000000" & X"000", -- 0x340: - "000000" & X"000", -- 0x341: - "000000" & X"000", -- 0x342: - "000000" & X"000", -- 0x343: - "000000" & X"000", -- 0x344: - "000000" & X"000", -- 0x345: - "000000" & X"000", -- 0x346: - "000000" & X"000", -- 0x347: - "000000" & X"000", -- 0x348: - "000000" & X"000", -- 0x349: - "000000" & X"000", -- 0x34A: - "000000" & X"000", -- 0x34B: - "000000" & X"000", -- 0x34C: - "000000" & X"000", -- 0x34D: - "000000" & X"000", -- 0x34E: - "000000" & X"000", -- 0x34F: - "000000" & X"000", -- 0x350: - "000000" & X"000", -- 0x351: - "000000" & X"000", -- 0x352: - "000000" & X"000", -- 0x353: - "000000" & X"000", -- 0x354: - "000000" & X"000", -- 0x355: - "000000" & X"000", -- 0x356: - "000000" & X"000", -- 0x357: - "000000" & X"000", -- 0x358: - "000000" & X"000", -- 0x359: - "000000" & X"000", -- 0x35A: - "000000" & X"000", -- 0x35B: - "000000" & X"000", -- 0x35C: - "000000" & X"000", -- 0x35D: - "000000" & X"000", -- 0x35E: - "000000" & X"000", -- 0x35F: - "000000" & X"000", -- 0x360: - "000000" & X"000", -- 0x361: - "000000" & X"000", -- 0x362: - "000000" & X"000", -- 0x363: - "000000" & X"000", -- 0x364: - "000000" & X"000", -- 0x365: - "000000" & X"000", -- 0x366: - "000000" & X"000", -- 0x367: - "000000" & X"000", -- 0x368: - "000000" & X"000", -- 0x369: - "000000" & X"000", -- 0x36A: - "000000" & X"000", -- 0x36B: - "000000" & X"000", -- 0x36C: - "000000" & X"000", -- 0x36D: - "000000" & X"000", -- 0x36E: - "000000" & X"000", -- 0x36F: - "000000" & X"000", -- 0x370: - "000000" & X"000", -- 0x371: - "000000" & X"000", -- 0x372: - "000000" & X"000", -- 0x373: - "000000" & X"000", -- 0x374: - "000000" & X"000", -- 0x375: - "000000" & X"000", -- 0x376: - "000000" & X"000", -- 0x377: - "000000" & X"000", -- 0x378: - "000000" & X"000", -- 0x379: - "000000" & X"000", -- 0x37A: - "000000" & X"000", -- 0x37B: - "000000" & X"000", -- 0x37C: - "000000" & X"000", -- 0x37D: - "000000" & X"000", -- 0x37E: - "000000" & X"000", -- 0x37F: - "000000" & X"000", -- 0x380: - "000000" & X"000", -- 0x381: - "000000" & X"000", -- 0x382: - "000000" & X"000", -- 0x383: - "000000" & X"000", -- 0x384: - "000000" & X"000", -- 0x385: - "000000" & X"000", -- 0x386: - "000000" & X"000", -- 0x387: - "000000" & X"000", -- 0x388: - "000000" & X"000", -- 0x389: - "000000" & X"000", -- 0x38A: - "000000" & X"000", -- 0x38B: - "000000" & X"000", -- 0x38C: - "000000" & X"000", -- 0x38D: - "000000" & X"000", -- 0x38E: - "000000" & X"000", -- 0x38F: - "000000" & X"000", -- 0x390: - "000000" & X"000", -- 0x391: - "000000" & X"000", -- 0x392: - "000000" & X"000", -- 0x393: - "000000" & X"000", -- 0x394: - "000000" & X"000", -- 0x395: - "000000" & X"000", -- 0x396: - "000000" & X"000", -- 0x397: - "000000" & X"000", -- 0x398: - "000000" & X"000", -- 0x399: - "000000" & X"000", -- 0x39A: - "000000" & X"000", -- 0x39B: - "000000" & X"000", -- 0x39C: - "000000" & X"000", -- 0x39D: - "000000" & X"000", -- 0x39E: - "000000" & X"000", -- 0x39F: - "000000" & X"000", -- 0x3A0: - "000000" & X"000", -- 0x3A1: - "000000" & X"000", -- 0x3A2: - "000000" & X"000", -- 0x3A3: - "000000" & X"000", -- 0x3A4: - "000000" & X"000", -- 0x3A5: - "000000" & X"000", -- 0x3A6: - "000000" & X"000", -- 0x3A7: - "000000" & X"000", -- 0x3A8: - "000000" & X"000", -- 0x3A9: - "000000" & X"000", -- 0x3AA: - "000000" & X"000", -- 0x3AB: - "000000" & X"000", -- 0x3AC: - "000000" & X"000", -- 0x3AD: - "000000" & X"000", -- 0x3AE: - "000000" & X"000", -- 0x3AF: - "000000" & X"000", -- 0x3B0: - "000000" & X"000", -- 0x3B1: - "000000" & X"000", -- 0x3B2: - "000000" & X"000", -- 0x3B3: - "000000" & X"000", -- 0x3B4: - "000000" & X"000", -- 0x3B5: - "000000" & X"000", -- 0x3B6: - "000000" & X"000", -- 0x3B7: - "000000" & X"000", -- 0x3B8: - "000000" & X"000", -- 0x3B9: - "000000" & X"000", -- 0x3BA: - "000000" & X"000", -- 0x3BB: - "000000" & X"000", -- 0x3BC: - "000000" & X"000", -- 0x3BD: - "000000" & X"000", -- 0x3BE: - "000000" & X"000", -- 0x3BF: - "000000" & X"000", -- 0x3C0: - "000000" & X"000", -- 0x3C1: - "000000" & X"000", -- 0x3C2: - "000000" & X"000", -- 0x3C3: - "000000" & X"000", -- 0x3C4: - "000000" & X"000", -- 0x3C5: - "000000" & X"000", -- 0x3C6: - "000000" & X"000", -- 0x3C7: - "000000" & X"000", -- 0x3C8: - "000000" & X"000", -- 0x3C9: - "000000" & X"000", -- 0x3CA: - "000000" & X"000", -- 0x3CB: - "000000" & X"000", -- 0x3CC: - "000000" & X"000", -- 0x3CD: - "000000" & X"000", -- 0x3CE: - "000000" & X"000", -- 0x3CF: - "000000" & X"000", -- 0x3D0: - "000000" & X"000", -- 0x3D1: - "000000" & X"000", -- 0x3D2: - "000000" & X"000", -- 0x3D3: - "000000" & X"000", -- 0x3D4: - "000000" & X"000", -- 0x3D5: - "000000" & X"000", -- 0x3D6: - "000000" & X"000", -- 0x3D7: - "000000" & X"000", -- 0x3D8: - "000000" & X"000", -- 0x3D9: - "000000" & X"000", -- 0x3DA: - "000000" & X"000", -- 0x3DB: - "000000" & X"000", -- 0x3DC: - "000000" & X"000", -- 0x3DD: - "000000" & X"000", -- 0x3DE: - "000000" & X"000", -- 0x3DF: - "000000" & X"000", -- 0x3E0: - "000000" & X"000", -- 0x3E1: - "000000" & X"000", -- 0x3E2: - "000000" & X"000", -- 0x3E3: - "000000" & X"000", -- 0x3E4: - "000000" & X"000", -- 0x3E5: - "000000" & X"000", -- 0x3E6: - "000000" & X"000", -- 0x3E7: - "000000" & X"000", -- 0x3E8: - "000000" & X"000", -- 0x3E9: - "000000" & X"000", -- 0x3EA: - "000000" & X"000", -- 0x3EB: - "000000" & X"000", -- 0x3EC: - "000000" & X"000", -- 0x3ED: - "000000" & X"000", -- 0x3EE: - "000000" & X"000", -- 0x3EF: - "000000" & X"000", -- 0x3F0: - "000000" & X"000", -- 0x3F1: - "000000" & X"000", -- 0x3F2: - "000000" & X"000", -- 0x3F3: - "000000" & X"000", -- 0x3F4: - "000000" & X"000", -- 0x3F5: - "000000" & X"000", -- 0x3F6: - "000000" & X"000", -- 0x3F7: - "000000" & X"000", -- 0x3F8: - "000000" & X"000", -- 0x3F9: - "000000" & X"000", -- 0x3FA: - "000000" & X"000", -- 0x3FB: - "000000" & X"000", -- 0x3FC: - "000000" & X"000", -- 0x3FD: - "000000" & X"000", -- 0x3FE: - "110000" & X"3FF" -- 0x3FF: JMP 0x3FF - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -end itest; - diff --git a/lib/CPUs/JCpu/src/itest_irom_ld.vhdl b/lib/CPUs/JCpu/src/itest_irom_ld.vhdl deleted file mode 100644 index d4371a1..0000000 --- a/lib/CPUs/JCpu/src/itest_irom_ld.vhdl +++ /dev/null @@ -1,1181 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from itest.jsm - type imem_rom_t is array (0 to 1023) of inst_t; - signal imem_rom : imem_rom_t := - ( - "110000" & X"010", -- 0x000: JMP 0x010 - "110000" & X"288", -- 0x001: JMP 0x288 - "000000" & X"000", -- 0x002: - "000000" & X"000", -- 0x003: - "000000" & X"000", -- 0x004: - "000000" & X"000", -- 0x005: - "000000" & X"000", -- 0x006: - "000000" & X"000", -- 0x007: - "000000" & X"000", -- 0x008: - "000000" & X"000", -- 0x009: - "000000" & X"000", -- 0x00A: - "000000" & X"000", -- 0x00B: - "000000" & X"000", -- 0x00C: - "000000" & X"000", -- 0x00D: - "000000" & X"000", -- 0x00E: - "000000" & X"000", -- 0x00F: - "111011" & X"03B", -- 0x010: CALL 0x03B - "101001" & X"000", -- 0x011: CIN R00, (0x00) - "100100" & X"000", -- 0x012: XOUT (0x00), R00 - "111011" & X"04C", -- 0x013: CALL 0x04C - "000011" & X"010", -- 0x014: MOV R00, 0x01 - "100100" & X"010", -- 0x015: XOUT (0x01), R00 - "111011" & X"08D", -- 0x016: CALL 0x08D - "000011" & X"020", -- 0x017: MOV R00, 0x02 - "100100" & X"010", -- 0x018: XOUT (0x01), R00 - "111011" & X"0C9", -- 0x019: CALL 0x0C9 - "000011" & X"030", -- 0x01A: MOV R00, 0x03 - "100100" & X"010", -- 0x01B: XOUT (0x01), R00 - "111011" & X"0DB", -- 0x01C: CALL 0x0DB - "000011" & X"040", -- 0x01D: MOV R00, 0x04 - "100100" & X"010", -- 0x01E: XOUT (0x01), R00 - "111011" & X"0ED", -- 0x01F: CALL 0x0ED - "000011" & X"050", -- 0x020: MOV R00, 0x05 - "100100" & X"010", -- 0x021: XOUT (0x01), R00 - "111011" & X"0FF", -- 0x022: CALL 0x0FF - "000011" & X"060", -- 0x023: MOV R00, 0x06 - "100100" & X"010", -- 0x024: XOUT (0x01), R00 - "111011" & X"115", -- 0x025: CALL 0x115 - "000011" & X"070", -- 0x026: MOV R00, 0x07 - "100100" & X"010", -- 0x027: XOUT (0x01), R00 - "111011" & X"12B", -- 0x028: CALL 0x12B - "000011" & X"080", -- 0x029: MOV R00, 0x08 - "100100" & X"010", -- 0x02A: XOUT (0x01), R00 - "111011" & X"137", -- 0x02B: CALL 0x137 - "000011" & X"090", -- 0x02C: MOV R00, 0x09 - "100100" & X"010", -- 0x02D: XOUT (0x01), R00 - "111011" & X"15A", -- 0x02E: CALL 0x15A - "000011" & X"0A0", -- 0x02F: MOV R00, 0x0A - "100100" & X"010", -- 0x030: XOUT (0x01), R00 - "111011" & X"22A", -- 0x031: CALL 0x22A - "000011" & X"0B0", -- 0x032: MOV R00, 0x0B - "100100" & X"010", -- 0x033: XOUT (0x01), R00 - "111011" & X"24D", -- 0x034: CALL 0x24D - "000011" & X"0C0", -- 0x035: MOV R00, 0x0C - "100100" & X"010", -- 0x036: XOUT (0x01), R00 - "111011" & X"278", -- 0x037: CALL 0x278 - "000011" & X"FF0", -- 0x038: MOV R00, 0xFF - "100100" & X"010", -- 0x039: XOUT (0x01), R00 - "110000" & X"2FF", -- 0x03A: JMP 0x2FF - "000011" & X"000", -- 0x03B: MOV R00, 0x00 - "000011" & X"001", -- 0x03C: MOV R01, 0x00 - "000011" & X"002", -- 0x03D: MOV R02, 0x00 - "000011" & X"003", -- 0x03E: MOV R03, 0x00 - "000011" & X"004", -- 0x03F: MOV R04, 0x00 - "000011" & X"005", -- 0x040: MOV R05, 0x00 - "000011" & X"006", -- 0x041: MOV R06, 0x00 - "000011" & X"007", -- 0x042: MOV R07, 0x00 - "000011" & X"008", -- 0x043: MOV R08, 0x00 - "000011" & X"009", -- 0x044: MOV R09, 0x00 - "000011" & X"00A", -- 0x045: MOV R10, 0x00 - "000011" & X"00B", -- 0x046: MOV R11, 0x00 - "000011" & X"00C", -- 0x047: MOV R12, 0x00 - "000011" & X"00D", -- 0x048: MOV R13, 0x00 - "000011" & X"00E", -- 0x049: MOV R14, 0x00 - "000011" & X"00F", -- 0x04A: MOV R15, 0x00 - "111110" & X"000", -- 0x04B: RET - "000011" & X"100", -- 0x04C: MOV R00, 0x10 - "001111" & X"100", -- 0x04D: CMP R00, 0x10 - "111010" & X"3FF", -- 0x04E: JNE 0x3FF - "010001" & X"010", -- 0x04F: ADD R00, 0x01 - "000010" & X"001", -- 0x050: MOV R01, R00 - "001111" & X"111", -- 0x051: CMP R01, 0x11 - "111010" & X"3FF", -- 0x052: JNE 0x3FF - "010001" & X"011", -- 0x053: ADD R01, 0x01 - "000010" & X"012", -- 0x054: MOV R02, R01 - "001111" & X"122", -- 0x055: CMP R02, 0x12 - "111010" & X"3FF", -- 0x056: JNE 0x3FF - "010001" & X"012", -- 0x057: ADD R02, 0x01 - "000010" & X"023", -- 0x058: MOV R03, R02 - "001111" & X"133", -- 0x059: CMP R03, 0x13 - "111010" & X"3FF", -- 0x05A: JNE 0x3FF - "010001" & X"013", -- 0x05B: ADD R03, 0x01 - "000010" & X"034", -- 0x05C: MOV R04, R03 - "001111" & X"144", -- 0x05D: CMP R04, 0x14 - "111010" & X"3FF", -- 0x05E: JNE 0x3FF - "010001" & X"014", -- 0x05F: ADD R04, 0x01 - "000010" & X"045", -- 0x060: MOV R05, R04 - "001111" & X"155", -- 0x061: CMP R05, 0x15 - "111010" & X"3FF", -- 0x062: JNE 0x3FF - "010001" & X"015", -- 0x063: ADD R05, 0x01 - "000010" & X"056", -- 0x064: MOV R06, R05 - "001111" & X"166", -- 0x065: CMP R06, 0x16 - "111010" & X"3FF", -- 0x066: JNE 0x3FF - "010001" & X"016", -- 0x067: ADD R06, 0x01 - "000010" & X"067", -- 0x068: MOV R07, R06 - "001111" & X"177", -- 0x069: CMP R07, 0x17 - "111010" & X"3FF", -- 0x06A: JNE 0x3FF - "010001" & X"017", -- 0x06B: ADD R07, 0x01 - "000010" & X"078", -- 0x06C: MOV R08, R07 - "001111" & X"188", -- 0x06D: CMP R08, 0x18 - "111010" & X"3FF", -- 0x06E: JNE 0x3FF - "010001" & X"018", -- 0x06F: ADD R08, 0x01 - "000010" & X"089", -- 0x070: MOV R09, R08 - "001111" & X"199", -- 0x071: CMP R09, 0x19 - "111010" & X"3FF", -- 0x072: JNE 0x3FF - "010001" & X"019", -- 0x073: ADD R09, 0x01 - "000010" & X"09A", -- 0x074: MOV R10, R09 - "001111" & X"1AA", -- 0x075: CMP R10, 0x1A - "111010" & X"3FF", -- 0x076: JNE 0x3FF - "010001" & X"01A", -- 0x077: ADD R10, 0x01 - "000010" & X"0AB", -- 0x078: MOV R11, R10 - "001111" & X"1BB", -- 0x079: CMP R11, 0x1B - "111010" & X"3FF", -- 0x07A: JNE 0x3FF - "010001" & X"01B", -- 0x07B: ADD R11, 0x01 - "000010" & X"0BC", -- 0x07C: MOV R12, R11 - "001111" & X"1CC", -- 0x07D: CMP R12, 0x1C - "111010" & X"3FF", -- 0x07E: JNE 0x3FF - "010001" & X"01C", -- 0x07F: ADD R12, 0x01 - "000010" & X"0CD", -- 0x080: MOV R13, R12 - "001111" & X"1DD", -- 0x081: CMP R13, 0x1D - "111010" & X"3FF", -- 0x082: JNE 0x3FF - "010001" & X"01D", -- 0x083: ADD R13, 0x01 - "000010" & X"0DE", -- 0x084: MOV R14, R13 - "001111" & X"1EE", -- 0x085: CMP R14, 0x1E - "111010" & X"3FF", -- 0x086: JNE 0x3FF - "010001" & X"01E", -- 0x087: ADD R14, 0x01 - "000010" & X"0EF", -- 0x088: MOV R15, R14 - "001111" & X"1FF", -- 0x089: CMP R15, 0x1F - "111010" & X"3FF", -- 0x08A: JNE 0x3FF - "010001" & X"01F", -- 0x08B: ADD R15, 0x01 - "111110" & X"000", -- 0x08C: RET - "000011" & X"000", -- 0x08D: MOV R00, 0x00 - "001111" & X"000", -- 0x08E: TST R00 - "110010" & X"3FF", -- 0x08F: JNZ 0x3FF - "110011" & X"3FF", -- 0x090: JC 0x3FF - "001111" & X"000", -- 0x091: CMP R00, 0x00 - "111010" & X"3FF", -- 0x092: JNE 0x3FF - "110101" & X"3FF", -- 0x093: JLT 0x3FF - "110110" & X"3FF", -- 0x094: JGT 0x3FF - "110111" & X"097", -- 0x095: JLE 0x097 - "110000" & X"3FF", -- 0x096: JMP 0x3FF - "111001" & X"099", -- 0x097: JEQ 0x099 - "110000" & X"3FF", -- 0x098: JMP 0x3FF - "111000" & X"09B", -- 0x099: JGE 0x09B - "110000" & X"3FF", -- 0x09A: JMP 0x3FF - "001111" & X"550", -- 0x09B: CMP R00, 0x55 - "111001" & X"3FF", -- 0x09C: JEQ 0x3FF - "110101" & X"09F", -- 0x09D: JLT 0x09F - "110000" & X"3FF", -- 0x09E: JMP 0x3FF - "110111" & X"0A1", -- 0x09F: JLE 0x0A1 - "110000" & X"3FF", -- 0x0A0: JMP 0x3FF - "111000" & X"3FF", -- 0x0A1: JGE 0x3FF - "110110" & X"3FF", -- 0x0A2: JGT 0x3FF - "000011" & X"550", -- 0x0A3: MOV R00, 0x55 - "001111" & X"000", -- 0x0A4: TST R00 - "110001" & X"3FF", -- 0x0A5: JZ 0x3FF - "110011" & X"3FF", -- 0x0A6: JC 0x3FF - "001111" & X"AA0", -- 0x0A7: CMP R00, 0xAA - "111001" & X"3FF", -- 0x0A8: JEQ 0x3FF - "111010" & X"0AB", -- 0x0A9: JNE 0x0AB - "110000" & X"3FF", -- 0x0AA: JMP 0x3FF - "110101" & X"0AD", -- 0x0AB: JLT 0x0AD - "110000" & X"3FF", -- 0x0AC: JMP 0x3FF - "110111" & X"0AF", -- 0x0AD: JLE 0x0AF - "110000" & X"3FF", -- 0x0AE: JMP 0x3FF - "110110" & X"3FF", -- 0x0AF: JGT 0x3FF - "001111" & X"550", -- 0x0B0: CMP R00, 0x55 - "111001" & X"0B3", -- 0x0B1: JEQ 0x0B3 - "110000" & X"3FF", -- 0x0B2: JMP 0x3FF - "111010" & X"3FF", -- 0x0B3: JNE 0x3FF - "110101" & X"3FF", -- 0x0B4: JLT 0x3FF - "110111" & X"0B7", -- 0x0B5: JLE 0x0B7 - "110000" & X"3FF", -- 0x0B6: JMP 0x3FF - "110110" & X"3FF", -- 0x0B7: JGT 0x3FF - "111000" & X"0BA", -- 0x0B8: JGE 0x0BA - "110000" & X"3FF", -- 0x0B9: JMP 0x3FF - "000011" & X"AA0", -- 0x0BA: MOV R00, 0xAA - "001111" & X"000", -- 0x0BB: TST R00 - "110001" & X"3FF", -- 0x0BC: JZ 0x3FF - "110011" & X"3FF", -- 0x0BD: JC 0x3FF - "001111" & X"550", -- 0x0BE: CMP R00, 0x55 - "111001" & X"3FF", -- 0x0BF: JEQ 0x3FF - "111010" & X"0C2", -- 0x0C0: JNE 0x0C2 - "110000" & X"3FF", -- 0x0C1: JMP 0x3FF - "110110" & X"0C4", -- 0x0C2: JGT 0x0C4 - "110000" & X"3FF", -- 0x0C3: JMP 0x3FF - "111000" & X"0C6", -- 0x0C4: JGE 0x0C6 - "110000" & X"3FF", -- 0x0C5: JMP 0x3FF - "110101" & X"3FF", -- 0x0C6: JLT 0x3FF - "110111" & X"3FF", -- 0x0C7: JLE 0x3FF - "111110" & X"000", -- 0x0C8: RET - "000011" & X"000", -- 0x0C9: MOV R00, 0x00 - "000011" & X"001", -- 0x0CA: MOV R01, 0x00 - "000010" & X"002", -- 0x0CB: MOV R02, R00 - "000010" & X"013", -- 0x0CC: MOV R03, R01 - "010001" & X"010", -- 0x0CD: ADD R00, 0x01 - "010011" & X"001", -- 0x0CE: ADDC R01, 0x00 - "010001" & X"012", -- 0x0CF: ADD R02, 0x01 - "001111" & X"002", -- 0x0D0: CMP R02, 0x00 - "111010" & X"0D4", -- 0x0D1: JNE 0x0D4 - "010001" & X"013", -- 0x0D2: ADD R03, 0x01 - "001111" & X"023", -- 0x0D3: CMP R03, 0x02 - "111010" & X"0CD", -- 0x0D4: JNE 0x0CD - "001110" & X"020", -- 0x0D5: CMP R00, R02 - "111010" & X"3FF", -- 0x0D6: JNE 0x3FF - "001110" & X"031", -- 0x0D7: CMP R01, R03 - "111010" & X"3FF", -- 0x0D8: JNE 0x3FF - "000011" & X"000", -- 0x0D9: MOV R00, 0x00 - "111110" & X"000", -- 0x0DA: RET - "000011" & X"000", -- 0x0DB: MOV R00, 0x00 - "000011" & X"031", -- 0x0DC: MOV R01, 0x03 - "000010" & X"002", -- 0x0DD: MOV R02, R00 - "000010" & X"013", -- 0x0DE: MOV R03, R01 - "010101" & X"010", -- 0x0DF: SUB R00, 0x01 - "010111" & X"001", -- 0x0E0: SUBC R01, 0x00 - "010101" & X"012", -- 0x0E1: SUB R02, 0x01 - "001111" & X"FF2", -- 0x0E2: CMP R02, 0xFF - "111010" & X"0E6", -- 0x0E3: JNE 0x0E6 - "010101" & X"013", -- 0x0E4: SUB R03, 0x01 - "001111" & X"003", -- 0x0E5: CMP R03, 0x00 - "111010" & X"0DF", -- 0x0E6: JNE 0x0DF - "001110" & X"020", -- 0x0E7: CMP R00, R02 - "111010" & X"3FF", -- 0x0E8: JNE 0x3FF - "001110" & X"031", -- 0x0E9: CMP R01, R03 - "111010" & X"3FF", -- 0x0EA: JNE 0x3FF - "000011" & X"000", -- 0x0EB: MOV R00, 0x00 - "111110" & X"000", -- 0x0EC: RET - "000011" & X"030", -- 0x0ED: MOV R00, 0x03 - "000011" & X"051", -- 0x0EE: MOV R01, 0x05 - "101110" & X"050", -- 0x0EF: SUB 0x05, R00 - "010101" & X"031", -- 0x0F0: SUB R01, 0x03 - "001110" & X"010", -- 0x0F1: CMP R00, R01 - "111010" & X"3FF", -- 0x0F2: JNE 0x3FF - "000011" & X"030", -- 0x0F3: MOV R00, 0x03 - "000011" & X"051", -- 0x0F4: MOV R01, 0x05 - "010100" & X"010", -- 0x0F5: SUB R00, R01 - "101111" & X"000", -- 0x0F6: SUBC 0x00, R00 - "001111" & X"010", -- 0x0F7: CMP R00, 0x01 - "111010" & X"3FF", -- 0x0F8: JNE 0x3FF - "010001" & X"000", -- 0x0F9: ADD R00, 0x00 - "010110" & X"001", -- 0x0FA: SUBC R01, R00 - "001111" & X"041", -- 0x0FB: CMP R01, 0x04 - "111010" & X"3FF", -- 0x0FC: JNE 0x3FF - "000011" & X"000", -- 0x0FD: MOV R00, 0x00 - "111110" & X"000", -- 0x0FE: RET - "000011" & X"010", -- 0x0FF: MOV R00, 0x01 - "001101" & X"5A0", -- 0x100: MOVC (0x5A), R00 - "010101" & X"010", -- 0x101: DEC R00 - "001101" & X"000", -- 0x102: MOVC (0x00), R00 - "001010" & X"5A1", -- 0x103: MOVC R01, (0x5A) - "001100" & X"A51", -- 0x104: MOVC (R01), 0xA5 - "001001" & X"010", -- 0x105: MOVC R00, (R01) - "001001" & X"011", -- 0x106: MOVC R01, (R01) - "010001" & X"5A1", -- 0x107: ADD R01, 0x5A - "001001" & X"010", -- 0x108: MOVC R00, (R01) - "001011" & X"000", -- 0x109: MOVC (R00), R00 - "001001" & X"002", -- 0x10A: MOVC R02, (R00) - "001110" & X"002", -- 0x10B: CMP R02, R00 - "111010" & X"3FF", -- 0x10C: JNE 0x3FF - "001011" & X"021", -- 0x10D: MOVC (R01), R02 - "001001" & X"022", -- 0x10E: MOVC R02, (R02) - "001110" & X"012", -- 0x10F: CMP R02, R01 - "111010" & X"3FF", -- 0x110: JNE 0x3FF - "010101" & X"011", -- 0x111: DEC R01 - "010001" & X"010", -- 0x112: INC R00 - "110010" & X"109", -- 0x113: JNZ 0x109 - "111110" & X"000", -- 0x114: RET - "000011" & X"010", -- 0x115: MOV R00, 0x01 - "001000" & X"600", -- 0x116: MOVX (0x60), R00 - "010101" & X"010", -- 0x117: DEC R00 - "001000" & X"060", -- 0x118: MOVX (0x06), R00 - "000101" & X"601", -- 0x119: MOVX R01, (0x60) - "000111" & X"A51", -- 0x11A: MOVX (R01), 0xA5 - "000100" & X"010", -- 0x11B: MOVX R00, (R01) - "000100" & X"011", -- 0x11C: MOVX R01, (R01) - "010001" & X"5A1", -- 0x11D: ADD R01, 0x5A - "000100" & X"010", -- 0x11E: MOVX R00, (R01) - "000110" & X"000", -- 0x11F: MOVX (R00), R00 - "000100" & X"002", -- 0x120: MOVX R02, (R00) - "001110" & X"002", -- 0x121: CMP R02, R00 - "111010" & X"3FF", -- 0x122: JNE 0x3FF - "000110" & X"021", -- 0x123: MOVX (R01), R02 - "000100" & X"022", -- 0x124: MOVX R02, (R02) - "001110" & X"012", -- 0x125: CMP R02, R01 - "111010" & X"3FF", -- 0x126: JNE 0x3FF - "010101" & X"011", -- 0x127: DEC R01 - "010001" & X"010", -- 0x128: INC R00 - "110010" & X"11F", -- 0x129: JNZ 0x11F - "111110" & X"000", -- 0x12A: RET - "000011" & X"AA0", -- 0x12B: MOV R00, 0xAA - "000011" & X"001", -- 0x12C: MOV R01, 0x00 - "111100" & X"000", -- 0x12D: PUSH R00 - "010001" & X"010", -- 0x12E: INC R00 - "010101" & X"011", -- 0x12F: DEC R01 - "110010" & X"12D", -- 0x130: JNZ 0x12D - "111101" & X"000", -- 0x131: POP R00 - "010101" & X"011", -- 0x132: DEC R01 - "110010" & X"131", -- 0x133: JNZ 0x131 - "001111" & X"AA0", -- 0x134: CMP R00, 0xAA - "111010" & X"3FF", -- 0x135: JNE 0x3FF - "111110" & X"000", -- 0x136: RET - "000011" & X"550", -- 0x137: MOV R00, 0x55 - "111100" & X"000", -- 0x138: PUSH R00 - "000011" & X"000", -- 0x139: MOV R00, 0x00 - "000011" & X"FF1", -- 0x13A: MOV R01, 0xFF - "111011" & X"151", -- 0x13B: CALL 0x151 - "111101" & X"000", -- 0x13C: POP R00 - "001111" & X"550", -- 0x13D: CMP R00, 0x55 - "111010" & X"3FF", -- 0x13E: JNE 0x3FF - "000011" & X"010", -- 0x13F: MOV R00, 0x01 - "000011" & X"481", -- 0x140: MOV R01, 0x48 - "100110" & X"050", -- 0x141: COUT (0x05), R00 - "111100" & X"001", -- 0x142: PUSH R01 - "000011" & X"000", -- 0x143: MOV R00, 0x00 - "000011" & X"3B1", -- 0x144: MOV R01, 0x3B - "100110" & X"050", -- 0x145: COUT (0x05), R00 - "111100" & X"001", -- 0x146: PUSH R01 - "111110" & X"000", -- 0x147: RET - "000011" & X"010", -- 0x148: MOV R00, 0x01 - "000011" & X"501", -- 0x149: MOV R01, 0x50 - "100110" & X"050", -- 0x14A: COUT (0x05), R00 - "111100" & X"001", -- 0x14B: PUSH R01 - "000011" & X"000", -- 0x14C: MOV R00, 0x00 - "000011" & X"3B1", -- 0x14D: MOV R01, 0x3B - "100110" & X"050", -- 0x14E: COUT (0x05), R00 - "111100" & X"001", -- 0x14F: PUSH R01 - "111110" & X"000", -- 0x150: RET - "001110" & X"010", -- 0x151: CMP R00, R01 - "111001" & X"155", -- 0x152: JEQ 0x155 - "010001" & X"010", -- 0x153: INC R00 - "110000" & X"158", -- 0x154: JMP 0x158 - "010101" & X"010", -- 0x155: DEC R00 - "010101" & X"011", -- 0x156: DEC R01 - "111110" & X"000", -- 0x157: RET - "111011" & X"151", -- 0x158: CALL 0x151 - "110000" & X"155", -- 0x159: JMP 0x155 - "000011" & X"A50", -- 0x15A: MOV R00, 0xA5 - "000011" & X"5A1", -- 0x15B: MOV R01, 0x5A - "101010" & X"000", -- 0x15C: SWAP R00 - "001111" & X"5A0", -- 0x15D: CMP R00, 0x5A - "111010" & X"3FF", -- 0x15E: JNE 0x3FF - "101010" & X"000", -- 0x15F: SWAP R00 - "001111" & X"A50", -- 0x160: CMP R00, 0xA5 - "111010" & X"3FF", -- 0x161: JNE 0x3FF - "000011" & X"D20", -- 0x162: MOV R00, 0xD2 - "101010" & X"000", -- 0x163: SWAP R00 - "001111" & X"2D0", -- 0x164: CMP R00, 0x2D - "111010" & X"3FF", -- 0x165: JNE 0x3FF - "101010" & X"001", -- 0x166: SWAP R01 - "001111" & X"2D0", -- 0x167: CMP R00, 0x2D - "111010" & X"3FF", -- 0x168: JNE 0x3FF - "001111" & X"A51", -- 0x169: CMP R01, 0xA5 - "111010" & X"3FF", -- 0x16A: JNE 0x3FF - "000011" & X"2D0", -- 0x16B: MOV R00, 0x2D - "011110" & X"000", -- 0x16C: SHL R00 - "001111" & X"5A0", -- 0x16D: CMP R00, 0x5A - "111010" & X"3FF", -- 0x16E: JNE 0x3FF - "011110" & X"000", -- 0x16F: SHL R00 - "001111" & X"B40", -- 0x170: CMP R00, 0xB4 - "111010" & X"3FF", -- 0x171: JNE 0x3FF - "011110" & X"000", -- 0x172: SHL R00 - "001111" & X"680", -- 0x173: CMP R00, 0x68 - "111010" & X"3FF", -- 0x174: JNE 0x3FF - "011110" & X"000", -- 0x175: SHL R00 - "001111" & X"D00", -- 0x176: CMP R00, 0xD0 - "111010" & X"3FF", -- 0x177: JNE 0x3FF - "011110" & X"000", -- 0x178: SHL R00 - "001111" & X"A00", -- 0x179: CMP R00, 0xA0 - "111010" & X"3FF", -- 0x17A: JNE 0x3FF - "011110" & X"000", -- 0x17B: SHL R00 - "001111" & X"400", -- 0x17C: CMP R00, 0x40 - "111010" & X"3FF", -- 0x17D: JNE 0x3FF - "011110" & X"000", -- 0x17E: SHL R00 - "001111" & X"800", -- 0x17F: CMP R00, 0x80 - "111010" & X"3FF", -- 0x180: JNE 0x3FF - "011110" & X"000", -- 0x181: SHL R00 - "001111" & X"000", -- 0x182: CMP R00, 0x00 - "111010" & X"3FF", -- 0x183: JNE 0x3FF - "000011" & X"841", -- 0x184: MOV R01, 0x84 - "011111" & X"001", -- 0x185: SHR R01 - "001111" & X"421", -- 0x186: CMP R01, 0x42 - "111010" & X"3FF", -- 0x187: JNE 0x3FF - "011111" & X"001", -- 0x188: SHR R01 - "001111" & X"211", -- 0x189: CMP R01, 0x21 - "111010" & X"3FF", -- 0x18A: JNE 0x3FF - "011111" & X"001", -- 0x18B: SHR R01 - "001111" & X"101", -- 0x18C: CMP R01, 0x10 - "111010" & X"3FF", -- 0x18D: JNE 0x3FF - "011111" & X"001", -- 0x18E: SHR R01 - "001111" & X"081", -- 0x18F: CMP R01, 0x08 - "111010" & X"3FF", -- 0x190: JNE 0x3FF - "011111" & X"001", -- 0x191: SHR R01 - "001111" & X"041", -- 0x192: CMP R01, 0x04 - "111010" & X"3FF", -- 0x193: JNE 0x3FF - "011111" & X"001", -- 0x194: SHR R01 - "001111" & X"021", -- 0x195: CMP R01, 0x02 - "111010" & X"3FF", -- 0x196: JNE 0x3FF - "011111" & X"001", -- 0x197: SHR R01 - "001111" & X"011", -- 0x198: CMP R01, 0x01 - "111010" & X"3FF", -- 0x199: JNE 0x3FF - "011111" & X"001", -- 0x19A: SHR R01 - "001111" & X"001", -- 0x19B: CMP R01, 0x00 - "111010" & X"3FF", -- 0x19C: JNE 0x3FF - "000011" & X"C50", -- 0x19D: MOV R00, 0xC5 - "100000" & X"000", -- 0x19E: ROL R00 - "001111" & X"8B0", -- 0x19F: CMP R00, 0x8B - "111010" & X"3FF", -- 0x1A0: JNE 0x3FF - "100000" & X"000", -- 0x1A1: ROL R00 - "001111" & X"170", -- 0x1A2: CMP R00, 0x17 - "111010" & X"3FF", -- 0x1A3: JNE 0x3FF - "100000" & X"000", -- 0x1A4: ROL R00 - "001111" & X"2E0", -- 0x1A5: CMP R00, 0x2E - "111010" & X"3FF", -- 0x1A6: JNE 0x3FF - "100000" & X"000", -- 0x1A7: ROL R00 - "001111" & X"5C0", -- 0x1A8: CMP R00, 0x5C - "111010" & X"3FF", -- 0x1A9: JNE 0x3FF - "100000" & X"000", -- 0x1AA: ROL R00 - "001111" & X"B80", -- 0x1AB: CMP R00, 0xB8 - "111010" & X"3FF", -- 0x1AC: JNE 0x3FF - "100000" & X"000", -- 0x1AD: ROL R00 - "001111" & X"710", -- 0x1AE: CMP R00, 0x71 - "111010" & X"3FF", -- 0x1AF: JNE 0x3FF - "100000" & X"000", -- 0x1B0: ROL R00 - "001111" & X"E20", -- 0x1B1: CMP R00, 0xE2 - "111010" & X"3FF", -- 0x1B2: JNE 0x3FF - "100000" & X"000", -- 0x1B3: ROL R00 - "001111" & X"C50", -- 0x1B4: CMP R00, 0xC5 - "111010" & X"3FF", -- 0x1B5: JNE 0x3FF - "000011" & X"631", -- 0x1B6: MOV R01, 0x63 - "100001" & X"001", -- 0x1B7: ROR R01 - "001111" & X"B11", -- 0x1B8: CMP R01, 0xB1 - "111010" & X"3FF", -- 0x1B9: JNE 0x3FF - "100001" & X"001", -- 0x1BA: ROR R01 - "001111" & X"D81", -- 0x1BB: CMP R01, 0xD8 - "111010" & X"3FF", -- 0x1BC: JNE 0x3FF - "100001" & X"001", -- 0x1BD: ROR R01 - "001111" & X"6C1", -- 0x1BE: CMP R01, 0x6C - "111010" & X"3FF", -- 0x1BF: JNE 0x3FF - "100001" & X"001", -- 0x1C0: ROR R01 - "001111" & X"361", -- 0x1C1: CMP R01, 0x36 - "111010" & X"3FF", -- 0x1C2: JNE 0x3FF - "100001" & X"001", -- 0x1C3: ROR R01 - "001111" & X"1B1", -- 0x1C4: CMP R01, 0x1B - "111010" & X"3FF", -- 0x1C5: JNE 0x3FF - "100001" & X"001", -- 0x1C6: ROR R01 - "001111" & X"8D1", -- 0x1C7: CMP R01, 0x8D - "111010" & X"3FF", -- 0x1C8: JNE 0x3FF - "100001" & X"001", -- 0x1C9: ROR R01 - "001111" & X"C61", -- 0x1CA: CMP R01, 0xC6 - "111010" & X"3FF", -- 0x1CB: JNE 0x3FF - "100001" & X"001", -- 0x1CC: ROR R01 - "001111" & X"631", -- 0x1CD: CMP R01, 0x63 - "111010" & X"3FF", -- 0x1CE: JNE 0x3FF - "011100" & X"000", -- 0x1CF: XOR R00, R00 - "000011" & X"C50", -- 0x1D0: MOV R00, 0xC5 - "100010" & X"000", -- 0x1D1: ROLC R00 - "111100" & X"000", -- 0x1D2: PUSH R00 - "100010" & X"000", -- 0x1D3: ROLC R00 - "111100" & X"000", -- 0x1D4: PUSH R00 - "100010" & X"000", -- 0x1D5: ROLC R00 - "111100" & X"000", -- 0x1D6: PUSH R00 - "100010" & X"000", -- 0x1D7: ROLC R00 - "111100" & X"000", -- 0x1D8: PUSH R00 - "100010" & X"000", -- 0x1D9: ROLC R00 - "111100" & X"000", -- 0x1DA: PUSH R00 - "100010" & X"000", -- 0x1DB: ROLC R00 - "111100" & X"000", -- 0x1DC: PUSH R00 - "100010" & X"000", -- 0x1DD: ROLC R00 - "111100" & X"000", -- 0x1DE: PUSH R00 - "100010" & X"000", -- 0x1DF: ROLC R00 - "111100" & X"000", -- 0x1E0: PUSH R00 - "100010" & X"000", -- 0x1E1: ROLC R00 - "001111" & X"C50", -- 0x1E2: CMP R00, 0xC5 - "111010" & X"3FF", -- 0x1E3: JNE 0x3FF - "111101" & X"000", -- 0x1E4: POP R00 - "001111" & X"620", -- 0x1E5: CMP R00, 0x62 - "111010" & X"3FF", -- 0x1E6: JNE 0x3FF - "111101" & X"000", -- 0x1E7: POP R00 - "001111" & X"B10", -- 0x1E8: CMP R00, 0xB1 - "111010" & X"3FF", -- 0x1E9: JNE 0x3FF - "111101" & X"000", -- 0x1EA: POP R00 - "001111" & X"580", -- 0x1EB: CMP R00, 0x58 - "111010" & X"3FF", -- 0x1EC: JNE 0x3FF - "111101" & X"000", -- 0x1ED: POP R00 - "001111" & X"AC0", -- 0x1EE: CMP R00, 0xAC - "111010" & X"3FF", -- 0x1EF: JNE 0x3FF - "111101" & X"000", -- 0x1F0: POP R00 - "001111" & X"560", -- 0x1F1: CMP R00, 0x56 - "111010" & X"3FF", -- 0x1F2: JNE 0x3FF - "111101" & X"000", -- 0x1F3: POP R00 - "001111" & X"2B0", -- 0x1F4: CMP R00, 0x2B - "111010" & X"3FF", -- 0x1F5: JNE 0x3FF - "111101" & X"000", -- 0x1F6: POP R00 - "001111" & X"150", -- 0x1F7: CMP R00, 0x15 - "111010" & X"3FF", -- 0x1F8: JNE 0x3FF - "111101" & X"000", -- 0x1F9: POP R00 - "001111" & X"8A0", -- 0x1FA: CMP R00, 0x8A - "111010" & X"3FF", -- 0x1FB: JNE 0x3FF - "011100" & X"011", -- 0x1FC: XOR R01, R01 - "000011" & X"631", -- 0x1FD: MOV R01, 0x63 - "100011" & X"001", -- 0x1FE: RORC R01 - "111100" & X"001", -- 0x1FF: PUSH R01 - "100011" & X"001", -- 0x200: RORC R01 - "111100" & X"001", -- 0x201: PUSH R01 - "100011" & X"001", -- 0x202: RORC R01 - "111100" & X"001", -- 0x203: PUSH R01 - "100011" & X"001", -- 0x204: RORC R01 - "111100" & X"001", -- 0x205: PUSH R01 - "100011" & X"001", -- 0x206: RORC R01 - "111100" & X"001", -- 0x207: PUSH R01 - "100011" & X"001", -- 0x208: RORC R01 - "111100" & X"001", -- 0x209: PUSH R01 - "100011" & X"001", -- 0x20A: RORC R01 - "111100" & X"001", -- 0x20B: PUSH R01 - "100011" & X"001", -- 0x20C: RORC R01 - "111100" & X"001", -- 0x20D: PUSH R01 - "100011" & X"001", -- 0x20E: RORC R01 - "001111" & X"631", -- 0x20F: CMP R01, 0x63 - "111010" & X"3FF", -- 0x210: JNE 0x3FF - "111101" & X"001", -- 0x211: POP R01 - "001111" & X"C61", -- 0x212: CMP R01, 0xC6 - "111010" & X"3FF", -- 0x213: JNE 0x3FF - "111101" & X"001", -- 0x214: POP R01 - "001111" & X"8C1", -- 0x215: CMP R01, 0x8C - "111010" & X"3FF", -- 0x216: JNE 0x3FF - "111101" & X"001", -- 0x217: POP R01 - "001111" & X"191", -- 0x218: CMP R01, 0x19 - "111010" & X"3FF", -- 0x219: JNE 0x3FF - "111101" & X"001", -- 0x21A: POP R01 - "001111" & X"331", -- 0x21B: CMP R01, 0x33 - "111010" & X"3FF", -- 0x21C: JNE 0x3FF - "111101" & X"001", -- 0x21D: POP R01 - "001111" & X"661", -- 0x21E: CMP R01, 0x66 - "111010" & X"3FF", -- 0x21F: JNE 0x3FF - "111101" & X"001", -- 0x220: POP R01 - "001111" & X"CC1", -- 0x221: CMP R01, 0xCC - "111010" & X"3FF", -- 0x222: JNE 0x3FF - "111101" & X"001", -- 0x223: POP R01 - "001111" & X"981", -- 0x224: CMP R01, 0x98 - "111010" & X"3FF", -- 0x225: JNE 0x3FF - "111101" & X"001", -- 0x226: POP R01 - "001111" & X"311", -- 0x227: CMP R01, 0x31 - "111010" & X"3FF", -- 0x228: JNE 0x3FF - "111110" & X"000", -- 0x229: RET - "000011" & X"A50", -- 0x22A: MOV R00, 0xA5 - "101010" & X"000", -- 0x22B: SWAP R00 - "111100" & X"000", -- 0x22C: PUSH R00 - "011001" & X"0F0", -- 0x22D: AND R00, 0x0F - "001111" & X"0A0", -- 0x22E: CMP R00, 0x0A - "111010" & X"3FF", -- 0x22F: JNE 0x3FF - "111101" & X"000", -- 0x230: POP R00 - "111100" & X"000", -- 0x231: PUSH R00 - "011001" & X"0F0", -- 0x232: AND R00, 0x0F - "001111" & X"0A0", -- 0x233: CMP R00, 0x0A - "111101" & X"001", -- 0x234: POP R01 - "111010" & X"3FF", -- 0x235: JNE 0x3FF - "101010" & X"001", -- 0x236: SWAP R01 - "000011" & X"0F2", -- 0x237: MOV R02, 0x0F - "011000" & X"021", -- 0x238: AND R01, R02 - "001111" & X"051", -- 0x239: CMP R01, 0x05 - "111010" & X"3FF", -- 0x23A: JNE 0x3FF - "000011" & X"050", -- 0x23B: MOV R00, 0x05 - "000011" & X"A02", -- 0x23C: MOV R02, 0xA0 - "101010" & X"000", -- 0x23D: SWAP R00 - "011010" & X"002", -- 0x23E: OR R02, R00 - "001111" & X"F02", -- 0x23F: CMP R02, 0xF0 - "111010" & X"3FF", -- 0x240: JNE 0x3FF - "101010" & X"000", -- 0x241: SWAP R00 - "011011" & X"500", -- 0x242: OR R00, 0x50 - "001111" & X"550", -- 0x243: CMP R00, 0x55 - "111010" & X"3FF", -- 0x244: JNE 0x3FF - "000011" & X"011", -- 0x245: MOV R01, 0x01 - "000011" & X"010", -- 0x246: MOV R00, 0x01 - "011101" & X"010", -- 0x247: XOR R00, 0x01 - "110010" & X"3FF", -- 0x248: JNZ 0x3FF - "011100" & X"010", -- 0x249: XOR R00, R01 - "001111" & X"010", -- 0x24A: CMP R00, 0x01 - "111010" & X"3FF", -- 0x24B: JNE 0x3FF - "111110" & X"000", -- 0x24C: RET - "000011" & X"030", -- 0x24D: MOV R00, 0x03 - "100110" & X"030", -- 0x24E: COUT (0x03), R00 - "101000" & X"020", -- 0x24F: XIN R00, (0x02) - "011011" & X"010", -- 0x250: OR R00, 0x01 - "100100" & X"020", -- 0x251: XOUT (0x02), R00 - "000000" & X"000", -- 0x252: NOP - "000000" & X"000", -- 0x253: NOP - "000000" & X"000", -- 0x254: NOP - "000000" & X"000", -- 0x255: NOP - "000000" & X"000", -- 0x256: NOP - "000000" & X"000", -- 0x257: NOP - "101000" & X"020", -- 0x258: XIN R00, (0x02) - "011001" & X"FE0", -- 0x259: AND R00, 0xFE - "100100" & X"020", -- 0x25A: XOUT (0x02), R00 - "000000" & X"000", -- 0x25B: NOP - "000000" & X"000", -- 0x25C: NOP - "000000" & X"000", -- 0x25D: NOP - "000000" & X"000", -- 0x25E: NOP - "101001" & X"030", -- 0x25F: CIN R00, (0x03) - "011011" & X"800", -- 0x260: OR R00, 0x80 - "100110" & X"030", -- 0x261: COUT (0x03), R00 - "000000" & X"000", -- 0x262: NOP - "101001" & X"030", -- 0x263: CIN R00, (0x03) - "011011" & X"800", -- 0x264: OR R00, 0x80 - "100110" & X"030", -- 0x265: COUT (0x03), R00 - "000000" & X"000", -- 0x266: NOP - "101001" & X"030", -- 0x267: CIN R00, (0x03) - "011011" & X"800", -- 0x268: OR R00, 0x80 - "100110" & X"030", -- 0x269: COUT (0x03), R00 - "000000" & X"000", -- 0x26A: NOP - "101001" & X"030", -- 0x26B: CIN R00, (0x03) - "011011" & X"800", -- 0x26C: OR R00, 0x80 - "100110" & X"030", -- 0x26D: COUT (0x03), R00 - "000000" & X"000", -- 0x26E: NOP - "000000" & X"000", -- 0x26F: NOP - "000000" & X"000", -- 0x270: NOP - "000000" & X"000", -- 0x271: NOP - "000000" & X"000", -- 0x272: NOP - "000000" & X"000", -- 0x273: NOP - "000000" & X"000", -- 0x274: NOP - "000000" & X"000", -- 0x275: NOP - "000000" & X"000", -- 0x276: NOP - "111110" & X"000", -- 0x277: RET - "010101" & X"000", -- 0x278: SUB R00, 0x00 - "110011" & X"3FF", -- 0x279: JC 0x3FF - "101011" & X"000", -- 0x27A: SETC - "110100" & X"3FF", -- 0x27B: JNC 0x3FF - "000000" & X"000", -- 0x27C: NOP - "010101" & X"000", -- 0x27D: SUB R00, 0x00 - "110011" & X"3FF", -- 0x27E: JC 0x3FF - "000011" & X"000", -- 0x27F: MOV R00, 0x00 - "010101" & X"000", -- 0x280: CLRC - "110011" & X"3FF", -- 0x281: JC 0x3FF - "101011" & X"000", -- 0x282: SETC - "110100" & X"3FF", -- 0x283: JNC 0x3FF - "000000" & X"000", -- 0x284: NOP - "010101" & X"000", -- 0x285: CLRC - "110011" & X"3FF", -- 0x286: JC 0x3FF - "111110" & X"000", -- 0x287: RET - "010001" & X"01E", -- 0x288: INC R14 - "111111" & X"000", -- 0x289: RETI - "000000" & X"000", -- 0x28A: - "000000" & X"000", -- 0x28B: - "000000" & X"000", -- 0x28C: - "000000" & X"000", -- 0x28D: - "000000" & X"000", -- 0x28E: - "000000" & X"000", -- 0x28F: - "000000" & X"000", -- 0x290: - "000000" & X"000", -- 0x291: - "000000" & X"000", -- 0x292: - "000000" & X"000", -- 0x293: - "000000" & X"000", -- 0x294: - "000000" & X"000", -- 0x295: - "000000" & X"000", -- 0x296: - "000000" & X"000", -- 0x297: - "000000" & X"000", -- 0x298: - "000000" & X"000", -- 0x299: - "000000" & X"000", -- 0x29A: - "000000" & X"000", -- 0x29B: - "000000" & X"000", -- 0x29C: - "000000" & X"000", -- 0x29D: - "000000" & X"000", -- 0x29E: - "000000" & X"000", -- 0x29F: - "000000" & X"000", -- 0x2A0: - "000000" & X"000", -- 0x2A1: - "000000" & X"000", -- 0x2A2: - "000000" & X"000", -- 0x2A3: - "000000" & X"000", -- 0x2A4: - "000000" & X"000", -- 0x2A5: - "000000" & X"000", -- 0x2A6: - "000000" & X"000", -- 0x2A7: - "000000" & X"000", -- 0x2A8: - "000000" & X"000", -- 0x2A9: - "000000" & X"000", -- 0x2AA: - "000000" & X"000", -- 0x2AB: - "000000" & X"000", -- 0x2AC: - "000000" & X"000", -- 0x2AD: - "000000" & X"000", -- 0x2AE: - "000000" & X"000", -- 0x2AF: - "000000" & X"000", -- 0x2B0: - "000000" & X"000", -- 0x2B1: - "000000" & X"000", -- 0x2B2: - "000000" & X"000", -- 0x2B3: - "000000" & X"000", -- 0x2B4: - "000000" & X"000", -- 0x2B5: - "000000" & X"000", -- 0x2B6: - "000000" & X"000", -- 0x2B7: - "000000" & X"000", -- 0x2B8: - "000000" & X"000", -- 0x2B9: - "000000" & X"000", -- 0x2BA: - "000000" & X"000", -- 0x2BB: - "000000" & X"000", -- 0x2BC: - "000000" & X"000", -- 0x2BD: - "000000" & X"000", -- 0x2BE: - "000000" & X"000", -- 0x2BF: - "000000" & X"000", -- 0x2C0: - "000000" & X"000", -- 0x2C1: - "000000" & X"000", -- 0x2C2: - "000000" & X"000", -- 0x2C3: - "000000" & X"000", -- 0x2C4: - "000000" & X"000", -- 0x2C5: - "000000" & X"000", -- 0x2C6: - "000000" & X"000", -- 0x2C7: - "000000" & X"000", -- 0x2C8: - "000000" & X"000", -- 0x2C9: - "000000" & X"000", -- 0x2CA: - "000000" & X"000", -- 0x2CB: - "000000" & X"000", -- 0x2CC: - "000000" & X"000", -- 0x2CD: - "000000" & X"000", -- 0x2CE: - "000000" & X"000", -- 0x2CF: - "000000" & X"000", -- 0x2D0: - "000000" & X"000", -- 0x2D1: - "000000" & X"000", -- 0x2D2: - "000000" & X"000", -- 0x2D3: - "000000" & X"000", -- 0x2D4: - "000000" & X"000", -- 0x2D5: - "000000" & X"000", -- 0x2D6: - "000000" & X"000", -- 0x2D7: - "000000" & X"000", -- 0x2D8: - "000000" & X"000", -- 0x2D9: - "000000" & X"000", -- 0x2DA: - "000000" & X"000", -- 0x2DB: - "000000" & X"000", -- 0x2DC: - "000000" & X"000", -- 0x2DD: - "000000" & X"000", -- 0x2DE: - "000000" & X"000", -- 0x2DF: - "000000" & X"000", -- 0x2E0: - "000000" & X"000", -- 0x2E1: - "000000" & X"000", -- 0x2E2: - "000000" & X"000", -- 0x2E3: - "000000" & X"000", -- 0x2E4: - "000000" & X"000", -- 0x2E5: - "000000" & X"000", -- 0x2E6: - "000000" & X"000", -- 0x2E7: - "000000" & X"000", -- 0x2E8: - "000000" & X"000", -- 0x2E9: - "000000" & X"000", -- 0x2EA: - "000000" & X"000", -- 0x2EB: - "000000" & X"000", -- 0x2EC: - "000000" & X"000", -- 0x2ED: - "000000" & X"000", -- 0x2EE: - "000000" & X"000", -- 0x2EF: - "000000" & X"000", -- 0x2F0: - "000000" & X"000", -- 0x2F1: - "000000" & X"000", -- 0x2F2: - "000000" & X"000", -- 0x2F3: - "000000" & X"000", -- 0x2F4: - "000000" & X"000", -- 0x2F5: - "000000" & X"000", -- 0x2F6: - "000000" & X"000", -- 0x2F7: - "000000" & X"000", -- 0x2F8: - "000000" & X"000", -- 0x2F9: - "000000" & X"000", -- 0x2FA: - "000000" & X"000", -- 0x2FB: - "000000" & X"000", -- 0x2FC: - "000000" & X"000", -- 0x2FD: - "000000" & X"000", -- 0x2FE: - "110000" & X"2FF", -- 0x2FF: JMP 0x2FF - "000000" & X"000", -- 0x300: - "000000" & X"000", -- 0x301: - "000000" & X"000", -- 0x302: - "000000" & X"000", -- 0x303: - "000000" & X"000", -- 0x304: - "000000" & X"000", -- 0x305: - "000000" & X"000", -- 0x306: - "000000" & X"000", -- 0x307: - "000000" & X"000", -- 0x308: - "000000" & X"000", -- 0x309: - "000000" & X"000", -- 0x30A: - "000000" & X"000", -- 0x30B: - "000000" & X"000", -- 0x30C: - "000000" & X"000", -- 0x30D: - "000000" & X"000", -- 0x30E: - "000000" & X"000", -- 0x30F: - "000000" & X"000", -- 0x310: - "000000" & X"000", -- 0x311: - "000000" & X"000", -- 0x312: - "000000" & X"000", -- 0x313: - "000000" & X"000", -- 0x314: - "000000" & X"000", -- 0x315: - "000000" & X"000", -- 0x316: - "000000" & X"000", -- 0x317: - "000000" & X"000", -- 0x318: - "000000" & X"000", -- 0x319: - "000000" & X"000", -- 0x31A: - "000000" & X"000", -- 0x31B: - "000000" & X"000", -- 0x31C: - "000000" & X"000", -- 0x31D: - "000000" & X"000", -- 0x31E: - "000000" & X"000", -- 0x31F: - "000000" & X"000", -- 0x320: - "000000" & X"000", -- 0x321: - "000000" & X"000", -- 0x322: - "000000" & X"000", -- 0x323: - "000000" & X"000", -- 0x324: - "000000" & X"000", -- 0x325: - "000000" & X"000", -- 0x326: - "000000" & X"000", -- 0x327: - "000000" & X"000", -- 0x328: - "000000" & X"000", -- 0x329: - "000000" & X"000", -- 0x32A: - "000000" & X"000", -- 0x32B: - "000000" & X"000", -- 0x32C: - "000000" & X"000", -- 0x32D: - "000000" & X"000", -- 0x32E: - "000000" & X"000", -- 0x32F: - "000000" & X"000", -- 0x330: - "000000" & X"000", -- 0x331: - "000000" & X"000", -- 0x332: - "000000" & X"000", -- 0x333: - "000000" & X"000", -- 0x334: - "000000" & X"000", -- 0x335: - "000000" & X"000", -- 0x336: - "000000" & X"000", -- 0x337: - "000000" & X"000", -- 0x338: - "000000" & X"000", -- 0x339: - "000000" & X"000", -- 0x33A: - "000000" & X"000", -- 0x33B: - "000000" & X"000", -- 0x33C: - "000000" & X"000", -- 0x33D: - "000000" & X"000", -- 0x33E: - "000000" & X"000", -- 0x33F: - "000000" & X"000", -- 0x340: - "000000" & X"000", -- 0x341: - "000000" & X"000", -- 0x342: - "000000" & X"000", -- 0x343: - "000000" & X"000", -- 0x344: - "000000" & X"000", -- 0x345: - "000000" & X"000", -- 0x346: - "000000" & X"000", -- 0x347: - "000000" & X"000", -- 0x348: - "000000" & X"000", -- 0x349: - "000000" & X"000", -- 0x34A: - "000000" & X"000", -- 0x34B: - "000000" & X"000", -- 0x34C: - "000000" & X"000", -- 0x34D: - "000000" & X"000", -- 0x34E: - "000000" & X"000", -- 0x34F: - "000000" & X"000", -- 0x350: - "000000" & X"000", -- 0x351: - "000000" & X"000", -- 0x352: - "000000" & X"000", -- 0x353: - "000000" & X"000", -- 0x354: - "000000" & X"000", -- 0x355: - "000000" & X"000", -- 0x356: - "000000" & X"000", -- 0x357: - "000000" & X"000", -- 0x358: - "000000" & X"000", -- 0x359: - "000000" & X"000", -- 0x35A: - "000000" & X"000", -- 0x35B: - "000000" & X"000", -- 0x35C: - "000000" & X"000", -- 0x35D: - "000000" & X"000", -- 0x35E: - "000000" & X"000", -- 0x35F: - "000000" & X"000", -- 0x360: - "000000" & X"000", -- 0x361: - "000000" & X"000", -- 0x362: - "000000" & X"000", -- 0x363: - "000000" & X"000", -- 0x364: - "000000" & X"000", -- 0x365: - "000000" & X"000", -- 0x366: - "000000" & X"000", -- 0x367: - "000000" & X"000", -- 0x368: - "000000" & X"000", -- 0x369: - "000000" & X"000", -- 0x36A: - "000000" & X"000", -- 0x36B: - "000000" & X"000", -- 0x36C: - "000000" & X"000", -- 0x36D: - "000000" & X"000", -- 0x36E: - "000000" & X"000", -- 0x36F: - "000000" & X"000", -- 0x370: - "000000" & X"000", -- 0x371: - "000000" & X"000", -- 0x372: - "000000" & X"000", -- 0x373: - "000000" & X"000", -- 0x374: - "000000" & X"000", -- 0x375: - "000000" & X"000", -- 0x376: - "000000" & X"000", -- 0x377: - "000000" & X"000", -- 0x378: - "000000" & X"000", -- 0x379: - "000000" & X"000", -- 0x37A: - "000000" & X"000", -- 0x37B: - "000000" & X"000", -- 0x37C: - "000000" & X"000", -- 0x37D: - "000000" & X"000", -- 0x37E: - "000000" & X"000", -- 0x37F: - "000000" & X"000", -- 0x380: - "000000" & X"000", -- 0x381: - "000000" & X"000", -- 0x382: - "000000" & X"000", -- 0x383: - "000000" & X"000", -- 0x384: - "000000" & X"000", -- 0x385: - "000000" & X"000", -- 0x386: - "000000" & X"000", -- 0x387: - "000000" & X"000", -- 0x388: - "000000" & X"000", -- 0x389: - "000000" & X"000", -- 0x38A: - "000000" & X"000", -- 0x38B: - "000000" & X"000", -- 0x38C: - "000000" & X"000", -- 0x38D: - "000000" & X"000", -- 0x38E: - "000000" & X"000", -- 0x38F: - "000000" & X"000", -- 0x390: - "000000" & X"000", -- 0x391: - "000000" & X"000", -- 0x392: - "000000" & X"000", -- 0x393: - "000000" & X"000", -- 0x394: - "000000" & X"000", -- 0x395: - "000000" & X"000", -- 0x396: - "000000" & X"000", -- 0x397: - "000000" & X"000", -- 0x398: - "000000" & X"000", -- 0x399: - "000000" & X"000", -- 0x39A: - "000000" & X"000", -- 0x39B: - "000000" & X"000", -- 0x39C: - "000000" & X"000", -- 0x39D: - "000000" & X"000", -- 0x39E: - "000000" & X"000", -- 0x39F: - "000000" & X"000", -- 0x3A0: - "000000" & X"000", -- 0x3A1: - "000000" & X"000", -- 0x3A2: - "000000" & X"000", -- 0x3A3: - "000000" & X"000", -- 0x3A4: - "000000" & X"000", -- 0x3A5: - "000000" & X"000", -- 0x3A6: - "000000" & X"000", -- 0x3A7: - "000000" & X"000", -- 0x3A8: - "000000" & X"000", -- 0x3A9: - "000000" & X"000", -- 0x3AA: - "000000" & X"000", -- 0x3AB: - "000000" & X"000", -- 0x3AC: - "000000" & X"000", -- 0x3AD: - "000000" & X"000", -- 0x3AE: - "000000" & X"000", -- 0x3AF: - "000000" & X"000", -- 0x3B0: - "000000" & X"000", -- 0x3B1: - "000000" & X"000", -- 0x3B2: - "000000" & X"000", -- 0x3B3: - "000000" & X"000", -- 0x3B4: - "000000" & X"000", -- 0x3B5: - "000000" & X"000", -- 0x3B6: - "000000" & X"000", -- 0x3B7: - "000000" & X"000", -- 0x3B8: - "000000" & X"000", -- 0x3B9: - "000000" & X"000", -- 0x3BA: - "000000" & X"000", -- 0x3BB: - "000000" & X"000", -- 0x3BC: - "000000" & X"000", -- 0x3BD: - "000000" & X"000", -- 0x3BE: - "000000" & X"000", -- 0x3BF: - "000000" & X"000", -- 0x3C0: - "000000" & X"000", -- 0x3C1: - "000000" & X"000", -- 0x3C2: - "000000" & X"000", -- 0x3C3: - "000000" & X"000", -- 0x3C4: - "000000" & X"000", -- 0x3C5: - "000000" & X"000", -- 0x3C6: - "000000" & X"000", -- 0x3C7: - "000000" & X"000", -- 0x3C8: - "000000" & X"000", -- 0x3C9: - "000000" & X"000", -- 0x3CA: - "000000" & X"000", -- 0x3CB: - "000000" & X"000", -- 0x3CC: - "000000" & X"000", -- 0x3CD: - "000000" & X"000", -- 0x3CE: - "000000" & X"000", -- 0x3CF: - "000000" & X"000", -- 0x3D0: - "000000" & X"000", -- 0x3D1: - "000000" & X"000", -- 0x3D2: - "000000" & X"000", -- 0x3D3: - "000000" & X"000", -- 0x3D4: - "000000" & X"000", -- 0x3D5: - "000000" & X"000", -- 0x3D6: - "000000" & X"000", -- 0x3D7: - "000000" & X"000", -- 0x3D8: - "000000" & X"000", -- 0x3D9: - "000000" & X"000", -- 0x3DA: - "000000" & X"000", -- 0x3DB: - "000000" & X"000", -- 0x3DC: - "000000" & X"000", -- 0x3DD: - "000000" & X"000", -- 0x3DE: - "000000" & X"000", -- 0x3DF: - "000000" & X"000", -- 0x3E0: - "000000" & X"000", -- 0x3E1: - "000000" & X"000", -- 0x3E2: - "000000" & X"000", -- 0x3E3: - "000000" & X"000", -- 0x3E4: - "000000" & X"000", -- 0x3E5: - "000000" & X"000", -- 0x3E6: - "000000" & X"000", -- 0x3E7: - "000000" & X"000", -- 0x3E8: - "000000" & X"000", -- 0x3E9: - "000000" & X"000", -- 0x3EA: - "000000" & X"000", -- 0x3EB: - "000000" & X"000", -- 0x3EC: - "000000" & X"000", -- 0x3ED: - "000000" & X"000", -- 0x3EE: - "000000" & X"000", -- 0x3EF: - "000000" & X"000", -- 0x3F0: - "000000" & X"000", -- 0x3F1: - "000000" & X"000", -- 0x3F2: - "000000" & X"000", -- 0x3F3: - "000000" & X"000", -- 0x3F4: - "000000" & X"000", -- 0x3F5: - "000000" & X"000", -- 0x3F6: - "000000" & X"000", -- 0x3F7: - "000000" & X"000", -- 0x3F8: - "000000" & X"000", -- 0x3F9: - "000000" & X"000", -- 0x3FA: - "000000" & X"000", -- 0x3FB: - "000000" & X"000", -- 0x3FC: - "000000" & X"000", -- 0x3FD: - "000000" & X"000", -- 0x3FE: - "110000" & X"3FF" -- 0x3FF: JMP 0x3FF - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : inst_addr_t; - signal jtag_ld_dout : inst_t; - signal jtag_ld_din : inst_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (31 downto 0); - constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1); - jtag_ld_din <= user_regi(inst_t'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/itest_xrom.vhdl b/lib/CPUs/JCpu/src/itest_xrom.vhdl deleted file mode 100644 index 4206abc..0000000 --- a/lib/CPUs/JCpu/src/itest_xrom.vhdl +++ /dev/null @@ -1,317 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); -END xrom; - -ARCHITECTURE itest OF xrom IS - - type xmem_rom_t is array (0 to 255) of dmem_data_t; - - -- Assembled from itest.jsm - constant xmem_rom : xmem_rom_t := - ( - X"48", -- 0x00 - X"61", -- 0x01 - X"6C", -- 0x02 - X"6C", -- 0x03 - X"6F", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -end itest; - diff --git a/lib/CPUs/JCpu/src/itest_xrom_ld.vhdl b/lib/CPUs/JCpu/src/itest_xrom_ld.vhdl deleted file mode 100644 index 60a84ac..0000000 --- a/lib/CPUs/JCpu/src/itest_xrom_ld.vhdl +++ /dev/null @@ -1,413 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); - -END xrom; - -ARCHITECTURE loadable OF xrom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from itest.jsm - type xmem_rom_t is array (0 to 255) of dmem_data_t; - signal xmem_rom : xmem_rom_t := - ( - X"48", -- 0x00 - X"61", -- 0x01 - X"6C", -- 0x02 - X"6C", -- 0x03 - X"6F", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : dmem_addr_t; - signal jtag_ld_dout : dmem_data_t; - signal jtag_ld_din : dmem_data_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (15 downto 0); - constant id : unsigned (15 downto 0) := X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1); - jtag_ld_din <= user_regi(dmem_data_t'left downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/mul8x8_irom.vhdl b/lib/CPUs/JCpu/src/mul8x8_irom.vhdl deleted file mode 100644 index 3b0de3b..0000000 --- a/lib/CPUs/JCpu/src/mul8x8_irom.vhdl +++ /dev/null @@ -1,88 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); -END irom; - -ARCHITECTURE mul8x8 OF irom IS - - type imem_rom_t is array (0 to 26) of inst_t; - - -- Assembled from mul8x8.jsm - constant imem_rom : imem_rom_t := - ( - "110000" & X"001", -- 0x000: JMP 0x001 - "000011" & X"450", -- 0x001: MOV R00, 0x45 - "000011" & X"F51", -- 0x002: MOV R01, 0xF5 - "111011" & X"005", -- 0x003: CALL 0x005 - "110000" & X"004", -- 0x004: JMP 0x004 - "111100" & X"002", -- 0x005: PUSH R02 - "111100" & X"003", -- 0x006: PUSH R03 - "111100" & X"004", -- 0x007: PUSH R04 - "000010" & X"014", -- 0x008: MOV R04, R01 - "000011" & X"001", -- 0x009: MOV R01, 0x00 - "000011" & X"002", -- 0x00A: MOV R02, 0x00 - "000011" & X"003", -- 0x00B: MOV R03, 0x00 - "001111" & X"014", -- 0x00C: CMP R04, 0x01 - "111001" & X"015", -- 0x00D: JEQ 0x015 - "011111" & X"004", -- 0x00E: SHR R04 - "110100" & X"012", -- 0x00F: JNC 0x012 - "010000" & X"002", -- 0x010: ADD R02, R00 - "010010" & X"013", -- 0x011: ADDC R03, R01 - "011110" & X"000", -- 0x012: SHL R00 - "100010" & X"001", -- 0x013: ROLC R01 - "110000" & X"00C", -- 0x014: JMP 0x00C - "010000" & X"020", -- 0x015: ADD R00, R02 - "010010" & X"031", -- 0x016: ADDC R01, R03 - "111101" & X"004", -- 0x017: POP R04 - "111101" & X"003", -- 0x018: POP R03 - "111101" & X"002", -- 0x019: POP R02 - "111110" & X"000" -- 0x01A: RET - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -end mul8x8; - diff --git a/lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl b/lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl deleted file mode 100644 index 4303d08..0000000 --- a/lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl +++ /dev/null @@ -1,1181 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from mul8x8.jsm - type imem_rom_t is array (0 to 1023) of inst_t; - signal imem_rom : imem_rom_t := - ( - "110000" & X"001", -- 0x000: JMP 0x001 - "000011" & X"450", -- 0x001: MOV R00, 0x45 - "000011" & X"F51", -- 0x002: MOV R01, 0xF5 - "111011" & X"005", -- 0x003: CALL 0x005 - "110000" & X"004", -- 0x004: JMP 0x004 - "111100" & X"002", -- 0x005: PUSH R02 - "111100" & X"003", -- 0x006: PUSH R03 - "111100" & X"004", -- 0x007: PUSH R04 - "000010" & X"014", -- 0x008: MOV R04, R01 - "000011" & X"001", -- 0x009: MOV R01, 0x00 - "000011" & X"002", -- 0x00A: MOV R02, 0x00 - "000011" & X"003", -- 0x00B: MOV R03, 0x00 - "001111" & X"014", -- 0x00C: CMP R04, 0x01 - "111001" & X"015", -- 0x00D: JEQ 0x015 - "011111" & X"004", -- 0x00E: SHR R04 - "110100" & X"012", -- 0x00F: JNC 0x012 - "010000" & X"002", -- 0x010: ADD R02, R00 - "010010" & X"013", -- 0x011: ADDC R03, R01 - "011110" & X"000", -- 0x012: SHL R00 - "100010" & X"001", -- 0x013: ROLC R01 - "110000" & X"00C", -- 0x014: JMP 0x00C - "010000" & X"020", -- 0x015: ADD R00, R02 - "010010" & X"031", -- 0x016: ADDC R01, R03 - "111101" & X"004", -- 0x017: POP R04 - "111101" & X"003", -- 0x018: POP R03 - "111101" & X"002", -- 0x019: POP R02 - "111110" & X"000", -- 0x01A: RET - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000" - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : inst_addr_t; - signal jtag_ld_dout : inst_t; - signal jtag_ld_din : inst_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (31 downto 0); - constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1); - jtag_ld_din <= user_regi(inst_t'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/mul8x8_xrom.vhdl b/lib/CPUs/JCpu/src/mul8x8_xrom.vhdl deleted file mode 100644 index 508e8cf..0000000 --- a/lib/CPUs/JCpu/src/mul8x8_xrom.vhdl +++ /dev/null @@ -1,317 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); -END xrom; - -ARCHITECTURE mul8x8 OF xrom IS - - type xmem_rom_t is array (0 to 255) of dmem_data_t; - - -- Assembled from mul8x8.jsm - constant xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"00", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -end mul8x8; - diff --git a/lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl b/lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl deleted file mode 100644 index a75d090..0000000 --- a/lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl +++ /dev/null @@ -1,413 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); - -END xrom; - -ARCHITECTURE loadable OF xrom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from mul8x8.jsm - type xmem_rom_t is array (0 to 255) of dmem_data_t; - signal xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"00", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : dmem_addr_t; - signal jtag_ld_dout : dmem_data_t; - signal jtag_ld_din : dmem_data_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (15 downto 0); - constant id : unsigned (15 downto 0) := X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1); - jtag_ld_din <= user_regi(dmem_data_t'left downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/reti_issue_irom.vhdl b/lib/CPUs/JCpu/src/reti_issue_irom.vhdl deleted file mode 100644 index 9355a7d..0000000 --- a/lib/CPUs/JCpu/src/reti_issue_irom.vhdl +++ /dev/null @@ -1,89 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); -END irom; - -ARCHITECTURE reti_issue OF irom IS - - type imem_rom_t is array (0 to 27) of inst_t; - - -- Assembled from reti_issue.jsm - constant imem_rom : imem_rom_t := - ( - "110000" & X"002", -- 0x000: JMP 0x002 - "111111" & X"000", -- 0x001: RETI - "000011" & X"050", -- 0x002: MOV R00, 0x05 - "100110" & X"030", -- 0x003: COUT (0x03), R00 - "000011" & X"000", -- 0x004: MOV R00, 0x00 - "000000" & X"000", -- 0x005: NOP - "010001" & X"010", -- 0x006: INC R00 - "000000" & X"000", -- 0x007: NOP - "111011" & X"01B", -- 0x008: CALL 0x01B - "000000" & X"000", -- 0x009: NOP - "111100" & X"003", -- 0x00A: PUSH R03 - "000000" & X"000", -- 0x00B: NOP - "111100" & X"002", -- 0x00C: PUSH R02 - "000000" & X"000", -- 0x00D: NOP - "111100" & X"001", -- 0x00E: PUSH R01 - "000000" & X"000", -- 0x00F: NOP - "111100" & X"000", -- 0x010: PUSH R00 - "000000" & X"000", -- 0x011: NOP - "111101" & X"000", -- 0x012: POP R00 - "000000" & X"000", -- 0x013: NOP - "111101" & X"001", -- 0x014: POP R01 - "000000" & X"000", -- 0x015: NOP - "111101" & X"002", -- 0x016: POP R02 - "000000" & X"000", -- 0x017: NOP - "111101" & X"003", -- 0x018: POP R03 - "000000" & X"000", -- 0x019: NOP - "110000" & X"005", -- 0x01A: JMP 0x005 - "111110" & X"000" -- 0x01B: RET - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -end reti_issue; - diff --git a/lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl b/lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl deleted file mode 100644 index d1b4bd1..0000000 --- a/lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl +++ /dev/null @@ -1,1181 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from reti_issue.jsm - type imem_rom_t is array (0 to 1023) of inst_t; - signal imem_rom : imem_rom_t := - ( - "110000" & X"002", -- 0x000: JMP 0x002 - "111111" & X"000", -- 0x001: RETI - "000011" & X"050", -- 0x002: MOV R00, 0x05 - "100110" & X"030", -- 0x003: COUT (0x03), R00 - "000011" & X"000", -- 0x004: MOV R00, 0x00 - "000000" & X"000", -- 0x005: NOP - "010001" & X"010", -- 0x006: INC R00 - "000000" & X"000", -- 0x007: NOP - "111011" & X"01B", -- 0x008: CALL 0x01B - "000000" & X"000", -- 0x009: NOP - "111100" & X"003", -- 0x00A: PUSH R03 - "000000" & X"000", -- 0x00B: NOP - "111100" & X"002", -- 0x00C: PUSH R02 - "000000" & X"000", -- 0x00D: NOP - "111100" & X"001", -- 0x00E: PUSH R01 - "000000" & X"000", -- 0x00F: NOP - "111100" & X"000", -- 0x010: PUSH R00 - "000000" & X"000", -- 0x011: NOP - "111101" & X"000", -- 0x012: POP R00 - "000000" & X"000", -- 0x013: NOP - "111101" & X"001", -- 0x014: POP R01 - "000000" & X"000", -- 0x015: NOP - "111101" & X"002", -- 0x016: POP R02 - "000000" & X"000", -- 0x017: NOP - "111101" & X"003", -- 0x018: POP R03 - "000000" & X"000", -- 0x019: NOP - "110000" & X"005", -- 0x01A: JMP 0x005 - "111110" & X"000", -- 0x01B: RET - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000" - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : inst_addr_t; - signal jtag_ld_dout : inst_t; - signal jtag_ld_din : inst_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (31 downto 0); - constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1); - jtag_ld_din <= user_regi(inst_t'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/reti_issue_xrom.vhdl b/lib/CPUs/JCpu/src/reti_issue_xrom.vhdl deleted file mode 100644 index a7a33f9..0000000 --- a/lib/CPUs/JCpu/src/reti_issue_xrom.vhdl +++ /dev/null @@ -1,317 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); -END xrom; - -ARCHITECTURE reti_issue OF xrom IS - - type xmem_rom_t is array (0 to 255) of dmem_data_t; - - -- Assembled from reti_issue.jsm - constant xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"00", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -end reti_issue; - diff --git a/lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl b/lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl deleted file mode 100644 index 244c1b5..0000000 --- a/lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl +++ /dev/null @@ -1,413 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); - -END xrom; - -ARCHITECTURE loadable OF xrom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from reti_issue.jsm - type xmem_rom_t is array (0 to 255) of dmem_data_t; - signal xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"00", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : dmem_addr_t; - signal jtag_ld_dout : dmem_data_t; - signal jtag_ld_din : dmem_data_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (15 downto 0); - constant id : unsigned (15 downto 0) := X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1); - jtag_ld_din <= user_regi(dmem_data_t'left downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/tb_cpu_embedded.vhd b/lib/CPUs/JCpu/src/tb_cpu_embedded.vhd deleted file mode 100644 index ede20d5..0000000 --- a/lib/CPUs/JCpu/src/tb_cpu_embedded.vhd +++ /dev/null @@ -1,129 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: testbench for embedded cpu with rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.cpu_pkg.all; - -ENTITY tb_cpu_embedded IS -END tb_cpu_embedded; - -ARCHITECTURE behavior OF tb_cpu_embedded IS - - COMPONENT cpu_embedded - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_wait : in STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0); - io_sel : out STD_LOGIC - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - type sram_t is array (integer range <>) of dmem_data_t; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal ce : std_logic := '0'; - signal int_in : std_logic := '0'; - signal int_ack : std_logic; - signal xmem_wait : std_logic := '0'; - signal xmem_din : dmem_data_t := (others => '-'); - signal xmem_dout : dmem_data_t; - signal xmem_addr : dmem_addr_t; - signal xmem_we : std_logic; - signal xmem_re : std_logic; - signal io_sel : std_logic; - signal sram : sram_t(0 to 2**dmem_addr_t'length-1); - - -BEGIN - -uut: cpu_embedded - PORT MAP( - rst => rst, - clk => clk, - ce => ce, - int_in => int_in, - int_ack => int_ack, - xmem_wait => xmem_wait, - xmem_we => xmem_we, - xmem_re => xmem_re, - xmem_din => xmem_din, - xmem_dout => xmem_dout, - xmem_addr => xmem_addr, - io_sel => io_sel - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - rst <= '0'; - wait for 2*CLK_PERIOD; - - wait until rising_edge(clk); - ce <= '1'; - - wait for 1000*CLK_PERIOD; - - assert false report "Test finished" severity error; - wait; - - end process; - -SRAM_RW: process(rst, clk, xmem_addr, xmem_dout, xmem_we) - begin - if (rst = '1') then - xmem_din <= X"00"; - elsif rising_edge(clk) then - if io_sel = '0' then - if xmem_we = '1' then - sram(to_integer(xmem_addr)) <= xmem_dout; - end if; - xmem_din <= to_01(sram(to_integer(xmem_addr))); - else - xmem_din <= X"FF"; - end if; - end if; - end process; - -END; diff --git a/lib/CPUs/JCpu/src/tb_cpu_itest.vhd b/lib/CPUs/JCpu/src/tb_cpu_itest.vhd deleted file mode 100644 index 80d8c43..0000000 --- a/lib/CPUs/JCpu/src/tb_cpu_itest.vhd +++ /dev/null @@ -1,218 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Formal test of correct function of JCPU, --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.cpu_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_cpu IS -END tb_cpu; - -ARCHITECTURE behavior OF tb_cpu IS - - COMPONENT cpu - Generic ( - use_instr_register : boolean; - use_ctrl_rom : boolean - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_wait : in STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0); - instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0); - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - io_sel : out STD_LOGIC - - ); - END COMPONENT; - - COMPONENT irom - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - type prom_t is array (integer range <>) of inst_t; - type sram_t is array (integer range <>) of dmem_data_t; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal ce : std_logic := '0'; - signal int_in : std_logic := '0'; - signal int_ack : std_logic; - signal xmem_wait : std_logic := '1'; - signal irom_data : unsigned (IMEM_DATA_WIDTH-1 downto 0) := (others => '-'); - signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0); - signal xmem_din : dmem_data_t := (others => '-'); - signal xmem_dout : dmem_data_t; - signal xmem_addr : unsigned (DMEM_DATA_WIDTH-1 downto 0); - signal xmem_we : std_logic; - signal xmem_re : std_logic; - signal io_sel : std_logic; - signal sram : sram_t(0 to 2**DMEM_DATA_WIDTH-1); - - type reg_t is record - revision : dmem_data_t; - testid : dmem_data_t; - interrupt : std_logic; - end record; - - signal reg : reg_t; - - -BEGIN - - int_in <= reg.interrupt; -uut: cpu - GENERIC MAP - ( - use_instr_register => false, - use_ctrl_rom => true - ) - PORT MAP( - rst => rst, - clk => clk, - ce => ce, - int_in => int_in, - int_ack => int_ack, - xmem_wait => xmem_wait, - xmem_we => xmem_we, - xmem_re => xmem_re, - instr_din => irom_data, - instr_addr => irom_addr, - xmem_din => xmem_din, - xmem_dout => xmem_dout, - xmem_addr => xmem_addr, - io_sel => io_sel - ); - -the_irom: irom - PORT MAP( - clk => clk, - ce => ce, - addr => irom_addr, - dout => irom_data - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -XWAIT_GEN:process(rst, clk) - variable cnt : unsigned(3 downto 0); - begin - if (rst = '1') then - cnt := (others => '1'); - elsif rising_edge(clk) then - if cnt /= "0000" then - cnt := cnt - 1; - else - cnt := (others => '1'); - xmem_wait <= not xmem_wait; - end if; - end if; - end process; - -STIMULUS: process - file RESULT: text open write_mode is "../tools/opc.list"; - variable L: line; - - begin - - for i in 0 to instr_name_array'length-1 loop - fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i)); - end loop; - - wait for 3*CLK_PERIOD; - rst <= '0'; - wait for 2*CLK_PERIOD; - - wait until rising_edge(clk); - ce <= '1'; - - assert false report "Test finished" severity error; - wait; - - end process; - -SRAM_RW: process(rst, clk) - begin - if (rst = '1') then - reg.revision <= (others => '0'); - reg.testid <= (others => '0'); - reg.interrupt <= '0'; - elsif rising_edge(clk) then - if int_ack = '1' then --- reg.interrupt <= '0'; - end if; - if xmem_we = '1' then - if io_sel = '0' then - sram(to_integer(xmem_addr)) <= xmem_dout; - else - case xmem_addr is - when X"00" => - reg.revision <= xmem_dout; - when X"01" => - reg.testid <= xmem_dout; - when X"02" => - reg.interrupt <= xmem_dout(0); - when others => null; - end case; - end if; - else - if io_sel = '0' then - xmem_din <= to_01(sram(to_integer(xmem_addr))); - else - case xmem_addr is - when X"00" => - xmem_din <= reg.revision; - when X"01" => - xmem_din <= reg.testid; - when others => - xmem_din <= X"BC"; - end case; - end if; - end if; - end if; - end process; - -END; diff --git a/lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj b/lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj deleted file mode 100644 index 18718bf..0000000 --- a/lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj +++ /dev/null @@ -1,10 +0,0 @@ -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu_pkg.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\stack_ctrl.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\reg_dual.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\pc.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\int_ctrl.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\dpath_ctrl.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipreg.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipram.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\alu.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu.vhd" diff --git a/lib/CPUs/JCpu/tools/eval_scan.rb b/lib/CPUs/JCpu/tools/eval_scan.rb deleted file mode 100644 index 0c38397..0000000 --- a/lib/CPUs/JCpu/tools/eval_scan.rb +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env ruby - -str1 = %Q!lbl: dc "Hallo", ", ", 0, 1, " der","Jens"! - -i=0; - -def get_stri_lit (str) - res = [""]; - state = "out" - - j = 0; - k = 0; - for i in (0..str.length-1) - c = str[i]; - nstate = state - case state - when "out" - if c == "\""[0] - nstate = "in" - end - when "in" - if c == "\""[0] - nstate = "out" - if j > 0 - k = k + 1; - res[k] = "" - end - else - res[k] = res[k] + format("%c", c); - j = j + 1; - end - end - state = nstate - end; - return res -end - -get_stri_lit(str1).each do |word| - puts word -end - - \ No newline at end of file diff --git a/lib/CPUs/JCpu/tools/insrom.rb b/lib/CPUs/JCpu/tools/insrom.rb deleted file mode 100644 index 6713f9f..0000000 --- a/lib/CPUs/JCpu/tools/insrom.rb +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env ruby - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: Insertion of code fragments into templates -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -arg = $* -rom_filename = arg[0].to_s -tpl_filename = arg[1].to_s - -subst_pattern = "JASM_ROM_INSERT_HERE" - -# -------------------------------------------------------- -# Open file -# -------------------------------------------------------- -romfile = File.open(rom_filename, "r") -tplfile = File.open(tpl_filename, "r") -re = Regexp.new(subst_pattern) - -while (line = tplfile.gets) - puts line - line.scan(re).each do |word| - romfile.each do |raw_line| - puts raw_line - end - end -end diff --git a/lib/CPUs/JCpu/tools/irom.vhd.tpl b/lib/CPUs/JCpu/tools/irom.vhd.tpl deleted file mode 100644 index 5f11f86..0000000 --- a/lib/CPUs/JCpu/tools/irom.vhd.tpl +++ /dev/null @@ -1,32 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE - diff --git a/lib/CPUs/JCpu/tools/irom_ld.vhd.tpl b/lib/CPUs/JCpu/tools/irom_ld.vhd.tpl deleted file mode 100644 index eaa41f3..0000000 --- a/lib/CPUs/JCpu/tools/irom_ld.vhd.tpl +++ /dev/null @@ -1,151 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : inst_addr_t; - signal jtag_ld_dout : inst_t; - signal jtag_ld_din : inst_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (31 downto 0); - constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1); - jtag_ld_din <= user_regi(inst_t'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/tools/jasm.bak.rb b/lib/CPUs/JCpu/tools/jasm.bak.rb deleted file mode 100644 index 4c9feb0..0000000 --- a/lib/CPUs/JCpu/tools/jasm.bak.rb +++ /dev/null @@ -1,494 +0,0 @@ -#!/usr/bin/env ruby - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: A small assembler for the JCPU - -# Copyright (C) 2007 J. Ahrensfeld - -# This library is free software; you can redistribute it and/or -# modify it under the terms of the GNU Lesser General Public -# License as published by the Free Software Foundation; either -# version 2.1 of the License, or (at your option) any later version. - -# This library is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -# Lesser General Public License for more details. - -# You should have received a copy of the GNU Lesser General Public -# License along with this library; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - -# For questions and ideas, please contact the author at jens@jayfield.org - -# --------------------------------------------------------------------- - -arg = $* -MAX_SIZE_ROM = 1024 -PROJECT_NAME = arg.to_s.gsub(/\..*/, "") -ENTITY_NAME = "rom" -ENTITY_DATA_TYPE = "inst_t" -ENTITY_ADDR_TYPE = "inst_addr_t" -OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list" - -# -------------------------------------------------------- -# Open file -# -------------------------------------------------------- -filename = arg.to_s -if !File.exists?(filename) - STDERR.puts "#{filename} does not exist" - exit 1 -end - -# -------------------------------------------------------- -# Pass 1 -# -------------------------------------------------------- -lc = 0 # Line counter -pc = 0 # Program counter -chip_dc = [0,0,0,0] # chip data counter -xmem_dc = 0 # xmem data counter -curr_segment = "UNDEF"; -page = 0 - -label_list=[[],[]] -instr_list=[nil] -file = File.open(filename, "r") -file.each do |raw_line| - lc += 1 - - # Make all upper case - iline = "#{raw_line}".strip.upcase - - # Remove comments - iline = iline.gsub(/;.*/, "") - - # Split instruction at spaces - iline_member = iline.split(" ") - - if iline_member[0] == nil - next - end - - mc = 0; - label = nil - clean_line = nil - if (iline_member[0] =~ /\w+:/) - mc += 1 - label = iline_member[0].delete(":") - if label_list.rindex(label) != nil - STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label) - exit 1 - end - end - - case iline_member[mc] - when nil - value = format("0x%3.3X",pc) - when "EQU" - if 0 == (iline_member[mc+1] =~ /\d+/) - value = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s)) - else - value = iline_member[mc+1] - end - when "ORG", "CODE" - pc = eval(iline_member[mc+1..iline_member.nitems].to_s) - value = format("0x%3.3X",pc) - when "CDATA", "CMEM" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: CDATA needs argument!", lc) - exit 1 - end - curr_segment = "CMEM"; - page = iline_member[mc+1].to_i(16) - when "XDATA", "XMEM" - curr_segment = "XMEM"; - when "DC" - len = 0; - iline.split("DC")[1].delete("0x").scan(/[0-9A-Fa-f]+/).each do |byte| - len += 1 - end - if curr_segment == "CMEM" - STDERR.puts format("Error in line %d: CDATA cannot be initialized!", lc) - exit 1 - else - value = format("0x%2.2X",xmem_dc) - puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment); - xmem_dc += len - end - when "DB" - len = iline_member[mc+1].to_i - if curr_segment == "CMEM" - value = format("0x%2.2X",chip_dc[page]) - puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, chip_dc[page], curr_segment, page); - chip_dc[page] += len - else - value = format("0x%2.2X",xmem_dc) - puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment); - xmem_dc += len - end - else - op_line = iline_member[mc+1..iline_member.nitems].to_s - value = format("0x%3.3X",pc) - opc = iline_member[mc] - if iline_member[mc+1] != nil - op1 = op_line.gsub(/,+.*$/, "") - end - if iline_member[mc+2] != nil - op2 = op_line.scan(/,.+$/).to_s.delete(", ") - end - if instr_list[pc] == nil - instr_list[pc] = [lc, pc, opc , op1 , op2] - pc += 1 - else - STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, pc) - exit 1 - end - end; - - # Push labels - if label - label_list = label_list + [label, value] - end -end -file.close - -# -------------------------------------------------------- -def instr(opcode) - return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0) -end - -def tcl_bits(pc, opcode) - return format("%10.10B%6.6B%12.12B",pc, opcode ,0) -end - -def instr_k(opcode, k) - return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k) -end - -def tcl_bits_k(pc, opcode, k) - return format("%10.10B%6.6B%12.12B",pc, opcode ,k) -end - -def instr_r(opcode, r) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r) -end - -def tcl_bits_r(pc, opcode, r) - return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode ,0,r) -end - -def instr_kr(opcode, k, r) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r) -end - -def tcl_bits_kr(pc, opcode, k, r) - return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r) -end - -def instr_rk(opcode, r, k) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r) -end - -def tcl_bits_rk(pc, opcode, r, k) - return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r) -end - -def instr_rr(opcode, ra, rb) - return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra) -end - -def tcl_bits_rr(pc, opcode, ra, rb) - return format("%10.10B%6.6B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra) -end - -# -------------------------------------------------------- -# Read mnemonic set -# -------------------------------------------------------- -filename = OPC_LIST_NAME -if !File.exists?(filename) - STDERR.puts "#{filename} does not exist" - exit 1 -end - -mnemo_list = [] -num_opcodes = 0 -file = File.open(filename, "r") -file.each do |raw_line| - mnemo_list[num_opcodes] = raw_line.split(" ")[1] - num_opcodes += 1 -end - -# -------------------------------------------------------- -# Pass 2 -# -------------------------------------------------------- -pc = 0 -opc_start = 2 -num_errors = 0 -vhdl_trans_list = [nil] -vhdl_comment_list = [nil] -vhdl_tcl_list = [nil] -instr_list.each do |instruct| - - # puts instruct - if instruct == nil - vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0) - vhdl_comment_list[pc] = format("0x%3.3X:", pc) - vhdl_tcl_list[pc] = tcl_bits(pc, 0) - pc += 1 - next - end - - # determine arglen of instruction - ilen = 0 - if instruct[opc_start+1] == nil - arglen = 0 - elsif instruct[opc_start+2] == nil - arglen = 1 - elsif instruct[opc_start+3] == nil - arglen = 2 - end - - # Symbol substitution - error = false - for i in (1..3) - subst_pos = opc_start+i - if instruct[subst_pos] == nil - next - end - expr_token = "" - expr_subst = nil - is_direct = true; - -# instruct[subst_pos] = instruct[subst_pos].delete(" ") - - # checks R0 .. R16, Mnemonics - instr_str = instruct[subst_pos] - if 0 == (instr_str =~ /\(.+\)/) - instr_str = instr_str.delete("()") - is_direct = false; - end - - expr_token = instr_str.split(/\+|\-|\*|\//)[0] - if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/)) - idx = label_list.rindex(expr_token) - if idx != nil - expr_subst = label_list[idx+1] - instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst) - else - STDERR.puts format("Error in line %d: Symbol \"%s\" not found", instruct[0], expr_token) - error = true - end - end - - if expr_subst != nil - if 0 == (expr_subst =~ /\d+/) - if is_direct == true - instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos])) - else - instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos])) - end - else - if 0 != (expr_subst =~ /R[0-9]+/) - STDERR.puts format("Error in line %d: Invalid expression \"%s\"", instruct[0], expr_subst) - error = true - end - end - end - end - - # Parse operands - reg = [0,0] - kk = 0 - format = instruct[opc_start] - for i in (0..1) - if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+") - # Check indirect addressing - reg[i] = instruct[opc_start+i+1].delete("R()").to_i - format += "|R" - if reg[i] > 15 - STDERR.puts format("Error in line %d: Invalid register \"R%d\" specified", instruct[0], reg[i]) - error = true - end - else - if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+") - kk = instruct[opc_start+i+1].delete("()").to_i(16) - format += "|K" - end - end - if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)") - format += "i"; - end - end - - # Output instruction - opcode = mnemo_list.rindex(format).to_i - mnemo = instruct[2]; - - case format - when "NOP", "HALT", "RET", "RETI" - vhdl_trans_list[pc] = instr(opcode) - vhdl_tcl_list[pc] = tcl_bits(pc, opcode) - minstr_comment = format("0x%3.3X: %s", pc, mnemo) - when "MOVC|R|Ri", "MOVX|R|Ri" - vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1]) - minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1]) - when "MOV|R|R", "SUB|R|R", "ADD|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R" - vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1]) - minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1]) - when "MOVC|Ri|R", "MOVX|Ri|R" - vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0]) - minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0]) - when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K" - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk) - when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki" - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk) - when "MOV|R|K", "SUB|R|K", "ADD|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K" - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk) - when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R" - vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]); - vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1]) - minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1]) - when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K" - vhdl_trans_list[pc] = instr_k(opcode, kk) - vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk) - minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk) - when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R" - vhdl_trans_list[pc] = instr_r(opcode, reg[0]) - vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0]) - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - when "TST|R" - kk = 0 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("CMP|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "INC|R" - kk = 1 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("ADD|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "DEC|R" - kk = 1 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("SUB|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - else - STDERR.puts format("Error in line %d: Not yet implemented %s", instruct[0], format) - error = true - end - - if error - num_errors += 1 - break - end - vhdl_comment_list[pc] = minstr_comment - - puts vhdl_trans_list[pc] + " -- " + minstr_comment - - pc += 1 -end - -# -------------------------------------------------------- -# Output ROM file -# -------------------------------------------------------- -if num_errors == 0 - - filename = format("rom_%s.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("ENTITY %s IS\n", ENTITY_NAME) - file.puts format("\tPort (\n") - file.puts format("\tclk\t\t\t: in STD_LOGIC;\n") - file.puts format("\tce\t\t\t: in STD_LOGIC;\n") - file.puts format("\taddr\t\t: in %s;\n", ENTITY_ADDR_TYPE) - file.puts format("\tdout\t\t: out %s\n", ENTITY_DATA_TYPE) - file.puts format("\t);\n") - file.puts format("END %s;\n", ENTITY_NAME) - file.puts format("\n") - file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, ENTITY_NAME) - file.puts format("\n") - file.puts format("\ttype instruction_rom_t is array (0 to %d) of %s;\n", pc-1, ENTITY_DATA_TYPE) - file.puts format("\n") - file.puts format("\tconstant instruction_rom : instruction_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..pc-2) - file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n" - end; - file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n" - file.puts format("\t);\n") - file.puts format("\n") - file.puts format("begin") - file.puts format("\n") - file.puts format("PROM_READ:") - file.puts format("\tprocess(clk, ce)\n") - file.puts format("\tbegin\n") - file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n") - file.puts format("\t\t\tdout <= instruction_rom(to_integer(addr));\n") - file.puts format("\t\tend if;\n") - file.puts format("\tend process;\n") - file.puts format("\n") - file.puts format("end %s;\n", PROJECT_NAME) - puts format("ROM file written to \"%s\"\n",filename) - file.close -end -if num_errors == 0 - - filename = format("preinit_%s.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("\tsignal instruction_rom : instruction_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..pc-2) - file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n" - end; - if pc < (MAX_SIZE_ROM-1) - file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n" - for i in (pc..(MAX_SIZE_ROM-2)) - file.puts "\t\t" + instr(0) + ",\n" - end; - file.puts "\t\t" + instr(0) + "\n" - else - file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n" - end - file.puts format("\t);\n") - puts format("PREINIT file written to \"%s\"\n",filename) - file.close -end -if num_errors == 0 - filename = format("rom_%s.tcl.snip", PROJECT_NAME) - file = File.open(filename, "w") - for i in (0..pc-1) - # Chipscope 8.1 -# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse); - - # Chipscope 9.1 - file.puts format("\# %s", vhdl_comment_list[i]) - file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2)); - end; - puts format("TCL snippet written to \"%s\"\n",filename) - file.close -end - -# -------------------------------------------------------- -# Output final statistics -# -------------------------------------------------------- -if num_errors == 0 - puts "Program uses #{pc} instruction addresses" - puts "No errors found" - exit 0 -else - puts "#{num_errors} errors found" - exit 1 -end diff --git a/lib/CPUs/JCpu/tools/jasm.rb b/lib/CPUs/JCpu/tools/jasm.rb deleted file mode 100644 index fdad0bb..0000000 --- a/lib/CPUs/JCpu/tools/jasm.rb +++ /dev/null @@ -1,814 +0,0 @@ -#!/usr/bin/env ruby - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: A small assembler for the JCPU -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -arg = $* -FILE_SUFFIX = "jsm" -IROM_MAX_SIZE = 1024 -IROM_ENTITY_NAME = "irom" -IROM_DATA_TYPE = "inst_t" -IROM_ADDR_TYPE = "inst_addr_t" -XROM_MAX_SIZE = 256 -XROM_DATA_TYPE = "dmem_data_t" -XROM_ADDR_TYPE = "dmem_addr_t" -XROM_ENTITY_NAME = "xrom" -OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list" - -# -------------------------------------------------------- -class Parser - def curr_segment - @curr_segment - end - def curr_segment=(arg) - @curr_segment=arg - end - def add_label(labelname, addr) - @label_list = @label_list + [labelname, addr] - end - def getLabelIdByName(label) - return @label_list.rindex(label) - end - def getLabelNameById(id) - return @label_list[id] - end - def put_instr(name, lc, opc , op1 , op2) - if get_instr != nil - STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, @pc) - exit 1 - end - @instr_list[@pc] = [lc, @pc, opc , op1 , op2, name] - end - def get_instr - return @instr_list[@pc] - end - def put_xmem(value, lc) - if get_xmem != nil - STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, xmem_dc, curr_segment) - exit 1 - end - @xmem[xmem_dc] = value - @xmem_dc = xmem_dc + 1 - end - def get_xmem - return @xmem[xmem_dc] - end - def xmem - return @xmem - end - def put_cmem(value, lc) - if get_cmem(page) != nil - STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, cmem_dc, curr_segment) - exit 1 - end - @cmem[page][cmem_dc] = value - @cmem_dc[page] = cmem_dc + 1 - end - def get_cmem(pg) - return @cmem[pg][cmem_dc] - end - def cmem(page) - return @cmem[page] - end - def cmem_dc=(addr) - @cmem_dc[page] = addr - end - def cmem_dc - @cmem_dc[page] - end - def xmem_dc=(addr) - @xmem_dc = addr - end - def xmem_dc - @xmem_dc - end - def page=(page) - @page = page; - end - def page - @page; - end - def pc=(pc) - @pc = pc; - if (pc > @pc_max) - @pc_max = pc - end - end - def pc - @pc; - end - def pc_max - @pc_max; - end - def instr_list - @instr_list - end - def label_list - @label_list - end - - def initialize() - @pc_max = 0 - @pc = 0 # Program counter - @cmem_dc = [0,0,0,0] # chip data counter - @xmem_dc = 0 # xmem data counter - @curr_segment = "UNDEF"; - @page = 0 - @label_list=[[],[]] - @instr_list=[nil] - @cmem = [[],[]]; - @xmem = []; - end - def method_missing(name, *args) - puts "I don't know the method #{name}" - end -end - -# -------------------------------------------------------- -def parse(name, obj) - -lc = 0 # Line counter -file = File.open(name, "r") - -file.each do |raw_line| - lc += 1 - - # Make all upper case - iline = "#{raw_line}".strip - - # Remove comments - iline = iline.gsub(/;.*/, "") - - # Split instruction at spaces - iline_member = iline.split(" ") - - if iline_member[0] == nil - next - end - - mc = 0; - label = nil - clean_line = nil - if (iline_member[0] =~ /\w+:/) - mc += 1 - label = iline_member[0].delete(":") - if obj.getLabelIdByName(label) != nil - STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label) - exit 1 - end - end - - token = iline_member[mc] - if token - token = token.upcase - end - - case token - when nil - if obj.curr_segment == "CMEM" - curr_addr = format("0x%3.3X",obj.cmem_dc) - elsif obj.curr_segment == "XMEM" - curr_addr = format("0x%3.3X",obj.xmem_dc) - elsif obj.curr_segment == "CODE" - curr_addr = format("0x%3.3X",obj.pc) - else - STDERR.puts format("Error in line %d: Undefined segment", lc) - exit 1 - end - when "INCLUDE" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - inc_name = iline_member[mc+1].delete("\"") - puts format("Inserting \"%s\" into \"%s\" at line %d", inc_name, name, lc); - parse(inc_name, obj) - when "EQU" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - if 0 == (iline_member[mc+1] =~ /\d+/) - curr_addr = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s)) - else - curr_addr = iline_member[mc+1] - end - when "ORG" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - offset = eval(iline_member[mc+1..iline_member.nitems].to_s) - case obj.curr_segment - when "CODE" - obj.pc = offset - curr_addr = format("0x%3.3X",obj.pc) - when "CMEM" - obj.cmem_dc = offset - when "XMEM" - obj.xmem_dc = offset - - end - when "CODE" - curr_addr = format("0x%3.3X",obj.pc) - obj.curr_segment = "CODE"; - when "CDATA", "CMEM" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - obj.curr_segment = "CMEM"; - obj.page = iline_member[mc+1].to_i(16) - when "XDATA", "XMEM" - obj.curr_segment = "XMEM"; - when "DC" - len = 0; - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - if obj.curr_segment == "CMEM" - STDERR.puts format("Error in line %d: %s cannot be initialized!", lc, obj.curr_segment) - exit 1 - elsif obj.curr_segment == "XMEM" - curr_addr = format("0x%2.2X",obj.xmem_dc) - dc_old = obj.xmem_dc; - val_array = raw_line.split(/dc|DC|Dc|dC/)[1].delete("\t").gsub(/;.*/, "").split(",") - - # Parse string literals - val_array.each do |item| - if 0 == (item =~ /.*\".*\"/) - str = item.delete("\"") - puts item - for nn in (0..str.length-1) - if str[nn] > 31 - obj.put_xmem(str[nn], lc); - puts "S: " + str[nn].to_s - len += 1 - end - end; - else - argument = item - puts "B: " + argument - obj.put_xmem(eval(argument), lc); - len += 1 - end - end - puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, dc_old, obj.curr_segment); - else - STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token) - exit 1 - end - when "DB" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - len = eval(iline_member[mc+1]).to_i - if obj.curr_segment == "CMEM" - curr_addr = format("0x%2.2X",obj.cmem_dc) - puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, obj.cmem_dc, obj.curr_segment, obj.page); - for nn in (1..len) - obj.put_cmem(0, lc) - end - elsif obj.curr_segment == "XMEM" - curr_addr = format("0x%2.2X",obj.xmem_dc) - puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, obj.xmem_dc, obj.curr_segment); - for nn in (1..len) - obj.put_xmem(0, lc) - end - else - STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token) - exit 1 - end - else - if obj.curr_segment != "CODE" - STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token) - exit 1 - end - - op_line = iline_member[mc+1..iline_member.nitems].to_s - curr_addr = format("0x%3.3X",obj.pc) - opc = token - if iline_member[mc+1] != nil - op1 = op_line.gsub(/,+.*$/, "") - end - if iline_member[mc+2] != nil - op2 = op_line.scan(/,.+$/).to_s.delete(", ") - end - obj.put_instr(name, lc, opc, op1, op2) - obj.pc = obj.pc + 1 - end; - - # Push labels - if label - obj.add_label(label, curr_addr) - end -end -file.close -return obj -end - -# -------------------------------------------------------- -# Instruction formatting -# -------------------------------------------------------- -def instr(opcode) - return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0) -end - -def tcl_bits(pc, opcode) - return format("%12.12B%8.8B%12.12B",pc, opcode ,0) -end - -def instr_k(opcode, k) - return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k) -end - -def tcl_bits_k(pc, opcode, k) - return format("%12.12B%8.8B%12.12B",pc, opcode ,k) -end - -def instr_r(opcode, r) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r) -end - -def tcl_bits_r(pc, opcode, r) - return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode ,0,r) -end - -def instr_kr(opcode, k, r) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r) -end - -def tcl_bits_kr(pc, opcode, k, r) - return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r) -end - -def instr_rk(opcode, r, k) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r) -end - -def tcl_bits_rk(pc, opcode, r, k) - return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r) -end - -def instr_rr(opcode, ra, rb) - return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra) -end - -def tcl_bits_rr(pc, opcode, ra, rb) - return format("%12.12B%8.8B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra) -end - -# -------------------------------------------------------- -# Open file -# -------------------------------------------------------- -filename = arg.to_s -if !File.exists?(filename) - STDERR.puts "#{filename} does not exist" - exit 1 -end -PROJECT_NAME = File.basename(filename, "." + FILE_SUFFIX) - -# -------------------------------------------------------- -# Pass 1 -# -------------------------------------------------------- -first_pass = Parser.new(); -parse(filename, first_pass) - -# -------------------------------------------------------- -# Read mnemonic set -# -------------------------------------------------------- -filename = OPC_LIST_NAME -if !File.exists?(filename) - STDERR.puts "#{filename} does not exist" - exit 1 -end - -mnemo_list = [] -num_opcodes = 0 -file = File.open(filename, "r") -file.each do |raw_line| - mnemo_list[num_opcodes] = raw_line.split(" ")[1] - num_opcodes += 1 -end - -# -------------------------------------------------------- -# Pass 2 -# -------------------------------------------------------- -pc = 0 -opc_start = 2 -num_errors = 0 -vhdl_trans_list = [nil] -vhdl_comment_list = [nil] -vhdl_tcl_list = [nil] - -# ToDo: Use class-methods -label_list = first_pass.label_list -instr_list = first_pass.instr_list - -instr_list.each do |instruct| - - # puts instruct - if instruct == nil - vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0) - vhdl_comment_list[pc] = format("0x%3.3X:", pc) - vhdl_tcl_list[pc] = tcl_bits(pc, 0) - pc += 1 - next - end - - # determine arglen of instruction - ilen = 0 - if instruct[opc_start+1] == nil - arglen = 0 - elsif instruct[opc_start+2] == nil - arglen = 1 - elsif instruct[opc_start+3] == nil - arglen = 2 - end - - # Symbol substitution - error = false - for i in (1..2) - subst_pos = opc_start+i - if instruct[subst_pos] == nil - next - end - expr_token = "" - expr_subst = nil - is_direct = true; - - # checks R0 .. R16, Mnemonics - instruct[subst_pos] = instruct[subst_pos].gsub(/'low/, "") - if (nil != (instruct[subst_pos] =~ /'high/)) - instruct[subst_pos]= format("%s/256", instruct[subst_pos].gsub(/'high/, "")) - end - instr_str = instruct[subst_pos] - if 0 == (instr_str =~ /\(.+\)/) - instr_str = instr_str.delete("()") - is_direct = false; - end - - expr_token = instr_str.split(/\+|\-|\*|\/|\||\&/)[0] - if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/)) - idx = label_list.rindex(expr_token) - if idx != nil - expr_subst = label_list[idx+1] - instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst) - else - STDERR.puts format("%s: Error in line %d: Symbol \"%s\" not found", instruct[5], instruct[0], expr_token) - error = true - end - end - - if expr_subst != nil - if 0 == (expr_subst =~ /\d+/) - if is_direct == true - instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos])) - else - instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos])) - end - else - if 0 != (expr_subst =~ /R[0-9]+/) - STDERR.puts format("%s: Error in line %d: Invalid expression \"%s\"", instruct[5], instruct[0], expr_subst) - error = true - end - end - end - end - - # Parse operands - reg = [0,0] - kk = 0 - format = instruct[opc_start] - for i in (0..1) - if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+") - # Check indirect addressing - reg[i] = instruct[opc_start+i+1].delete("R()").to_i - format += "|R" - if reg[i] > 15 - STDERR.puts format("%s: Error in line %d: Invalid register \"R%d\" specified", instruct[5], instruct[0], reg[i]) - error = true - end - else - if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+") - kk = eval(instruct[opc_start+i+1].delete("()")) - format += "|K" - end - end - if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)") - format += "i"; - end - end - - if error - num_errors += 1 - break - end - - # Output instruction - opcode = mnemo_list.rindex(format).to_i - mnemo = instruct[2]; - - case format - # Native instructions - when "NOP", "HALT", "RET", "RETI", "SETC" - vhdl_trans_list[pc] = instr(opcode) - vhdl_tcl_list[pc] = tcl_bits(pc, opcode) - minstr_comment = format("0x%3.3X: %s", pc, mnemo) - when "MOVC|R|Ri", "MOVX|R|Ri" - vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1]) - minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1]) - when "MOV|R|R", "SUB|R|R", "SUBC|R|R", "ADD|R|R", "ADDC|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R" - vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1]) - minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1]) - when "MOVC|Ri|R", "MOVX|Ri|R" - vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0]) - minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0]) - when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K" - kk = kk % 256; - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk) - when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki" - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk) - when "MOV|R|K", "SUB|R|K", "SUBC|R|K", "ADD|R|K", "ADDC|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K" - kk = kk % 256; - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk) - when "SUB|K|R", "SUBC|K|R" - kk = kk % 256; - vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]); - vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1]) - minstr_comment = format("0x%3.3X: %s 0x%2.2d, R%2.2X", pc, mnemo, kk, reg[1]) - when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R" - vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]); - vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1]) - minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1]) - when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K" - vhdl_trans_list[pc] = instr_k(opcode, kk) - vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk) - minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk) - when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R", "SWAP|R" - vhdl_trans_list[pc] = instr_r(opcode, reg[0]) - vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0]) - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - # Synthetic instructions - when "CLRC" - kk = 0; - minstr_comment = format("0x%3.3X: %s", pc, mnemo) - opcode = mnemo_list.rindex("SUB|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "TST|R" - kk = 0 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("CMP|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "NEG|R" - kk = 0 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("SUB|K|R").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "NOT|R" - kk = 0 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("XOR|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "INC|R" - kk = 1 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("ADD|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "DEC|R" - kk = 1 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("SUB|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - else - STDERR.puts format("%s: Error in line %d: Not yet implemented %s", instruct[5], instruct[0], format) - error = true - end - - if error - num_errors += 1 - break - end - - vhdl_comment_list[pc] = minstr_comment - - puts vhdl_trans_list[pc] + " -- " + minstr_comment - - pc += 1 -end - -# -------------------------------------------------------- -# Output ROM file -# -------------------------------------------------------- -if num_errors == 0 - - # I-ROM VHDL-ROM - filename = format("%s.irom.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("ENTITY %s IS\n", IROM_ENTITY_NAME) - file.puts format("\tPort (\n") - file.puts format("\tclk\t\t\t: in STD_LOGIC;\n") - file.puts format("\tce\t\t\t: in STD_LOGIC;\n") - file.puts format("\taddr\t\t: in %s;\n", IROM_ADDR_TYPE) - file.puts format("\tdout\t\t: out %s\n", IROM_DATA_TYPE) - file.puts format("\t);\n") - file.puts format("END %s;\n", IROM_ENTITY_NAME) - file.puts format("\n") - file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, IROM_ENTITY_NAME) - file.puts format("\n") - file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", [IROM_MAX_SIZE, pc].min-1 , IROM_DATA_TYPE) - file.puts format("\n") - file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("\tconstant imem_rom : imem_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..[IROM_MAX_SIZE, pc].min-2) - file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n" - end; - file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n" - file.puts format("\t);\n") - file.puts format("\n") - file.puts format("begin") - file.puts format("\n") - file.puts format("PROM_READ:") - file.puts format("\tprocess(clk, ce)\n") - file.puts format("\tbegin\n") - file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n") - file.puts format("\t\t\tdout <= imem_rom(to_integer(addr));\n") - file.puts format("\t\tend if;\n") - file.puts format("\tend process;\n") - file.puts format("\n") - file.puts format("end %s;\n", PROJECT_NAME) - puts format("I-ROM file written to \"%s\"\n",filename) - file.close - - # I-ROM VHDL-ROM (loadable) - filename = format("%s.irom_ld.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", IROM_MAX_SIZE-1, IROM_DATA_TYPE) - file.puts format("\tsignal imem_rom : imem_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..pc-2) - file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n" - end; - if pc < (IROM_MAX_SIZE-1) - file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n" - for i in (pc..(IROM_MAX_SIZE-2)) - file.puts "\t\t" + instr(0) + ",\n" - end; - file.puts "\t\t" + instr(0) + "\n" - else - file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n" - end - file.puts format("\t);\n") - puts format("I-ROM (loadable) file written to \"%s\"\n",filename) - file.close - - # I-ROM TCL-Loader - filename = format("%s.irom.tcl.snip", PROJECT_NAME) - file = File.open(filename, "w") - file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("# ---------------------------------------------------------------"); - file.puts format("# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA"); - file.puts format("# User 1") - file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n") - for i in (0..pc-1) - # Chipscope 8.1 -# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse); - - # Chipscope 9.1 - file.puts format("\# %s", vhdl_comment_list[i]) - file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2)); - end; - puts format("I-ROM TCL-loader written to \"%s\"\n",filename) - file.close - - # X-ROM VHDL-ROM - filename = format("%s.xrom.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("ENTITY %s IS\n", XROM_ENTITY_NAME) - file.puts format("\tPort (\n") - file.puts format("\tclk\t\t\t: in STD_LOGIC;\n") - file.puts format("\tce\t\t\t: in STD_LOGIC;\n") - file.puts format("\taddr\t\t: in %s;\n", XROM_ADDR_TYPE) - file.puts format("\tdout\t\t: out %s\n", XROM_DATA_TYPE) - file.puts format("\t);\n") - file.puts format("END %s;\n", XROM_ENTITY_NAME) - file.puts format("\n") - file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, XROM_ENTITY_NAME) - file.puts format("\n") - file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE) - file.puts format("\n") - file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("\tconstant xmem_rom : xmem_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..XROM_MAX_SIZE-2) - file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i) - end; - i = XROM_MAX_SIZE-1 - file.puts format("\t\tX\"%2.2X\" -- 0x%2.2X\n", first_pass.xmem[i], i) - file.puts format("\t);\n") - file.puts format("\n") - file.puts format("begin") - file.puts format("\n") - file.puts format("PROM_READ:") - file.puts format("\tprocess(clk, ce)\n") - file.puts format("\tbegin\n") - file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n") - file.puts format("\t\t\tdout <= xmem_rom(to_integer(addr));\n") - file.puts format("\t\tend if;\n") - file.puts format("\tend process;\n") - file.puts format("\n") - file.puts format("end %s;\n", PROJECT_NAME) - puts format("X-ROM file written to \"%s\"\n",filename) - file.close - - # X-ROM VHDL-ROM (loadable) - filename = format("%s.xrom_ld.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE) - file.puts format("\tsignal xmem_rom : xmem_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..XROM_MAX_SIZE-2) - file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i) - end; - i = XROM_MAX_SIZE-1 - file.puts format("\t\tX\"%2.2X\" -- 0x%2.2X\n", first_pass.xmem[i], i) - file.puts format("\t);\n") - puts format("X-ROM (loadable) file written to \"%s\"\n",filename) - file.close - - # X-ROM TCL-Loader - filename = format("%s.xrom.tcl.snip", PROJECT_NAME) - file = File.open(filename, "w") - file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("# ---------------------------------------------------------------"); - file.puts format("# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA"); - file.puts format("# User 2") - file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n") - for i in (0..first_pass.xmem.length-1) - # Chipscope 8.1 -# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse); - - # Chipscope 9.1 - file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%2.2X%2.2X\"\n", 16, i, first_pass.xmem[i]); - end; - puts format("X-ROM TCL-loader written to \"%s\"\n",filename) - file.close - -end - -# -------------------------------------------------------- -# Output final statistics -# -------------------------------------------------------- -if num_errors == 0 - puts "Program uses #{first_pass.pc_max} instruction addresses" - puts "No errors found" - exit 0 -else - puts "#{num_errors} errors found" - exit 1 -end - diff --git a/lib/CPUs/JCpu/tools/lib/cg.inc.jsm b/lib/CPUs/JCpu/tools/lib/cg.inc.jsm deleted file mode 100644 index 01c36c4..0000000 --- a/lib/CPUs/JCpu/tools/lib/cg.inc.jsm +++ /dev/null @@ -1,72 +0,0 @@ -; ------------------------------------------------- -; lcd.inc.jsm -; ------------------------------------------------- -; needs xio-address equates for -; reg_cg_char_addr: equ 0xXX ; RW -; reg_cg_line_addr: equ 0xXX ; RW -; reg_cg_data: equ 0xXX ; RW -; reg_cg_ctrl: equ 0xXX ; WO - -; needs delay.inc.jsm - -; ------------------------------------------------- -cg_clr_line: push R0 - mov R0, 2 - xout (reg_cg_ctrl), R0 - pop R0 - ret - -; ------------------------------------------------- -cg_clr_screen: push R0 - mov R0, 1 - xout (reg_cg_ctrl), R0 - pop R0 - ret - -; ------------------------------------------------- -; R0 : char address -; R1 : line address -cg_set_addr: call cg_wait_rdy - xout (reg_cg_line_addr), R1 - xout (reg_cg_char_addr), R0 - ret - -; ------------------------------------------------- -; R0 : character -cg_putchar: call cg_wait_rdy - xout (reg_cg_data), R0 - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_puts: push R0 -cg_p_lp: movx R0, (R1) - inc R1 - tst R0 - jz ex_cgp - call cg_putchar - jmp cg_p_lp -ex_cgp: pop R0 - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_clr_puts: call cg_clr_line - call cg_puts - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_puts_clr: call cg_puts - call cg_clr_line - ret - -; ------------------------------------------------- -cg_wait_rdy: push R0 -cg_wr_lp: xin R0, (reg_hwstat) - and R0, 0x02 - jz cg_wr_lp - pop R0 - ret - -; ------------------------------------------------- diff --git a/lib/CPUs/JCpu/tools/lib/cregs.inc.jsm b/lib/CPUs/JCpu/tools/lib/cregs.inc.jsm deleted file mode 100644 index 06d39d9..0000000 --- a/lib/CPUs/JCpu/tools/lib/cregs.inc.jsm +++ /dev/null @@ -1,7 +0,0 @@ -; JCPU On-Chip register -cpu_revision: equ 0x00 ; RO -cpu_control: equ 0x01 ; R/W -cpu_status: equ 0x02 ; RO -cpu_int_ctrl: equ 0x03 ; RW -cpu_cmem_high: equ 0x04 ; RW -cpu_stack_high: equ 0x05 ; RW diff --git a/lib/CPUs/JCpu/tools/lib/delays.inc.jsm b/lib/CPUs/JCpu/tools/lib/delays.inc.jsm deleted file mode 100644 index 6f002ee..0000000 --- a/lib/CPUs/JCpu/tools/lib/delays.inc.jsm +++ /dev/null @@ -1,64 +0,0 @@ -; ------------------------------------------------- -; Delays -; ------------------------------------------------- -delay1s: push R15 - mov R15, 10 -loop1s: call delay100ms - dec R15 - jnz loop1s - pop R15 - ret - -delay100ms: push R15 - mov R15, 10 -loop100ms: call delay10ms - dec R15 - jnz loop100ms - pop R15 - ret - -delay10ms: push R15 - mov R15, 10 -loop10ms: call delay1ms - dec R15 - jnz loop10ms - pop R15 - ret - -delay1ms: push R15 - mov R15, 10 -loop1ms: call delay100us - dec R15 - jnz loop1ms - pop R15 - ret - -delay100us: push R15 - mov R15, 10 -loop100us: call delay10us - dec R15 - jnz loop100us - pop R15 - ret - -delay10us: push R15 - mov R15, 99 -loop10us: nop - nop - nop - dec R15 - jnz loop10us - pop R15 - ret - -delay1us: push R15 - mov R15, 9 -loop1us: nop - nop - nop - dec R15 - jnz loop1us - pop R15 - ret - -; ------------------------------------------------- diff --git a/lib/CPUs/JCpu/tools/lib/lcd.inc.jsm b/lib/CPUs/JCpu/tools/lib/lcd.inc.jsm deleted file mode 100644 index d2883fa..0000000 --- a/lib/CPUs/JCpu/tools/lib/lcd.inc.jsm +++ /dev/null @@ -1,208 +0,0 @@ -; ------------------------------------------------- -; lcd.inc.jsm -; ------------------------------------------------- -; needs xmem-address definition for -; - lcd_port (LCD-Base) - -; needs delay.inc.jsm - -; ------------------------------------------------- -lcd_cmd: equ 0x00 -lcd_rd: equ 0x20 -lcd_data: equ 0x40 -lcd_enable: equ 0x80 - -LCD_CMD_Z1: equ 0x80 -LCD_CMD_Z2: equ 0xC0 -LCD_CMD_CLEAR: equ 0x01 - -; ------------------------------------------------- -; Init LCD -; ------------------------------------------------- -LCD_init: mov R2, 0x00 - mov R0, 0x03 - call _write_lcd - call delay10ms - mov R2, 0x00 - mov R0, 0x03 - call _write_lcd - call delay10ms - - mov R2, 0x00 - mov R0, 0x02 - call _write_lcd - call delay1ms - - ; 1. Function set: 4-Bit mode, two display lines - mov R0, 0x28 - call LCD_writecmd - - ; 2. Display on, no cursor - mov R0, 0x0C - call LCD_writecmd - - ; 3. Cursor shift during write - mov R0, 0x06 - call LCD_writecmd - - ; 4. Display clear - mov R0, 0x01 - call LCD_writecmd - - ret - -; ------------------------------------------------- -; LCD_waitbsy -; ------------------------------------------------- -LCD_waitbsy: push R0 -bsy_loop: call LCD_readstat - and R0, 0x80 - jz ex_bsy - call delay1us - jmp bsy_loop -ex_bsy: pop R0 - ret - -; ------------------------------------------------- -; LCD_writecmd -; ------------------------------------------------- -; R0 = cmd -LCD_writeaddr: -LCD_writecmd: push R2 - mov R2, lcd_cmd - call LCD_write - pop R2 - ret - -; ------------------------------------------------- -; LCD_putsx -; ------------------------------------------------- -; R1 = address of null-terminated string in XMEM -LCD_putsx: push R0 -putsx_loop: movx R0, (R1) - inc R1 - tst R0 - jz putsx_ex - call LCD_writechar - jmp putsx_loop -putsx_ex: pop R0 - ret - -; ------------------------------------------------- -; LCD_putsc -; ------------------------------------------------- -; R1 = address of null-terminated string in CMEM -LCD_putsc: push R0 -putsc_loop: movc R0, (R1) - inc R1 - tst R0 - jz putsc_ex - call LCD_writechar - jmp putsc_loop -putsc_ex: pop R0 - ret - -; ------------------------------------------------- -; LCD_writechar -; ------------------------------------------------- -; R0 = char -LCD_writedata: -LCD_writechar: push R2 - mov R2, lcd_data - call LCD_write - pop R2 - ret - -; ------------------------------------------------- -; LCD_write -; ------------------------------------------------- -; R0 = input -; R2 = register -LCD_write: call LCD_waitbsy - push R0 - swap R0 - call _write_lcd - pop R0 - call _write_lcd - ret - -; ------------------------------------------------- -; LCD_readstat -; ------------------------------------------------- -; R0 = status -LCD_readstat: push R2 - mov R2, lcd_cmd - call LCD_read - pop R2 - ret - -; ------------------------------------------------- -; LCD_read -; ------------------------------------------------- -; R0 = output -; R2 = register -LCD_read: call _read_lcd - swap R0 - push R0 - call _read_lcd - pop R2 - or R0, R2 - ret - -; ------------------------------------------------- -; _write -; ------------------------------------------------- -; R0 = input -_write_lcd: push R1 - - and R0, 0x0F - mov R1, R0 - or R1, R2 - xout (lcd_port), R1 - call delay1us - - mov R1, R0 - or R1, R2 - or R1, lcd_enable - xout (lcd_port), R1 - call delay1us - - mov R1, R0 - or R1, R2 - xout (lcd_port), R1 - call delay1us - - or R1, lcd_rd - xout (lcd_port), R1 - - pop R1 - ret - -; ------------------------------------------------- -; _read -; ------------------------------------------------- -; R0 = output -_read_lcd: push R1 - - mov R1, lcd_rd - or R1, R2 - xout (lcd_port), R1 - call delay1us - - mov R1, lcd_rd - or R1, R2 - or R1, lcd_enable - xout (lcd_port), R1 - call delay1us - xin R0, (lcd_port) - and R0, 0x0F - - mov R1, lcd_rd - or R1, R2 - xout (lcd_port), R1 - call delay1us - - pop R1 - ret - - \ No newline at end of file diff --git a/lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm b/lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm deleted file mode 100644 index 2f66e2a..0000000 --- a/lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm +++ /dev/null @@ -1,42 +0,0 @@ -; ------------------------------------------------- -; mul8x8.inc.jsm -; ------------------------------------------------- - -; ------------------------------------------------- -; Parameter: -; R0 : operand 1 -; R1 : operand 2 -; Return: -; R0 : product low -; R1 : product high -mul8x8: push R2 - push R3 - push R4 - - mov R4, R1 - mov R1, 0 - mov R2, 0 - mov R3, 0 - -loop1: cmp R4, 0x01 - jeq ende1 - - shr R4 - jnc next1 - - add R2, R0 - addc R3, R1 - -next1: shl R0 - rolc R1 - jmp loop1 - -ende1: add R0, R2 - addc R1, R3 - - pop R4 - pop R3 - pop R2 - ret - -; ------------------------------------------------- diff --git a/lib/CPUs/JCpu/tools/lib/uart.inc.jsm b/lib/CPUs/JCpu/tools/lib/uart.inc.jsm deleted file mode 100644 index 1733305..0000000 --- a/lib/CPUs/JCpu/tools/lib/uart.inc.jsm +++ /dev/null @@ -1,32 +0,0 @@ -; ------------------------------------------------- -; uart.inc.jsm -; ------------------------------------------------- -; needs xmem-address definition for -; - uart_status (Status register) -; - uart_data (Data register) - -; ------------------------------------------------- -; sout -; ------------------------------------------------- -; R0 = input -sout: push R1 -sout1: xin R1, (uart_status) - and R1, 0x02 - jnz sout1 - xout (uart_data), R0 - pop R1 - ret - -; ------------------------------------------------- -; sin -; ------------------------------------------------- -; R0 = output -sin: push R1 -sin1: xin R1, (uart_status) - and R1, 0x10 - jnz sin1 - xin R0, (uart_data) - pop R1 - ret - -; ------------------------------------------------- diff --git a/lib/CPUs/JCpu/tools/lib/utils.inc.jsm b/lib/CPUs/JCpu/tools/lib/utils.inc.jsm deleted file mode 100644 index f354d7c..0000000 --- a/lib/CPUs/JCpu/tools/lib/utils.inc.jsm +++ /dev/null @@ -1,32 +0,0 @@ -; ------------------------------------------------- -; utils.inc.jsm -; ------------------------------------------------- - - -; ------------------------------------------------- -; Parameter -; R0 : Bin value in lower nibble -; Return -; R0 : Hex character representing lower nibble -nibble2hex: and R0, 0x0F - cmp R0, 0x0A - jlt isNum1 - add R0, 0x07 -isNum1: add R0, 0x30 - ret - -; ------------------------------------------------- -; Parameter -; R0 : Bin value -; Return -; R0 : Hex character high -; R1 : Hex character low -bin2hex: push R0 - call nibble2hex - mov R1, R0 - pop R0 - swap R0 - call nibble2hex - ret - -; ------------------------------------------------- diff --git a/lib/CPUs/JCpu/tools/opc.list b/lib/CPUs/JCpu/tools/opc.list deleted file mode 100644 index 59b3cfa..0000000 --- a/lib/CPUs/JCpu/tools/opc.list +++ /dev/null @@ -1,64 +0,0 @@ -0 NOP -1 HALT -2 MOV|R|R -3 MOV|R|K -4 MOVX|R|Ri -5 MOVX|R|Ki -6 MOVX|Ri|R -7 MOVX|Ri|K -8 MOVX|Ki|R -9 MOVC|R|Ri -10 MOVC|R|Ki -11 MOVC|Ri|R -12 MOVC|Ri|K -13 MOVC|Ki|R -14 CMP|R|R -15 CMP|R|K -16 ADD|R|R -17 ADD|R|K -18 ADDC|R|R -19 ADDC|R|K -20 SUB|R|R -21 SUB|R|K -22 SUBC|R|R -23 SUBC|R|K -24 AND|R|R -25 AND|R|K -26 OR|R|R -27 OR|R|K -28 XOR|R|R -29 XOR|R|K -30 SHL|R -31 SHR|R -32 ROL|R -33 ROR|R -34 ROLC|R -35 RORC|R -36 XOUT|Ki|R -37 XOUT|Ri|K -38 COUT|Ki|R -39 COUT|Ri|K -40 XIN|R|Ki -41 CIN|R|Ki -42 SWAP|R -43 SETC -44 UNDEF -45 UNDEF -46 SUB|K|R -47 SUBC|K|R -48 JMP|K -49 JZ|K -50 JNZ|K -51 JC|K -52 JNC|K -53 JLT|K -54 JGT|K -55 JLE|K -56 JGE|K -57 JEQ|K -58 JNE|K -59 CALL|K -60 PUSH|R -61 POP|R -62 RET -63 RETI diff --git a/lib/CPUs/JCpu/tools/regx.rb b/lib/CPUs/JCpu/tools/regx.rb deleted file mode 100644 index 47775c9..0000000 --- a/lib/CPUs/JCpu/tools/regx.rb +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env ruby - -st = "\033[7m" -en = "\033[m" - - while TRUE - print "str> " - STDOUT.flush - str = gets - break if not str - str.chop! - print "pat> " - STDOUT.flush - re = gets - break if not re - re.chop! - str.gsub! re, "#{st}\\&#{en}" - print str, "\n" -end -print "\n" diff --git a/lib/CPUs/JCpu/tools/rom.tcl.tpl b/lib/CPUs/JCpu/tools/rom.tcl.tpl deleted file mode 100644 index 9f5c0dc..0000000 --- a/lib/CPUs/JCpu/tools/rom.tcl.tpl +++ /dev/null @@ -1,61 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/JCpu/tools/templates.rb b/lib/CPUs/JCpu/tools/templates.rb deleted file mode 100644 index 632f11c..0000000 --- a/lib/CPUs/JCpu/tools/templates.rb +++ /dev/null @@ -1,44 +0,0 @@ -#!/usr/bin/env ruby - - -template = <<'END' - -- (tv #1342) read output FIFO - ( - cycles => 1, - cm_i => bus_read_init(addr => ADDR_KS_OFIFO_DOUT), - sep => msg(""), - cm_o => bus_no_ack, - irq => (others => '0') - ), - - -- (tv #1343) wait while FIFO is read - ( - cycles => 2, - cm_i => bus_wait_ack, - sep => msg(""), - cm_o => bus_no_ack, - irq => (others => '0') - ), - - -- (tv #1343) wait for ack - ( - cycles => 1, - cm_i => bus_wait_ack, - sep => msg(""), - cm_o => bus_read_ack(dat => #{exp_data}), - irq => (others => '0') - ), - -END - -puts "KS-128 testvectors:\n" -puts "\n" * 3 - - -0.upto(10) { |sk_no| - 3.downto(0) { |sl_no| - exp_data = "slice_32(TC1_SUBKEYS(#{sk_no}), #{sl_no})" - t = template.gsub(/"/, '\\"') - puts eval("format(\"#{t}\")") - } -} diff --git a/lib/CPUs/JCpu/tools/xrom.vhd.tpl b/lib/CPUs/JCpu/tools/xrom.vhd.tpl deleted file mode 100644 index 5f11f86..0000000 --- a/lib/CPUs/JCpu/tools/xrom.vhd.tpl +++ /dev/null @@ -1,32 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE - diff --git a/lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl b/lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl deleted file mode 100644 index 696487f..0000000 --- a/lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl +++ /dev/null @@ -1,151 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); - -END xrom; - -ARCHITECTURE loadable OF xrom IS - - -- JASM_ROM_INSERT_HERE - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : dmem_addr_t; - signal jtag_ld_dout : dmem_data_t; - signal jtag_ld_din : dmem_data_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (15 downto 0); - constant id : unsigned (15 downto 0) := X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1); - jtag_ld_din <= user_regi(dmem_data_t'left downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/MIPS/sim/compile_simprim.do b/lib/CPUs/MIPS/sim/compile_simprim.do deleted file mode 100644 index 16b23bb..0000000 --- a/lib/CPUs/MIPS/sim/compile_simprim.do +++ /dev/null @@ -1,6 +0,0 @@ -vlib simprim - -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd diff --git a/lib/CPUs/MIPS/sim/compile_unisim.do b/lib/CPUs/MIPS/sim/compile_unisim.do deleted file mode 100644 index d35d8c9..0000000 --- a/lib/CPUs/MIPS/sim/compile_unisim.do +++ /dev/null @@ -1,6 +0,0 @@ -vlib unisim - -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd diff --git a/lib/CPUs/MIPS/sim/tb_eval_muldiv.fdo b/lib/CPUs/MIPS/sim/tb_eval_muldiv.fdo deleted file mode 100644 index 3b3c920..0000000 --- a/lib/CPUs/MIPS/sim/tb_eval_muldiv.fdo +++ /dev/null @@ -1,13 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/tb_eval_muldiv.vhd" -vsim -t 1ps -lib work tb_eval_muldiv -do {tb_eval_muldiv.wdo} -view wave - -view structure -view signals -run 2400ns diff --git a/lib/CPUs/MIPS/sim/tb_eval_muldiv.wdo b/lib/CPUs/MIPS/sim/tb_eval_muldiv.wdo deleted file mode 100644 index e742ca4..0000000 --- a/lib/CPUs/MIPS/sim/tb_eval_muldiv.wdo +++ /dev/null @@ -1,27 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_eval_muldiv/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op1_in -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op2_in -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp0 -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp1 -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp2 -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp3 -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result_reg -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {693234 ps} 0} {{Cursor 2} {290409 ps} 0} -configure wave -namecolwidth 149 -configure wave -valuecolwidth 171 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {2520 ns} diff --git a/lib/CPUs/MIPS/sim/tb_mips_embedded.fdo b/lib/CPUs/MIPS/sim/tb_mips_embedded.fdo deleted file mode 100644 index 49ea3ab..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_embedded.fdo +++ /dev/null @@ -1,22 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/core/mips_idecode_rom.vhd" -vcom -explicit -93 "../src/core/mips_reg.vhd" -vcom -explicit -93 "../src/core/mips_shifter.vhd" -vcom -explicit -93 "../src/core/mips_alu.vhd" -vcom -explicit -93 "../src/core/mips_bcu.vhd" -vcom -explicit -93 "../src/core/mips_pipeline.vhd" -vcom -explicit -93 "../src/core/mips_top.vhd" -vcom -explicit -93 "../src/ram.vhd" -vcom -explicit -93 "../asm/fibonacci.vhd" -vcom -explicit -93 "../src/mips_embedded.vhd" -vcom -explicit -93 "../src/tb_mips_embedded.vhd" -vsim -t 1ps -lib work tb_mips_embedded -do {tb_mips_embedded.wdo} -view wave -view structure -view signals -run 20us diff --git a/lib/CPUs/MIPS/sim/tb_mips_embedded.wdo b/lib/CPUs/MIPS/sim/tb_mips_embedded.wdo deleted file mode 100644 index 7115717..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_embedded.wdo +++ /dev/null @@ -1,41 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mips_embedded/rst -add wave -noupdate -format Logic /tb_mips_embedded/clk -add wave -noupdate -format Logic /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/exception -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/pc -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/inst_ram/sram -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_dout -add wave -noupdate -format Logic -radix hexadecimal /tb_mips_embedded/uut/dmem_re -add wave -noupdate -format Logic -radix hexadecimal /tb_mips_embedded/uut/dmem_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/imem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/imem_din -add wave -noupdate -format Logic /tb_mips_embedded/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/id_stage -add wave -noupdate -format Logic /tb_mips_embedded/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/ex_stage -add wave -noupdate -format Logic /tb_mips_embedded/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/mem_stage -add wave -noupdate -format Logic /tb_mips_embedded/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/wb_stage -add wave -noupdate -format Logic /tb_mips_embedded/clk -add wave -noupdate -format Literal /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/hdu -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {624000 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {2520 ns} diff --git a/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.fdo b/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.fdo deleted file mode 100644 index 97872a0..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.fdo +++ /dev/null @@ -1,31 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/core/mips_idecode_rom.vhd" -vcom -explicit -93 "../src/core/mips_reg.vhd" -vcom -explicit -93 "../src/core/mips_shifter.vhd" -vcom -explicit -93 "../src/core/mips_alu.vhd" -vcom -explicit -93 "../src/core/mips_bcu.vhd" -vcom -explicit -93 "../src/core/mips_pipeline.vhd" -vcom -explicit -93 "../src/core/mips_muldiv.vhd" -vcom -explicit -93 "../src/core/mips_cop.vhd" -vcom -explicit -93 "../src/core/mips_bui.vhd" -vcom -explicit -93 "../src/core/mips_top.vhd" -vcom -explicit -93 "../src/core/dcache.vhd" -vcom -explicit -93 "../asm/testbench.ROM.vhd" -vcom -explicit -93 "../src/mips_embedded.vhd" -vcom -explicit -93 "../src/mips_embedded_syn.vhd" -vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd" -vcom -explicit -93 "../../../uart/kcuart_rx.vhd" -vcom -explicit -93 "../../../uart/kcuart_tx.vhd" -vcom -explicit -93 "../../../uart/uart_rx.vhd" -vcom -explicit -93 "../../../uart/uart_tx.vhd" -vcom -explicit -93 "../src/tb_mips_embedded_syn.vhd" -vsim -t 1ps -lib work tb_mips_embedded_syn -do {tb_mips_embedded_syn.wdo} -view wave -view structure -view signals -run 100us diff --git a/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.tdo b/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.tdo deleted file mode 100644 index f9e8902..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.tdo +++ /dev/null @@ -1,13 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work - -vcom -explicit -93 "../syn/ise9/netgen/par/mips_embedded_syn_timesim.vhd" -vcom -explicit -93 "../src/tb_mips_embedded_syn.vhd" -vsim -t 1ps -sdfmax "/uut=../syn/ise9/netgen/par/mips_embedded_syn_timesim.sdf" -lib work tb_mips_embedded_syn -do {tb_mips_embedded_syn.wdo} -view wave -#add wave * -view structure -view signals -run 2400ns diff --git a/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.wdo b/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.wdo deleted file mode 100644 index 9b1276c..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.wdo +++ /dev/null @@ -1,112 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/sys_rx -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/sys_tx -add wave -noupdate -format Logic /tb_mips_embedded_syn/sys_rst_n_in -add wave -noupdate -format Logic /tb_mips_embedded_syn/sys_clk_in -add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_led -add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_dip -add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_btn -add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_error -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/cpu_rst -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/cpu_run -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_rx -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_tx -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_baud -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/uart_status_port -add wave -noupdate -format Literal -radix decimal /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_usec -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_usec_en -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_sec -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_rdy -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_en -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_re -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_dout -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_bui/s -add wave -noupdate -divider DMEM -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_dout -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_en -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_we -add wave -noupdate -divider IMEM -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/imem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/imem_din -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/imem_en -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/pc_run -add wave -noupdate -divider PC -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/pc -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/hdu -add wave -noupdate -divider Stages -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/halt -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_reg_dual_a/reg_mem -add wave -noupdate -divider Cop -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ir_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_pipe_id -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_pipe_ex -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_ex_en -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ctrl_in -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ctrl_out -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exc_entered -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/epc -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cause -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/test_reg_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/test_reg -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/events -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/eflags -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/badvaddr -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/rst -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exception -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status_save -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status_rest -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exc_strobe -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ip -add wave -noupdate -divider Stages -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/id_stage -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_dout -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/ex_stage -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/mem_stage -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/wb_stage -add wave -noupdate -divider Muldiv -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/result -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/start -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/busy -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/hilo_sel -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/din_hi -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/din_lo -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1121030000 ps} 0} {{Cursor 2} {1436367 ps} 0} {{Cursor 3} {1122030000 ps} 0} -configure wave -namecolwidth 179 -configure wave -valuecolwidth 89 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {1351336 ps} {1583596 ps} diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo deleted file mode 100644 index b272e38..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo +++ /dev/null @@ -1,15 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/core/mips_muldiv.vhd" -vcom -explicit -93 "../src/tb_mips_muldiv.vhd" -vsim -t 1ps -lib work tb_mips_muldiv -do {tb_mips_muldiv.wdo} -view wave - -view structure -view signals -run 5000us diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.ndo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.ndo deleted file mode 100644 index 70cb8bb..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_muldiv.ndo +++ /dev/null @@ -1,19 +0,0 @@ -## NOTE: Do not edit this file. -## Auto generated by Project Navigator for Post-Translate Simulation -## -vlib work -## Compile Post-Translate Model -vcom -explicit -93 "../syn/eval_muldiv/netgen/translate/muldiv_translate.vhd" -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/tb_mips_muldiv.vhd" - -vsim -t 1ps -lib work tb_mips_muldiv -#do {tb_mips_muldiv.udo} -view wave -add wave * -view structure -view signals -run 1000ns -## End diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.sdo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.sdo deleted file mode 100644 index 9546784..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_muldiv.sdo +++ /dev/null @@ -1,19 +0,0 @@ -## NOTE: Do not edit this file. -## Auto generated by Project Navigator for Post-Translate Simulation -## -vlib work -## Compile Post-Translate Model -vcom -explicit -93 "../syn/eval_muldiv/netgen/synthesis/muldiv_synthesis.vhd" -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/tb_mips_muldiv.vhd" - -vsim -t 1ps -lib work tb_mips_muldiv -do {tb_mips_muldiv.wdo} -view wave -#add wave * -view structure -view signals -run 1000ns -## End diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo deleted file mode 100644 index 2fc4121..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo +++ /dev/null @@ -1,79 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mips_muldiv/rst -add wave -noupdate -format Logic /tb_mips_muldiv/clk -add wave -noupdate -format Logic /tb_mips_muldiv/mul_divn -add wave -noupdate -format Logic /tb_mips_muldiv/start -add wave -noupdate -format Logic /tb_mips_muldiv/busy -add wave -noupdate -format Logic /tb_mips_muldiv/s_un -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo -add wave -noupdate -format Logic /tb_mips_muldiv/hilo_sel -add wave -noupdate -format Logic /tb_mips_muldiv/hilo_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/result -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_result -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_lo -add wave -noupdate -format Logic /tb_mips_muldiv/uut/pre_sum_vld -add wave -noupdate -format Logic /tb_mips_muldiv/uut/mul_en -add wave -noupdate -format Logic /tb_mips_muldiv/uut/sum_en -add wave -noupdate -divider FSM -add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt -add wave -noupdate -format Logic /tb_mips_muldiv/uut/cycle_cnt_load -add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset -add wave -noupdate -format Literal /tb_mips_muldiv/uut/s -add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn -add wave -noupdate -divider {Multiplier internals} -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_muldiv/uut/pprod -add wave -noupdate -format Literal /tb_mips_muldiv/uut/ppadd_cyi -add wave -noupdate -format Literal /tb_mips_muldiv/uut/ppadd_cyo -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_res -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_op2_r -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_res -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_reg -add wave -noupdate -divider {Divider internals} -add wave -noupdate -format Logic /tb_mips_muldiv/busy -add wave -noupdate -format Logic /tb_mips_muldiv/s_un -add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_start -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result -add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_add_cyi -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_res -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_m -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_m_n -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_q -add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_qbit -add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_en -add wave -noupdate -divider FSM -add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt -add wave -noupdate -format Logic /tb_mips_muldiv/uut/cycle_cnt_load -add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset -add wave -noupdate -format Literal /tb_mips_muldiv/uut/s -add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {4999822285 ps} 0} {{Cursor 2} {1278050000 ps} 0} -configure wave -namecolwidth 149 -configure wave -valuecolwidth 171 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {5250 us} diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.fdo b/lib/CPUs/MIPS/sim/tb_mips_top.fdo deleted file mode 100644 index 811b0b8..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top.fdo +++ /dev/null @@ -1,22 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/core/mips_idecode_rom.vhd" -vcom -explicit -93 "../src/core/mips_reg.vhd" -vcom -explicit -93 "../src/core/mips_shifter.vhd" -vcom -explicit -93 "../src/core/mips_alu.vhd" -vcom -explicit -93 "../src/core/mips_bcu.vhd" -vcom -explicit -93 "../src/core/mips_pipeline.vhd" -vcom -explicit -93 "../src/core/mips_top.vhd" -vcom -explicit -93 "../asm/fibonacci.vhd" -vcom -explicit -93 "../src/ram.vhd" -vcom -explicit -93 "../src/tb_mips_top.vhd" -vsim -t 1ps -lib work tb_mips_top -do {tb_mips_top.wdo} -view wave -view structure -view signals -run 40000ns diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.mdo b/lib/CPUs/MIPS/sim/tb_mips_top.mdo deleted file mode 100644 index 1ba3832..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top.mdo +++ /dev/null @@ -1,18 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -## Compile Post-Map Model -vcom -explicit -93 "../syn/ise9/netgen/map/mips_top_map.vhd" -vsim -t 1ps -sdfmax "/mips_top=../syn/ise9/netgen/map/mips_top_map.sdf" -lib work mips_top -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/irom_hello.vhd" -vcom -explicit -93 "../src/tb_mips_top.vhd" -vsim -t 1ps -lib work tb_mips_top -do {tb_mips_top.mwdo} -view wave -#add wave * -view structure -view signals -run 2400ns diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.mwdo b/lib/CPUs/MIPS/sim/tb_mips_top.mwdo deleted file mode 100644 index b24adae..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top.mwdo +++ /dev/null @@ -1,31 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mips_top/rst -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/ce -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr -add wave -noupdate -format Logic /tb_mips_top/dmem_we -add wave -noupdate -format Logic /tb_mips_top/dmem_re -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline_ex_stage_alu_op2 -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline_ex_stage_alu_result -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {77481 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {729730 ps} diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.sdo b/lib/CPUs/MIPS/sim/tb_mips_top.sdo deleted file mode 100644 index 25435ef..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top.sdo +++ /dev/null @@ -1,16 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../syn/ise9/netgen/synthesis/mips_top_synthesis.vhd" -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/irom_hello.vhd" -vcom -explicit -93 "../src/tb_mips_top.vhd" -vsim -t 1ps -lib work tb_mips_top -#do {tb_mips_top.wdo} -view wave -add wave * -view structure -view signals -run 2400ns diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo deleted file mode 100644 index 833e5af..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top.wdo +++ /dev/null @@ -1,51 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mips_top/rst -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/cpu_halt -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout -add wave -noupdate -format Logic /tb_mips_top/dmem_re -add wave -noupdate -format Logic /tb_mips_top/dmem_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_ram/sram -add wave -noupdate -divider ALU -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -divider PC -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/pc -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/exception -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/stall -add wave -noupdate -divider PC -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/if_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage -add wave -noupdate -format Logic /tb_mips_top/clk -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {0 ps} 0} -configure wave -namecolwidth 188 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {42 us} diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.mdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.mdo deleted file mode 100644 index 91b4dc0..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top_syn.mdo +++ /dev/null @@ -1,17 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -## Compile Post-Map Model -vcom -explicit -93 "../syn/ise9/netgen/map/mips_top_syn_map.vhd" -vsim -t 1ps -sdfmax "/mips_top_syn=../syn/ise9/netgen/map/mips_top_syn_map.sdf" -lib work mips_top_syn -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/irom_hello.vhd" -vcom -explicit -93 "../src/tb_mips_top_syn.vhd" -vsim -t 1ps -lib work tb_mips_top_syn -do {tb_mips_top_syn.wdo} -view wave -#add wave * -view structure -view signals -run 2400ns diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.tdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.tdo deleted file mode 100644 index cc7c65d..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top_syn.tdo +++ /dev/null @@ -1,17 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -## Compile Post-Map Model -vcom -explicit -93 "../syn/ise9/netgen/par/mips_top_syn_timesim.vhd" -vsim -t 1ps -sdfmax "/mips_top_syn=../syn/ise9/netgen/par/mips_top_syn_timesim.sdf" -lib work mips_top_syn -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/irom_hello.vhd" -vcom -explicit -93 "../src/tb_mips_top_syn.vhd" -vsim -t 1ps -lib work tb_mips_top_syn -do {tb_mips_top_syn.wdo} -view wave -#add wave * -view structure -view signals -run 2400ns diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo deleted file mode 100644 index eafadd7..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo +++ /dev/null @@ -1,31 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mips_top_syn/rst -add wave -noupdate -format Logic /tb_mips_top_syn/clk -add wave -noupdate -format Logic /tb_mips_top_syn/ce -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/irom_data -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/irom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_addr -add wave -noupdate -format Logic /tb_mips_top_syn/dmem_we -add wave -noupdate -format Logic /tb_mips_top_syn/dmem_re -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/uut/inst_mips_top_inst_pipeline_id_stage_boff -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/uut/inst_mips_top_inst_pipeline_stage_ex_inst_alu_sum_res -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top_syn/sram -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {118199 ps} 0} -configure wave -namecolwidth 188 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {2520 ns} diff --git a/lib/CPUs/MIPS/src/core/dcache.vhd b/lib/CPUs/MIPS/src/core/dcache.vhd deleted file mode 100644 index 367c9d5..0000000 --- a/lib/CPUs/MIPS/src/core/dcache.vhd +++ /dev/null @@ -1,430 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - -library work; -use work.mips_types.all; - -ENTITY dcache IS - Generic - ( - cache_size : natural := 2048; -- words - line_size : natural := 8 -- words - ); - Port - ( - clk : in STD_LOGIC; - rst : in STD_LOGIC; - en : in STD_LOGIC; - cpu_en : in STD_LOGIC; - cpu_r_wn : in STD_LOGIC; - cpu_we : in unsigned(3 downto 0); - cpu_addr : in word_t; - cpu_din : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC; - mem_req : out STD_LOGIC; - mem_gnt : in STD_LOGIC; - mem_en : out STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC - ); -END dcache; - -ARCHITECTURE behavior OF dcache IS - -COMPONENT dpram_1w1r - GENERIC - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - PORT ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -END COMPONENT; - -COMPONENT dpram_2w2r is - GENERIC - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - PORT - ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -END COMPONENT; - - function lg2(x : natural) return natural is - begin - return natural(ceil(log2(real(x)))); - end lg2; - - function po2(x : natural) return natural is - begin - - return 2**lg2(x); - end po2; - - constant word_index_width : natural := lg2(line_size); - constant cache_index_width : natural := lg2(cache_size) - word_index_width; - constant tag_width : natural := 32 - word_index_width - cache_index_width - 2; - constant tag_parity_width : natural := 3; - constant tram_data_width : natural := 2 + tag_parity_width + tag_width; - constant tram_addr_width : natural := cache_index_width; - - subtype tram_data_t is unsigned (tram_data_width-1 downto 0); - - type dcache_entry_t is record - valid : std_logic; - dirty : std_logic; - tv_p : unsigned(tag_parity_width-1 downto 0); - tag : unsigned(tag_width-1 downto 0); - end record; - - alias cpu_word_index is cpu_addr(word_index_width+1 downto 2); - alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - - function to_dcache_entry(x : tram_data_t) return dcache_entry_t is - variable result : dcache_entry_t; - begin - result.valid := x(0); - result.dirty := x(1); - result.tv_p := x(4 downto 2); - result.tag := x(tag_width+4 downto 5); - - return result; - end to_dcache_entry; - - function to_tram_data(x : dcache_entry_t) return tram_data_t is - variable result : tram_data_t; - begin - result(0) := x.valid; - result(1) := x.dirty; - result(4 downto 2) := x.tv_p; - result(tag_width+4 downto 5) := x.tag; - - return result; - end to_tram_data; - - type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache, wr_cache); - signal s, sn : cache_state_t; - - signal cache_busy : std_logic; - signal cache_read_miss : std_logic; - signal cache_write_miss : std_logic; - signal tag_match : std_logic; - signal word_index_reg : unsigned(word_index_width-1 downto 0); - signal cache_index_reg : unsigned(cache_index_width-1 downto 0); - signal tag_index_reg : unsigned(tag_width-1 downto 0); - - signal cache_entry_in : dcache_entry_t; - signal cache_entry_out : dcache_entry_t; - signal cpu_dram_addr : unsigned(lg2(cache_size)-1 downto 0); - signal cpu_dram_dout : word_t; - signal cpu_dram_din : word_t; - signal cpu_data_reg : word_t; - signal cpu_we_reg : unsigned(3 downto 0); - signal ctrl_force_we : unsigned(3 downto 0); - signal cpu_was_write : std_logic; - signal ctrl_dram_addr : unsigned(lg2(cache_size)-1 downto 0); - signal ctrl_dram_din : word_t; - signal ctrl_dram_we : unsigned(3 downto 0); - signal cpu_dram_we : unsigned(3 downto 0); - signal dram_en : std_logic; - signal cpu_was_en : std_logic; - - signal tram_addr_rd : unsigned(cache_index_width-1 downto 0); - signal tram_dout : tram_data_t; - signal tram_addr_wr : unsigned(cache_index_width-1 downto 0); - signal tram_din : tram_data_t; - signal tram_re : std_logic; - signal tram_we : std_logic; - - signal ram_index_count : natural range 0 to 2**word_index_width-1; - signal ram_index_count_rst : std_logic; - signal cache_index_count : natural range 0 to 2**cache_index_width-1; - signal cache_index_count_en : std_logic; - signal mem_index_count : natural range 0 to 2**word_index_width-1; - signal mem_index_count_en : std_logic; - signal mem_index_count_rst : std_logic; - signal cpu_reg_en : std_logic; - signal was_miss : std_logic; - signal data_write : std_logic; - signal cpu_we2 : std_logic; - -begin - - -cpu_index_reg: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - cache_index_reg <= (others => '0'); - tag_index_reg <= (others => '0'); - cpu_was_write <= '0'; - elsif cpu_reg_en = '1' and en = '1' then - word_index_reg <= cpu_word_index; - cache_index_reg <= cpu_cache_index; - tag_index_reg <= cpu_tag; - cpu_data_reg <= cpu_din; - cpu_we_reg <= cpu_we; - cpu_was_write <= not cpu_r_wn; - end if; - end if; - end process; - -cpu_was_wr_reg: - process(clk) - begin - if rising_edge(clk) then - cpu_was_en <= '0'; - cpu_we2 <= '0'; - if cpu_en = '1' and en = '1' then - cpu_we2 <= not cpu_r_wn; - cpu_was_en <= '1'; - cpu_dram_din <= cpu_din; - end if; - end if; - end process; - -inst_tag_ram : dpram_1w1r - GENERIC MAP ( - addr_width => tram_addr_width, - data_width => tram_data_width - ) - PORT MAP ( - clka => clk, - clkb => clk, - en_a => '1', - en_b => tram_re, - we_a => tram_we, - addr_a => tram_addr_wr, - addr_b => tram_addr_rd, - din_a => tram_din, - dout_b => tram_dout - ); - -gen_data_ram: - for i in 0 to 3 generate - begin - - inst_data_ram : dpram_2w2r - GENERIC MAP ( - addr_width => lg2(cache_size), - data_width => word_t'length/4 - ) - PORT MAP ( - clk_a => clk, - clk_b => clk, - en_a => '1', - en_b => dram_en, - we_a => ctrl_dram_we(i), - we_b => cpu_dram_we(i), - addr_a => ctrl_dram_addr, - addr_b => cpu_dram_addr, - din_a => ctrl_dram_din(8*(i+1)-1 downto 8*i), - din_b => cpu_dram_din(8*(i+1)-1 downto 8*i), - dout_a => open, - dout_b => cpu_dram_dout(8*(i+1)-1 downto 8*i) - ); - end generate; - -cache_state_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - - cpu_busy <= cache_busy; - cpu_dout <= cpu_dram_dout; - - tag_match <= '1' when tag_index_reg = cache_entry_out.tag else '0'; - cache_read_miss <= not (tag_match and cache_entry_out.valid) and not cpu_was_write; - cache_write_miss <= not (tag_match and cache_entry_out.valid and cpu_was_write); - tram_din <= to_tram_data(cache_entry_in); - tram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg; - cache_entry_out <= to_dcache_entry(tram_dout); - cpu_dram_addr <= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_we2 = '0') else (cache_index_reg & word_index_reg); - mem_addr <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00"; - ctrl_dram_addr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width); - ctrl_dram_din <= mem_din; - ctrl_dram_we <= (3 downto 0 => (data_write and mem_valid)) or ctrl_force_we; - cpu_dram_we <= cpu_we_reg when (cpu_we2 = '1' and cache_write_miss = '0') else (others => '0'); - -cache_state: - process(s, cache_read_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, mem_valid, tag_index_reg, cpu_en, cpu_r_wn, mem_gnt, mem_rdy, cpu_was_en, cpu_was_write, cpu_we_reg) - begin - cpu_reg_en <= '0'; - cache_busy <= '1'; - tram_we <= '0'; - cache_index_count_en <= '0'; - ram_index_count_rst <= '0'; - mem_index_count_en <= '0'; - mem_index_count_rst <= '0'; - mem_req <= '0'; - mem_en <= '0'; - dram_en <= '0'; - tram_re <= '0'; - was_miss <= '0'; - data_write <= '0'; - tram_addr_wr <= to_unsigned(cache_index_count, cache_index_width); - cache_entry_in.tv_p <= (others => '0'); - cache_entry_in.tag <= tag_index_reg; - cache_entry_in.valid <= '0'; - cache_entry_in.dirty <= '0'; - ctrl_force_we <= (others => '0'); - sn <= s; - - case s is - when init => - sn <= flush; - when ready => - cache_busy <= '0'; - cpu_reg_en <= '1'; - dram_en <= cpu_en or cpu_was_en; - tram_re <= cpu_en; - if cpu_was_en = '1' then - if cache_read_miss = '1' then - sn <= mem_request; - cpu_reg_en <= '0'; - cache_busy <= '1'; - end if; - end if; - when flush => - cache_index_count_en <= '1'; - tram_addr_wr <= to_unsigned(cache_index_count, cache_index_width); - tram_we <= '1'; - cache_entry_in.valid <= '0'; - cache_entry_in.tag <= (others => '0'); - if cache_index_count = 0 then - sn <= ready; - if cpu_en = '1' then - cpu_reg_en <= '1'; - dram_en <= '1'; - tram_re <= '1'; - end if; - end if; - when mem_request => - ram_index_count_rst <= '1'; - mem_index_count_rst <= '1'; - mem_req <= '1'; - if mem_gnt = '1' then - sn <= mem_access; - end if; - when mem_access => - data_write <= '1'; - mem_req <= '1'; - if mem_rdy = '1' then - mem_index_count_en <= '1'; - mem_en <= '1'; - if mem_index_count = 2**word_index_width-1 then - sn <= mem_data; - end if; - end if; - when mem_data => - mem_req <= '1'; - data_write <= '1'; - if ram_index_count = 2**word_index_width-1 then - if mem_valid = '1' then - sn <= upd_cache; - end if; - end if; - when upd_cache => - mem_req <= '1'; - tram_addr_wr <= cache_index_reg; - tram_we <= '1'; - cache_entry_in.valid <= '1'; - if cpu_was_write = '1' then - sn <= wr_cache; - else - sn <= rd_cache; - end if; - - when rd_cache => - tram_re <= '1'; - dram_en <= '1'; - was_miss <= '1'; - sn <= ready; - - when wr_cache => - tram_re <= '1'; - ctrl_force_we <= cpu_we_reg; - sn <= ready; - when others => - sn <= ready; - end case; - end process; - -cache_index_counter: - process(clk) - begin - if rising_edge(clk) then - if cache_index_count_en = '0' then - cache_index_count <= 2**cache_index_width-1; - elsif cache_index_count /= 0 then - cache_index_count <= cache_index_count - 1; - end if; - end if; - end process; - -ram_index_counter: - process(clk) - begin - if rising_edge(clk) then - if ram_index_count_rst = '1' then - ram_index_count <= 0; - elsif data_write = '1' and mem_valid = '1' then - if ram_index_count /= 2**word_index_width-1 then - ram_index_count <= ram_index_count + 1; - end if; - end if; - end if; - end process; - -mem_index_counter: - process(clk) - begin - if rising_edge(clk) then - if mem_index_count_rst = '1' then - mem_index_count <= 0; - elsif mem_index_count_en = '1' then - if mem_index_count /= 2**word_index_width-1 then - mem_index_count <= mem_index_count + 1; - end if; - end if; - end if; - end process; - -end behavior; diff --git a/lib/CPUs/MIPS/src/core/icache.vhd b/lib/CPUs/MIPS/src/core/icache.vhd deleted file mode 100644 index d7e3026..0000000 --- a/lib/CPUs/MIPS/src/core/icache.vhd +++ /dev/null @@ -1,356 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - -library work; -use work.mips_types.all; - -ENTITY icache IS - Generic - ( - cache_size : natural := 2048; -- words - line_size : natural := 8 -- words - ); - Port - ( - clk : in STD_LOGIC; - rst : in STD_LOGIC; - en : in STD_LOGIC; - cpu_en : in STD_LOGIC; - cpu_addr : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC; - mem_req : out STD_LOGIC; - mem_gnt : in STD_LOGIC; - mem_en : out STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC - ); -END icache; - -ARCHITECTURE behavior OF icache IS - -COMPONENT dpram_1w1r - GENERIC - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - PORT ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -END COMPONENT; - - function lg2(x : natural) return natural is - begin - return natural(ceil(log2(real(x)))); - end lg2; - - function po2(x : natural) return natural is - begin - - return 2**lg2(x); - end po2; - - constant word_index_width : natural := lg2(line_size); - constant cache_index_width : natural := lg2(cache_size) - word_index_width; - constant tag_width : natural := 32 - word_index_width - cache_index_width - 2; - constant tag_parity_width : natural := 3; - constant tag_ram_data_width : natural := 1 + tag_parity_width + tag_width; - constant tag_ram_addr_width : natural := cache_index_width; - - subtype tag_ram_data_t is unsigned (tag_ram_data_width-1 downto 0); - - type icache_entry_t is record - valid : std_logic; - tv_p : unsigned(tag_parity_width-1 downto 0); - tag : unsigned(tag_width-1 downto 0); - end record; - - alias cpu_word_index is cpu_addr(word_index_width+1 downto 2); - alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - - function to_icache_entry(x : tag_ram_data_t) return icache_entry_t is - variable result : icache_entry_t; - begin - result.valid := x(0); - result.tv_p := x(3 downto 1); - result.tag := x(tag_width+3 downto 4); - - return result; - end to_icache_entry; - - function to_tag_ram_data(x : icache_entry_t) return tag_ram_data_t is - variable result : tag_ram_data_t; - begin - result(0) := x.valid; - result(3 downto 1) := x.tv_p; - result(tag_width+3 downto 4) := x.tag; - - return result; - end to_tag_ram_data; - - type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache); - signal s, sn : cache_state_t; - - signal cache_busy : std_logic; - signal cache_miss : std_logic; - signal tag_match : std_logic; - signal word_index_reg : unsigned(word_index_width-1 downto 0); - signal cache_index_reg : unsigned(cache_index_width-1 downto 0); - signal tag_index_reg : unsigned(tag_width-1 downto 0); - - signal cache_entry_in : icache_entry_t; - signal cache_entry_out : icache_entry_t; - signal data_ram_addr_rd : unsigned(lg2(cache_size)-1 downto 0); - signal data_ram_data_rd : word_t; - signal data_ram_addr_wr : unsigned(lg2(cache_size)-1 downto 0); - signal data_ram_data_wr : word_t; - signal data_ram_we : std_logic; - signal data_ram_re : std_logic; - - signal tag_ram_addr_rd : unsigned(cache_index_width-1 downto 0); - signal tag_ram_data_rd : tag_ram_data_t; - signal tag_ram_addr_wr : unsigned(cache_index_width-1 downto 0); - signal tag_ram_data_wr : tag_ram_data_t; - signal tag_ram_re : std_logic; - signal tag_ram_we : std_logic; - - signal ram_index_count : natural range 0 to 2**word_index_width-1; - signal ram_index_count_rst : std_logic; - signal cache_index_count : natural range 0 to 2**cache_index_width-1; - signal cache_index_count_en : std_logic; - signal mem_index_count : natural range 0 to 2**word_index_width-1; - signal mem_index_count_en : std_logic; - signal mem_index_count_rst : std_logic; - signal cpu_reg_en : std_logic; - signal was_miss : std_logic; - signal data_write : std_logic; - -begin - - -cpu_index_reg: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - cache_index_reg <= (others => '0'); - tag_index_reg <= (others => '0'); - elsif cpu_reg_en = '1' then - word_index_reg <= cpu_word_index; - cache_index_reg <= cpu_cache_index; - tag_index_reg <= cpu_tag; - end if; - end if; - end process; - -inst_tag_ram : dpram_1w1r - GENERIC MAP ( - addr_width => tag_ram_addr_width, - data_width => tag_ram_data_width - ) - PORT MAP ( - clka => clk, - clkb => clk, - en_a => '1', - en_b => tag_ram_re, - we_a => tag_ram_we, - addr_a => tag_ram_addr_wr, - addr_b => tag_ram_addr_rd, - din_a => tag_ram_data_wr, - dout_b => tag_ram_data_rd - ); - -inst_data_ram : dpram_1w1r - GENERIC MAP ( - addr_width => lg2(cache_size), - data_width => word_t'length - ) - PORT MAP ( - clka => clk, - clkb => clk, - en_a => '1', - en_b => data_ram_re, - we_a => data_ram_we, - addr_a => data_ram_addr_wr, - addr_b => data_ram_addr_rd, - din_a => data_ram_data_wr, - dout_b => data_ram_data_rd - ); - - -cache_state_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - - cpu_busy <= cache_busy; - cpu_dout <= data_ram_data_rd; - - tag_match <= '1' when tag_index_reg = cache_entry_out.tag else '0'; - cache_miss <= not (tag_match and cache_entry_out.valid); - tag_ram_data_wr <= to_tag_ram_data(cache_entry_in); - tag_ram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg; - cache_entry_out <= to_icache_entry(tag_ram_data_rd); - data_ram_addr_rd <= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (cache_index_reg & word_index_reg); - mem_addr <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00"; - data_ram_addr_wr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width); - data_ram_data_wr <= mem_din; - data_ram_we <= data_write and mem_valid; - -cache_state: - process(s, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, mem_valid, tag_index_reg, cpu_en, mem_gnt, mem_rdy, en) - begin - cpu_reg_en <= '0'; - cache_busy <= '1'; - tag_ram_we <= '0'; - cache_index_count_en <= '0'; - ram_index_count_rst <= '0'; - mem_index_count_en <= '0'; - mem_index_count_rst <= '0'; - mem_req <= '0'; - mem_en <= '0'; - data_ram_re <= '0'; - tag_ram_re <= '0'; - was_miss <= '0'; - data_write <= '0'; - tag_ram_addr_wr <= to_unsigned(cache_index_count, cache_index_width); - cache_entry_in.tv_p <= (others => '0'); - cache_entry_in.tag <= tag_index_reg; - cache_entry_in.valid <= '0'; - sn <= s; - - case s is - when init => - sn <= flush; - when ready => - if en = '1' then - cache_busy <= '0'; - if cache_miss = '1' then - sn <= mem_request; - cpu_reg_en <= '0'; - cache_busy <= '1'; - elsif cpu_en = '1' then - cpu_reg_en <= '1'; - data_ram_re <= '1'; - tag_ram_re <= '1'; - end if; - end if; - when flush => - cache_index_count_en <= '1'; - tag_ram_addr_wr <= to_unsigned(cache_index_count, cache_index_width); - tag_ram_we <= '1'; - cache_entry_in.valid <= '0'; - cache_entry_in.tag <= (others => '0'); - if cache_index_count = 0 then - sn <= ready; - if cpu_en = '1' then - cpu_reg_en <= '1'; - data_ram_re <= '1'; - tag_ram_re <= '1'; - end if; - end if; - when mem_request => - ram_index_count_rst <= '1'; - mem_index_count_rst <= '1'; - mem_req <= '1'; - if mem_gnt = '1' then - sn <= mem_access; - end if; - when mem_access => - data_write <= '1'; - mem_req <= '1'; - if mem_rdy = '1' then - mem_index_count_en <= '1'; - mem_en <= '1'; - if mem_index_count = 2**word_index_width-1 then - sn <= mem_data; - end if; - end if; - when mem_data => - mem_req <= '1'; - data_write <= '1'; - if ram_index_count = 2**word_index_width-1 then - if mem_valid = '1' then - sn <= upd_cache; - end if; - end if; - when upd_cache => - mem_req <= '1'; - tag_ram_addr_wr <= cache_index_reg; - tag_ram_we <= '1'; - cache_entry_in.valid <= '1'; - sn <= rd_cache; - - when rd_cache => --- mem_req <= '1'; - tag_ram_re <= '1'; - data_ram_re <= '1'; - was_miss <= '1'; - sn <= ready; - when others => - sn <= ready; - end case; - end process; - -cache_index_counter: - process(clk) - begin - if rising_edge(clk) then - if cache_index_count_en = '0' then - cache_index_count <= 2**cache_index_width-1; - elsif cache_index_count /= 0 then - cache_index_count <= cache_index_count - 1; - end if; - end if; - end process; - -ram_index_counter: - process(clk) - begin - if rising_edge(clk) then - if ram_index_count_rst = '1' then - ram_index_count <= 0; - elsif data_write = '1' and mem_valid = '1' then - if ram_index_count /= 2**word_index_width-1 then - ram_index_count <= ram_index_count + 1; - end if; - end if; - end if; - end process; - -mem_index_counter: - process(clk) - begin - if rising_edge(clk) then - if mem_index_count_rst = '1' then - mem_index_count <= 0; - elsif mem_index_count_en = '1' then - if mem_index_count /= 2**word_index_width-1 then - mem_index_count <= mem_index_count + 1; - end if; - end if; - end if; - end process; - -end behavior; diff --git a/lib/CPUs/MIPS/src/core/mips_alu.vhd b/lib/CPUs/MIPS/src/core/mips_alu.vhd deleted file mode 100644 index a64b5a4..0000000 --- a/lib/CPUs/MIPS/src/core/mips_alu.vhd +++ /dev/null @@ -1,184 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity alu is - Generic - ( - data_width : integer := 8 - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - op2_shifted : in unsigned (data_width-1 downto 0); - ctrl : in alu_ctrl_t; - result : out unsigned (data_width-1 downto 0); - flags : out alu_flags_t - ); -end alu; - -architecture Behavioral of alu is - - signal sum_res : unsigned (data_width-1 downto 0); - signal and_res : unsigned (data_width-1 downto 0); - signal xor_res : unsigned (data_width-1 downto 0); - signal nor_res : unsigned (data_width-1 downto 0); - signal or_res : unsigned (data_width-1 downto 0); - signal eq, sa, sb, sr, c, z : STD_LOGIC; - signal lts, ltu : STD_LOGIC; - --------------------------------------------------------------------------- -begin - - eq <= '1' when op1_in = op2_in else '0' after 3 ns; - sa <= op1_in(op1_in'left); - sb <= op2_in(op2_in'left); - sr <= sum_res(sum_res'left); - z <= '1' when op1_in = (data_width-1 downto 0 => '0') else '0' after 2 ns; - - flags.uvf <= (not ctrl.add) and ((sa and (not sb) and (not sr)) or ((not sa) and sb and sr)); - flags.ovf <= ctrl.add and ((sa and sb and (not sr)) or ((not sa) and (not sb) and sr)); --- lts <= (not eq) and (((not c) and sa and sb) or (((not sr) and sa) or (sa and (not sb)) or (sr and (not sb)))); - lts <= not eq and ((not c and sa) or (not sb and sa) or (not sb and sr)); - - ltu <= (not eq) and (not c); - flags.lts <= lts; - flags.ltu <= ltu; - flags.c <= c; - --------------------------------------------------------------------------- -proc_op_and: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - and_res <= (x1 and x2) after 1 ns; - - end process; - --------------------------------------------------------------------------- -proc_proc_xor: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - xor_res <= (x1 xor x2) after 2 ns; - - end process; - --------------------------------------------------------------------------- -proc_proc_nor: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - nor_res <= (x1 nor x2) after 1 ns; - - end process; - --------------------------------------------------------------------------- -proc_proc_or: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - or_res <= (x1 or x2) after 1 ns; - - end process; - --------------------------------------------------------------------------- -proc_alu_out: - process(ctrl, sum_res, and_res, xor_res, nor_res, or_res, op2_shifted, lts, ltu) - begin - - result <= sum_res; - - case ctrl.outsel is - - when alu_adder => - result <= sum_res; - - when alu_and => - result <= and_res; - - when alu_xor => - result <= xor_res; - - when alu_nor => - result <= nor_res; - - when alu_or => - result <= or_res; - - when alu_shift2 => - result <= op2_shifted; - - when alu_ltu => - result <= (data_width-1 downto 1 => '0') & ltu; - - when alu_lts => - result <= (data_width-1 downto 1 => '0') & lts; - - when others => null; - - end case; - - end process; - --------------------------------------------------------------------------- -alu_addsub: - process(op1_in, op2_in, ctrl) - variable sum : unsigned(data_width+1 downto 0); - variable op1, op2 : unsigned(data_width+1 downto 0); - begin - - op1 := '0' & op1_in & not ctrl.add; - if (ctrl.add = '1') then - op2 := '0' & op2_in & '0'; - else - op2 := '0' & not op2_in & '1'; - end if; - sum := op1 + op2; - - -- Form sum + carry - sum_res <= unsigned(sum(data_width downto 1)) after 4 ns; - c <= sum(sum'left) after 4 ns; - - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_bcu.vhd b/lib/CPUs/MIPS/src/core/mips_bcu.vhd deleted file mode 100644 index 14e3f36..0000000 --- a/lib/CPUs/MIPS/src/core/mips_bcu.vhd +++ /dev/null @@ -1,53 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity bcu is - Generic - ( - data_width : integer := 8 - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - flags : out bcu_flags_t - ); -end bcu; - -architecture Behavioral of bcu is - --------------------------------------------------------------------------- -begin - - flags.eq <= '1' when op1_in = op2_in else '0' after 3 ns; - flags.z <= '1' when op1_in = (data_width-1 downto 0 => '0') else '0' after 2 ns; - flags.ltz <= op1_in(op1_in'left) after 1 ns; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd deleted file mode 100644 index b1adabe..0000000 --- a/lib/CPUs/MIPS/src/core/mips_bui.vhd +++ /dev/null @@ -1,396 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: JIPS top file --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - -entity bui is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - cpu_wait : out STD_LOGIC; - cpu_imem_rdy : out STD_LOGIC; - cpu_imem_en : in STD_LOGIC; - cpu_imem_addr : in word_t; - cpu_imem_din : out word_t; - cpu_dmem_rdy : out STD_LOGIC; - cpu_dmem_en : in STD_LOGIC; - cpu_dmem_re : in STD_LOGIC; - cpu_dmem_we : in unsigned(3 downto 0); - cpu_dmem_dout : in word_t; - cpu_dmem_din : out word_t; - cpu_dmem_addr : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_dout : out word_t; - mem_re : out STD_LOGIC; - mem_we : out unsigned(3 downto 0); - mem_ce : out STD_LOGIC - ); - -end bui; - -architecture behavior of bui is - -COMPONENT icache - GENERIC - ( - cache_size : natural := 2048; -- words - line_size : natural := 8 -- words - ); - PORT - ( - clk : in STD_LOGIC; - rst : in STD_LOGIC; - en : in STD_LOGIC; - cpu_en : in STD_LOGIC; - cpu_addr : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC; - mem_en : out STD_LOGIC; - mem_req : out STD_LOGIC; - mem_gnt : in STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC - ); -END COMPONENT; - -COMPONENT dcache - GENERIC - ( - cache_size : natural := 2048; -- words - line_size : natural := 8 -- words - ); - PORT - ( - clk : in STD_LOGIC; - rst : in STD_LOGIC; - en : in STD_LOGIC; - cpu_en : in STD_LOGIC; - cpu_r_wn : in STD_LOGIC; - cpu_we : in unsigned(3 downto 0); - cpu_addr : in word_t; - cpu_din : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC; - mem_req : out STD_LOGIC; - mem_gnt : in STD_LOGIC; - mem_en : out STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC - ); -END COMPONENT; - - type bus_state_t is (init, ready, i_cache_bus_access, d_cache_bus_access, d_bus_start, d_bus_access, d_bus_finish); - - signal s, sn : bus_state_t; - signal dmem_re : std_logic; - signal dmem_we : unsigned(3 downto 0); - signal dcache_dout : word_t; - signal dmem_dout : word_t; - signal dmem_din : word_t; - signal dmem_addr : word_t; - signal imem_addr : word_t; - signal imem_mem_out_en : std_logic; - signal dmem_mem_out_en : std_logic; - signal imem_valid : std_logic; - signal dmem_valid : std_logic; - signal dmem_ack : std_logic; - signal dcache_req : std_logic; - signal dcache_busy1 : std_logic; - signal dcache_busy2 : std_logic; - signal icache_busy : std_logic; - signal bus_req : std_logic; - signal bus_bsy : std_logic; - signal icache_mem_en : std_logic; - signal icache_mem_req : std_logic; - signal icache_mem_gnt : std_logic; - signal icache_mem_addr : word_t; - signal dcache_mem_en : std_logic; - signal dcache_mem_req : std_logic; - signal dcache_mem_gnt : std_logic; - signal dcache_mem_addr : word_t; - signal contention : std_logic; - signal dcached : std_logic; - signal duncached_access : std_logic; - -begin - - mem_ce <= mem_rdy and bus_req; - contention <= dcache_req and icache_mem_req; - - cpu_imem_rdy <= not icache_busy after 4.5 ns; --- cpu_imem_din <= imem_din; --- cpu_wait <= busy after 5.5 ns; - cpu_wait <= '0'; - cpu_dmem_rdy <= not (dcache_busy1 or dcache_busy2) after 4.5 ns; - -inst_icache : icache - GENERIC MAP - ( - cache_size => 2048, -- words - line_size => 8 - ) - PORT MAP - ( - clk => clk, - rst => rst, - en => '1', - cpu_en => cpu_imem_en, - cpu_addr => cpu_imem_addr, - cpu_dout => cpu_imem_din, - cpu_busy => icache_busy, - mem_en => icache_mem_en, - mem_req => icache_mem_req, - mem_gnt => icache_mem_gnt, - mem_addr => icache_mem_addr, - mem_din => mem_din, - mem_valid => imem_valid, - mem_rdy => mem_rdy - ); - -inst_dcache : dcache - GENERIC MAP - ( - cache_size => 2048, -- words - line_size => 8 - ) - PORT MAP - ( - clk => clk, - rst => rst, - en => dcached, - cpu_en => cpu_dmem_en, - cpu_r_wn => cpu_dmem_re, - cpu_we => cpu_dmem_we, - cpu_addr => cpu_dmem_addr, - cpu_din => cpu_dmem_dout, - cpu_dout => dcache_dout, - cpu_busy => dcache_busy2, - mem_req => dcache_mem_req, - mem_gnt => dcache_mem_gnt, - mem_en => dcache_mem_en, - mem_addr => dcache_mem_addr, - mem_din => mem_din, - mem_valid => dmem_valid, - mem_rdy => mem_rdy - ); - - dcached <= '1' when cpu_dmem_addr(31 downto 28) /= X"A" else '0'; - cpu_dmem_din <= dmem_din when duncached_access = '1' else dcache_dout; -- when dmem_valid = '1' else ram_dout after 0.5 ns; - -dcache_flags: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - dcache_busy1 <= '0'; - dcache_req <= '0'; - else - duncached_access <= '0'; - if dmem_ack = '1' then - duncached_access <= '1'; - dcache_req <= '0'; - if dmem_re = '1' then - if dmem_valid = '1' then - dcache_busy1 <= '0'; - end if; - else - dcache_busy1 <= '0'; - end if; - end if; - if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then - dcache_req <= '1'; - dcache_busy1 <= '1'; - if dcached = '1' and cpu_dmem_re = '1' then - dcache_req <= '0'; - dcache_busy1 <= '0'; - end if; - end if; - end if; - end if; - end process; - -dcache_regs: - process(clk) - begin - if rising_edge(clk) then - if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then - dmem_dout <= cpu_dmem_dout; - dmem_addr <= cpu_dmem_addr; - dmem_re <= cpu_dmem_re; - dmem_we <= cpu_dmem_we; - end if; - end if; - end process; - -dcache_data: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - dmem_din <= (others => '0'); - elsif dmem_valid = '1' then - dmem_din <= mem_din; - end if; - end if; - end process; - -bus_state_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - s <= init; - elsif ce = '1' then - s <= sn; - end if; - end if; - end process; - -bus_state: - process(s, icache_mem_en, icache_mem_req, dcache_mem_req, dcache_mem_en, dcache_req, dmem_re, mem_rdy, mem_valid) - begin - - imem_mem_out_en <= '0'; - dmem_mem_out_en <= '0'; - icache_mem_gnt <= '0'; - dcache_mem_gnt <= '0'; - imem_valid <= '0'; - dmem_valid <= '0'; - dmem_ack <= '0'; - bus_bsy <= '1'; - - sn <= s; - case s is - when init => - if mem_rdy = '1' then - sn <= ready; - end if; - when ready => - bus_bsy <= not mem_rdy; - if dcache_req = '1' then - if dcache_busy1 = '1' then - if mem_rdy = '1' then - dmem_mem_out_en <= '1'; - if dmem_re = '0' then - dmem_ack <= '1'; - else - sn <= d_bus_access; - end if; - end if; - end if; - elsif icache_mem_req = '1' then - sn <= i_cache_bus_access; - elsif dcache_mem_req = '1' then - sn <= d_cache_bus_access; - end if; - when i_cache_bus_access => - icache_mem_gnt <= '1'; - if icache_mem_en = '1' then - imem_mem_out_en <= '1'; - elsif icache_mem_req = '0' then - sn <= ready; - end if; - imem_valid <= mem_valid; - when d_cache_bus_access => - dcache_mem_gnt <= '1'; - if dcache_mem_en = '1' then - dmem_mem_out_en <= '1'; - elsif dcache_mem_req = '0' then - sn <= ready; - end if; - dmem_valid <= mem_valid; - when d_bus_access => - if mem_valid = '1' then - dmem_ack <= '1'; - dmem_valid <= '1'; - sn <= ready; - end if; - when d_bus_finish => - if mem_rdy = '1' then - sn <= ready; - end if; - when others => - sn <= ready; - end case; - - end process; - -bus_request: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - bus_req <= '0'; - elsif dmem_mem_out_en = '1' or imem_mem_out_en = '1' then - bus_req <= '1'; - elsif mem_rdy = '1' then - bus_req <= '0'; - end if; - end if; - end process; - -bus_out: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - mem_dout <= (others => '0'); - mem_addr <= (others => '0'); - mem_re <= '0'; - mem_we <= (others => '0'); - elsif dmem_mem_out_en = '1' then - if dcache_mem_gnt = '1' then - mem_addr <= dcache_mem_addr; - mem_re <= '1'; - mem_we <= (others => '0'); - else - mem_dout <= dmem_dout; - mem_addr <= dmem_addr; - mem_re <= dmem_re; - mem_we <= dmem_we; - end if; - elsif imem_mem_out_en = '1' then - mem_addr <= icache_mem_addr; - mem_re <= '1'; - mem_we <= (others => '0'); - end if; - end if; - end process; - -------------------------------------------------------------------- - -end behavior; diff --git a/lib/CPUs/MIPS/src/core/mips_cop.vhd b/lib/CPUs/MIPS/src/core/mips_cop.vhd deleted file mode 100644 index d37de20..0000000 --- a/lib/CPUs/MIPS/src/core/mips_cop.vhd +++ /dev/null @@ -1,415 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; -use work.mips_instr.all; - -entity cop is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - sdu : in sdu_t; - IR_valid : in STD_LOGIC; - IR : in word_t; - events : in event_t; - ctrl_in : in cop_ctrl_in_t; - ctrl_out : out cop_ctrl_out_t; - din : in word_t; - dout : out word_t - ); -end cop; - -architecture Behavioral of cop is - - signal epc : word_t; - signal cause : word_t; - signal status : word_t; - signal BadVAddr : word_t; - signal exc_code : unsigned(4 downto 0); - signal test_reg : word_t; - signal test_reg_we : STD_LOGIC; - signal stat_reg_we : STD_LOGIC; - signal eflags_reg_we : STD_LOGIC; - signal epc_reg_we : STD_LOGIC; - signal code_reg_we : STD_LOGIC; - signal ip_reg_we : STD_LOGIC; - signal bd : STD_LOGIC; - signal ip : unsigned(7 downto 0); - signal im : unsigned(7 downto 0); - signal status_save : STD_LOGIC; - signal status_rest : STD_LOGIC; - signal exception : STD_LOGIC; - signal exception_end : STD_LOGIC; - signal eflags : exc_flags_t; - signal exc_enable : STD_LOGIC; - signal cop_EX_en : STD_LOGIC; - - type cop_pipe_t is record - din : word_t; - rs : reg_ptr_t; - rd : reg_ptr_t; - func : func_t; - we : std_logic; - re : std_logic; - cs : std_logic; - end record; - - signal cop_pipe_ID : cop_pipe_t; - signal cop_pipe_EX : cop_pipe_t; - - function eval_int(ip, im : unsigned) return STD_LOGIC is - variable result : STD_LOGIC; - begin - result := '0'; - for i in ip'range loop - result := result or (ip(i) and im(i)); - end loop; - - return result; - end eval_int; - - type exc_state_t is (exc_init, exc_idle, exc_commit_ID, exc_commit_EX, exc_commit_MEM); - signal exc_state, exc_staten : exc_state_t; - --------------------------------------------------------------------------- -begin - - cop_pipe_ID.din <= din; - cop_pipe_ID.cs <= IR_valid; - cop_pipe_ID.rs <= extract_rs(IR); - cop_pipe_ID.rd <= extract_rd(IR); - cop_pipe_ID.func <= extract_func(IR); - cop_pipe_ID.re <= cop_pipe_ID.cs when cop_pipe_ID.rs = "00000" else '0'; - cop_pipe_ID.we <= cop_pipe_ID.cs when cop_pipe_ID.rs = "00100" else '0'; - cop_EX_en <= exc_enable and not status_save; - - ctrl_out.ee <= exc_enable; - ctrl_out.ec <= status_save; - ctrl_out.RE <= status(25); - ctrl_out.user_mode <= status(1); - ctrl_out.int <= eflags.Int; - - ctrl_out.cop_read <= cop_pipe_EX.cs and cop_pipe_EX.re after 1 ns; - ctrl_out.reg_write <= cop_pipe_ID.re after 1 ns; - - im <= status(15 downto 8); - cause <= bd & (30 downto 16 => '0') & ip & '0' & exc_code & "00"; - - eflags.Ov <= events.alu_ovf or events.alu_uvf; - eflags.DAdEL <= events.data_load_err; - eflags.DAdES <= events.data_store_err; - eflags.IAdEL <= events.inst_load_err; - eflags.IAdEK <= events.inst_priv_addr and status(1); - eflags.Sys <= events.syscall; - eflags.Bp <= events.break; - eflags.RI <= events.illegal; - eflags.Int <= eval_int(ip, im) and status(0); - - exception <= eflags.Ov or eflags.Sys or eflags.Bp or eflags.RI or eflags.IAdEL or eflags.IAdEK or eflags.DAdEL or eflags.DAdES or eflags.Int after 1 ns; - -exception_state: - process(exc_state, ctrl_in, exception, sdu) - begin - - exc_enable <= '0'; - ctrl_out.exc_commit <= '0'; - ctrl_out.exc_pending <= '0'; - epc_reg_we <= '0'; - code_reg_we <= '0'; - status_save <= '0'; - eflags_reg_we <= '0'; - - exc_staten <= exc_state; - - case exc_state is - - when exc_init => - exc_staten <= exc_idle; - - when exc_idle => - exc_enable <= '1'; - if exception = '1' then - status_save <= '1'; - eflags_reg_we <= '1'; - code_reg_we <= '1'; - exc_staten <= exc_commit_ID; - end if; - - when exc_commit_ID => - ctrl_out.exc_pending <= '1'; - ctrl_out.exc_commit <= '1'; - if sdu.ID_stall = '0' then - exc_staten <= exc_commit_EX; - end if; - - when exc_commit_EX => - ctrl_out.exc_pending <= '1'; - ctrl_out.exc_commit <= '1'; - if sdu.EX_stall = '0' then - exc_staten <= exc_commit_MEM; - end if; - - when exc_commit_MEM => - ctrl_out.exc_pending <= '1'; - if sdu.MEM_stall = '0' then - epc_reg_we <= '1'; - exc_staten <= exc_idle; - end if; - - when others => - exc_staten <= exc_idle; - - end case; - end process; - -exception_state_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - exc_state <= exc_init; - else - exc_state <= exc_staten; - end if; - end if; - end process; - -cop_exception_epc_write: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - bd <= '0'; - epc <= (others => '0'); - elsif epc_reg_we = '1' then - bd <= '0'; - epc <= ctrl_in.epc_mem; - if ctrl_in.bd_wb = '1' then - bd <= '1'; - epc <= ctrl_in.epc_wb; - end if; - end if; - end if; - end process; - -cop_exception_map: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - exc_code <= (others => '0'); - BadVAddr <= (others => '0'); - elsif code_reg_we = '1' then - if eflags.Ov = '1' then - exc_code <= "01100"; - elsif eflags.Sys = '1' then - exc_code <= "01000"; - elsif eflags.Bp = '1' then - exc_code <= "01001"; - elsif eflags.RI = '1' then - exc_code <= "01010"; - elsif eflags.IAdEL = '1' then - exc_code <= "00100"; - BadVAddr <= ctrl_in.imem_addr; - elsif eflags.IAdEK = '1' then - exc_code <= "00100"; - BadVAddr <= ctrl_in.imem_addr; - elsif eflags.DAdEL = '1' then - exc_code <= "00100"; - BadVAddr <= ctrl_in.dmem_addr; - elsif eflags.DAdES = '1' then - exc_code <= "00101"; - BadVAddr <= ctrl_in.dmem_addr; - elsif eflags.Int = '1' then - exc_code <= "00000"; - end if; - end if; - end if; - end process; - - status_rest <= exception_end and ctrl_in.exc_left; - -cop_status_restore: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - exception_end <= '0'; - ctrl_out.exc_exit <= '0'; - else - if cop_pipe_ID.func = "10000" and exception_end = '0' then -- RFE - exception_end <= cop_pipe_ID.cs; - ctrl_out.exc_exit <= cop_pipe_ID.cs; - elsif exception_end = '1' and ctrl_in.exc_left = '1' then - exception_end <= '0'; - ctrl_out.exc_exit <= '0'; - end if; - end if; - end if; - end process; - -cop_ip_reg_write: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - ip(1 downto 0) <= (others => '0'); - elsif ip_reg_we = '1' then - ip(1 downto 0) <= cop_pipe_EX.din(9 downto 8); - end if; - ip(7 downto 2) <= events.Int; - end if; - end process; - -cop_exc_vector: - process(clk) - begin - if rising_edge(clk) then - ctrl_out.exc_vec <= X"80000180"; - if status(22) = '1' then - ctrl_out.exc_vec <= X"BFC00180"; - end if; - end if; - end process; - -cop_pipe: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - cop_pipe_EX.cs <= '0'; - cop_pipe_EX.we <= '0'; - cop_pipe_EX.re <= '0'; - else - if sdu.EX_stall = '0' then - cop_pipe_EX <= cop_pipe_ID; - end if; - end if; - end if; - end process; - -cop_register_read: - process(clk) - variable reg : word_t; - begin - if rising_edge(clk) and cop_pipe_ID.re = '1' and sdu.ID_stall = '0' then - case cop_pipe_ID.rd is - when "01000" => -- BadVAddr - reg := BadVAddr; - - when "01100" => -- Status - reg := status; - - when "01101" => -- Cause - reg := cause; - - when "01110" => -- EPC (Exception Program Counter) - reg := epc; - - when "01111" => -- PRId (Processor Revision Register) - reg := X"000002" & to_unsigned(REVISION ,8); - - when "11111" => -- test_reg - reg := test_reg; - - when others => - reg := X"DEADBEEF"; - - end case; - dout <= reg; - end if; - end process; - -cop_we_gen: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - test_reg_we <= '0'; - stat_reg_we <= '0'; - ip_reg_we <= '0'; - else - test_reg_we <= '0'; - stat_reg_we <= '0'; - ip_reg_we <= '0'; - if (cop_EX_en and cop_pipe_EX.we) = '1' then - - case cop_pipe_EX.rd is - - when "01100" => - stat_reg_we <= not status(1) or status(28); - when "01101" => - ip_reg_we <= not status(1) or status(28); - when "11111" => - test_reg_we <= not status(1) or status(28); - when others => null; - - end case; - - end if; - end if; - end if; - end process; - -cop_test_reg_write: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - test_reg <= (others => '0'); - else --if ce = '1' then - if test_reg_we = '1' then - test_reg <= cop_pipe_EX.din; - end if; - end if; - end if; - end process; - -cop_status_reg_write: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - status <= X"00400000"; - else - if status_save = '1' then - status(5 downto 4) <= status(3 downto 2); - status(3 downto 2) <= status(1 downto 0); - status(1 downto 0) <= "00"; - elsif status_rest = '1' then - status(1 downto 0) <= status(3 downto 2); - status(3 downto 2) <= status(5 downto 4); - elsif stat_reg_we = '1' then - status <= cop_pipe_EX.din; - end if; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd b/lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd deleted file mode 100644 index 720e65c..0000000 --- a/lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd +++ /dev/null @@ -1,101 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The datapath controller --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; - -entity idecode_rom is - Port - ( - nop : in std_logic; - inst_in : in word_t; - ctrl_out : out ctrl_lines_t - ); -end idecode_rom; - -architecture Behavioral of idecode_rom is - - signal ctrl_special : ctrl_lines_t; - signal ctrl_regimm : ctrl_lines_t; - signal ctrl_opcode : ctrl_lines_t; - - signal rom_special : rom_special_t := gen_rom_special; - signal rom_regimm : rom_regimm_t := gen_rom_regimm; - signal rom_opcode : rom_opcode_t := gen_rom_opcode; - - attribute rom_style : string; - - attribute rom_style of rom_special: signal is "distributed"; - attribute rom_style of rom_regimm: signal is "distributed"; - attribute rom_style of rom_opcode: signal is "distributed"; - -begin - -i_dec_special: - process(inst_in, rom_special) - variable func : func_t; - begin - func := extract_func(inst_in); - ctrl_special <= rom_special(to_integer(func)); - end process; - -i_dec_regimm: - process(inst_in, rom_regimm) - variable rt : reg_ptr_t; - begin - rt := extract_rt(inst_in); - ctrl_regimm <= rom_regimm(to_integer(rt)); - end process; - -i_dec_opcode: - process(inst_in, rom_opcode) - variable opc : opcode_t; - begin - opc := extract_opc(inst_in); - ctrl_opcode <= rom_opcode(to_integer(opc)); - end process; - -proc_decode: - process(inst_in, ctrl_special, ctrl_regimm, ctrl_opcode, nop) - variable opclass : opcode_t; - begin - opclass := extract_opc(inst_in); - ctrl_out <= ctrl_lines_default after 2 ns; - if nop = '0' then - case opclass is - when "000000" => - ctrl_out <= ctrl_special after 2 ns; - when "000001" => - ctrl_out <= ctrl_regimm after 2 ns; - when others => - ctrl_out <= ctrl_opcode after 2 ns; - end case; - end if; - end process; - -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_instr.vhd b/lib/CPUs/MIPS/src/core/mips_instr.vhd deleted file mode 100644 index 97a0c0b..0000000 --- a/lib/CPUs/MIPS/src/core/mips_instr.vhd +++ /dev/null @@ -1,997 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Types, constants and functions for JCPU --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - --------------------------------------------------------------------------- -package mips_instr is - - function extract_opc(instr : word_t) return opcode_t; - function extract_rs(instr : word_t) return reg_ptr_t; - function extract_rt(instr : word_t) return reg_ptr_t; - function extract_rd(instr : word_t) return reg_ptr_t; - function extract_shamt(instr : word_t) return shamt_t; - function extract_func(instr : word_t) return func_t; - function extract_simm32(instr : word_t) return word_t; - function extract_uimm16(instr : word_t) return word_t; - function extract_jimm32(instr, pc : word_t) return word_t; - function extract_bimm18(instr, pc : word_t) return word_t; - function decode_op(instr : word_t) return op_t; - function ctrl_lines_default return ctrl_lines_t; - function special_ctrl_lines(func : func_t) return ctrl_lines_t; - function regimm_ctrl_lines(rt : reg_ptr_t) return ctrl_lines_t; - function opcode_ctrl_lines(opc : opcode_t) return ctrl_lines_t; - function gen_rom_opcode return rom_opcode_t; - function gen_rom_regimm return rom_regimm_t; - function gen_rom_special return rom_special_t; - -end mips_instr; - --------------------------------------------------------------------------- -library work; -use work.mips_types.all; - -package body mips_instr is - - function extract_opc(instr : word_t) return opcode_t is - variable result : opcode_t; - begin - result := instr(31 downto 26); - - return result; - - end extract_opc; - - function extract_rs(instr : word_t) return reg_ptr_t is - variable result : reg_ptr_t; - begin - result := instr(25 downto 21); - - return result; - - end extract_rs; - - function extract_rt(instr : word_t) return reg_ptr_t is - variable result : reg_ptr_t; - begin - result := instr(20 downto 16); - - return result; - - end extract_rt; - - function extract_rd(instr : word_t) return reg_ptr_t is - variable result : reg_ptr_t; - begin - result := instr(15 downto 11); - - return result; - - end extract_rd; - - function extract_shamt(instr : word_t) return shamt_t is - variable result : shamt_t; - begin - result := instr(10 downto 6); - - return result; - - end extract_shamt; - - function extract_func(instr : word_t) return func_t is - variable result : func_t; - begin - result := instr(5 downto 0); - - return result; - - end extract_func; - - function extract_simm32(instr : word_t) return word_t is - variable result : word_t; - begin - result := (31 downto 16 => instr(15)) & instr(15 downto 0); - - return result; - - end extract_simm32; - - function extract_uimm16(instr : word_t) return word_t is - variable result : word_t; - begin - result := (31 downto 16 => '0') & instr(15 downto 0); - - return result; - - end extract_uimm16; - - function extract_jimm32(instr, pc : word_t) return word_t is - variable result : word_t; - begin - result := pc(31 downto 28) & instr(25 downto 0) & "00"; - - return result; - - end extract_jimm32; - - function extract_bimm18(instr, pc : word_t) return word_t is - variable result : word_t; - begin - result := (31 downto 18 => instr(15)) & instr(15 downto 0) & "00"; - - return result; - - end extract_bimm18; - - function decode_op(instr : word_t) return op_t is - variable result : op_t; - variable opc : natural range 0 to 63; - variable func : natural range 0 to 63; - variable rt : natural range 0 to 31; - - begin - - opc := to_integer(extract_opc(instr)); - func := to_integer(extract_func(instr)); - rt := to_integer(extract_rt(instr)); - - result := op_sll; - - case opc is - - when 0 => - case func is - - when 0 => - result := op_sll; - - when 2 => - result := op_srl; - - when 3 => - result := op_sra; - - when 4 => - result := op_sllv; - - when 6 => - result := op_srlv; - - when 7 => - result := op_srav; - - when 8 => - result := op_jr; - - when 9 => - result := op_jalr; - - when 12 => - result := op_syscall; - - when 13 => - result := op_break; - - when 16 => - result := op_mfhi; - - when 17 => - result := op_mthi; - - when 18 => - result := op_mflo; - - when 19 => - result := op_mtlo; - - when 24 => - result := op_mult; - - when 25 => - result := op_multu; - - when 26 => - result := op_div; - - when 27 => - result := op_divu; - - when 32 => - result := op_add; - - when 33 => - result := op_addu; - - when 34 => - result := op_sub; - - when 35 => - result := op_subu; - - when 36 => - result := op_and; - - when 37 => - result := op_or; - - when 38 => - result := op_xor; - - when 39 => - result := op_nor; - - when 42 => - result := op_slt; - - when 43 => - result := op_sltu; - - when others => null; -- undef - - end case; - - when 1 => - case rt is - - when 0 => - result := op_bltz; - - when 1 => - result := op_bgez; - - when 16 => - result := op_bltzal; - - when 17 => - result := op_bgezal; - - when others => null; -- undef - - end case; - - when 2 => - result := op_j; - - when 3 => - result := op_jal; - - when 4 => - result := op_beq; - - when 5 => - result := op_bne; - - when 6 => - result := op_blez; - - when 7 => - result := op_bgtz; - - when 8 => - result := op_addi; - - when 9 => - result := op_addiu; - - when 10 => - result := op_slti; - - when 11 => - result := op_sltiu; - - when 12 => - result := op_andi; - - when 13 => - result := op_ori; - - when 14 => - result := op_xori; - - when 15 => - result := op_lui; - - when 16 => - result := op_cop0; - - when 17 => - result := op_cop1; - - when 18 => - result := op_cop2; - - when 19 => - result := op_cop3; - - when 32 => - result := op_lb; - - when 33 => - result := op_lh; - - when 34 => - result := op_lwl; - - when 35 => - result := op_lw; - - when 36 => - result := op_lbu; - - when 37 => - result := op_lhu; - - when 38 => - result := op_lwr; - - when 40 => - result := op_sb; - - when 41 => - result := op_sh; - - when 42 => - result := op_swl; - - when 43 => - result := op_sw; - - when 46 => - result := op_swr; - - when 49 => - result := op_lwc1; - - when 50 => - result := op_lwc2; - - when 51 => - result := op_lwc3; - - when 57 => - result := op_swc1; - - when 58 => - result := op_swc2; - - when 59 => - result := op_swc3; - - when others => null; -- undef - - end case; - - return result; - - end decode_op; - - function ctrl_lines_default return ctrl_lines_t is - variable result : ctrl_lines_t; - begin - result.cop_instr_en := '0'; - result.jump := '0'; - result.jump_long := '0'; - result.branch := '0'; - result.bc_src := bc_eq_ne; - result.bc_not := '0'; - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.shift_right := '0'; - result.alu.shift_arith := '0'; - result.shamt2_srcsel := sa_src_imm; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.imm_src := src_imm16; - result.reg_write := '0'; - result.dmem_we := '0'; - result.dmem_en := '0'; - result.wptr_srcsel := wptr_src_imm; - result.reg_link := '0'; - result.shift_offset := "00"; - result.shift_byp := '1'; - result.byte_en_byp := '1'; - result.sign_ext_byp := '1'; - result.word4_en := '0'; - result.word2_en := '0'; - result.align_left := '0'; - result.load_signed := '0'; - result.mul_access := '0'; - result.mul_hilo_we := '0'; - result.mul_start := '0'; - result.mul_s_un := '0'; - result.mul_mul_divn := '0'; - result.mul_hilo_sel := '1'; - result.exc_break := '0'; - result.exc_syscall := '0'; - result.exc_illegal := '0'; - result.except_en := '0'; - result.alu_exc_en := '0'; - - return result; - - end ctrl_lines_default; - - - function special_ctrl_lines(func : func_t) return ctrl_lines_t is - variable result : ctrl_lines_t; - variable op : integer range 0 to 2**func_t'length-1; - begin - - result := ctrl_lines_default; - - op := to_integer(func); - case op is - --- when op_add => - when 32 => - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - result.alu_exc_en := '1'; - --- when op_addu => - when 33 => - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - --- when op_and => - when 36 => - result.alu.outsel := alu_and; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - --- when op_break => - when 13 => - result.exc_break := '1'; - result.except_en := '1'; - --- when op_div => - when 26 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '1'; - result.mul_mul_divn := '0'; - --- when op_divu => - when 27 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '0'; - result.mul_mul_divn := '0'; - --- when op_jalr => - when 9 => - result.jump_long := '1'; - result.wptr_srcsel := wptr_src_imm; - result.reg_write := '1'; - result.reg_link := '1'; - --- when op_jr => - when 8 => - result.jump_long := '1'; - --- when op_mfhi => - when 16 => - result.reg_write := '1'; - result.mul_access := '1'; - result.mul_hilo_sel := '1'; - --- when op_mflo => - when 18 => - result.reg_write := '1'; - result.mul_access := '1'; - result.mul_hilo_sel := '0'; - --- when op_mthi => - when 17 => - result.mul_hilo_we := '1'; - result.mul_hilo_sel := '1'; - --- when op_mtlo => - when 19 => - result.mul_hilo_we := '1'; - result.mul_hilo_sel := '0'; - --- when op_mult => - when 24 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '1'; - result.mul_mul_divn := '1'; - --- when op_multu => - when 25 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '0'; - result.mul_mul_divn := '1'; - --- when op_or => - when 37 => - result.alu.outsel := alu_or; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - --- when op_nor => - when 39 => - result.alu.outsel := alu_nor; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - --- when op_sll => - when 0 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '0'; - result.shamt2_srcsel := sa_src_imm; - result.reg_write := '1'; - --- when op_sllv => - when 4 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '0'; - result.shamt2_srcsel := sa_src_reg; - result.reg_write := '1'; - --- when op_slt => - when 42 => - result.alu.outsel := alu_lts; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - --- when op_sltu => - when 43 => - result.alu.outsel := alu_ltu; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - --- when op_sra => - when 3 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '1'; - result.shamt2_srcsel := sa_src_imm; - result.reg_write := '1'; - --- when op_srav => - when 7 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '1'; - result.shamt2_srcsel := sa_src_reg; - result.reg_write := '1'; - --- when op_srl => - when 2 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '0'; - result.shamt2_srcsel := sa_src_imm; - result.reg_write := '1'; - --- when op_srlv => - when 6 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '0'; - result.shamt2_srcsel := sa_src_reg; - result.reg_write := '1'; - --- when op_sub => - when 34 => - result.alu.outsel := alu_adder; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - result.alu_exc_en := '1'; - --- when op_subu => - when 35 => - result.alu.outsel := alu_adder; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - --- when op_syscall => - when 12 => - result.exc_syscall := '1'; - result.except_en := '1'; - --- when op_xor => - when 38 => - result.alu.outsel := alu_xor; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - when others => - result.exc_illegal := '1'; - - end case; - - return result; - - end special_ctrl_lines; - - function gen_rom_special return rom_special_t is - variable result : rom_special_t; - variable func : func_t; - begin - - for i in 0 to 2**func_t'length-1 loop - func := to_unsigned(i, func_t'length); - result(i) := special_ctrl_lines(func); - end loop; - - return result; - end gen_rom_special; - - function regimm_ctrl_lines(rt : reg_ptr_t) return ctrl_lines_t is - variable result : ctrl_lines_t; - variable op : integer range 0 to 2**reg_ptr_t'length-1; - begin - - result := ctrl_lines_default; - - op := to_integer(rt); - case op is - --- when op_bgez => - when 1 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '1'; - --- when op_bgezal => - when 17 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '1'; - result.wptr_srcsel := wptr_src_const; - result.reg_write := '1'; - result.reg_link := '1'; - --- when op_bltz => - when 0 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '0'; - --- when op_bltzal => - when 16 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '0'; - result.wptr_srcsel := wptr_src_const; - result.reg_write := '1'; - result.reg_link := '1'; - - when others => - result.exc_illegal := '1'; - - end case; - - return result; - - end regimm_ctrl_lines; - - function gen_rom_regimm return rom_regimm_t is - variable result : rom_regimm_t; - variable rt : reg_ptr_t; - begin - - for i in 0 to 2**reg_ptr_t'length-1 loop - rt := to_unsigned(i, reg_ptr_t'length); - result(i) := regimm_ctrl_lines(rt); - end loop; - - return result; - end gen_rom_regimm; - - function opcode_ctrl_lines(opc : opcode_t) return ctrl_lines_t is - variable result : ctrl_lines_t; - variable op : integer range 0 to 2**opcode_t'length-1; - begin - - result := ctrl_lines_default; - - op := to_integer(opc); - case op is - --- when op_addi => - when 8 => - result.imm_src := src_imm32; - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - result.alu_exc_en := '1'; - --- when op_addiu => - when 9 => - result.imm_src := src_imm32; - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - --- when op_andi => - when 12 => - result.imm_src := src_imm16; - result.alu.outsel := alu_and; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - --- when op_beq => - when 4 => - result.branch := '1'; - result.bc_src := bc_eq_ne; - result.bc_not := '0'; - --- when op_bgtz => - when 7 => - result.branch := '1'; - result.bc_src := bc_lez_gtz; - result.bc_not := '1'; - --- when op_blez => - when 6 => - result.branch := '1'; - result.bc_src := bc_lez_gtz; - result.bc_not := '0'; - --- when op_bne => - when 5 => - result.branch := '1'; - result.bc_src := bc_eq_ne; - result.bc_not := '1'; - --- when op_cop => - when 16 | 17 | 18 | 19 => - result.cop_instr_en := '1'; - --- when op_j => - when 2 => - result.jump := '1'; - --- when op_jal => - when 3 => - result.jump := '1'; - result.wptr_srcsel := wptr_src_const; - result.reg_write := '1'; - result.reg_link := '1'; - --- when op_lb => - when 32 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '1'; - result.sign_ext_byp := '0'; - result.load_signed := '1'; - result.word4_en := '1'; - --- when op_lbu => - when 36 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '1'; - result.sign_ext_byp := '0'; - result.load_signed := '0'; - result.word4_en := '1'; - --- when op_lh => - when 33 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.sign_ext_byp := '0'; - result.byte_en_byp := '1'; - result.load_signed := '1'; - result.word2_en := '1'; - result.except_en := '1'; - --- when op_lhu => - when 37 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.sign_ext_byp := '0'; - result.byte_en_byp := '1'; - result.load_signed := '0'; - result.word2_en := '1'; - result.except_en := '1'; - --- when op_lui => - when 15 => - result.imm_src := src_imm16_high; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.alu.outsel := alu_adder; - result.reg_write := '1'; - result.alu.add := '1'; - --- when op_lw => - when 35 => --- result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.except_en := '1'; - --- when op_lwl => - when 34 => --- result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.shift_offset := "01"; - result.align_left := '1'; - --- when op_lwr => - when 38 => --- result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.shift_offset := "00"; - result.align_left := '0'; - --- when op_ori => - when 13 => - result.imm_src := src_imm16; - result.alu.outsel := alu_or; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - --- when op_sb => - when 40 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.word4_en := '1'; - --- when op_sh => - when 41 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.word2_en := '1'; - result.except_en := '1'; - --- when op_slti => - when 10 => - result.alu.outsel := alu_lts; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.imm_src := src_imm32; - result.reg_write := '1'; - --- when op_sltiu => - when 11 => - result.alu.outsel := alu_ltu; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.imm_src := src_imm32; - result.reg_write := '1'; - --- when op_sw => - when 43 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.except_en := '1'; - --- when op_swl => - when 42 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.shift_offset := "01"; - --- when op_swr => - when 46 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.align_left := '1'; - --- when op_xori => - when 14 => - result.imm_src := src_imm16; - result.alu.outsel := alu_xor; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - - when others => - result.exc_illegal := '1'; - - end case; - - return result; - - end opcode_ctrl_lines; - - function gen_rom_opcode return rom_opcode_t is - variable result : rom_opcode_t; - variable opc : opcode_t; - begin - - for i in 0 to 2**opcode_t'length-1 loop - opc := to_unsigned(i, opcode_t'length); - result(i) := opcode_ctrl_lines(opc); - end loop; - - return result; - end gen_rom_opcode; - -end mips_instr; - --------------------------------------------------------------------------- --------------------------------------------------------------------------- - diff --git a/lib/CPUs/MIPS/src/core/mips_muldiv.vhd b/lib/CPUs/MIPS/src/core/mips_muldiv.vhd deleted file mode 100644 index efce36b..0000000 --- a/lib/CPUs/MIPS/src/core/mips_muldiv.vhd +++ /dev/null @@ -1,454 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity muldiv is - Port - ( - rst : in std_logic; - clk : in std_logic; - hilo_we : in std_logic; - din_hi : in word_t; - din_lo : in word_t; - mul_divn : in std_logic; - start : in std_logic; - s_un : in std_logic; - hilo_sel : in std_logic; - busy : out std_logic; - dout : out word_t - ); -end muldiv; - -architecture Behavioral of muldiv is - - subtype pprod_t is unsigned (39 downto 0); - subtype prod_t is unsigned (63 downto 0); - subtype byte_t is unsigned (7 downto 0); - - type pprod_array_t is array (natural range <>) of pprod_t; - type word_array_t is array (natural range <>) of word_t; - type byte_array_t is array (natural range <>) of byte_t; - - signal pprod : pprod_array_t(0 to 3); - signal sign1 : std_logic; - signal sign2 : std_logic; - signal s1_r : std_logic; - signal s2_r : std_logic; - signal sr_r : std_logic; - signal cy : unsigned (3 downto 0); - signal mul_start : std_logic; - signal mul_en : std_logic; - signal sum_en : std_logic; - signal pre_sum_vld : std_logic; - signal pp_reg : unsigned (63 downto 8); - signal pre_const : word_array_t(0 to 1); - signal result : prod_t; - signal add_op1 : unsigned (39 downto 0); - signal add_op2 : unsigned (39 downto 0); - signal add_res : unsigned (39 downto 0); - signal ppadd_op1 : word_array_t(0 to 3); - signal ppadd_op2 : word_array_t(0 to 3); - signal ppadd_res : word_array_t(0 to 3); - signal ppadd_cyi : unsigned (3 downto 0); - signal ppadd_cyo : unsigned (3 downto 0); - - signal pp_op1_r : word_t; - signal pp_op1 : word_t; - signal pp_op2 : word_t; - signal pp_op2_r : byte_array_t(0 to 3); - signal bsy : std_logic; - - signal div_add_res : unsigned (32 downto 0); - signal div_add_op1 : unsigned (32 downto 0); - signal div_add_op2 : unsigned (32 downto 0); - signal div_add_cyi : std_logic; - signal div_qbit : std_logic; - signal div_start : std_logic; - signal div_en : std_logic; - - signal div_A : unsigned (32 downto 0); - signal div_M : unsigned (32 downto 0); - signal div_M_n : unsigned (32 downto 0); - signal div_Q : word_t; - - type md_state_t is (md_rdy, mul_pre1, mul_pre2, mul_pp, mul_sum, div_process, div_post1, div_post2, div_post3); - signal s, sn : md_state_t; - signal cycle_cnt : natural range 0 to 31; - signal cycle_cnt_preset : natural range 0 to 31; - signal cycle_cnt_load : std_logic; - signal div_fin_en : unsigned (2 downto 0); - --------------------------------------------------------------------------- -begin --- 9A0CD0570B88D78 - - busy <= bsy; - - sign1 <= din_hi(din_hi'left) and s_un; - sign2 <= din_lo(din_lo'left) and s_un; - pp_op1 <= not din_hi when sign1 = '1' else din_hi; - pp_op2 <= not din_lo when sign2 = '1' else din_lo; - --------------------------------------------------------------------------- -md_state: - process(s, start, mul_divn, cycle_cnt) - begin - - bsy <= '1'; - cycle_cnt_load <= '0'; - cycle_cnt_preset <= 7; - - mul_en <= '0'; - div_en <= '0'; - sum_en <= '0'; - pre_sum_vld <= '0'; - mul_start <= '0'; - div_start <= '0'; - div_fin_en <= "000"; - sn <= s; - case s is - when md_rdy => - bsy <= '0'; - if start = '1' then - if mul_divn = '1' then - sn <= mul_pre1; - cycle_cnt_load <= '1'; - cycle_cnt_preset <= 7; - mul_start <= '1'; - else - sn <= div_process; - cycle_cnt_load <= '1'; - cycle_cnt_preset <= 31; - div_start <= '1'; - end if; - end if; - when mul_pre1 => - pre_sum_vld <= '1'; - mul_en <= '1'; - sn <= mul_pre2; - when mul_pre2 => - pre_sum_vld <= '1'; - mul_en <= '1'; - sn <= mul_pp; - when mul_pp => - mul_en <= '1'; - if cycle_cnt = 0 then - cycle_cnt_load <= '1'; - cycle_cnt_preset <= 3; - sn <= mul_sum; - end if; - when mul_sum => - sum_en <= '1'; - if cycle_cnt = 0 then - bsy <= '0'; - sn <= md_rdy; - end if; - when div_process => - div_en <= '1'; - if cycle_cnt = 0 then - sn <= div_post1; - end if; - when div_post1 => - div_fin_en <= "001"; - sn <= div_post2; - when div_post2 => - div_fin_en <= "010"; - sn <= div_post3; - when div_post3 => - div_fin_en <= "100"; - sn <= md_rdy; - bsy <= '0'; - when others => - sn <= md_rdy; - end case; - - end process; - -md_state_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - s <= md_rdy; - else - s <= sn; - end if; - end if; - end process; - -md_cycle_cnt: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - cycle_cnt <= 0; - elsif cycle_cnt_load = '1' then - cycle_cnt <= cycle_cnt_preset; - elsif cycle_cnt /= 0 then - cycle_cnt <= cycle_cnt - 1; - end if; - end if; - end process; - -proc_out_reg: - process(hilo_sel, result) - begin - if hilo_sel = '1' then - dout <= result(63 downto 32); - else - dout <= result(31 downto 0); - end if; - end process; - -proc_in_reg: - process(clk) - variable pre_cond : unsigned(1 downto 0); - begin - if rising_edge(clk) then - if mul_start = '1' or div_start = '1' then - pp_op1_r <= pp_op1; - pre_const(0) <= (others => '0'); - pre_const(1) <= (others => '0'); - pre_cond := (din_hi(din_hi'left) and s_un) & (din_lo(din_lo'left) and s_un); - s1_r <= pre_cond(1); - s2_r <= pre_cond(0); - sr_r <= pre_cond(0) xor pre_cond(1); - case pre_cond is - when "01" => - pre_const(0) <= din_hi; - pre_const(1) <= X"FFFF_FFFF"; - when "10" => - pre_const(0) <= X"0000_0000"; - pre_const(1) <= X"FFFF_FFFF"; - when "11" => - pre_const(0) <= not din_hi; - pre_const(1) <= X"0000_0001"; - when others => null; - end case; - elsif pre_sum_vld = '1' then - pre_const(0) <= pre_const(1); - end if; - end if; - end process; - -proc_mul_sr: - process(clk) - begin - if rising_edge(clk) then - if mul_start = '1' then - for i in 0 to 3 loop - cy(i) <= '0'; - pprod(i) <= ppadd_res(i) & X"00"; - end loop; - elsif mul_en = '1' then - for i in 0 to 3 loop - cy(i) <= ppadd_cyo(i); - pprod(i) <= ppadd_res(i) & pprod(i)(8 downto 1); - end loop; - elsif sum_en = '1' then - for i in 1 to 3 loop - pprod(i-1) <= pprod(i); - end loop; - end if; - end if; - end process; - -gen_mul32x8pp: - for i in 0 to 3 generate - begin - - pp_adder_mux: - process(mul_start, pp_op1, pp_op2, pp_op1_r, pp_op2_r(i), s1_r, sign1, pprod(i), cy(i)) - variable v2 : unsigned(7 downto 0); - begin - ppadd_cyi(i) <= '0'; - ppadd_op1(i) <= (others => '0'); - if mul_start = '1' then - ppadd_op2(i) <= (others => '0'); - v2 := pp_op2(8*(i+1)-1 downto 8*i); - if v2(0) = '1' then - ppadd_cyi(i) <= sign1; - ppadd_op1(i) <= pp_op1; - end if; - else - ppadd_op2(i) <= cy(i) & pprod(i)(39 downto 9); - v2 := pp_op2_r(i); - if v2(0) = '1' then - ppadd_cyi(i) <= s1_r; - ppadd_op1(i) <= pp_op1_r; - end if; - end if; - end process; - - pp_adder: - process(ppadd_op1(i), ppadd_op2(i), ppadd_cyi(i)) - variable sum_pp : unsigned(33 downto 0); - begin - sum_pp := ('0' & ppadd_op1(i) & ppadd_cyi(i)) + ('0' & ppadd_op2(i) & ppadd_cyi(i)); - ppadd_res(i) <= sum_pp(sum_pp'left-1 downto 1); - ppadd_cyo(i) <= sum_pp(sum_pp'left); - end process; - - proc_mul_ctrl: - process(clk) - begin - if rising_edge(clk) then - if mul_start = '1' then - pp_op2_r(i) <= '0' & pp_op2(8*(i+1)-1 downto 8*i+1); - elsif mul_en = '1' then - pp_op2_r(i) <= '0' & pp_op2_r(i)(7 downto 1); - end if; - end if; - end process; - - end generate; - -comb_mul_adder: - process(add_op1, add_op2) - variable sum_mul : unsigned(39 downto 0); - begin - sum_mul := (add_op1) + (add_op2); - add_res <= sum_mul(sum_mul'left downto 0); - end process; - -comb_mul_adder_mux: - process(pre_const, pre_sum_vld, pp_reg, pprod, sr_r) - variable s_ext : std_logic; - begin - if pre_sum_vld = '1' then - add_op1 <= pp_reg(63 downto 24); - add_op2 <= pre_const(0) & X"00"; - else - s_ext := pp_reg(63) and sr_r; - add_op1 <= (7 downto 0 => s_ext) & pp_reg(63 downto 32); - add_op2 <= pprod(0); - end if; - end process; - -comb_mul: - process(clk) - variable tmp : prod_t; - begin - if rising_edge(clk) then - if mul_start = '1' then - pp_reg <= (others => '0'); - elsif pre_sum_vld = '1' then - pp_reg <= add_res & X"0000"; - elsif sum_en = '1' then - tmp := add_res & pp_reg(31 downto 8); - pp_reg <= tmp(63 downto 8); - result <= tmp; - if sr_r = '1' then - result <= not tmp; - end if; - elsif div_fin_en(1) = '1' then - result(63 downto 32) <= div_A(31 downto 0); - if s1_r = '1' then - result(63 downto 32) <= div_add_res(31 downto 0); - end if; - elsif div_fin_en(2) = '1' then - result(31 downto 0) <= div_Q; - if sr_r = '1' then - result(31 downto 0) <= div_add_res(31 downto 0); - end if; - elsif hilo_we = '1' then - if hilo_sel = '1' then - result(63 downto 32) <= din_hi; - else - result(31 downto 0) <= din_hi; - end if; - end if; - end if; - end process; - -div_adder: - process(div_add_op1, div_add_op2, div_add_cyi) - variable sum_div : unsigned(33 downto 0); - begin - sum_div := (div_add_op1 & div_add_cyi) + (div_add_op2 & div_add_cyi); - div_add_res <= sum_div(sum_div'left downto 1); - end process; - -div_adder_mux: - process(div_start, div_en, div_fin_en, div_A, div_Q, pp_op1, sign1, s1_r, s2_r, sr_r, div_qbit, div_M, div_M_n) - begin - - div_add_cyi <= s2_r xor div_qbit; - div_add_op1 <= div_A(31 downto 0) & div_Q(31); - div_add_op2 <= (others => '0'); - if div_start = '1' then - div_add_op1 <= '0' & pp_op1; - div_add_cyi <= sign1; - elsif div_en = '1' then - div_add_op2 <= div_M; - if div_qbit = '1' then - div_add_op2 <= div_M_n; - end if; - elsif div_fin_en(0) = '1' then - div_add_op2 <= div_M; - div_add_cyi <= s2_r; - div_add_op1 <= '0' & div_A(31 downto 0); - elsif div_fin_en(1) = '1' then - div_add_cyi <= s1_r; - div_add_op1 <= '0' & not div_A(31 downto 0); - elsif div_fin_en(2) = '1' then - div_add_cyi <= sr_r; - div_add_op1 <= '0' & not div_Q; - end if; - end process; - -divide: - process(clk) - variable quo : std_logic; - begin - if rising_edge(clk) then - if div_start = '1' then - div_qbit <= '1'; - div_Q <= div_add_res(31 downto 0); - div_A <= (others => '0'); - if sign2 = '1' then - div_M_n <= '1' & din_lo; - div_M <= '0' & not din_lo; - else - div_M_n <= '1' & not din_lo; - div_M <= '0' & din_lo; - end if; - elsif div_en = '1' then - div_qbit <= not div_add_res(32); - div_A <= div_add_res(32 downto 0); - div_Q <= div_Q(30 downto 0) & not div_add_res(32); - elsif div_fin_en(0) = '1' then - if div_A(32) = '1' then - div_A <= '0' & div_add_res(31 downto 0); - end if; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd deleted file mode 100644 index fbdc1e8..0000000 --- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd +++ /dev/null @@ -1,914 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The pipeline --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; - -entity pipeline is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - halt : in STD_LOGIC; - int : in unsigned(5 downto 0); - imem_rdy : in STD_LOGIC; - imem_en : out STD_LOGIC; - imem_addr : out word_t; - imem_data : in word_t; - dmem_rdy : in STD_LOGIC; - dmem_en : out STD_LOGIC; - dmem_re : out STD_LOGIC; - dmem_we : out unsigned(3 downto 0); - dmem_addr : out word_t; - dmem_din : in word_t; - dmem_dout : out word_t - ); -end pipeline; - -architecture Behavioral of pipeline is - --------------------------------------------------------------------------- - COMPONENT reg_dual is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clk_w : in STD_LOGIC; - en : in STD_LOGIC; - we : in STD_LOGIC; - wptr : in unsigned (addr_width-1 downto 0); - din : in unsigned (data_width-1 downto 0); - rptr_a : in unsigned (addr_width-1 downto 0); - rptr_b : in unsigned (addr_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT idecode_rom is - Port - ( - nop : in std_logic; - inst_in : in word_t; - ctrl_out : out ctrl_lines_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT shifter is - Generic - ( - data_width : integer - ); - Port - ( - shift_ctrl : in shift_ctrl_t; - din : in unsigned (data_width-1 downto 0); - dout : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT alu is - Generic - ( - data_width : integer - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - op2_shifted : in unsigned (data_width-1 downto 0); - ctrl : in alu_ctrl_t; - result : out unsigned (data_width-1 downto 0); - flags : out alu_flags_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT bcu is - Generic - ( - data_width : integer - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - flags : out bcu_flags_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT cop is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - sdu : in sdu_t; - IR_valid : in STD_LOGIC; - IR : in word_t; - events : in event_t; - ctrl_in : in cop_ctrl_in_t; - ctrl_out : out cop_ctrl_out_t; - din : in word_t; - dout : out word_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT muldiv is - Port - ( - rst : in std_logic; - clk : in std_logic; - hilo_we : in std_logic; - din_hi : in word_t; - din_lo : in word_t; - mul_divn : in std_logic; - start : in std_logic; - s_un : in std_logic; - hilo_sel : in std_logic; - busy : out std_logic; - dout : out word_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - constant RESET_VECTOR : word_t := X"BFC00000"; - - signal ID_stage : ID_t; - signal EX_stage : EX_t; - signal MEM_stage : MEM_t; - signal WB_stage : WB_t; - signal clk_2, clk_1 : STD_LOGIC; - signal hdu : hdu_t; - signal sdu : sdu_t; - signal cpu_rst : STD_LOGIC; - signal reg_a : word_t; - signal reg_b : word_t; - signal ctrl_lines : ctrl_lines_t; - signal cpu_run : STD_LOGIC; - signal branch_ce : STD_LOGIC; - signal run_en : STD_LOGIC; - signal mul_dep : STD_LOGIC; - signal imem_dep : STD_LOGIC; - signal dmem_dep : STD_LOGIC; - signal cop_ctrl : cop_ctrl_in_t; - signal cop_stat : cop_ctrl_out_t; - signal cop_din : word_t; - signal cop_dout : word_t; - signal alu_result : word_t; - signal mul_result : word_t; - signal mul_busy : STD_LOGIC; - signal EX_events_instr : event_t; - signal EX_events_alu : event_t; - signal EX_events_mem : event_t; - signal EX_events : event_t; - signal MEM_events : event_t; - signal bcu_op_a : word_t; - signal bcu_op_b : word_t; - signal bcu_flags : bcu_flags_t; - signal vaddr : word_t; - - attribute ram_style : string; - - attribute ram_style of reg_a: signal is "distributed"; - attribute ram_style of reg_b: signal is "distributed"; - - signal pc : pc_t; - --------------------------------------------------------------------------- -begin - - clk_1 <= clk; - clk_2 <= not clk; - cpu_run <= run_en; - - -- Stall Detection Unit --------------------------------------------------- - sdu.ID_nop <= imem_dep or cop_stat.exc_pending or EX_stage.exc or MEM_stage.exc; - sdu.EX_nop <= mul_dep or ID_stage.nop or ID_stage.exc; - sdu.MEM_nop <= EX_stage.nop or EX_stage.exc; - sdu.WB_nop <= dmem_dep or MEM_stage.nop; - - sdu.ID_stall <= dmem_dep or imem_dep or mul_dep or ID_stage.exc; - sdu.EX_stall <= dmem_dep; - sdu.MEM_stall <= dmem_dep; - sdu.WB_stall <= '0'; - - mul_dep <= ID_stage.ctrl.mul_access and (EX_stage.ctrl.mul_start or mul_busy); - imem_dep <= not imem_rdy; - dmem_dep <= not dmem_rdy and MEM_stage.ctrl.dmem_en; - --------------------------------------------------------------------------- - imem_en <= cpu_run and not (mul_dep or dmem_dep or cop_stat.exc_commit); - --------------------------------------------------------------------------- --- Muldiv --------------------------------------------------------------------------- -inst_muldiv: muldiv - PORT MAP - ( - rst => cpu_rst, - clk => clk, - hilo_we => EX_stage.ctrl.mul_hilo_we, - din_hi => EX_stage.reg_a, - din_lo => EX_stage.reg_b, - mul_divn => EX_stage.ctrl.mul_mul_divn, - start => EX_stage.ctrl.mul_start, - s_un => EX_stage.ctrl.mul_s_un, - hilo_sel => EX_stage.ctrl.mul_hilo_sel, - busy => mul_busy, - dout => mul_result - ); - --------------------------------------------------------------------------- --- Coprocessor --------------------------------------------------------------------------- -inst_cop: cop - PORT MAP - ( - rst => cpu_rst, - clk => clk, - sdu => sdu, - events => MEM_stage.events, - IR_valid => ID_stage.ctrl.cop_instr_en, - IR => ID_stage.IR, - ctrl_in => cop_ctrl, - ctrl_out => cop_stat, - dout => cop_dout, - din => cop_din - ); - - cop_ctrl.bd_wb <= WB_stage.bd; - cop_ctrl.epc_mem <= MEM_stage.pcn; - cop_ctrl.epc_wb <= MEM_stage.epc; - cop_ctrl.imem_addr <= pc.nxt; - cop_ctrl.dmem_addr <= MEM_stage.va; - --------------------------------------------------------------------------- --- IF stage --------------------------------------------------------------------------- - imem_addr <= pc.curr; - -proc_stage_pc: - process(pc, rst, cop_stat) - begin - if rst = '1' then - pc.curr <= RESET_VECTOR after 2 ns; - else - if pc.is_branch and cop_stat.exc_pending = '0' then - pc.curr <= pc.pc_branch after 2 ns; - else - pc.curr <= pc.nxt after 2 ns; - end if; - end if; - end process; - -proc_stage_pc_branch: - process(clk_1) - begin - if rising_edge(clk_1) then - if sdu.ID_stall = '0' then - pc.pc_branch <= pc.curr + ID_stage.bimm18; - end if; - end if; - end process; - -proc_stage_pc_next: - process(clk_1) - begin - if rising_edge(clk_1) then - branch_ce <= '0'; - cop_ctrl.exc_left <= '0'; - if rst = '1' then - pc.nxt <= RESET_VECTOR; - pc.last <= RESET_VECTOR; - elsif cop_stat.exc_commit = '1' then - pc.nxt <= cop_stat.exc_vec; - elsif sdu.ID_stall = '0' then - cop_ctrl.exc_left <= cop_stat.exc_exit; - branch_ce <= '1'; - pc.last <= pc.curr; - if ID_stage.ctrl.jump = '1' then - pc.nxt <= ID_stage.jimm32; - elsif ID_stage.ctrl.jump_long = '1' then - pc.nxt <= ID_stage.reg_a; - else - pc.nxt <= pc.curr + 4; - end if; - end if; - end if; - end process; - -proc_stage_branch: - process(clk_2) - begin - if rising_edge(clk_2) and branch_ce = '1' then - pc.is_branch <= false; - if EX_stage.ctrl.branch = '1' then - - case EX_stage.ctrl.bc_src is - - when bc_eq_ne => - if (EX_stage.ctrl.bc_not xor bcu_flags.eq) = '1' then - pc.is_branch <= true; - end if; - - when bc_lez_gtz => - if (EX_stage.ctrl.bc_not xor (bcu_flags.z or bcu_flags.ltz)) = '1' then - pc.is_branch <= true; - end if; - - when bc_ltz_gez => - if (EX_stage.ctrl.bc_not xor bcu_flags.ltz) = '1' then - pc.is_branch <= true; - end if; - - when others => null; - end case; - end if; - end if; - end process; - - process(rst, clk_1) - variable reset_delay : unsigned (5 downto 0); - begin - if rising_edge(clk_1) then - if rst = '1' then - reset_delay := (others => '1'); - cpu_rst <= '1'; - run_en <= '0'; - elsif reset_delay /= (5 downto 0 => '0') then - reset_delay := reset_delay - 1; - else - cpu_rst <= '0'; - end if; - if reset_delay(reset_delay'left-1) = '0' then - run_en <= '1'; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ID stage --------------------------------------------------------------------------- - ID_stage.IR <= to_01(imem_data); - ID_stage.pcn <= pc.curr; - ID_stage.op <= decode_op(ID_stage.IR); - ID_stage.jimm32 <= extract_jimm32(ID_stage.IR, ID_stage.pcn); - ID_stage.bimm18 <= extract_bimm18(ID_stage.IR, ID_stage.pcn); - ID_stage.shamt <= extract_shamt(ID_stage.IR); - ID_stage.reg_a_rptr <= extract_rs(ID_stage.IR); - ID_stage.reg_b_rptr <= extract_rt(ID_stage.IR); - ID_stage.ctrl <= ctrl_lines; - ID_stage.reg_write <= ID_stage.ctrl.reg_write or cop_stat.reg_write; - ID_stage.epc <= pc.last; - ID_stage.exc <= event_is_active(ID_stage.events); -- Todo: works - ID_stage.nop <= sdu.ID_nop; - -proc_ID_except: - process(ID_stage, cop_stat, pc) - begin - ID_stage.events <= events_clr; - ID_stage.events.inst_load_err <= pc.nxt(1) or pc.nxt(0); - ID_stage.events.inst_priv_addr <= pc.nxt(word_t'left) and cop_stat.user_mode; - end process; - -proc_stage_hdu: - process(ID_stage, EX_stage, MEM_stage, WB_stage) - variable read_a, read_b : boolean; - variable raw_a_EX, raw_a_MEM, raw_a_WB : boolean; - variable raw_b_EX, raw_b_MEM, raw_b_WB : boolean; - variable reg_ptr_a : reg_ptr_t; - variable reg_ptr_b : reg_ptr_t; - begin - - reg_ptr_a := ID_stage.reg_a_rptr; - reg_ptr_b := ID_stage.reg_b_rptr; - raw_a_EX := reg_ptr_a = EX_stage.reg_wptr and EX_stage.wreg_we = '1'; - raw_a_MEM := reg_ptr_a = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1'; - raw_a_WB := reg_ptr_a = WB_stage.reg_wptr and WB_stage.wreg_we = '1'; - raw_b_EX := reg_ptr_b = EX_stage.reg_wptr and EX_stage.wreg_we = '1'; - raw_b_MEM := reg_ptr_b = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1'; - raw_b_WB := reg_ptr_b = WB_stage.reg_wptr and WB_stage.wreg_we = '1'; - - hdu.alu_fwd_a_ex <= raw_a_EX after 1 ns; - hdu.alu_fwd_a_mem <= raw_a_MEM after 1 ns; - hdu.alu_fwd_a_wb <= raw_a_WB after 1 ns; - hdu.alu_fwd_b_ex <= raw_b_EX after 1 ns; - hdu.alu_fwd_b_mem <= raw_b_MEM after 1 ns; - hdu.alu_fwd_b_wb <= raw_b_WB after 1 ns; - - end process; - -proc_stage_fwd_a: - process(reg_a, hdu, EX_stage, MEM_stage, WB_stage) - variable data : word_t; - begin - data := reg_a; - if hdu.alu_fwd_a_ex then - data := EX_stage.result; - elsif hdu.alu_fwd_a_mem then - data := MEM_stage.data; - elsif hdu.alu_fwd_a_wb then - data := WB_stage.data; - end if; - ID_stage.reg_a <= to_01(data) after 2 ns; - end process; - -proc_stage_fwd_b: - process(reg_b, hdu, EX_stage, MEM_stage, WB_stage) - variable data : word_t; - begin - data := reg_b; - if hdu.alu_fwd_b_ex then - data := EX_stage.result; - elsif hdu.alu_fwd_b_mem then - data := MEM_stage.data; - elsif hdu.alu_fwd_b_wb then - data := WB_stage.data; - end if; - ID_stage.reg_b <= to_01(data) after 2 ns; - end process; - -proc_imm_mux: - process(ID_stage) - variable data : word_t; - begin - data := extract_uimm16(ID_stage.IR); - - case ID_stage.ctrl.imm_src is - - when src_imm32 => - data := extract_simm32(ID_stage.IR); - - when src_imm16 => - data := extract_uimm16(ID_stage.IR); - - when src_imm16_high => - data := ID_stage.IR(word_t'length/2-1 downto 0) & (word_t'length/2-1 downto 0 => '0'); - - when others => null; - - end case; - - ID_stage.imm <= data after 2 ns; - - end process; - --------------------------------------------------------------------------- -inst_idecode_rom: idecode_rom - PORT MAP - ( - nop => sdu.ID_nop, - inst_in => ID_stage.IR, - ctrl_out => ctrl_lines - ); - -inst_reg_dual: reg_dual - GENERIC MAP - ( - addr_width => reg_ptr_t'length, - data_width => word_t'length - ) - PORT MAP - ( - clk_w => clk_1, - we => WB_stage.wreg_we, - en => '1', - wptr => WB_stage.reg_wptr, - din => WB_stage.data, - rptr_a => ID_stage.reg_a_rptr, - rptr_b => ID_stage.reg_b_rptr, - dout_a => reg_a, - dout_b => reg_b - ); - --------------------------------------------------------------------------- --- EX stage --------------------------------------------------------------------------- - EX_stage.reg_a_rptr <= extract_rs(EX_stage.IR); - EX_stage.reg_b_rptr <= extract_rt(EX_stage.IR); - EX_stage.result <= mul_result when EX_stage.ctrl.mul_access = '1' else alu_result; - -proc_stage_ID_EX_1: - process(clk_1) - begin - if rising_edge(clk_1) then - if rst = '1' then - EX_stage.op <= NOP; - EX_stage.IR <= (others => '0'); - EX_stage.ctrl <= ctrl_lines_default; - EX_stage.reg_write <= '0'; - EX_stage.epc <= (others => '0'); - EX_stage.pcn <= (others => '0'); - EX_stage.events_in <= events_clr; - elsif sdu.EX_stall = '0' then - EX_stage.reg_a <= ID_stage.reg_a; - EX_stage.reg_b <= ID_stage.reg_b; - EX_stage.events_in <= ID_stage.events; - EX_stage.op <= ID_stage.op; - EX_stage.ctrl <= ID_stage.ctrl; - EX_stage.reg_write <= ID_stage.reg_write; - EX_stage.nop <= sdu.EX_nop; - EX_stage.IR <= ID_stage.IR; - EX_stage.pcn <= ID_stage.pcn; - if sdu.EX_nop = '1' then - EX_stage.op <= NOP; - EX_stage.IR <= (others => '0'); - EX_stage.ctrl <= ctrl_lines_default; - EX_stage.reg_write <= '0'; - else - EX_stage.epc <= ID_stage.epc; - end if; - end if; - end if; - end process; - -proc_stage_EX_instr_except: - process(EX_stage) - begin - EX_events_instr <= events_clr; - EX_events_instr.illegal <= EX_stage.ctrl.exc_illegal; - EX_events_instr.break <= EX_stage.ctrl.exc_break; - EX_events_instr.syscall <= EX_stage.ctrl.exc_syscall; - end process; - -proc_stage_EX_alu_except: - process(EX_stage) - begin - EX_events_alu <= events_clr; - if EX_stage.ctrl.alu_exc_en = '1' then - if EX_stage.alu_flags.ovf = '1' then - EX_events_alu.alu_ovf <= '1'; - end if; - if EX_stage.alu_flags.uvf = '1' then - EX_events_alu.alu_uvf <= '1'; - end if; - end if; - end process; - - vaddr <= ID_stage.reg_a + extract_simm32(ID_stage.IR); - -proc_stage_EX_mem_except: - process(clk_1) - begin - if rising_edge(clk_1) then - if rst = '1' then - dmem_en <= '0'; - elsif sdu.EX_stall = '0' then - EX_events_mem <= events_clr; - dmem_en <= '0'; - if ID_stage.ctrl.dmem_en = '1' then - dmem_en <= '1'; - if ID_stage.ctrl.except_en = '1' then - if ID_stage.ctrl.word2_en = '1' then - if vaddr(0) = '1' then - EX_events_mem.data_load_err <= not ID_stage.ctrl.dmem_we; - EX_events_mem.data_store_err <= ID_stage.ctrl.dmem_we; - dmem_en <= '0'; - end if; - elsif vaddr(1 downto 0) /= "00" then - EX_events_mem.data_load_err <= not ID_stage.ctrl.dmem_we; - EX_events_mem.data_store_err <= ID_stage.ctrl.dmem_we; - dmem_en <= '0'; - end if; - end if; - end if; - end if; - end if; - end process; - -proc_stage_DMEM_ADDR: - process(clk_1) - begin - if rising_edge(clk_1) then - if sdu.EX_stall = '0' then --and ID_stage.ctrl.dmem_en = '1' then - EX_stage.va <= vaddr; - if cop_stat.RE = '1' then - EX_stage.pa_off <= not vaddr(1 downto 0); - else - EX_stage.pa_off <= vaddr(1 downto 0); - end if; - end if; - end if; - end process; - dmem_we <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns; - dmem_re <= not EX_stage.ctrl.dmem_we; - dmem_dout <= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns; - dmem_addr <= EX_stage.va; - cop_din <= EX_stage.reg_b; - EX_stage.events <= EX_events_instr or EX_events_mem or EX_events_alu or EX_stage.events_in; - EX_stage.exc <= event_is_active(EX_stage.events); - --------------------------------------------------------------------------- -proc_wptr_mux: - process(EX_stage) - variable opclass : opcode_t; - variable reg_wptr : reg_ptr_t; - begin - - opclass := extract_opc(EX_stage.IR); - case opclass is - when "000000" => - reg_wptr := extract_rd(EX_stage.IR); - when others => - reg_wptr := extract_rt(EX_stage.IR); - end case; - - EX_stage.wreg_we <= EX_stage.reg_write after 1 ns; - if reg_wptr = "00000" then - EX_stage.wreg_we <= '0' after 1 ns; - end if; - - EX_stage.reg_wptr <= reg_wptr after 1 ns; - case EX_stage.ctrl.wptr_srcsel is - when wptr_src_imm => - EX_stage.reg_wptr <= reg_wptr after 1 ns; - - when wptr_src_const => - EX_stage.reg_wptr <= to_unsigned(31, reg_ptr_t'length) after 1 ns; - EX_stage.wreg_we <= '1' after 1 ns; - - when others => null; - end case; - - end process; - --------------------------------------------------------------------------- -proc_stage_bcu_op: - process(clk_1) - begin - if rising_edge(clk_1) then - bcu_op_a <= ID_stage.reg_a; - bcu_op_b <= ID_stage.reg_b; - end if; - end process; - -alu_op1_mux: - process(EX_stage) - variable data : word_t; - begin - - data := EX_stage.reg_a; - --- case EX_stage.ctrl.alu.op1_src is --- --- when alu_src_reg => --- data := EX_stage.reg_a; --- --- when alu_src_muldiv => --- data := mul_result; --- --- when others => null; --- --- end case; - - EX_stage.alu_op1 <= data; - - end process; - -alu_op2_mux: - process(clk_1) - variable data : word_t; - begin - - if rising_edge(clk_1) and sdu.EX_stall = '0' then - data := ID_stage.reg_b; - - case ID_stage.ctrl.alu.op2_src is - - when alu_src_reg => - data := ID_stage.reg_b; - - when alu_src_imm => - data := ID_stage.imm; - - when others => null; - - end case; - - EX_stage.alu_op2 <= data; - end if; - - end process; - -shifter_sa_mux: - process(clk_1) - variable data : shamt_t; - variable data_inv : shamt_t; - - begin - if rising_edge(clk_1) and sdu.EX_stall = '0' then - data := ID_stage.reg_a(4 downto 0); - case ID_stage.ctrl.shamt2_srcsel is - - when sa_src_reg => - data := ID_stage.reg_a(4 downto 0); - - when sa_src_imm => - data := ID_stage.shamt; - - when others => null; - - end case; - data_inv := not data + 1; - if ID_stage.ctrl.alu.shift_right = '0' then - EX_stage.shift_ctrl.shamt_rnd <= data_inv after 2 ns; - else - EX_stage.shift_ctrl.shamt_rnd <= data after 2 ns; - end if; - EX_stage.shift_ctrl.shamt_nrm <= data after 1 ns; - EX_stage.shift_ctrl.shift_right <= ID_stage.ctrl.alu.shift_right; - EX_stage.shift_ctrl.shift_arith <= ID_stage.ctrl.alu.shift_arith; - end if; - - end process; - --------------------------------------------------------------------------- -inst_shifter: shifter - GENERIC MAP - ( - data_width => word_t'length - ) - PORT MAP - ( - shift_ctrl => EX_stage.shift_ctrl, - din => EX_stage.reg_b, - dout => EX_stage.alu_op2_s - ); - -inst_alu: alu - GENERIC MAP - ( - data_width => word_t'length - ) - PORT MAP - ( - op1_in => EX_stage.alu_op1, - op2_in => EX_stage.alu_op2, - op2_shifted => EX_stage.alu_op2_s, - ctrl => EX_stage.ctrl.alu, - result => alu_result, - flags => EX_stage.alu_flags - ); - -inst_bcu: bcu - GENERIC MAP - ( - data_width => word_t'length - ) - PORT MAP - ( - op1_in => bcu_op_a, - op2_in => bcu_op_b, - flags => bcu_flags - ); - --------------------------------------------------------------------------- --- MEM stage --------------------------------------------------------------------------- -proc_stage_MEM_n: - process(clk_1) - begin - if rising_edge(clk_1) then - if rst = '1' then - MEM_stage.op <= NOP; - MEM_stage.wreg_we <= '0'; - MEM_stage.ctrl <= ctrl_lines_default; - MEM_stage.pa_off <= (others => '0'); - MEM_stage.events_in <= events_clr; --- MEM_stage.epc <= (others => '0'); --- MEM_stage.pcn <= (others => '0'); --- MEM_stage.va <= (others => '0'); --- MEM_stage.reg_wptr <= (others => '0'); --- MEM_stage.ex_result <= (others => '0'); - elsif sdu.MEM_stall = '0' then - MEM_stage.events_in <= EX_stage.events; - MEM_stage.op <= EX_stage.op; - MEM_stage.wreg_we <= EX_stage.wreg_we; - MEM_stage.ctrl <= EX_stage.ctrl; - MEM_stage.va <= EX_stage.va; - MEM_stage.pa_off <= EX_stage.pa_off; - MEM_stage.reg_wptr <= EX_stage.reg_wptr; - MEM_stage.nop <= sdu.MEM_nop; - if EX_stage.ctrl.dmem_en = '1' then - MEM_stage.ex_result <= EX_stage.reg_b; - else - MEM_stage.ex_result <= EX_stage.result; - if cop_stat.cop_read = '1' then - MEM_stage.ex_result <= cop_dout; - end if; - end if; - if sdu.MEM_nop = '1' then - MEM_stage.op <= NOP; - MEM_stage.wreg_we <= '0'; - MEM_stage.ctrl <= ctrl_lines_default; - else - MEM_stage.pcn <= EX_stage.pcn; - MEM_stage.epc <= EX_stage.epc; - end if; - end if; - end if; - end process; - -proc_stage_MEM_mux: - process(MEM_stage, dmem_din) - variable temp1 : word_t; - variable temp2 : word_t; - variable data : word_t; - variable be : unsigned(3 downto 0); - begin - data := MEM_stage.ex_result; - be := load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp); - if MEM_stage.ctrl.reg_link = '1' then - data := MEM_stage.pcn + 4; - elsif MEM_stage.ctrl.dmem_en = '1' then - temp1 := load_shift(dmem_din, MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp); - temp2 := load_sign_ext(temp1, MEM_stage.ctrl.sign_ext_byp, MEM_stage.ctrl.load_signed, MEM_stage.ctrl.word2_en, MEM_stage.ctrl.word4_en); - if be(0) = '1' then - data(7 downto 0) := temp2(7 downto 0); - end if; - if be(1) = '1' then - data(15 downto 8) := temp2(15 downto 8); - end if; - if be(2) = '1' then - data(23 downto 16) := temp2(23 downto 16); - end if; - if be(3) = '1' then - data(31 downto 24) := temp2(31 downto 24); - end if; - end if; - MEM_stage.data <= data after 1 ns; - - end process; - -proc_stage_MEM_except: - process(MEM_stage, int) - begin - MEM_stage.events <= MEM_stage.events_in; - MEM_stage.events.Int <= int; - end process; - - MEM_stage.exc <= cop_stat.int or event_is_active(MEM_stage.events_in); - --------------------------------------------------------------------------- --- WB stage --------------------------------------------------------------------------- -proc_stage_WB_p: - process(clk_1) - begin - if rising_edge(clk_1) then - if rst = '1' then - WB_stage.op <= NOP; - WB_stage.wreg_we <= '0'; --- WB_stage.epc <= (others => '0'); --- WB_stage.reg_wptr <= (others => '0'); --- WB_stage.data <= (others => '0'); - elsif sdu.WB_stall = '0' then - WB_stage.op <= MEM_stage.op; - WB_stage.wreg_we <= MEM_stage.wreg_we; - WB_stage.reg_wptr <= MEM_stage.reg_wptr; - WB_stage.data <= MEM_stage.data; - WB_stage.nop <= sdu.WB_nop; - if sdu.WB_nop = '1' then - WB_stage.op <= NOP; - WB_stage.wreg_we <= '0'; - else - WB_stage.epc <= MEM_stage.epc; - WB_stage.bd <= MEM_stage.ctrl.branch or MEM_stage.ctrl.jump or MEM_stage.ctrl.jump_long; -- Todo: works - end if; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_reg.vhd b/lib/CPUs/MIPS/src/core/mips_reg.vhd deleted file mode 100644 index da76225..0000000 --- a/lib/CPUs/MIPS/src/core/mips_reg.vhd +++ /dev/null @@ -1,81 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: On-Chip work registers --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity reg_dual is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clk_w : in STD_LOGIC; - we : in STD_LOGIC; - en : in STD_LOGIC; - wptr : in unsigned (addr_width-1 downto 0); - din : in unsigned (data_width-1 downto 0); - rptr_a : in unsigned (addr_width-1 downto 0); - rptr_b : in unsigned (addr_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end reg_dual; - -architecture Behavioral of reg_dual is - - constant depth : integer := 2**addr_width; - type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0); - - function mem_clear(depth : natural) return mem_t is - variable result : mem_t; - begin - for i in 0 to depth-1 loop - result(i) := (others => '0'); - end loop; - return result; - end mem_clear; - - signal reg_mem : mem_t := mem_clear(depth); - -begin - -reg_in: - process(clk_w) - begin - if rising_edge(clk_w) then - if we = '1' and en = '1' then - reg_mem(to_integer(wptr)) <= din; - end if; - end if; - end process; - - dout_a <= reg_mem(to_integer(rptr_a)) after 2 ns; - dout_b <= reg_mem(to_integer(rptr_b)) after 2 ns; - -end Behavioral; - diff --git a/lib/CPUs/MIPS/src/core/mips_shifter.vhd b/lib/CPUs/MIPS/src/core/mips_shifter.vhd deleted file mode 100644 index cff2c7d..0000000 --- a/lib/CPUs/MIPS/src/core/mips_shifter.vhd +++ /dev/null @@ -1,114 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The shifter unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity shifter is - Generic - ( - data_width : integer := 8 - ); - Port - ( - shift_ctrl : in shift_ctrl_t; - din : in unsigned (data_width-1 downto 0); - dout : out unsigned (data_width-1 downto 0) - ); -end shifter; - -architecture Behavioral of shifter is - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 5) of word_t; - - signal rot_data : word_array_t; - signal sa_rnd : unsigned (4 downto 0); - signal fill : std_logic; - --------------------------------------------------------------------------- -function rot_stage(x : unsigned; en : std_logic; stage_num : natural) return unsigned is - variable result : unsigned(x'range); - constant sa : natural := 2**stage_num; - begin - if en = '1' then - result := x(sa-1 downto 0) & x(x'left downto sa); - else - result := x; - end if; - return result; - -end rot_stage; - -function rot_fill(x : unsigned; fill : std_logic; shift_right : std_logic; sa : natural) return unsigned is - variable result : unsigned(x'range) := (others => '0'); - variable j : integer; - begin - - if shift_right = '0' then - for i in 0 to x'left loop - if i >= sa then - result(i) := x(i); - else - result(i) := fill; - end if; - end loop; - else - j := x'left; - for i in 0 to x'left loop - if i < sa then - result(j) := fill; - else - result(j) := x(j); - end if; - j := j - 1; - end loop; - end if; - return result; - -end rot_fill; - --------------------------------------------------------------------------- -begin - - rot_data(0) <= din; - -gen_rotate_right: - for stage in 0 to 4 generate - begin - rot_data(stage+1) <= rot_stage(rot_data(stage), sa_rnd(stage), stage); - end generate; - - sa_rnd <= shift_ctrl.shamt_rnd; - fill <= shift_ctrl.shift_arith and din(data_width-1); - dout <= rot_fill(rot_data(5), fill, shift_ctrl.shift_right, to_integer(shift_ctrl.shamt_nrm)) after 5 ns; --- dout <= rot_data(5); - - - --------------------------------------------------------------------------- -end Behavioral; - diff --git a/lib/CPUs/MIPS/src/core/mips_top.vhd b/lib/CPUs/MIPS/src/core/mips_top.vhd deleted file mode 100644 index 3d25c3e..0000000 --- a/lib/CPUs/MIPS/src/core/mips_top.vhd +++ /dev/null @@ -1,164 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: JIPS top file --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - -entity mips_top is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - int : in unsigned (5 downto 0); - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC; - mem_en : out STD_LOGIC; - mem_re : out STD_LOGIC; - mem_we : out unsigned(3 downto 0); - mem_din : in unsigned (WORD_WIDTH-1 downto 0); - mem_dout : out unsigned (WORD_WIDTH-1 downto 0); - mem_addr : out unsigned (WORD_WIDTH-1 downto 0) - ); - -end mips_top; - -architecture rtl of mips_top is - - COMPONENT pipeline is - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - halt : in STD_LOGIC; - int : in unsigned (5 downto 0); - imem_rdy : in STD_LOGIC; - imem_en : out STD_LOGIC; - imem_addr : out word_t; - imem_data : in word_t; - dmem_rdy : in STD_LOGIC; - dmem_en : out STD_LOGIC; - dmem_re : out STD_LOGIC; - dmem_we : out unsigned(3 downto 0); - dmem_addr : out word_t; - dmem_din : in word_t; - dmem_dout : out word_t - ); - END COMPONENT; - signal halt : std_logic; - signal imem_rdy : std_logic; - signal imem_en : std_logic; - signal imem_addr : word_t; - signal imem_din : word_t; - signal dmem_rdy : std_logic; - signal dmem_en : std_logic; - signal dmem_re : std_logic; - signal dmem_addr : word_t; - signal dmem_dout : word_t; - signal dmem_din : word_t; - signal dmem_we : unsigned(3 downto 0); - - COMPONENT bui - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - cpu_wait : out STD_LOGIC; - cpu_imem_rdy : out STD_LOGIC; - cpu_imem_en : in STD_LOGIC; - cpu_imem_addr : in word_t; - cpu_imem_din : out word_t; - cpu_dmem_rdy : out STD_LOGIC; - cpu_dmem_en : in STD_LOGIC; - cpu_dmem_re : in STD_LOGIC; - cpu_dmem_we : in unsigned(3 downto 0); - cpu_dmem_addr : in word_t; - cpu_dmem_din : out word_t; - cpu_dmem_dout : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_dout : out word_t; - mem_re : out STD_LOGIC; - mem_we : out unsigned(3 downto 0); - mem_ce : out STD_LOGIC - ); - END COMPONENT; - -begin - -------------------------------------------------------------------- - -inst_pipeline: pipeline - PORT MAP - ( - rst => rst, - clk => clk, - halt => halt, - int => int, - imem_rdy => imem_rdy, - imem_en => imem_en, - imem_addr => imem_addr, - imem_data => imem_din, - dmem_rdy => dmem_rdy, - dmem_en => dmem_en, - dmem_re => dmem_re, - dmem_we => dmem_we, - dmem_addr => dmem_addr, - dmem_din => dmem_din, - dmem_dout => dmem_dout - ); - -inst_bui: bui - PORT MAP - ( - rst => rst, - clk => clk, - ce => '1', - cpu_wait => halt, - cpu_imem_rdy => imem_rdy, - cpu_imem_en => imem_en, - cpu_imem_addr => imem_addr, - cpu_imem_din => imem_din, - cpu_dmem_rdy => dmem_rdy, - cpu_dmem_en => dmem_en, - cpu_dmem_re => dmem_re, - cpu_dmem_we => dmem_we, - cpu_dmem_addr => dmem_addr, - cpu_dmem_din => dmem_din, - cpu_dmem_dout => dmem_dout, - mem_valid => mem_valid, - mem_rdy => mem_rdy, - mem_addr => mem_addr, - mem_din => mem_din, - mem_dout => mem_dout, - mem_re => mem_re, - mem_we => mem_we, - mem_ce => mem_en - ); - -end rtl; diff --git a/lib/CPUs/MIPS/src/core/mips_types.vhd b/lib/CPUs/MIPS/src/core/mips_types.vhd deleted file mode 100644 index 0dec8a1..0000000 --- a/lib/CPUs/MIPS/src/core/mips_types.vhd +++ /dev/null @@ -1,620 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Types, constants and functions for JIPS --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - - --------------------------------------------------------------------------- -package mips_types is - - -- Revision of the CPU - constant REVISION : integer := 1; - constant WORD_WIDTH : integer := 32; - - --Types - subtype instr_name_t is string(1 to 12); - type instr_name_array_t is array (0 to 63) of instr_name_t; - subtype opcode_t is unsigned (5 downto 0); - subtype word_t is unsigned (WORD_WIDTH-1 downto 0); - subtype reg_ptr_t is unsigned (4 downto 0); - subtype shamt_t is unsigned(4 downto 0); - subtype sa_t is natural range 0 to 63; - subtype func_t is unsigned(5 downto 0); - - type opclass_t is (special, regimm, opcode); - - type op_t is - ( - nop, - op_sll, - op_srl, - op_sra, - op_sllv, - op_srlv, - op_srav, - op_jr, - op_jalr, - op_syscall, - op_break, - op_mfhi, - op_mthi, - op_mflo, - op_mtlo, - op_mult, - op_multu, - op_div, - op_divu, - op_add, - op_addu, - op_sub, - op_subu, - op_and, - op_or, - op_xor, - op_nor, - op_slt, - op_sltu, - op_bltz, - op_bgez, - op_bltzal, - op_bgezal, - op_j, - op_jal, - op_beq, - op_bne, - op_blez, - op_bgtz, - op_addi, - op_addiu, - op_slti, - op_sltiu, - op_andi, - op_ori, - op_xori, - op_lui, - op_lb, - op_lh, - op_lwl, - op_lw, - op_lbu, - op_lhu, - op_lwr, - op_sb, - op_sh, - op_swl, - op_sw, - op_swr, - op_cop0, - op_cop1, - op_cop2, - op_cop3, - op_lwc1, - op_lwc2, - op_lwc3, - op_swc1, - op_swc2, - op_swc3 - ); - - attribute ENUM_ENCODING : string; - - type imm_src_t is (src_imm32, src_imm16, src_imm16_high); - type sa_src_t is (sa_src_reg, sa_src_imm); - type alu_src1_t is (alu_src_reg); - type alu_src2_t is (alu_src_reg, alu_src_imm); - type bc_src_t is (bc_eq_ne, bc_lez_gtz, bc_ltz_gez); - type shift_opsel_t is (shift_sll, shift_srl, shift_sra); - type wptr_src_t is (wptr_src_imm, wptr_src_const); - --- attribute ENUM_ENCODING of itype_t: type is "ONE-HOT"; - - type pc_t is record - curr : word_t; - last : word_t; - nxt : word_t; - pc_branch : word_t; - is_branch : boolean; - end record; - - type alu_outsel_t is - ( - alu_adder, - alu_shift2, - alu_and, - alu_or, - alu_xor, - alu_nor, - alu_ltu, - alu_lts - ); - - type alu_flags_t is record - c : STD_LOGIC; - uvf : STD_LOGIC; - ovf : STD_LOGIC; - ltu : STD_LOGIC; - lts : STD_LOGIC; - end record; - - type bcu_flags_t is record - z : STD_LOGIC; - eq : STD_LOGIC; - ltz : STD_LOGIC; - end record; - - type event_t is record - Int : unsigned(5 downto 0); - data_load_err : STD_LOGIC; - data_store_err : STD_LOGIC; - inst_load_err : STD_LOGIC; - inst_priv_addr : STD_LOGIC; - alu_ovf : STD_LOGIC; - alu_uvf : STD_LOGIC; - syscall : STD_LOGIC; - break : STD_LOGIC; - illegal : STD_LOGIC; - end record; - - type exc_flags_t is record - Int : STD_LOGIC; - DAdEL : STD_LOGIC; - DAdES : STD_LOGIC; - IAdEL : STD_LOGIC; - IAdEK : STD_LOGIC; - Ov : STD_LOGIC; - Sys : STD_LOGIC; - Bp : STD_LOGIC; - RI : STD_LOGIC; - IBE : STD_LOGIC; - DBE : STD_LOGIC; - end record; - - type except_t is record - act : STD_LOGIC; - epc : word_t; - cause : word_t; - end record; - - type cop_ctrl_in_t is record - bd_wb : STD_LOGIC; - epc_mem : word_t; - epc_wb : word_t; - imem_addr : word_t; - dmem_addr : word_t; - exc_left : STD_LOGIC; - end record; - - type cop_ctrl_out_t is record - RE : STD_LOGIC; - ee : STD_LOGIC; - ec : STD_LOGIC; - exc_commit : STD_LOGIC; - exc_pending : STD_LOGIC; - exc_exit : STD_LOGIC; - reg_write : STD_LOGIC; - cop_read : STD_LOGIC; - user_mode : STD_LOGIC; - int : STD_LOGIC; - exc_vec : word_t; - end record; - - type sdu_t is record - ID_nop : STD_LOGIC; - EX_nop : STD_LOGIC; - MEM_nop : STD_LOGIC; - WB_nop : STD_LOGIC; - ID_stall : STD_LOGIC; - EX_stall : STD_LOGIC; - MEM_stall : STD_LOGIC; - WB_stall : STD_LOGIC; - end record; - - type hdu_t is record - alu_fwd_a_ex : boolean; - alu_fwd_a_mem : boolean; - alu_fwd_a_wb : boolean; - alu_fwd_b_ex : boolean; - alu_fwd_b_mem : boolean; - alu_fwd_b_wb : boolean; - end record; - - type alu_ctrl_t is record - outsel : alu_outsel_t; - add : STD_LOGIC; - shift_right : STD_LOGIC; - shift_arith : STD_LOGIC; - op1_src : alu_src1_t; - op2_src : alu_src2_t; - end record; - - type shift_ctrl_t is record - shamt_nrm : shamt_t; - shamt_rnd : shamt_t; - shift_right : STD_LOGIC; - shift_arith : STD_LOGIC; - end record; - - type ctrl_lines_t is record - branch : STD_LOGIC; - jump_long : STD_LOGIC; - jump : STD_LOGIC; - bc_not : STD_LOGIC; - bc_src : bc_src_t; - imm_src : imm_src_t; - alu : alu_ctrl_t; - reg_write : STD_LOGIC; - reg_link : STD_LOGIC; - dmem_we : STD_LOGIC; - dmem_en : STD_LOGIC; - shamt2_srcsel : sa_src_t; - wptr_srcsel : wptr_src_t; - cop_instr_en : STD_LOGIC; - shift_offset : unsigned(1 downto 0); - shift_byp : STD_LOGIC; - byte_en_byp : STD_LOGIC; - sign_ext_byp : STD_LOGIC; - word4_en : STD_LOGIC; - word2_en : STD_LOGIC; - align_left : STD_LOGIC; - load_signed : STD_LOGIC; - mul_access : STD_LOGIC; - mul_hilo_we : STD_LOGIC; - mul_mul_divn : STD_LOGIC; - mul_start : STD_LOGIC; - mul_s_un : STD_LOGIC; - mul_hilo_sel : STD_LOGIC; - exc_break : STD_LOGIC; - exc_syscall : STD_LOGIC; - exc_illegal : STD_LOGIC; - except_en : STD_LOGIC; - alu_exc_en : STD_LOGIC; - end record; - - type ID_t is record - nop : STD_LOGIC; - exc : std_logic; - IR : word_t; - op : op_t; - pcn : word_t; - epc : word_t; - jimm32 : word_t; - bimm18 : word_t; - imm : word_t; - shamt : shamt_t; - ctrl : ctrl_lines_t; - reg_write : STD_LOGIC; - reg_a_rptr : reg_ptr_t; - reg_b_rptr : reg_ptr_t; - reg_a : word_t; - reg_b : word_t; - events : event_t; - end record; - - type EX_t is record - nop : STD_LOGIC; - exc : std_logic; - IR : word_t; - op : op_t; - pcn : word_t; - epc : word_t; - reg_a : word_t; - reg_b : word_t; - ctrl : ctrl_lines_t; - shift_ctrl : shift_ctrl_t; - alu_op1 : word_t; - alu_op2 : word_t; - alu_op2_s : word_t; - alu_flags : alu_flags_t; - result : word_t; - reg_write : STD_LOGIC; - wreg_we : STD_LOGIC; - reg_wptr : reg_ptr_t; - reg_a_rptr : reg_ptr_t; - reg_b_rptr : reg_ptr_t; - va : word_t; - pa_off : unsigned(1 downto 0); - events_in : event_t; - events : event_t; - end record; - - type MEM_t is record - nop : STD_LOGIC; - exc : std_logic; - op : op_t; - pcn : word_t; - epc : word_t; - ctrl : ctrl_lines_t; - ex_result : word_t; - reg_wptr : reg_ptr_t; - wreg_we : STD_LOGIC; - data : word_t; - va : word_t; - pa_off : unsigned(1 downto 0); - events_in : event_t; - events : event_t; - end record; - - type WB_t is record - nop : STD_LOGIC; - op : op_t; - epc : word_t; - reg_wptr : reg_ptr_t; - wreg_we : STD_LOGIC; - data : word_t; - bd : STD_LOGIC; - end record; - - - type rom_special_t is array (0 to 2**func_t'length-1) of ctrl_lines_t; - type rom_regimm_t is array (0 to 2**reg_ptr_t'length-1) of ctrl_lines_t; - type rom_opcode_t is array (0 to 2**opcode_t'length-1) of ctrl_lines_t; - - function store_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t; - function store_be(va : unsigned(1 downto 0); be_src, word2_en, word4_en, align_left, bypass : std_logic) return unsigned; - function load_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t; - function load_be(va : unsigned(1 downto 0); align_left, bypass : std_logic) return unsigned; - function load_sign_ext(x : word_t; bypass, signed, word2_en, word4_en : std_logic) return word_t; - function events_clr return event_t; - function event_is_active(e : event_t) return std_logic; - function "or" (a, b : event_t) return event_t; - -end mips_types; - --------------------------------------------------------------------------- -package body mips_types is - - function store_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t is - variable stage1 : word_t; - variable result : word_t; - variable sa : unsigned(1 downto 0); - begin - - if bypass = '1' then - sa := "00"; - else - sa := va + shift_off; - end if; - - stage1 := x; - if sa(0) = '1' then - stage1 := x(23 downto 0) & x(31 downto 24); - end if; - result := stage1; - if sa(1) = '1' then - result := stage1(15 downto 0) & stage1(31 downto 16); - end if; - - return result; - end store_shift; - --------------------------------------------------------------------------- - function store_be(va : unsigned(1 downto 0); be_src, word2_en, word4_en, align_left, bypass : std_logic) return unsigned is - variable result : unsigned(3 downto 0); - begin - if bypass = '1' then - result := (3 downto 0 => be_src); - elsif word2_en = '1' then - case va is - when "00" | "01" => - result := "00" & be_src & be_src; - when "10" | "11" => - result := be_src & be_src & "00"; - when others => - result := "0000"; - end case; - elsif word4_en = '1' then - case va is - when "00" => - result := "000" & be_src; - when "01" => - result := "00" & be_src & '0'; - when "10" => - result := '0' & be_src & "00"; - when "11" => - result := be_src & "000"; - when others => - result := "0000"; - end case; - elsif align_left = '1' then - case va is - when "00" => - result := be_src & be_src & be_src & be_src; - when "01" => - result := be_src & be_src & be_src & '0'; - when "10" => - result := be_src & be_src & "00"; - when "11" => - result := be_src & "000"; - when others => - result := "0000"; - end case; - else - case va is - when "00" => - result := "000" & be_src; - when "01" => - result := "00" & be_src & be_src; - when "10" => - result := '0' & be_src & be_src & be_src; - when "11" => - result := be_src & be_src & be_src & be_src; - when others => - result := "0000"; - end case; - end if; - - return result; - - end store_be; - --------------------------------------------------------------------------- - function load_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t is - variable stage1 : word_t; - variable result : word_t; - variable sa : unsigned(1 downto 0); - - begin - if bypass = '1' then - sa := "00"; - else - sa := va + shift_off; - end if; - - stage1 := x; - if sa(0) = '1' then - stage1 := x(7 downto 0) & x(31 downto 8); - end if; - result := stage1; - if sa(1) = '1' then - result := stage1(15 downto 0) & stage1(31 downto 16); - end if; - - return result; - end load_shift; - --------------------------------------------------------------------------- - function load_be(va : unsigned(1 downto 0); align_left, bypass : std_logic) return unsigned is - variable result : unsigned(3 downto 0); - begin - if bypass = '1' then - result := (3 downto 0 => '1'); - elsif align_left = '1' then - case va is - when "00" => - result := "1000"; - when "01" => - result := "1100"; - when "10" => - result := "1110"; - when "11" => - result := "1111"; - when others => - result := "0000"; - end case; - else - case va is - when "00" => - result := "1111"; - when "01" => - result := "0111"; - when "10" => - result := "0011"; - when "11" => - result := "0001"; - when others => - result := "0000"; - end case; - end if; - - return result; - - end load_be; - --------------------------------------------------------------------------- - function load_sign_ext(x : word_t; bypass, signed, word2_en, word4_en : std_logic) return word_t is - variable result : word_t; - variable sign : std_logic; - - begin - if bypass = '1' then - result := x; - elsif word2_en = '1' then - sign := signed and x(15); - result := (31 downto 16 => sign) & x(15 downto 0); - else - sign := signed and x(7); - result := (31 downto 8 => sign) & x(7 downto 0); - end if; - - return result; - end load_sign_ext; - --------------------------------------------------------------------------- - function events_clr return event_t is - variable result : event_t; - begin - result.Int := (others => '0'); - result.data_load_err := '0'; - result.data_store_err := '0'; - result.inst_load_err := '0'; - result.inst_priv_addr := '0'; - result.alu_ovf := '0'; - result.alu_uvf := '0'; - result.syscall := '0'; - result.break := '0'; - result.illegal := '0'; - - return result; - - end events_clr; - - function event_is_active(e : event_t) return std_logic is - variable result : std_logic; - begin - result := '0'; - - for i in e.Int'range loop - result := result or e.Int(i); - end loop; - - result := result or e.data_load_err; - result := result or e.data_store_err; - result := result or e.inst_load_err; - result := result or e.inst_priv_addr; - result := result or e.alu_ovf; - result := result or e.alu_uvf; - result := result or e.syscall; - result := result or e.break; - result := result or e.illegal; - - return result; - - end event_is_active; - - function "or" (a, b : event_t) return event_t is - variable result : event_t; - begin - for i in a.Int'range loop - result.Int(i) := a.Int(i) or b.Int(i); - end loop; - result.data_load_err := a.data_load_err or b.data_load_err; - result.data_store_err := a.data_store_err or b.data_store_err; - result.inst_load_err := a.inst_load_err or b.inst_load_err; - result.inst_priv_addr := a.inst_priv_addr or b.inst_priv_addr; - result.alu_ovf := a.alu_ovf or b.alu_ovf; - result.alu_uvf := a.alu_uvf or b.alu_uvf; - result.syscall := a.syscall or b.syscall; - result.break := a.break or b.break; - result.illegal := a.illegal or b.illegal; - - return result; - - end "or"; - --------------------------------------------------------------------------- -end mips_types; - --------------------------------------------------------------------------- --------------------------------------------------------------------------- diff --git a/lib/CPUs/MIPS/src/fibonacci.ROM_ld.vhd b/lib/CPUs/MIPS/src/fibonacci.ROM_ld.vhd deleted file mode 100644 index 759ad2a..0000000 --- a/lib/CPUs/MIPS/src/fibonacci.ROM_ld.vhd +++ /dev/null @@ -1,2174 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY rom IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END rom; - -ARCHITECTURE data OF rom IS - - subtype word_t is unsigned(31 downto 0); - type word_array_t is array (0 to 2047) of word_t; - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : unsigned (15 downto 0); - signal jtag_ld_dout : unsigned (31 downto 0); - signal jtag_ld_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - - signal word_array : word_array_t := - ( - - X"401A6000", -- 00000000 - X"3C1B0040", -- 00000004 - X"035BD024", -- 00000008 - X"375A000C", -- 0000000C - X"409A6000", -- 00000010 - X"401A7800", -- 00000014 - X"00000000", -- 00000018 - X"409AF800", -- 0000001C - X"3C1D7FFF", -- 00000020 - X"37BDEFFC", -- 00000024 - X"3C1A0040", -- 00000028 - X"275A02E4", -- 0000002C - X"0340F809", -- 00000030 - X"42000010", -- 00000034 - X"00000000", -- 00000038 - X"00000000", -- 0000003C - X"00000000", -- 00000040 - X"00000000", -- 00000044 - X"00000000", -- 00000048 - X"00000000", -- 0000004C - X"00000000", -- 00000050 - X"00000000", -- 00000054 - X"00000000", -- 00000058 - X"00000000", -- 0000005C - X"00000000", -- 00000060 - X"00000000", -- 00000064 - X"00000000", -- 00000068 - X"00000000", -- 0000006C - X"00000000", -- 00000070 - X"00000000", -- 00000074 - X"00000000", -- 00000078 - X"00000000", -- 0000007C - X"00000000", -- 00000080 - X"00000000", -- 00000084 - X"00000000", -- 00000088 - X"00000000", -- 0000008C - X"00000000", -- 00000090 - X"00000000", -- 00000094 - X"00000000", -- 00000098 - X"00000000", -- 0000009C - X"00000000", -- 000000A0 - X"00000000", -- 000000A4 - X"00000000", -- 000000A8 - X"00000000", -- 000000AC - X"00000000", -- 000000B0 - X"00000000", -- 000000B4 - X"00000000", -- 000000B8 - X"00000000", -- 000000BC - X"00000000", -- 000000C0 - X"00000000", -- 000000C4 - X"00000000", -- 000000C8 - X"00000000", -- 000000CC - X"00000000", -- 000000D0 - X"00000000", -- 000000D4 - X"00000000", -- 000000D8 - X"00000000", -- 000000DC - X"00000000", -- 000000E0 - X"00000000", -- 000000E4 - X"00000000", -- 000000E8 - X"00000000", -- 000000EC - X"00000000", -- 000000F0 - X"00000000", -- 000000F4 - X"00000000", -- 000000F8 - X"00000000", -- 000000FC - X"00000000", -- 00000100 - X"00000000", -- 00000104 - X"00000000", -- 00000108 - X"00000000", -- 0000010C - X"00000000", -- 00000110 - X"00000000", -- 00000114 - X"00000000", -- 00000118 - X"00000000", -- 0000011C - X"00000000", -- 00000120 - X"00000000", -- 00000124 - X"00000000", -- 00000128 - X"00000000", -- 0000012C - X"00000000", -- 00000130 - X"00000000", -- 00000134 - X"00000000", -- 00000138 - X"00000000", -- 0000013C - X"00000000", -- 00000140 - X"00000000", -- 00000144 - X"00000000", -- 00000148 - X"00000000", -- 0000014C - X"00000000", -- 00000150 - X"00000000", -- 00000154 - X"00000000", -- 00000158 - X"00000000", -- 0000015C - X"00000000", -- 00000160 - X"00000000", -- 00000164 - X"00000000", -- 00000168 - X"00000000", -- 0000016C - X"00000000", -- 00000170 - X"00000000", -- 00000174 - X"00000000", -- 00000178 - X"00000000", -- 0000017C - X"401A6800", -- 00000180 - X"3C1B8000", -- 00000184 - X"001AD082", -- 00000188 - X"335A000F", -- 0000018C - X"035BD025", -- 00000190 - X"AF7A0000", -- 00000194 - X"401A7000", -- 00000198 - X"00000000", -- 0000019C - X"03400008", -- 000001A0 - X"42000010", -- 000001A4 - X"24080002", -- 000001A8 - X"0107102A", -- 000001AC - X"ACC40000", -- 000001B0 - X"1040000B", -- 000001B4 - X"ACC50004", -- 000001B8 - X"24C60008", -- 000001BC - X"24E8FFFE", -- 000001C0 - X"8CC2FFF8", -- 000001C4 - X"8CC3FFFC", -- 000001C8 - X"2508FFFF", -- 000001CC - X"00431021", -- 000001D0 - X"ACC20000", -- 000001D4 - X"1500FFFA", -- 000001D8 - X"24C60004", -- 000001DC - X"00E04021", -- 000001E0 - X"03E00008", -- 000001E4 - X"01001021", -- 000001E8 - X"94820002", -- 000001EC - X"A0800000", -- 000001F0 - X"2442FFFF", -- 000001F4 - X"00021C00", -- 000001F8 - X"A4820002", -- 000001FC - X"00031C03", -- 00000200 - X"2402FFFF", -- 00000204 - X"8C850004", -- 00000208 - X"1062000F", -- 0000020C - X"00000000", -- 00000210 - X"2406FFFF", -- 00000214 - X"90A30000", -- 00000218 - X"90820000", -- 0000021C - X"00000000", -- 00000220 - X"00431021", -- 00000224 - X"A0820000", -- 00000228 - X"A0A20000", -- 0000022C - X"94830002", -- 00000230 - X"24A50001", -- 00000234 - X"2463FFFF", -- 00000238 - X"00031400", -- 0000023C - X"00021403", -- 00000240 - X"1446FFF4", -- 00000244 - X"A4830002", -- 00000248 - X"80820002", -- 0000024C - X"03E00008", -- 00000250 - X"00000000", -- 00000254 - X"3C028000", -- 00000258 - X"00042600", -- 0000025C - X"00042603", -- 00000260 - X"34450004", -- 00000264 - X"34430008", -- 00000268 - X"90620000", -- 0000026C - X"00000000", -- 00000270 - X"00021042", -- 00000274 - X"30420001", -- 00000278 - X"1440FFFB", -- 0000027C - X"00000000", -- 00000280 - X"03E00008", -- 00000284 - X"A0A40000", -- 00000288 - X"27BDFFE0", -- 0000028C - X"AFB10014", -- 00000290 - X"AFB00010", -- 00000294 - X"AFBF0018", -- 00000298 - X"80820000", -- 0000029C - X"00808821", -- 000002A0 - X"1040000A", -- 000002A4 - X"00008021", -- 000002A8 - X"00801821", -- 000002AC - X"80640000", -- 000002B0 - X"0C100096", -- 000002B4 - X"26100001", -- 000002B8 - X"02301821", -- 000002BC - X"80620000", -- 000002C0 - X"00000000", -- 000002C4 - X"1440FFF9", -- 000002C8 - X"00000000", -- 000002CC - X"8FBF0018", -- 000002D0 - X"8FB10014", -- 000002D4 - X"8FB00010", -- 000002D8 - X"03E00008", -- 000002DC - X"27BD0020", -- 000002E0 - X"27BDF020", -- 000002E4 - X"3C02AAAA", -- 000002E8 - X"24040041", -- 000002EC - X"AFBF0FDC", -- 000002F0 - X"AFBE0FD8", -- 000002F4 - X"AFB70FD4", -- 000002F8 - X"AFB60FD0", -- 000002FC - X"AFB50FCC", -- 00000300 - X"AFB40FC8", -- 00000304 - X"AFB30FC4", -- 00000308 - X"AFB00FB8", -- 0000030C - X"AFB20FC0", -- 00000310 - X"3450AAAA", -- 00000314 - X"0C100096", -- 00000318 - X"AFB10FBC", -- 0000031C - X"0C100096", -- 00000320 - X"24040020", -- 00000324 - X"0C100096", -- 00000328 - X"24040041", -- 0000032C - X"0C100096", -- 00000330 - X"24040020", -- 00000334 - X"0C100096", -- 00000338 - X"24040041", -- 0000033C - X"0C100096", -- 00000340 - X"24040020", -- 00000344 - X"0C100096", -- 00000348 - X"24040041", -- 0000034C - X"0C100096", -- 00000350 - X"24040020", -- 00000354 - X"0C100096", -- 00000358 - X"24040030", -- 0000035C - X"0C100096", -- 00000360 - X"24040031", -- 00000364 - X"0C100096", -- 00000368 - X"24040032", -- 0000036C - X"0C100096", -- 00000370 - X"24040033", -- 00000374 - X"0C100096", -- 00000378 - X"24040034", -- 0000037C - X"0C100096", -- 00000380 - X"24040035", -- 00000384 - X"0C100096", -- 00000388 - X"24040036", -- 0000038C - X"0C100096", -- 00000390 - X"24040037", -- 00000394 - X"0C100096", -- 00000398 - X"24040038", -- 0000039C - X"0C100096", -- 000003A0 - X"24040039", -- 000003A4 - X"0C100096", -- 000003A8 - X"24040041", -- 000003AC - X"0C100096", -- 000003B0 - X"24040042", -- 000003B4 - X"0C100096", -- 000003B8 - X"24040043", -- 000003BC - X"0C100096", -- 000003C0 - X"24040044", -- 000003C4 - X"0C100096", -- 000003C8 - X"24040045", -- 000003CC - X"0C100096", -- 000003D0 - X"24040046", -- 000003D4 - X"0C100096", -- 000003D8 - X"2404000D", -- 000003DC - X"0C100096", -- 000003E0 - X"2404000A", -- 000003E4 - X"3C148000", -- 000003E8 - X"00009821", -- 000003EC - X"27BE0010", -- 000003F0 - X"27B70FB0", -- 000003F4 - X"241503E8", -- 000003F8 - X"3C164000", -- 000003FC - X"00008821", -- 00000400 - X"00002021", -- 00000404 - X"03C01021", -- 00000408 - X"240603E7", -- 0000040C - X"24C6FFFF", -- 00000410 - X"AC500000", -- 00000414 - X"04C1FFFD", -- 00000418 - X"24420004", -- 0000041C - X"02041026", -- 00000420 - X"24920001", -- 00000424 - X"24420001", -- 00000428 - X"02402821", -- 0000042C - X"27A60010", -- 00000430 - X"240703E8", -- 00000434 - X"0C10006A", -- 00000438 - X"00028040", -- 0000043C - X"24070002", -- 00000440 - X"27C50008", -- 00000444 - X"08100116", -- 00000448 - X"240603E5", -- 0000044C - X"04C0000A", -- 00000450 - X"00000000", -- 00000454 - X"8CA20000", -- 00000458 - X"8CA3FFFC", -- 0000045C - X"8CA4FFF8", -- 00000460 - X"00431023", -- 00000464 - X"24C6FFFF", -- 00000468 - X"1482FFF8", -- 0000046C - X"24A50004", -- 00000470 - X"04C1FFF8", -- 00000474 - X"24E70001", -- 00000478 - X"10F50013", -- 0000047C - X"00000000", -- 00000480 - X"2A4203E8", -- 00000484 - X"1440FFDF", -- 00000488 - X"02402021", -- 0000048C - X"12350010", -- 00000490 - X"00000000", -- 00000494 - X"02761025", -- 00000498 - X"AE820000", -- 0000049C - X"02E02021", -- 000004A0 - X"24020FA0", -- 000004A4 - X"A7A20FB2", -- 000004A8 - X"A3A00FB0", -- 000004AC - X"0C10007B", -- 000004B0 - X"AFBE0FB4", -- 000004B4 - X"02028026", -- 000004B8 - X"26730001", -- 000004BC - X"00008821", -- 000004C0 - X"08100102", -- 000004C4 - X"00002021", -- 000004C8 - X"08100121", -- 000004CC - X"26310001", -- 000004D0 - X"08100128", -- 000004D4 - X"AE930000", -- 000004D8 - X"00000000", -- 000004DC - X"00000000", -- 000004E0 - X"00000000", -- 000004E4 - X"00000000", -- 000004E8 - X"00000000", -- 000004EC - X"00000000", -- 000004F0 - X"00000000", -- 000004F4 - X"00000000", -- 000004F8 - X"00000000", -- 000004FC - X"00000000", -- 00000500 - X"00000000", -- 00000504 - X"00000000", -- 00000508 - X"00000000", -- 0000050C - X"00000000", -- 00000510 - X"00000000", -- 00000514 - X"00000000", -- 00000518 - X"00000000", -- 0000051C - X"00000000", -- 00000520 - X"00000000", -- 00000524 - X"00000000", -- 00000528 - X"00000000", -- 0000052C - X"00000000", -- 00000530 - X"00000000", -- 00000534 - X"00000000", -- 00000538 - X"00000000", -- 0000053C - X"00000000", -- 00000540 - X"00000000", -- 00000544 - X"00000000", -- 00000548 - X"00000000", -- 0000054C - X"00000000", -- 00000550 - X"00000000", -- 00000554 - X"00000000", -- 00000558 - X"00000000", -- 0000055C - X"00000000", -- 00000560 - X"00000000", -- 00000564 - X"00000000", -- 00000568 - X"00000000", -- 0000056C - X"00000000", -- 00000570 - X"00000000", -- 00000574 - X"00000000", -- 00000578 - X"00000000", -- 0000057C - X"00000000", -- 00000580 - X"00000000", -- 00000584 - X"00000000", -- 00000588 - X"00000000", -- 0000058C - X"00000000", -- 00000590 - X"00000000", -- 00000594 - X"00000000", -- 00000598 - X"00000000", -- 0000059C - X"00000000", -- 000005A0 - X"00000000", -- 000005A4 - X"00000000", -- 000005A8 - X"00000000", -- 000005AC - X"00000000", -- 000005B0 - X"00000000", -- 000005B4 - X"00000000", -- 000005B8 - X"00000000", -- 000005BC - X"00000000", -- 000005C0 - X"00000000", -- 000005C4 - X"00000000", -- 000005C8 - X"00000000", -- 000005CC - X"00000000", -- 000005D0 - X"00000000", -- 000005D4 - X"00000000", -- 000005D8 - X"00000000", -- 000005DC - X"00000000", -- 000005E0 - X"00000000", -- 000005E4 - X"00000000", -- 000005E8 - X"00000000", -- 000005EC - X"00000000", -- 000005F0 - X"00000000", -- 000005F4 - X"00000000", -- 000005F8 - X"00000000", -- 000005FC - X"00000000", -- 00000600 - X"00000000", -- 00000604 - X"00000000", -- 00000608 - X"00000000", -- 0000060C - X"00000000", -- 00000610 - X"00000000", -- 00000614 - X"00000000", -- 00000618 - X"00000000", -- 0000061C - X"00000000", -- 00000620 - X"00000000", -- 00000624 - X"00000000", -- 00000628 - X"00000000", -- 0000062C - X"00000000", -- 00000630 - X"00000000", -- 00000634 - X"00000000", -- 00000638 - X"00000000", -- 0000063C - X"00000000", -- 00000640 - X"00000000", -- 00000644 - X"00000000", -- 00000648 - X"00000000", -- 0000064C - X"00000000", -- 00000650 - X"00000000", -- 00000654 - X"00000000", -- 00000658 - X"00000000", -- 0000065C - X"00000000", -- 00000660 - X"00000000", -- 00000664 - X"00000000", -- 00000668 - X"00000000", -- 0000066C - X"00000000", -- 00000670 - X"00000000", -- 00000674 - X"00000000", -- 00000678 - X"00000000", -- 0000067C - X"00000000", -- 00000680 - X"00000000", -- 00000684 - X"00000000", -- 00000688 - X"00000000", -- 0000068C - X"00000000", -- 00000690 - X"00000000", -- 00000694 - X"00000000", -- 00000698 - X"00000000", -- 0000069C - X"00000000", -- 000006A0 - X"00000000", -- 000006A4 - X"00000000", -- 000006A8 - X"00000000", -- 000006AC - X"00000000", -- 000006B0 - X"00000000", -- 000006B4 - X"00000000", -- 000006B8 - X"00000000", -- 000006BC - X"00000000", -- 000006C0 - X"00000000", -- 000006C4 - X"00000000", -- 000006C8 - X"00000000", -- 000006CC - X"00000000", -- 000006D0 - X"00000000", -- 000006D4 - X"00000000", -- 000006D8 - X"00000000", -- 000006DC - X"00000000", -- 000006E0 - X"00000000", -- 000006E4 - X"00000000", -- 000006E8 - X"00000000", -- 000006EC - X"00000000", -- 000006F0 - X"00000000", -- 000006F4 - X"00000000", -- 000006F8 - X"00000000", -- 000006FC - X"00000000", -- 00000700 - X"00000000", -- 00000704 - X"00000000", -- 00000708 - X"00000000", -- 0000070C - X"00000000", -- 00000710 - X"00000000", -- 00000714 - X"00000000", -- 00000718 - X"00000000", -- 0000071C - X"00000000", -- 00000720 - X"00000000", -- 00000724 - X"00000000", -- 00000728 - X"00000000", -- 0000072C - X"00000000", -- 00000730 - X"00000000", -- 00000734 - X"00000000", -- 00000738 - X"00000000", -- 0000073C - X"00000000", -- 00000740 - X"00000000", -- 00000744 - X"00000000", -- 00000748 - X"00000000", -- 0000074C - X"00000000", -- 00000750 - X"00000000", -- 00000754 - X"00000000", -- 00000758 - X"00000000", -- 0000075C - X"00000000", -- 00000760 - X"00000000", -- 00000764 - X"00000000", -- 00000768 - X"00000000", -- 0000076C - X"00000000", -- 00000770 - X"00000000", -- 00000774 - X"00000000", -- 00000778 - X"00000000", -- 0000077C - X"00000000", -- 00000780 - X"00000000", -- 00000784 - X"00000000", -- 00000788 - X"00000000", -- 0000078C - X"00000000", -- 00000790 - X"00000000", -- 00000794 - X"00000000", -- 00000798 - X"00000000", -- 0000079C - X"00000000", -- 000007A0 - X"00000000", -- 000007A4 - X"00000000", -- 000007A8 - X"00000000", -- 000007AC - X"00000000", -- 000007B0 - X"00000000", -- 000007B4 - X"00000000", -- 000007B8 - X"00000000", -- 000007BC - X"00000000", -- 000007C0 - X"00000000", -- 000007C4 - X"00000000", -- 000007C8 - X"00000000", -- 000007CC - X"00000000", -- 000007D0 - X"00000000", -- 000007D4 - X"00000000", -- 000007D8 - X"00000000", -- 000007DC - X"00000000", -- 000007E0 - X"00000000", -- 000007E4 - X"00000000", -- 000007E8 - X"00000000", -- 000007EC - X"00000000", -- 000007F0 - X"00000000", -- 000007F4 - X"00000000", -- 000007F8 - X"00000000", -- 000007FC - X"00000000", -- 00000800 - X"00000000", -- 00000804 - X"00000000", -- 00000808 - X"00000000", -- 0000080C - X"00000000", -- 00000810 - X"00000000", -- 00000814 - X"00000000", -- 00000818 - X"00000000", -- 0000081C - X"00000000", -- 00000820 - X"00000000", -- 00000824 - X"00000000", -- 00000828 - X"00000000", -- 0000082C - X"00000000", -- 00000830 - X"00000000", -- 00000834 - X"00000000", -- 00000838 - X"00000000", -- 0000083C - X"00000000", -- 00000840 - X"00000000", -- 00000844 - X"00000000", -- 00000848 - X"00000000", -- 0000084C - X"00000000", -- 00000850 - X"00000000", -- 00000854 - X"00000000", -- 00000858 - X"00000000", -- 0000085C - X"00000000", -- 00000860 - X"00000000", -- 00000864 - X"00000000", -- 00000868 - X"00000000", -- 0000086C - X"00000000", -- 00000870 - X"00000000", -- 00000874 - X"00000000", -- 00000878 - X"00000000", -- 0000087C - X"00000000", -- 00000880 - X"00000000", -- 00000884 - X"00000000", -- 00000888 - X"00000000", -- 0000088C - X"00000000", -- 00000890 - X"00000000", -- 00000894 - X"00000000", -- 00000898 - X"00000000", -- 0000089C - X"00000000", -- 000008A0 - X"00000000", -- 000008A4 - X"00000000", -- 000008A8 - X"00000000", -- 000008AC - X"00000000", -- 000008B0 - X"00000000", -- 000008B4 - X"00000000", -- 000008B8 - X"00000000", -- 000008BC - X"00000000", -- 000008C0 - X"00000000", -- 000008C4 - X"00000000", -- 000008C8 - X"00000000", -- 000008CC - X"00000000", -- 000008D0 - X"00000000", -- 000008D4 - X"00000000", -- 000008D8 - X"00000000", -- 000008DC - X"00000000", -- 000008E0 - X"00000000", -- 000008E4 - X"00000000", -- 000008E8 - X"00000000", -- 000008EC - X"00000000", -- 000008F0 - X"00000000", -- 000008F4 - X"00000000", -- 000008F8 - X"00000000", -- 000008FC - X"00000000", -- 00000900 - X"00000000", -- 00000904 - X"00000000", -- 00000908 - X"00000000", -- 0000090C - X"00000000", -- 00000910 - X"00000000", -- 00000914 - X"00000000", -- 00000918 - X"00000000", -- 0000091C - X"00000000", -- 00000920 - X"00000000", -- 00000924 - X"00000000", -- 00000928 - X"00000000", -- 0000092C - X"00000000", -- 00000930 - X"00000000", -- 00000934 - X"00000000", -- 00000938 - X"00000000", -- 0000093C - X"00000000", -- 00000940 - X"00000000", -- 00000944 - X"00000000", -- 00000948 - X"00000000", -- 0000094C - X"00000000", -- 00000950 - X"00000000", -- 00000954 - X"00000000", -- 00000958 - X"00000000", -- 0000095C - X"00000000", -- 00000960 - X"00000000", -- 00000964 - X"00000000", -- 00000968 - X"00000000", -- 0000096C - X"00000000", -- 00000970 - X"00000000", -- 00000974 - X"00000000", -- 00000978 - X"00000000", -- 0000097C - X"00000000", -- 00000980 - X"00000000", -- 00000984 - X"00000000", -- 00000988 - X"00000000", -- 0000098C - X"00000000", -- 00000990 - X"00000000", -- 00000994 - X"00000000", -- 00000998 - X"00000000", -- 0000099C - X"00000000", -- 000009A0 - X"00000000", -- 000009A4 - X"00000000", -- 000009A8 - X"00000000", -- 000009AC - X"00000000", -- 000009B0 - X"00000000", -- 000009B4 - X"00000000", -- 000009B8 - X"00000000", -- 000009BC - X"00000000", -- 000009C0 - X"00000000", -- 000009C4 - X"00000000", -- 000009C8 - X"00000000", -- 000009CC - X"00000000", -- 000009D0 - X"00000000", -- 000009D4 - X"00000000", -- 000009D8 - X"00000000", -- 000009DC - X"00000000", -- 000009E0 - X"00000000", -- 000009E4 - X"00000000", -- 000009E8 - X"00000000", -- 000009EC - X"00000000", -- 000009F0 - X"00000000", -- 000009F4 - X"00000000", -- 000009F8 - X"00000000", -- 000009FC - X"00000000", -- 00000A00 - X"00000000", -- 00000A04 - X"00000000", -- 00000A08 - X"00000000", -- 00000A0C - X"00000000", -- 00000A10 - X"00000000", -- 00000A14 - X"00000000", -- 00000A18 - X"00000000", -- 00000A1C - X"00000000", -- 00000A20 - X"00000000", -- 00000A24 - X"00000000", -- 00000A28 - X"00000000", -- 00000A2C - X"00000000", -- 00000A30 - X"00000000", -- 00000A34 - X"00000000", -- 00000A38 - X"00000000", -- 00000A3C - X"00000000", -- 00000A40 - X"00000000", -- 00000A44 - X"00000000", -- 00000A48 - X"00000000", -- 00000A4C - X"00000000", -- 00000A50 - X"00000000", -- 00000A54 - X"00000000", -- 00000A58 - X"00000000", -- 00000A5C - X"00000000", -- 00000A60 - X"00000000", -- 00000A64 - X"00000000", -- 00000A68 - X"00000000", -- 00000A6C - X"00000000", -- 00000A70 - X"00000000", -- 00000A74 - X"00000000", -- 00000A78 - X"00000000", -- 00000A7C - X"00000000", -- 00000A80 - X"00000000", -- 00000A84 - X"00000000", -- 00000A88 - X"00000000", -- 00000A8C - X"00000000", -- 00000A90 - X"00000000", -- 00000A94 - X"00000000", -- 00000A98 - X"00000000", -- 00000A9C - X"00000000", -- 00000AA0 - X"00000000", -- 00000AA4 - X"00000000", -- 00000AA8 - X"00000000", -- 00000AAC - X"00000000", -- 00000AB0 - X"00000000", -- 00000AB4 - X"00000000", -- 00000AB8 - X"00000000", -- 00000ABC - X"00000000", -- 00000AC0 - X"00000000", -- 00000AC4 - X"00000000", -- 00000AC8 - X"00000000", -- 00000ACC - X"00000000", -- 00000AD0 - X"00000000", -- 00000AD4 - X"00000000", -- 00000AD8 - X"00000000", -- 00000ADC - X"00000000", -- 00000AE0 - X"00000000", -- 00000AE4 - X"00000000", -- 00000AE8 - X"00000000", -- 00000AEC - X"00000000", -- 00000AF0 - X"00000000", -- 00000AF4 - X"00000000", -- 00000AF8 - X"00000000", -- 00000AFC - X"00000000", -- 00000B00 - X"00000000", -- 00000B04 - X"00000000", -- 00000B08 - X"00000000", -- 00000B0C - X"00000000", -- 00000B10 - X"00000000", -- 00000B14 - X"00000000", -- 00000B18 - X"00000000", -- 00000B1C - X"00000000", -- 00000B20 - X"00000000", -- 00000B24 - X"00000000", -- 00000B28 - X"00000000", -- 00000B2C - X"00000000", -- 00000B30 - X"00000000", -- 00000B34 - X"00000000", -- 00000B38 - X"00000000", -- 00000B3C - X"00000000", -- 00000B40 - X"00000000", -- 00000B44 - X"00000000", -- 00000B48 - X"00000000", -- 00000B4C - X"00000000", -- 00000B50 - X"00000000", -- 00000B54 - X"00000000", -- 00000B58 - X"00000000", -- 00000B5C - X"00000000", -- 00000B60 - X"00000000", -- 00000B64 - X"00000000", -- 00000B68 - X"00000000", -- 00000B6C - X"00000000", -- 00000B70 - X"00000000", -- 00000B74 - X"00000000", -- 00000B78 - X"00000000", -- 00000B7C - X"00000000", -- 00000B80 - X"00000000", -- 00000B84 - X"00000000", -- 00000B88 - X"00000000", -- 00000B8C - X"00000000", -- 00000B90 - X"00000000", -- 00000B94 - X"00000000", -- 00000B98 - X"00000000", -- 00000B9C - X"00000000", -- 00000BA0 - X"00000000", -- 00000BA4 - X"00000000", -- 00000BA8 - X"00000000", -- 00000BAC - X"00000000", -- 00000BB0 - X"00000000", -- 00000BB4 - X"00000000", -- 00000BB8 - X"00000000", -- 00000BBC - X"00000000", -- 00000BC0 - X"00000000", -- 00000BC4 - X"00000000", -- 00000BC8 - X"00000000", -- 00000BCC - X"00000000", -- 00000BD0 - X"00000000", -- 00000BD4 - X"00000000", -- 00000BD8 - X"00000000", -- 00000BDC - X"00000000", -- 00000BE0 - X"00000000", -- 00000BE4 - X"00000000", -- 00000BE8 - X"00000000", -- 00000BEC - X"00000000", -- 00000BF0 - X"00000000", -- 00000BF4 - X"00000000", -- 00000BF8 - X"00000000", -- 00000BFC - X"00000000", -- 00000C00 - X"00000000", -- 00000C04 - X"00000000", -- 00000C08 - X"00000000", -- 00000C0C - X"00000000", -- 00000C10 - X"00000000", -- 00000C14 - X"00000000", -- 00000C18 - X"00000000", -- 00000C1C - X"00000000", -- 00000C20 - X"00000000", -- 00000C24 - X"00000000", -- 00000C28 - X"00000000", -- 00000C2C - X"00000000", -- 00000C30 - X"00000000", -- 00000C34 - X"00000000", -- 00000C38 - X"00000000", -- 00000C3C - X"00000000", -- 00000C40 - X"00000000", -- 00000C44 - X"00000000", -- 00000C48 - X"00000000", -- 00000C4C - X"00000000", -- 00000C50 - X"00000000", -- 00000C54 - X"00000000", -- 00000C58 - X"00000000", -- 00000C5C - X"00000000", -- 00000C60 - X"00000000", -- 00000C64 - X"00000000", -- 00000C68 - X"00000000", -- 00000C6C - X"00000000", -- 00000C70 - X"00000000", -- 00000C74 - X"00000000", -- 00000C78 - X"00000000", -- 00000C7C - X"00000000", -- 00000C80 - X"00000000", -- 00000C84 - X"00000000", -- 00000C88 - X"00000000", -- 00000C8C - X"00000000", -- 00000C90 - X"00000000", -- 00000C94 - X"00000000", -- 00000C98 - X"00000000", -- 00000C9C - X"00000000", -- 00000CA0 - X"00000000", -- 00000CA4 - X"00000000", -- 00000CA8 - X"00000000", -- 00000CAC - X"00000000", -- 00000CB0 - X"00000000", -- 00000CB4 - X"00000000", -- 00000CB8 - X"00000000", -- 00000CBC - X"00000000", -- 00000CC0 - X"00000000", -- 00000CC4 - X"00000000", -- 00000CC8 - X"00000000", -- 00000CCC - X"00000000", -- 00000CD0 - X"00000000", -- 00000CD4 - X"00000000", -- 00000CD8 - X"00000000", -- 00000CDC - X"00000000", -- 00000CE0 - X"00000000", -- 00000CE4 - X"00000000", -- 00000CE8 - X"00000000", -- 00000CEC - X"00000000", -- 00000CF0 - X"00000000", -- 00000CF4 - X"00000000", -- 00000CF8 - X"00000000", -- 00000CFC - X"00000000", -- 00000D00 - X"00000000", -- 00000D04 - X"00000000", -- 00000D08 - X"00000000", -- 00000D0C - X"00000000", -- 00000D10 - X"00000000", -- 00000D14 - X"00000000", -- 00000D18 - X"00000000", -- 00000D1C - X"00000000", -- 00000D20 - X"00000000", -- 00000D24 - X"00000000", -- 00000D28 - X"00000000", -- 00000D2C - X"00000000", -- 00000D30 - X"00000000", -- 00000D34 - X"00000000", -- 00000D38 - X"00000000", -- 00000D3C - X"00000000", -- 00000D40 - X"00000000", -- 00000D44 - X"00000000", -- 00000D48 - X"00000000", -- 00000D4C - X"00000000", -- 00000D50 - X"00000000", -- 00000D54 - X"00000000", -- 00000D58 - X"00000000", -- 00000D5C - X"00000000", -- 00000D60 - X"00000000", -- 00000D64 - X"00000000", -- 00000D68 - X"00000000", -- 00000D6C - X"00000000", -- 00000D70 - X"00000000", -- 00000D74 - X"00000000", -- 00000D78 - X"00000000", -- 00000D7C - X"00000000", -- 00000D80 - X"00000000", -- 00000D84 - X"00000000", -- 00000D88 - X"00000000", -- 00000D8C - X"00000000", -- 00000D90 - X"00000000", -- 00000D94 - X"00000000", -- 00000D98 - X"00000000", -- 00000D9C - X"00000000", -- 00000DA0 - X"00000000", -- 00000DA4 - X"00000000", -- 00000DA8 - X"00000000", -- 00000DAC - X"00000000", -- 00000DB0 - X"00000000", -- 00000DB4 - X"00000000", -- 00000DB8 - X"00000000", -- 00000DBC - X"00000000", -- 00000DC0 - X"00000000", -- 00000DC4 - X"00000000", -- 00000DC8 - X"00000000", -- 00000DCC - X"00000000", -- 00000DD0 - X"00000000", -- 00000DD4 - X"00000000", -- 00000DD8 - X"00000000", -- 00000DDC - X"00000000", -- 00000DE0 - X"00000000", -- 00000DE4 - X"00000000", -- 00000DE8 - X"00000000", -- 00000DEC - X"00000000", -- 00000DF0 - X"00000000", -- 00000DF4 - X"00000000", -- 00000DF8 - X"00000000", -- 00000DFC - X"00000000", -- 00000E00 - X"00000000", -- 00000E04 - X"00000000", -- 00000E08 - X"00000000", -- 00000E0C - X"00000000", -- 00000E10 - X"00000000", -- 00000E14 - X"00000000", -- 00000E18 - X"00000000", -- 00000E1C - X"00000000", -- 00000E20 - X"00000000", -- 00000E24 - X"00000000", -- 00000E28 - X"00000000", -- 00000E2C - X"00000000", -- 00000E30 - X"00000000", -- 00000E34 - X"00000000", -- 00000E38 - X"00000000", -- 00000E3C - X"00000000", -- 00000E40 - X"00000000", -- 00000E44 - X"00000000", -- 00000E48 - X"00000000", -- 00000E4C - X"00000000", -- 00000E50 - X"00000000", -- 00000E54 - X"00000000", -- 00000E58 - X"00000000", -- 00000E5C - X"00000000", -- 00000E60 - X"00000000", -- 00000E64 - X"00000000", -- 00000E68 - X"00000000", -- 00000E6C - X"00000000", -- 00000E70 - X"00000000", -- 00000E74 - X"00000000", -- 00000E78 - X"00000000", -- 00000E7C - X"00000000", -- 00000E80 - X"00000000", -- 00000E84 - X"00000000", -- 00000E88 - X"00000000", -- 00000E8C - X"00000000", -- 00000E90 - X"00000000", -- 00000E94 - X"00000000", -- 00000E98 - X"00000000", -- 00000E9C - X"00000000", -- 00000EA0 - X"00000000", -- 00000EA4 - X"00000000", -- 00000EA8 - X"00000000", -- 00000EAC - X"00000000", -- 00000EB0 - X"00000000", -- 00000EB4 - X"00000000", -- 00000EB8 - X"00000000", -- 00000EBC - X"00000000", -- 00000EC0 - X"00000000", -- 00000EC4 - X"00000000", -- 00000EC8 - X"00000000", -- 00000ECC - X"00000000", -- 00000ED0 - X"00000000", -- 00000ED4 - X"00000000", -- 00000ED8 - X"00000000", -- 00000EDC - X"00000000", -- 00000EE0 - X"00000000", -- 00000EE4 - X"00000000", -- 00000EE8 - X"00000000", -- 00000EEC - X"00000000", -- 00000EF0 - X"00000000", -- 00000EF4 - X"00000000", -- 00000EF8 - X"00000000", -- 00000EFC - X"00000000", -- 00000F00 - X"00000000", -- 00000F04 - X"00000000", -- 00000F08 - X"00000000", -- 00000F0C - X"00000000", -- 00000F10 - X"00000000", -- 00000F14 - X"00000000", -- 00000F18 - X"00000000", -- 00000F1C - X"00000000", -- 00000F20 - X"00000000", -- 00000F24 - X"00000000", -- 00000F28 - X"00000000", -- 00000F2C - X"00000000", -- 00000F30 - X"00000000", -- 00000F34 - X"00000000", -- 00000F38 - X"00000000", -- 00000F3C - X"00000000", -- 00000F40 - X"00000000", -- 00000F44 - X"00000000", -- 00000F48 - X"00000000", -- 00000F4C - X"00000000", -- 00000F50 - X"00000000", -- 00000F54 - X"00000000", -- 00000F58 - X"00000000", -- 00000F5C - X"00000000", -- 00000F60 - X"00000000", -- 00000F64 - X"00000000", -- 00000F68 - X"00000000", -- 00000F6C - X"00000000", -- 00000F70 - X"00000000", -- 00000F74 - X"00000000", -- 00000F78 - X"00000000", -- 00000F7C - X"00000000", -- 00000F80 - X"00000000", -- 00000F84 - X"00000000", -- 00000F88 - X"00000000", -- 00000F8C - X"00000000", -- 00000F90 - X"00000000", -- 00000F94 - X"00000000", -- 00000F98 - X"00000000", -- 00000F9C - X"00000000", -- 00000FA0 - X"00000000", -- 00000FA4 - X"00000000", -- 00000FA8 - X"00000000", -- 00000FAC - X"00000000", -- 00000FB0 - X"00000000", -- 00000FB4 - X"00000000", -- 00000FB8 - X"00000000", -- 00000FBC - X"00000000", -- 00000FC0 - X"00000000", -- 00000FC4 - X"00000000", -- 00000FC8 - X"00000000", -- 00000FCC - X"00000000", -- 00000FD0 - X"00000000", -- 00000FD4 - X"00000000", -- 00000FD8 - X"00000000", -- 00000FDC - X"00000000", -- 00000FE0 - X"00000000", -- 00000FE4 - X"00000000", -- 00000FE8 - X"00000000", -- 00000FEC - X"00000000", -- 00000FF0 - X"00000000", -- 00000FF4 - X"00000000", -- 00000FF8 - X"00000000", -- 00000FFC - X"00000000", -- 00001000 - X"00000000", -- 00001004 - X"00000000", -- 00001008 - X"00000000", -- 0000100C - X"00000000", -- 00001010 - X"00000000", -- 00001014 - X"00000000", -- 00001018 - X"00000000", -- 0000101C - X"00000000", -- 00001020 - X"00000000", -- 00001024 - X"00000000", -- 00001028 - X"00000000", -- 0000102C - X"00000000", -- 00001030 - X"00000000", -- 00001034 - X"00000000", -- 00001038 - X"00000000", -- 0000103C - X"00000000", -- 00001040 - X"00000000", -- 00001044 - X"00000000", -- 00001048 - X"00000000", -- 0000104C - X"00000000", -- 00001050 - X"00000000", -- 00001054 - X"00000000", -- 00001058 - X"00000000", -- 0000105C - X"00000000", -- 00001060 - X"00000000", -- 00001064 - X"00000000", -- 00001068 - X"00000000", -- 0000106C - X"00000000", -- 00001070 - X"00000000", -- 00001074 - X"00000000", -- 00001078 - X"00000000", -- 0000107C - X"00000000", -- 00001080 - X"00000000", -- 00001084 - X"00000000", -- 00001088 - X"00000000", -- 0000108C - X"00000000", -- 00001090 - X"00000000", -- 00001094 - X"00000000", -- 00001098 - X"00000000", -- 0000109C - X"00000000", -- 000010A0 - X"00000000", -- 000010A4 - X"00000000", -- 000010A8 - X"00000000", -- 000010AC - X"00000000", -- 000010B0 - X"00000000", -- 000010B4 - X"00000000", -- 000010B8 - X"00000000", -- 000010BC - X"00000000", -- 000010C0 - X"00000000", -- 000010C4 - X"00000000", -- 000010C8 - X"00000000", -- 000010CC - X"00000000", -- 000010D0 - X"00000000", -- 000010D4 - X"00000000", -- 000010D8 - X"00000000", -- 000010DC - X"00000000", -- 000010E0 - X"00000000", -- 000010E4 - X"00000000", -- 000010E8 - X"00000000", -- 000010EC - X"00000000", -- 000010F0 - X"00000000", -- 000010F4 - X"00000000", -- 000010F8 - X"00000000", -- 000010FC - X"00000000", -- 00001100 - X"00000000", -- 00001104 - X"00000000", -- 00001108 - X"00000000", -- 0000110C - X"00000000", -- 00001110 - X"00000000", -- 00001114 - X"00000000", -- 00001118 - X"00000000", -- 0000111C - X"00000000", -- 00001120 - X"00000000", -- 00001124 - X"00000000", -- 00001128 - X"00000000", -- 0000112C - X"00000000", -- 00001130 - X"00000000", -- 00001134 - X"00000000", -- 00001138 - X"00000000", -- 0000113C - X"00000000", -- 00001140 - X"00000000", -- 00001144 - X"00000000", -- 00001148 - X"00000000", -- 0000114C - X"00000000", -- 00001150 - X"00000000", -- 00001154 - X"00000000", -- 00001158 - X"00000000", -- 0000115C - X"00000000", -- 00001160 - X"00000000", -- 00001164 - X"00000000", -- 00001168 - X"00000000", -- 0000116C - X"00000000", -- 00001170 - X"00000000", -- 00001174 - X"00000000", -- 00001178 - X"00000000", -- 0000117C - X"00000000", -- 00001180 - X"00000000", -- 00001184 - X"00000000", -- 00001188 - X"00000000", -- 0000118C - X"00000000", -- 00001190 - X"00000000", -- 00001194 - X"00000000", -- 00001198 - X"00000000", -- 0000119C - X"00000000", -- 000011A0 - X"00000000", -- 000011A4 - X"00000000", -- 000011A8 - X"00000000", -- 000011AC - X"00000000", -- 000011B0 - X"00000000", -- 000011B4 - X"00000000", -- 000011B8 - X"00000000", -- 000011BC - X"00000000", -- 000011C0 - X"00000000", -- 000011C4 - X"00000000", -- 000011C8 - X"00000000", -- 000011CC - X"00000000", -- 000011D0 - X"00000000", -- 000011D4 - X"00000000", -- 000011D8 - X"00000000", -- 000011DC - X"00000000", -- 000011E0 - X"00000000", -- 000011E4 - X"00000000", -- 000011E8 - X"00000000", -- 000011EC - X"00000000", -- 000011F0 - X"00000000", -- 000011F4 - X"00000000", -- 000011F8 - X"00000000", -- 000011FC - X"00000000", -- 00001200 - X"00000000", -- 00001204 - X"00000000", -- 00001208 - X"00000000", -- 0000120C - X"00000000", -- 00001210 - X"00000000", -- 00001214 - X"00000000", -- 00001218 - X"00000000", -- 0000121C - X"00000000", -- 00001220 - X"00000000", -- 00001224 - X"00000000", -- 00001228 - X"00000000", -- 0000122C - X"00000000", -- 00001230 - X"00000000", -- 00001234 - X"00000000", -- 00001238 - X"00000000", -- 0000123C - X"00000000", -- 00001240 - X"00000000", -- 00001244 - X"00000000", -- 00001248 - X"00000000", -- 0000124C - X"00000000", -- 00001250 - X"00000000", -- 00001254 - X"00000000", -- 00001258 - X"00000000", -- 0000125C - X"00000000", -- 00001260 - X"00000000", -- 00001264 - X"00000000", -- 00001268 - X"00000000", -- 0000126C - X"00000000", -- 00001270 - X"00000000", -- 00001274 - X"00000000", -- 00001278 - X"00000000", -- 0000127C - X"00000000", -- 00001280 - X"00000000", -- 00001284 - X"00000000", -- 00001288 - X"00000000", -- 0000128C - X"00000000", -- 00001290 - X"00000000", -- 00001294 - X"00000000", -- 00001298 - X"00000000", -- 0000129C - X"00000000", -- 000012A0 - X"00000000", -- 000012A4 - X"00000000", -- 000012A8 - X"00000000", -- 000012AC - X"00000000", -- 000012B0 - X"00000000", -- 000012B4 - X"00000000", -- 000012B8 - X"00000000", -- 000012BC - X"00000000", -- 000012C0 - X"00000000", -- 000012C4 - X"00000000", -- 000012C8 - X"00000000", -- 000012CC - X"00000000", -- 000012D0 - X"00000000", -- 000012D4 - X"00000000", -- 000012D8 - X"00000000", -- 000012DC - X"00000000", -- 000012E0 - X"00000000", -- 000012E4 - X"00000000", -- 000012E8 - X"00000000", -- 000012EC - X"00000000", -- 000012F0 - X"00000000", -- 000012F4 - X"00000000", -- 000012F8 - X"00000000", -- 000012FC - X"00000000", -- 00001300 - X"00000000", -- 00001304 - X"00000000", -- 00001308 - X"00000000", -- 0000130C - X"00000000", -- 00001310 - X"00000000", -- 00001314 - X"00000000", -- 00001318 - X"00000000", -- 0000131C - X"00000000", -- 00001320 - X"00000000", -- 00001324 - X"00000000", -- 00001328 - X"00000000", -- 0000132C - X"00000000", -- 00001330 - X"00000000", -- 00001334 - X"00000000", -- 00001338 - X"00000000", -- 0000133C - X"00000000", -- 00001340 - X"00000000", -- 00001344 - X"00000000", -- 00001348 - X"00000000", -- 0000134C - X"00000000", -- 00001350 - X"00000000", -- 00001354 - X"00000000", -- 00001358 - X"00000000", -- 0000135C - X"00000000", -- 00001360 - X"00000000", -- 00001364 - X"00000000", -- 00001368 - X"00000000", -- 0000136C - X"00000000", -- 00001370 - X"00000000", -- 00001374 - X"00000000", -- 00001378 - X"00000000", -- 0000137C - X"00000000", -- 00001380 - X"00000000", -- 00001384 - X"00000000", -- 00001388 - X"00000000", -- 0000138C - X"00000000", -- 00001390 - X"00000000", -- 00001394 - X"00000000", -- 00001398 - X"00000000", -- 0000139C - X"00000000", -- 000013A0 - X"00000000", -- 000013A4 - X"00000000", -- 000013A8 - X"00000000", -- 000013AC - X"00000000", -- 000013B0 - X"00000000", -- 000013B4 - X"00000000", -- 000013B8 - X"00000000", -- 000013BC - X"00000000", -- 000013C0 - X"00000000", -- 000013C4 - X"00000000", -- 000013C8 - X"00000000", -- 000013CC - X"00000000", -- 000013D0 - X"00000000", -- 000013D4 - X"00000000", -- 000013D8 - X"00000000", -- 000013DC - X"00000000", -- 000013E0 - X"00000000", -- 000013E4 - X"00000000", -- 000013E8 - X"00000000", -- 000013EC - X"00000000", -- 000013F0 - X"00000000", -- 000013F4 - X"00000000", -- 000013F8 - X"00000000", -- 000013FC - X"00000000", -- 00001400 - X"00000000", -- 00001404 - X"00000000", -- 00001408 - X"00000000", -- 0000140C - X"00000000", -- 00001410 - X"00000000", -- 00001414 - X"00000000", -- 00001418 - X"00000000", -- 0000141C - X"00000000", -- 00001420 - X"00000000", -- 00001424 - X"00000000", -- 00001428 - X"00000000", -- 0000142C - X"00000000", -- 00001430 - X"00000000", -- 00001434 - X"00000000", -- 00001438 - X"00000000", -- 0000143C - X"00000000", -- 00001440 - X"00000000", -- 00001444 - X"00000000", -- 00001448 - X"00000000", -- 0000144C - X"00000000", -- 00001450 - X"00000000", -- 00001454 - X"00000000", -- 00001458 - X"00000000", -- 0000145C - X"00000000", -- 00001460 - X"00000000", -- 00001464 - X"00000000", -- 00001468 - X"00000000", -- 0000146C - X"00000000", -- 00001470 - X"00000000", -- 00001474 - X"00000000", -- 00001478 - X"00000000", -- 0000147C - X"00000000", -- 00001480 - X"00000000", -- 00001484 - X"00000000", -- 00001488 - X"00000000", -- 0000148C - X"00000000", -- 00001490 - X"00000000", -- 00001494 - X"00000000", -- 00001498 - X"00000000", -- 0000149C - X"00000000", -- 000014A0 - X"00000000", -- 000014A4 - X"00000000", -- 000014A8 - X"00000000", -- 000014AC - X"00000000", -- 000014B0 - X"00000000", -- 000014B4 - X"00000000", -- 000014B8 - X"00000000", -- 000014BC - X"00000000", -- 000014C0 - X"00000000", -- 000014C4 - X"00000000", -- 000014C8 - X"00000000", -- 000014CC - X"00000000", -- 000014D0 - X"00000000", -- 000014D4 - X"00000000", -- 000014D8 - X"00000000", -- 000014DC - X"00000000", -- 000014E0 - X"00000000", -- 000014E4 - X"00000000", -- 000014E8 - X"00000000", -- 000014EC - X"00000000", -- 000014F0 - X"00000000", -- 000014F4 - X"00000000", -- 000014F8 - X"00000000", -- 000014FC - X"00000000", -- 00001500 - X"00000000", -- 00001504 - X"00000000", -- 00001508 - X"00000000", -- 0000150C - X"00000000", -- 00001510 - X"00000000", -- 00001514 - X"00000000", -- 00001518 - X"00000000", -- 0000151C - X"00000000", -- 00001520 - X"00000000", -- 00001524 - X"00000000", -- 00001528 - X"00000000", -- 0000152C - X"00000000", -- 00001530 - X"00000000", -- 00001534 - X"00000000", -- 00001538 - X"00000000", -- 0000153C - X"00000000", -- 00001540 - X"00000000", -- 00001544 - X"00000000", -- 00001548 - X"00000000", -- 0000154C - X"00000000", -- 00001550 - X"00000000", -- 00001554 - X"00000000", -- 00001558 - X"00000000", -- 0000155C - X"00000000", -- 00001560 - X"00000000", -- 00001564 - X"00000000", -- 00001568 - X"00000000", -- 0000156C - X"00000000", -- 00001570 - X"00000000", -- 00001574 - X"00000000", -- 00001578 - X"00000000", -- 0000157C - X"00000000", -- 00001580 - X"00000000", -- 00001584 - X"00000000", -- 00001588 - X"00000000", -- 0000158C - X"00000000", -- 00001590 - X"00000000", -- 00001594 - X"00000000", -- 00001598 - X"00000000", -- 0000159C - X"00000000", -- 000015A0 - X"00000000", -- 000015A4 - X"00000000", -- 000015A8 - X"00000000", -- 000015AC - X"00000000", -- 000015B0 - X"00000000", -- 000015B4 - X"00000000", -- 000015B8 - X"00000000", -- 000015BC - X"00000000", -- 000015C0 - X"00000000", -- 000015C4 - X"00000000", -- 000015C8 - X"00000000", -- 000015CC - X"00000000", -- 000015D0 - X"00000000", -- 000015D4 - X"00000000", -- 000015D8 - X"00000000", -- 000015DC - X"00000000", -- 000015E0 - X"00000000", -- 000015E4 - X"00000000", -- 000015E8 - X"00000000", -- 000015EC - X"00000000", -- 000015F0 - X"00000000", -- 000015F4 - X"00000000", -- 000015F8 - X"00000000", -- 000015FC - X"00000000", -- 00001600 - X"00000000", -- 00001604 - X"00000000", -- 00001608 - X"00000000", -- 0000160C - X"00000000", -- 00001610 - X"00000000", -- 00001614 - X"00000000", -- 00001618 - X"00000000", -- 0000161C - X"00000000", -- 00001620 - X"00000000", -- 00001624 - X"00000000", -- 00001628 - X"00000000", -- 0000162C - X"00000000", -- 00001630 - X"00000000", -- 00001634 - X"00000000", -- 00001638 - X"00000000", -- 0000163C - X"00000000", -- 00001640 - X"00000000", -- 00001644 - X"00000000", -- 00001648 - X"00000000", -- 0000164C - X"00000000", -- 00001650 - X"00000000", -- 00001654 - X"00000000", -- 00001658 - X"00000000", -- 0000165C - X"00000000", -- 00001660 - X"00000000", -- 00001664 - X"00000000", -- 00001668 - X"00000000", -- 0000166C - X"00000000", -- 00001670 - X"00000000", -- 00001674 - X"00000000", -- 00001678 - X"00000000", -- 0000167C - X"00000000", -- 00001680 - X"00000000", -- 00001684 - X"00000000", -- 00001688 - X"00000000", -- 0000168C - X"00000000", -- 00001690 - X"00000000", -- 00001694 - X"00000000", -- 00001698 - X"00000000", -- 0000169C - X"00000000", -- 000016A0 - X"00000000", -- 000016A4 - X"00000000", -- 000016A8 - X"00000000", -- 000016AC - X"00000000", -- 000016B0 - X"00000000", -- 000016B4 - X"00000000", -- 000016B8 - X"00000000", -- 000016BC - X"00000000", -- 000016C0 - X"00000000", -- 000016C4 - X"00000000", -- 000016C8 - X"00000000", -- 000016CC - X"00000000", -- 000016D0 - X"00000000", -- 000016D4 - X"00000000", -- 000016D8 - X"00000000", -- 000016DC - X"00000000", -- 000016E0 - X"00000000", -- 000016E4 - X"00000000", -- 000016E8 - X"00000000", -- 000016EC - X"00000000", -- 000016F0 - X"00000000", -- 000016F4 - X"00000000", -- 000016F8 - X"00000000", -- 000016FC - X"00000000", -- 00001700 - X"00000000", -- 00001704 - X"00000000", -- 00001708 - X"00000000", -- 0000170C - X"00000000", -- 00001710 - X"00000000", -- 00001714 - X"00000000", -- 00001718 - X"00000000", -- 0000171C - X"00000000", -- 00001720 - X"00000000", -- 00001724 - X"00000000", -- 00001728 - X"00000000", -- 0000172C - X"00000000", -- 00001730 - X"00000000", -- 00001734 - X"00000000", -- 00001738 - X"00000000", -- 0000173C - X"00000000", -- 00001740 - X"00000000", -- 00001744 - X"00000000", -- 00001748 - X"00000000", -- 0000174C - X"00000000", -- 00001750 - X"00000000", -- 00001754 - X"00000000", -- 00001758 - X"00000000", -- 0000175C - X"00000000", -- 00001760 - X"00000000", -- 00001764 - X"00000000", -- 00001768 - X"00000000", -- 0000176C - X"00000000", -- 00001770 - X"00000000", -- 00001774 - X"00000000", -- 00001778 - X"00000000", -- 0000177C - X"00000000", -- 00001780 - X"00000000", -- 00001784 - X"00000000", -- 00001788 - X"00000000", -- 0000178C - X"00000000", -- 00001790 - X"00000000", -- 00001794 - X"00000000", -- 00001798 - X"00000000", -- 0000179C - X"00000000", -- 000017A0 - X"00000000", -- 000017A4 - X"00000000", -- 000017A8 - X"00000000", -- 000017AC - X"00000000", -- 000017B0 - X"00000000", -- 000017B4 - X"00000000", -- 000017B8 - X"00000000", -- 000017BC - X"00000000", -- 000017C0 - X"00000000", -- 000017C4 - X"00000000", -- 000017C8 - X"00000000", -- 000017CC - X"00000000", -- 000017D0 - X"00000000", -- 000017D4 - X"00000000", -- 000017D8 - X"00000000", -- 000017DC - X"00000000", -- 000017E0 - X"00000000", -- 000017E4 - X"00000000", -- 000017E8 - X"00000000", -- 000017EC - X"00000000", -- 000017F0 - X"00000000", -- 000017F4 - X"00000000", -- 000017F8 - X"00000000", -- 000017FC - X"00000000", -- 00001800 - X"00000000", -- 00001804 - X"00000000", -- 00001808 - X"00000000", -- 0000180C - X"00000000", -- 00001810 - X"00000000", -- 00001814 - X"00000000", -- 00001818 - X"00000000", -- 0000181C - X"00000000", -- 00001820 - X"00000000", -- 00001824 - X"00000000", -- 00001828 - X"00000000", -- 0000182C - X"00000000", -- 00001830 - X"00000000", -- 00001834 - X"00000000", -- 00001838 - X"00000000", -- 0000183C - X"00000000", -- 00001840 - X"00000000", -- 00001844 - X"00000000", -- 00001848 - X"00000000", -- 0000184C - X"00000000", -- 00001850 - X"00000000", -- 00001854 - X"00000000", -- 00001858 - X"00000000", -- 0000185C - X"00000000", -- 00001860 - X"00000000", -- 00001864 - X"00000000", -- 00001868 - X"00000000", -- 0000186C - X"00000000", -- 00001870 - X"00000000", -- 00001874 - X"00000000", -- 00001878 - X"00000000", -- 0000187C - X"00000000", -- 00001880 - X"00000000", -- 00001884 - X"00000000", -- 00001888 - X"00000000", -- 0000188C - X"00000000", -- 00001890 - X"00000000", -- 00001894 - X"00000000", -- 00001898 - X"00000000", -- 0000189C - X"00000000", -- 000018A0 - X"00000000", -- 000018A4 - X"00000000", -- 000018A8 - X"00000000", -- 000018AC - X"00000000", -- 000018B0 - X"00000000", -- 000018B4 - X"00000000", -- 000018B8 - X"00000000", -- 000018BC - X"00000000", -- 000018C0 - X"00000000", -- 000018C4 - X"00000000", -- 000018C8 - X"00000000", -- 000018CC - X"00000000", -- 000018D0 - X"00000000", -- 000018D4 - X"00000000", -- 000018D8 - X"00000000", -- 000018DC - X"00000000", -- 000018E0 - X"00000000", -- 000018E4 - X"00000000", -- 000018E8 - X"00000000", -- 000018EC - X"00000000", -- 000018F0 - X"00000000", -- 000018F4 - X"00000000", -- 000018F8 - X"00000000", -- 000018FC - X"00000000", -- 00001900 - X"00000000", -- 00001904 - X"00000000", -- 00001908 - X"00000000", -- 0000190C - X"00000000", -- 00001910 - X"00000000", -- 00001914 - X"00000000", -- 00001918 - X"00000000", -- 0000191C - X"00000000", -- 00001920 - X"00000000", -- 00001924 - X"00000000", -- 00001928 - X"00000000", -- 0000192C - X"00000000", -- 00001930 - X"00000000", -- 00001934 - X"00000000", -- 00001938 - X"00000000", -- 0000193C - X"00000000", -- 00001940 - X"00000000", -- 00001944 - X"00000000", -- 00001948 - X"00000000", -- 0000194C - X"00000000", -- 00001950 - X"00000000", -- 00001954 - X"00000000", -- 00001958 - X"00000000", -- 0000195C - X"00000000", -- 00001960 - X"00000000", -- 00001964 - X"00000000", -- 00001968 - X"00000000", -- 0000196C - X"00000000", -- 00001970 - X"00000000", -- 00001974 - X"00000000", -- 00001978 - X"00000000", -- 0000197C - X"00000000", -- 00001980 - X"00000000", -- 00001984 - X"00000000", -- 00001988 - X"00000000", -- 0000198C - X"00000000", -- 00001990 - X"00000000", -- 00001994 - X"00000000", -- 00001998 - X"00000000", -- 0000199C - X"00000000", -- 000019A0 - X"00000000", -- 000019A4 - X"00000000", -- 000019A8 - X"00000000", -- 000019AC - X"00000000", -- 000019B0 - X"00000000", -- 000019B4 - X"00000000", -- 000019B8 - X"00000000", -- 000019BC - X"00000000", -- 000019C0 - X"00000000", -- 000019C4 - X"00000000", -- 000019C8 - X"00000000", -- 000019CC - X"00000000", -- 000019D0 - X"00000000", -- 000019D4 - X"00000000", -- 000019D8 - X"00000000", -- 000019DC - X"00000000", -- 000019E0 - X"00000000", -- 000019E4 - X"00000000", -- 000019E8 - X"00000000", -- 000019EC - X"00000000", -- 000019F0 - X"00000000", -- 000019F4 - X"00000000", -- 000019F8 - X"00000000", -- 000019FC - X"00000000", -- 00001A00 - X"00000000", -- 00001A04 - X"00000000", -- 00001A08 - X"00000000", -- 00001A0C - X"00000000", -- 00001A10 - X"00000000", -- 00001A14 - X"00000000", -- 00001A18 - X"00000000", -- 00001A1C - X"00000000", -- 00001A20 - X"00000000", -- 00001A24 - X"00000000", -- 00001A28 - X"00000000", -- 00001A2C - X"00000000", -- 00001A30 - X"00000000", -- 00001A34 - X"00000000", -- 00001A38 - X"00000000", -- 00001A3C - X"00000000", -- 00001A40 - X"00000000", -- 00001A44 - X"00000000", -- 00001A48 - X"00000000", -- 00001A4C - X"00000000", -- 00001A50 - X"00000000", -- 00001A54 - X"00000000", -- 00001A58 - X"00000000", -- 00001A5C - X"00000000", -- 00001A60 - X"00000000", -- 00001A64 - X"00000000", -- 00001A68 - X"00000000", -- 00001A6C - X"00000000", -- 00001A70 - X"00000000", -- 00001A74 - X"00000000", -- 00001A78 - X"00000000", -- 00001A7C - X"00000000", -- 00001A80 - X"00000000", -- 00001A84 - X"00000000", -- 00001A88 - X"00000000", -- 00001A8C - X"00000000", -- 00001A90 - X"00000000", -- 00001A94 - X"00000000", -- 00001A98 - X"00000000", -- 00001A9C - X"00000000", -- 00001AA0 - X"00000000", -- 00001AA4 - X"00000000", -- 00001AA8 - X"00000000", -- 00001AAC - X"00000000", -- 00001AB0 - X"00000000", -- 00001AB4 - X"00000000", -- 00001AB8 - X"00000000", -- 00001ABC - X"00000000", -- 00001AC0 - X"00000000", -- 00001AC4 - X"00000000", -- 00001AC8 - X"00000000", -- 00001ACC - X"00000000", -- 00001AD0 - X"00000000", -- 00001AD4 - X"00000000", -- 00001AD8 - X"00000000", -- 00001ADC - X"00000000", -- 00001AE0 - X"00000000", -- 00001AE4 - X"00000000", -- 00001AE8 - X"00000000", -- 00001AEC - X"00000000", -- 00001AF0 - X"00000000", -- 00001AF4 - X"00000000", -- 00001AF8 - X"00000000", -- 00001AFC - X"00000000", -- 00001B00 - X"00000000", -- 00001B04 - X"00000000", -- 00001B08 - X"00000000", -- 00001B0C - X"00000000", -- 00001B10 - X"00000000", -- 00001B14 - X"00000000", -- 00001B18 - X"00000000", -- 00001B1C - X"00000000", -- 00001B20 - X"00000000", -- 00001B24 - X"00000000", -- 00001B28 - X"00000000", -- 00001B2C - X"00000000", -- 00001B30 - X"00000000", -- 00001B34 - X"00000000", -- 00001B38 - X"00000000", -- 00001B3C - X"00000000", -- 00001B40 - X"00000000", -- 00001B44 - X"00000000", -- 00001B48 - X"00000000", -- 00001B4C - X"00000000", -- 00001B50 - X"00000000", -- 00001B54 - X"00000000", -- 00001B58 - X"00000000", -- 00001B5C - X"00000000", -- 00001B60 - X"00000000", -- 00001B64 - X"00000000", -- 00001B68 - X"00000000", -- 00001B6C - X"00000000", -- 00001B70 - X"00000000", -- 00001B74 - X"00000000", -- 00001B78 - X"00000000", -- 00001B7C - X"00000000", -- 00001B80 - X"00000000", -- 00001B84 - X"00000000", -- 00001B88 - X"00000000", -- 00001B8C - X"00000000", -- 00001B90 - X"00000000", -- 00001B94 - X"00000000", -- 00001B98 - X"00000000", -- 00001B9C - X"00000000", -- 00001BA0 - X"00000000", -- 00001BA4 - X"00000000", -- 00001BA8 - X"00000000", -- 00001BAC - X"00000000", -- 00001BB0 - X"00000000", -- 00001BB4 - X"00000000", -- 00001BB8 - X"00000000", -- 00001BBC - X"00000000", -- 00001BC0 - X"00000000", -- 00001BC4 - X"00000000", -- 00001BC8 - X"00000000", -- 00001BCC - X"00000000", -- 00001BD0 - X"00000000", -- 00001BD4 - X"00000000", -- 00001BD8 - X"00000000", -- 00001BDC - X"00000000", -- 00001BE0 - X"00000000", -- 00001BE4 - X"00000000", -- 00001BE8 - X"00000000", -- 00001BEC - X"00000000", -- 00001BF0 - X"00000000", -- 00001BF4 - X"00000000", -- 00001BF8 - X"00000000", -- 00001BFC - X"00000000", -- 00001C00 - X"00000000", -- 00001C04 - X"00000000", -- 00001C08 - X"00000000", -- 00001C0C - X"00000000", -- 00001C10 - X"00000000", -- 00001C14 - X"00000000", -- 00001C18 - X"00000000", -- 00001C1C - X"00000000", -- 00001C20 - X"00000000", -- 00001C24 - X"00000000", -- 00001C28 - X"00000000", -- 00001C2C - X"00000000", -- 00001C30 - X"00000000", -- 00001C34 - X"00000000", -- 00001C38 - X"00000000", -- 00001C3C - X"00000000", -- 00001C40 - X"00000000", -- 00001C44 - X"00000000", -- 00001C48 - X"00000000", -- 00001C4C - X"00000000", -- 00001C50 - X"00000000", -- 00001C54 - X"00000000", -- 00001C58 - X"00000000", -- 00001C5C - X"00000000", -- 00001C60 - X"00000000", -- 00001C64 - X"00000000", -- 00001C68 - X"00000000", -- 00001C6C - X"00000000", -- 00001C70 - X"00000000", -- 00001C74 - X"00000000", -- 00001C78 - X"00000000", -- 00001C7C - X"00000000", -- 00001C80 - X"00000000", -- 00001C84 - X"00000000", -- 00001C88 - X"00000000", -- 00001C8C - X"00000000", -- 00001C90 - X"00000000", -- 00001C94 - X"00000000", -- 00001C98 - X"00000000", -- 00001C9C - X"00000000", -- 00001CA0 - X"00000000", -- 00001CA4 - X"00000000", -- 00001CA8 - X"00000000", -- 00001CAC - X"00000000", -- 00001CB0 - X"00000000", -- 00001CB4 - X"00000000", -- 00001CB8 - X"00000000", -- 00001CBC - X"00000000", -- 00001CC0 - X"00000000", -- 00001CC4 - X"00000000", -- 00001CC8 - X"00000000", -- 00001CCC - X"00000000", -- 00001CD0 - X"00000000", -- 00001CD4 - X"00000000", -- 00001CD8 - X"00000000", -- 00001CDC - X"00000000", -- 00001CE0 - X"00000000", -- 00001CE4 - X"00000000", -- 00001CE8 - X"00000000", -- 00001CEC - X"00000000", -- 00001CF0 - X"00000000", -- 00001CF4 - X"00000000", -- 00001CF8 - X"00000000", -- 00001CFC - X"00000000", -- 00001D00 - X"00000000", -- 00001D04 - X"00000000", -- 00001D08 - X"00000000", -- 00001D0C - X"00000000", -- 00001D10 - X"00000000", -- 00001D14 - X"00000000", -- 00001D18 - X"00000000", -- 00001D1C - X"00000000", -- 00001D20 - X"00000000", -- 00001D24 - X"00000000", -- 00001D28 - X"00000000", -- 00001D2C - X"00000000", -- 00001D30 - X"00000000", -- 00001D34 - X"00000000", -- 00001D38 - X"00000000", -- 00001D3C - X"00000000", -- 00001D40 - X"00000000", -- 00001D44 - X"00000000", -- 00001D48 - X"00000000", -- 00001D4C - X"00000000", -- 00001D50 - X"00000000", -- 00001D54 - X"00000000", -- 00001D58 - X"00000000", -- 00001D5C - X"00000000", -- 00001D60 - X"00000000", -- 00001D64 - X"00000000", -- 00001D68 - X"00000000", -- 00001D6C - X"00000000", -- 00001D70 - X"00000000", -- 00001D74 - X"00000000", -- 00001D78 - X"00000000", -- 00001D7C - X"00000000", -- 00001D80 - X"00000000", -- 00001D84 - X"00000000", -- 00001D88 - X"00000000", -- 00001D8C - X"00000000", -- 00001D90 - X"00000000", -- 00001D94 - X"00000000", -- 00001D98 - X"00000000", -- 00001D9C - X"00000000", -- 00001DA0 - X"00000000", -- 00001DA4 - X"00000000", -- 00001DA8 - X"00000000", -- 00001DAC - X"00000000", -- 00001DB0 - X"00000000", -- 00001DB4 - X"00000000", -- 00001DB8 - X"00000000", -- 00001DBC - X"00000000", -- 00001DC0 - X"00000000", -- 00001DC4 - X"00000000", -- 00001DC8 - X"00000000", -- 00001DCC - X"00000000", -- 00001DD0 - X"00000000", -- 00001DD4 - X"00000000", -- 00001DD8 - X"00000000", -- 00001DDC - X"00000000", -- 00001DE0 - X"00000000", -- 00001DE4 - X"00000000", -- 00001DE8 - X"00000000", -- 00001DEC - X"00000000", -- 00001DF0 - X"00000000", -- 00001DF4 - X"00000000", -- 00001DF8 - X"00000000", -- 00001DFC - X"00000000", -- 00001E00 - X"00000000", -- 00001E04 - X"00000000", -- 00001E08 - X"00000000", -- 00001E0C - X"00000000", -- 00001E10 - X"00000000", -- 00001E14 - X"00000000", -- 00001E18 - X"00000000", -- 00001E1C - X"00000000", -- 00001E20 - X"00000000", -- 00001E24 - X"00000000", -- 00001E28 - X"00000000", -- 00001E2C - X"00000000", -- 00001E30 - X"00000000", -- 00001E34 - X"00000000", -- 00001E38 - X"00000000", -- 00001E3C - X"00000000", -- 00001E40 - X"00000000", -- 00001E44 - X"00000000", -- 00001E48 - X"00000000", -- 00001E4C - X"00000000", -- 00001E50 - X"00000000", -- 00001E54 - X"00000000", -- 00001E58 - X"00000000", -- 00001E5C - X"00000000", -- 00001E60 - X"00000000", -- 00001E64 - X"00000000", -- 00001E68 - X"00000000", -- 00001E6C - X"00000000", -- 00001E70 - X"00000000", -- 00001E74 - X"00000000", -- 00001E78 - X"00000000", -- 00001E7C - X"00000000", -- 00001E80 - X"00000000", -- 00001E84 - X"00000000", -- 00001E88 - X"00000000", -- 00001E8C - X"00000000", -- 00001E90 - X"00000000", -- 00001E94 - X"00000000", -- 00001E98 - X"00000000", -- 00001E9C - X"00000000", -- 00001EA0 - X"00000000", -- 00001EA4 - X"00000000", -- 00001EA8 - X"00000000", -- 00001EAC - X"00000000", -- 00001EB0 - X"00000000", -- 00001EB4 - X"00000000", -- 00001EB8 - X"00000000", -- 00001EBC - X"00000000", -- 00001EC0 - X"00000000", -- 00001EC4 - X"00000000", -- 00001EC8 - X"00000000", -- 00001ECC - X"00000000", -- 00001ED0 - X"00000000", -- 00001ED4 - X"00000000", -- 00001ED8 - X"00000000", -- 00001EDC - X"00000000", -- 00001EE0 - X"00000000", -- 00001EE4 - X"00000000", -- 00001EE8 - X"00000000", -- 00001EEC - X"00000000", -- 00001EF0 - X"00000000", -- 00001EF4 - X"00000000", -- 00001EF8 - X"00000000", -- 00001EFC - X"00000000", -- 00001F00 - X"00000000", -- 00001F04 - X"00000000", -- 00001F08 - X"00000000", -- 00001F0C - X"00000000", -- 00001F10 - X"00000000", -- 00001F14 - X"00000000", -- 00001F18 - X"00000000", -- 00001F1C - X"00000000", -- 00001F20 - X"00000000", -- 00001F24 - X"00000000", -- 00001F28 - X"00000000", -- 00001F2C - X"00000000", -- 00001F30 - X"00000000", -- 00001F34 - X"00000000", -- 00001F38 - X"00000000", -- 00001F3C - X"00000000", -- 00001F40 - X"00000000", -- 00001F44 - X"00000000", -- 00001F48 - X"00000000", -- 00001F4C - X"00000000", -- 00001F50 - X"00000000", -- 00001F54 - X"00000000", -- 00001F58 - X"00000000", -- 00001F5C - X"00000000", -- 00001F60 - X"00000000", -- 00001F64 - X"00000000", -- 00001F68 - X"00000000", -- 00001F6C - X"00000000", -- 00001F70 - X"00000000", -- 00001F74 - X"00000000", -- 00001F78 - X"00000000", -- 00001F7C - X"00000000", -- 00001F80 - X"00000000", -- 00001F84 - X"00000000", -- 00001F88 - X"00000000", -- 00001F8C - X"00000000", -- 00001F90 - X"00000000", -- 00001F94 - X"00000000", -- 00001F98 - X"00000000", -- 00001F9C - X"00000000", -- 00001FA0 - X"00000000", -- 00001FA4 - X"00000000", -- 00001FA8 - X"00000000", -- 00001FAC - X"00000000", -- 00001FB0 - X"00000000", -- 00001FB4 - X"00000000", -- 00001FB8 - X"00000000", -- 00001FBC - X"00000000", -- 00001FC0 - X"00000000", -- 00001FC4 - X"00000000", -- 00001FC8 - X"00000000", -- 00001FCC - X"00000000", -- 00001FD0 - X"00000000", -- 00001FD4 - X"00000000", -- 00001FD8 - X"00000000", -- 00001FDC - X"00000000", -- 00001FE0 - X"00000000", -- 00001FE4 - X"00000000", -- 00001FE8 - X"00000000", -- 00001FEC - X"00000000", -- 00001FF0 - X"00000000", -- 00001FF4 - X"00000000", -- 00001FF8 - X"00000000" -- 00001FFC - ); - -begin - -PROM_READ: - process(clk) - begin - if rising_edge(clk) and ce = '1' then - dout <= word_array(to_integer(addr(12 downto 2))); - end if; - end process; - - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length); - jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout; - - end if; - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - word_array(to_integer(jtag_ld_addr(10 downto 0))) <= jtag_ld_din; - else - jtag_ld_dout <= word_array(to_integer(jtag_ld_addr(10 downto 0))); - end if; - end if; - end process; - -end data; diff --git a/lib/CPUs/MIPS/src/irom_hello.vhd b/lib/CPUs/MIPS/src/irom_hello.vhd deleted file mode 100644 index 21ee2eb..0000000 --- a/lib/CPUs/MIPS/src/irom_hello.vhd +++ /dev/null @@ -1,320 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - clk : in STD_LOGIC; - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"3C1D7FFF", -- 00000000 - X"0C100014", -- 00000004 - X"37BDEFFC", -- 00000008 - X"24080002", -- 0000000C - X"0107102A", -- 00000010 - X"ACC40000", -- 00000014 - X"1040000B", -- 00000018 - X"ACC50004", -- 0000001C - X"24C60008", -- 00000020 - X"24E8FFFE", -- 00000024 - X"8CC2FFF8", -- 00000028 - X"8CC3FFFC", -- 0000002C - X"2508FFFF", -- 00000030 - X"00431021", -- 00000034 - X"ACC20000", -- 00000038 - X"1500FFFA", -- 0000003C - X"24C60004", -- 00000040 - X"00E04021", -- 00000044 - X"03E00008", -- 00000048 - X"01001021", -- 0000004C - X"27BDFF78", -- 00000050 - X"3C021003", -- 00000054 - X"3C030001", -- 00000058 - X"AFB60078", -- 0000005C - X"3456FFFC", -- 00000060 - X"3C02AAAA", -- 00000064 - X"AFB7007C", -- 00000068 - X"AFB50074", -- 0000006C - X"AFB40070", -- 00000070 - X"AFB20068", -- 00000074 - X"AFB00060", -- 00000078 - X"AFBF0080", -- 0000007C - X"AFB3006C", -- 00000080 - X"AFB10064", -- 00000084 - X"AEC00000", -- 00000088 - X"3450AAAA", -- 0000008C - X"347786A0", -- 00000090 - X"27B20010", -- 00000094 - X"24150014", -- 00000098 - X"3474869F", -- 0000009C - X"00009821", -- 000000A0 - X"00002021", -- 000000A4 - X"02401021", -- 000000A8 - X"24060013", -- 000000AC - X"24C6FFFF", -- 000000B0 - X"AC500000", -- 000000B4 - X"04C1FFFD", -- 000000B8 - X"24420004", -- 000000BC - X"02041026", -- 000000C0 - X"24910001", -- 000000C4 - X"24420001", -- 000000C8 - X"02202821", -- 000000CC - X"27A60010", -- 000000D0 - X"24070014", -- 000000D4 - X"0C100003", -- 000000D8 - X"00028040", -- 000000DC - X"24070002", -- 000000E0 - X"26450008", -- 000000E4 - X"0810003E", -- 000000E8 - X"24060011", -- 000000EC - X"04C0000A", -- 000000F0 - X"00000000", -- 000000F4 - X"8CA20000", -- 000000F8 - X"8CA3FFFC", -- 000000FC - X"8CA4FFF8", -- 00000100 - X"00431023", -- 00000104 - X"24C6FFFF", -- 00000108 - X"1482FFF8", -- 0000010C - X"24A50004", -- 00000110 - X"04C1FFF8", -- 00000114 - X"24E70001", -- 00000118 - X"10F5000C", -- 0000011C - X"00000000", -- 00000120 - X"0291102A", -- 00000124 - X"1040FFDF", -- 00000128 - X"02202021", -- 0000012C - X"1677FFDB", -- 00000130 - X"00009821", -- 00000134 - X"8EC20000", -- 00000138 - X"00000000", -- 0000013C - X"24420001", -- 00000140 - X"AEC20000", -- 00000144 - X"0810002A", -- 00000148 - X"00002021", -- 0000014C - X"08100049", -- 00000150 - X"26730001", -- 00000154 - X"00000000", -- 00000158 - X"00000000", -- 0000015C - X"00000000", -- 00000160 - X"00000000", -- 00000164 - X"00000000", -- 00000168 - X"00000000", -- 0000016C - X"00000000", -- 00000170 - X"00000000", -- 00000174 - X"00000000", -- 00000178 - X"00000000", -- 0000017C - X"00000000", -- 00000180 - X"00000000", -- 00000184 - X"00000000", -- 00000188 - X"00000000", -- 0000018C - X"00000000", -- 00000190 - X"00000000", -- 00000194 - X"00000000", -- 00000198 - X"00000000", -- 0000019C - X"00000000", -- 000001A0 - X"00000000", -- 000001A4 - X"00000000", -- 000001A8 - X"00000000", -- 000001AC - X"00000000", -- 000001B0 - X"00000000", -- 000001B4 - X"00000000", -- 000001B8 - X"00000000", -- 000001BC - X"00000000", -- 000001C0 - X"00000000", -- 000001C4 - X"00000000", -- 000001C8 - X"00000000", -- 000001CC - X"00000000", -- 000001D0 - X"00000000", -- 000001D4 - X"00000000", -- 000001D8 - X"00000000", -- 000001DC - X"00000000", -- 000001E0 - X"00000000", -- 000001E4 - X"00000000", -- 000001E8 - X"00000000", -- 000001EC - X"00000000", -- 000001F0 - X"00000000", -- 000001F4 - X"00000000", -- 000001F8 - X"00000000", -- 000001FC - X"00000000", -- 00000200 - X"00000000", -- 00000204 - X"00000000", -- 00000208 - X"00000000", -- 0000020C - X"00000000", -- 00000210 - X"00000000", -- 00000214 - X"00000000", -- 00000218 - X"00000000", -- 0000021C - X"00000000", -- 00000220 - X"00000000", -- 00000224 - X"00000000", -- 00000228 - X"00000000", -- 0000022C - X"00000000", -- 00000230 - X"00000000", -- 00000234 - X"00000000", -- 00000238 - X"00000000", -- 0000023C - X"00000000", -- 00000240 - X"00000000", -- 00000244 - X"00000000", -- 00000248 - X"00000000", -- 0000024C - X"00000000", -- 00000250 - X"00000000", -- 00000254 - X"00000000", -- 00000258 - X"00000000", -- 0000025C - X"00000000", -- 00000260 - X"00000000", -- 00000264 - X"00000000", -- 00000268 - X"00000000", -- 0000026C - X"00000000", -- 00000270 - X"00000000", -- 00000274 - X"00000000", -- 00000278 - X"00000000", -- 0000027C - X"00000000", -- 00000280 - X"00000000", -- 00000284 - X"00000000", -- 00000288 - X"00000000", -- 0000028C - X"00000000", -- 00000290 - X"00000000", -- 00000294 - X"00000000", -- 00000298 - X"00000000", -- 0000029C - X"00000000", -- 000002A0 - X"00000000", -- 000002A4 - X"00000000", -- 000002A8 - X"00000000", -- 000002AC - X"00000000", -- 000002B0 - X"00000000", -- 000002B4 - X"00000000", -- 000002B8 - X"00000000", -- 000002BC - X"00000000", -- 000002C0 - X"00000000", -- 000002C4 - X"00000000", -- 000002C8 - X"00000000", -- 000002CC - X"00000000", -- 000002D0 - X"00000000", -- 000002D4 - X"00000000", -- 000002D8 - X"00000000", -- 000002DC - X"00000000", -- 000002E0 - X"00000000", -- 000002E4 - X"00000000", -- 000002E8 - X"00000000", -- 000002EC - X"00000000", -- 000002F0 - X"00000000", -- 000002F4 - X"00000000", -- 000002F8 - X"00000000", -- 000002FC - X"00000000", -- 00000300 - X"00000000", -- 00000304 - X"00000000", -- 00000308 - X"00000000", -- 0000030C - X"00000000", -- 00000310 - X"00000000", -- 00000314 - X"00000000", -- 00000318 - X"00000000", -- 0000031C - X"00000000", -- 00000320 - X"00000000", -- 00000324 - X"00000000", -- 00000328 - X"00000000", -- 0000032C - X"00000000", -- 00000330 - X"00000000", -- 00000334 - X"00000000", -- 00000338 - X"00000000", -- 0000033C - X"00000000", -- 00000340 - X"00000000", -- 00000344 - X"00000000", -- 00000348 - X"00000000", -- 0000034C - X"00000000", -- 00000350 - X"00000000", -- 00000354 - X"00000000", -- 00000358 - X"00000000", -- 0000035C - X"00000000", -- 00000360 - X"00000000", -- 00000364 - X"00000000", -- 00000368 - X"00000000", -- 0000036C - X"00000000", -- 00000370 - X"00000000", -- 00000374 - X"00000000", -- 00000378 - X"00000000", -- 0000037C - X"00000000", -- 00000380 - X"00000000", -- 00000384 - X"00000000", -- 00000388 - X"00000000", -- 0000038C - X"00000000", -- 00000390 - X"00000000", -- 00000394 - X"00000000", -- 00000398 - X"00000000", -- 0000039C - X"00000000", -- 000003A0 - X"00000000", -- 000003A4 - X"00000000", -- 000003A8 - X"00000000", -- 000003AC - X"00000000", -- 000003B0 - X"00000000", -- 000003B4 - X"00000000", -- 000003B8 - X"00000000", -- 000003BC - X"00000000", -- 000003C0 - X"00000000", -- 000003C4 - X"00000000", -- 000003C8 - X"00000000", -- 000003CC - X"00000000", -- 000003D0 - X"00000000", -- 000003D4 - X"00000000", -- 000003D8 - X"00000000", -- 000003DC - X"00000000", -- 000003E0 - X"00000000", -- 000003E4 - X"00000000", -- 000003E8 - X"00000000", -- 000003EC - X"00000000", -- 000003F0 - X"00000000", -- 000003F4 - X"00000000", -- 000003F8 - X"00000000" -- 000003FC - ); - -begin - -PROM_READ: - process(clk) - begin - if rising_edge(clk) then - dout <= word_array(to_integer(addr)); - end if; - end process; - - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test1.vhd b/lib/CPUs/MIPS/src/irom_test1.vhd deleted file mode 100644 index 24007c4..0000000 --- a/lib/CPUs/MIPS/src/irom_test1.vhd +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"08100001", -- [0x00400000] j 0x00400004 [main] - X"3c011234", -- [0x00400004] lui $1, 4660 - X"34215678", -- [0x00400008] ori $1, $1, 22136 - X"3021f00f", -- [0x0040000c] andi $1, $1, -4081 - X"2021affc", -- [0x00400010] addi $1, $1, -20484 - X"2021ffff", -- [0x00400014] addi $1, $1, -1 - X"1c20fffe", -- [0x00400018] bgtz $1 -8 [loop-0x00400018] - X"3c020000", -- [0x0040001c] lui $2, 0 - X"34420001", -- [0x00400020] ori $2, $2, 1 - X"3c010000", -- [0x00400024] lui $1, 0 - X"34210004", -- [0x00400028] ori $1, $1, 4 - X"00220822", -- [0x0040002c] sub $1, $1, $2 - X"1c20fffe", -- [0x00400030] bgtz $1 -8 [loop2-0x00400030] - X"3c1f0040", -- [0x00400034] lui $31, 64 - X"03e00008", -- [0x00400038] jr $31 - X"00000000", -- [0x0040003c] nop - X"00000000", -- [0x00400040] nop - X"00000000", -- [0x00400044] nop - X"00000000", -- [0x00400048] nop - X"00000000", -- [0x0040004c] nop - X"00000000", -- [0x00400050] nop - X"00000000", -- [0x00400054] nop - X"00000000", -- [0x00400058] nop - X"00000000", -- [0x0040005c] nop - X"00000000", -- [0x00400060] nop - X"00000000", -- [0x00400064] nop - X"00000000", -- [0x00400068] nop - X"00000000", -- [0x0040006c] nop - X"00000000", -- [0x00400070] nop - X"00000000", -- [0x00400074] nop - X"00000000", -- [0x00400078] nop - X"00000000", -- [0x0040007c] nop - X"00000000", -- [0x00400080] nop - X"00000000", -- [0x00400084] nop - X"00000000", -- [0x00400088] nop - X"00000000", -- [0x0040008c] nop - X"00000000", -- [0x00400090] nop - X"00000000", -- [0x00400094] nop - X"00000000", -- [0x00400098] nop - X"00000000", -- [0x0040009c] nop - X"00000000", -- [0x004000a0] nop - X"00000000", -- [0x004000a4] nop - X"00000000", -- [0x004000a8] nop - X"00000000", -- [0x004000ac] nop - X"00000000", -- [0x004000b0] nop - X"00000000", -- [0x004000b4] nop - X"00000000", -- [0x004000b8] nop - X"00000000", -- [0x004000bc] nop - X"00000000", -- [0x004000c0] nop - X"00000000", -- [0x004000c4] nop - X"00000000", -- [0x004000c8] nop - X"00000000", -- [0x004000cc] nop - X"00000000", -- [0x004000d0] nop - X"00000000", -- [0x004000d4] nop - X"00000000", -- [0x004000d8] nop - X"00000000", -- [0x004000dc] nop - X"00000000", -- [0x004000e0] nop - X"00000000", -- [0x004000e4] nop - X"00000000", -- [0x004000e8] nop - X"00000000", -- [0x004000ec] nop - X"00000000", -- [0x004000f0] nop - X"00000000", -- [0x004000f4] nop - X"00000000", -- [0x004000f8] nop - X"00000000" -- [0x004000fc] nop - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test2.vhd b/lib/CPUs/MIPS/src/irom_test2.vhd deleted file mode 100644 index 289c9f9..0000000 --- a/lib/CPUs/MIPS/src/irom_test2.vhd +++ /dev/null @@ -1,73 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"08100001", -- j 0x00400004 [main] ; 5: j main - X"3c011234", -- lui $1, 4660 ; 7: lui $1, 0x1234 - X"34215678", -- ori $1, $1, 22136 ; 8: ori $1, $1, 0x5678 - X"3c035555", -- lui $3, 21845 ; 9: lui $3, 0x5555 - X"3463aaaa", -- ori $3, $3, -21846 ; 10: ori $3, $3, 0xAAAA - X"3c021000", -- lui $2, 4096 ; 11: lui $2, 0x1000 - X"ac410000", -- sw $1, 0($2) ; 12: sw $1, 0($2) - X"ac430004", -- sw $3, 4($2) ; 13: sw $3, 4($2) - X"00000000", -- nop ; 14: sll $0, $0, 0 - X"ac400000", -- sw $0, 0($2) ; 15: sw $0, 0($2) - X"ac400004", -- sw $0, 4($2) ; 16: sw $0, 4($2) - X"8c410000", -- lw $1, 0($2) ; 17: lw $1, 0($2) - X"8c430004", -- lw $3, 4($2) ; 18: lw $3, 4($2) - X"00000000", -- nop ; 19: sll $0, $0, 0 - X"00000000", -- nop ; 20: sll $0, $0, 0 - X"08100001" -- j 0x00400004 [main] ; 21: j main - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test3.vhd b/lib/CPUs/MIPS/src/irom_test3.vhd deleted file mode 100644 index 7d53d2a..0000000 --- a/lib/CPUs/MIPS/src/irom_test3.vhd +++ /dev/null @@ -1,122 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - - X"08100001", -- [0x00400000] j 0x00400004 [main] - X"3c011234", -- [0x00400004] lui $1, 4660 - X"34215a5a", -- [0x00400008] ori $1, $1, 23130 - X"00010840", -- [0x0040000c] sll $1, $1, 1 - X"00010900", -- [0x00400010] sll $1, $1, 4 - X"00010880", -- [0x00400014] sll $1, $1, 2 - X"00010840", -- [0x00400018] sll $1, $1, 1 - X"00010a00", -- [0x0040001c] sll $1, $1, 8 - X"00010882", -- [0x00400020] srl $1, $1, 2 - X"00010942", -- [0x00400024] srl $1, $1, 5 - X"00010842", -- [0x00400028] srl $1, $1, 1 - X"00010a02", -- [0x0040002c] srl $1, $1, 8 - X"3821ffff", -- [0x00400030] xori $1, $1, -1 - X"3c1f0040", -- [0x00400034] lui $31, 64 - X"03e00008", -- [0x00400038] jr $31 - X"003f0826", -- [0x0040003c] xor $1, $1, $31 - X"00000000", -- [0x00400040] nop - X"00000000", -- [0x00400044] nop - X"00000000", -- [0x00400048] nop - X"00000000", -- [0x0040004c] nop - X"00000000", -- [0x00400050] nop - X"00000000", -- [0x00400054] nop - X"00000000", -- [0x00400058] nop - X"00000000", -- [0x0040005c] nop - X"00000000", -- [0x00400060] nop - X"00000000", -- [0x00400064] nop - X"00000000", -- [0x00400068] nop - X"00000000", -- [0x0040006c] nop - X"00000000", -- [0x00400070] nop - X"00000000", -- [0x00400074] nop - X"00000000", -- [0x00400078] nop - X"00000000", -- [0x0040007c] nop - X"00000000", -- [0x00400080] nop - X"00000000", -- [0x00400084] nop - X"00000000", -- [0x00400088] nop - X"00000000", -- [0x0040008c] nop - X"00000000", -- [0x00400090] nop - X"00000000", -- [0x00400094] nop - X"00000000", -- [0x00400098] nop - X"00000000", -- [0x0040009c] nop - X"00000000", -- [0x004000a0] nop - X"00000000", -- [0x004000a4] nop - X"00000000", -- [0x004000a8] nop - X"00000000", -- [0x004000ac] nop - X"00000000", -- [0x004000b0] nop - X"00000000", -- [0x004000b4] nop - X"00000000", -- [0x004000b8] - X"00000000", -- [0x004000bc] - X"00000000", -- [0x004000c0] - X"00000000", -- [0x004000c4] - X"00000000", -- [0x004000c8] - X"00000000", -- [0x004000cc] - X"00000000", -- [0x004000d0] - X"00000000", -- [0x004000d4] - X"00000000", -- [0x004000d8] - X"00000000", -- [0x004000dc] - X"00000000", -- [0x004000e0] - X"00000000", -- [0x004000e4] - X"00000000", -- [0x004000e8] - X"00000000", -- [0x004000ec] - X"00000000", -- [0x004000f0] - X"00000000", -- [0x004000f4] - X"00000000", -- [0x004000f8] - X"00000000" -- [0x004000fc] - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test4.vhd b/lib/CPUs/MIPS/src/irom_test4.vhd deleted file mode 100644 index bbce904..0000000 --- a/lib/CPUs/MIPS/src/irom_test4.vhd +++ /dev/null @@ -1,122 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - - X"08100001", -- [0x00400000] j 0x00400004 [main] ; 5: j main - X"00000000", -- [0x00400004] nop ; 7: sll $0, $0, 0 - X"3c011000", -- [0x00400008] lui $1, 4096 ; 8: lui $1, 0x1000 - X"20220000", -- [0x0040000c] addi $2, $1, 0 ; 9: addi $2, $1, 0 - X"3c071234", -- [0x00400010] lui $7, 4660 ; 10: lui $7, 0x1234 - X"3c050001", -- [0x00400014] lui $5, 1 ; 11: lui $5, 0x0001 - X"ac270000", -- [0x00400018] sw $7, 0($1) ; 12: sw $7, 0($1) - X"8c430000", -- [0x0040001c] lw $3, 0($2) ; 13: lw $3, 0($2) - X"00654020", -- [0x00400020] add $8, $3, $5 ; 14: add $8, $3, $5 - X"00654820", -- [0x00400024] add $9, $3, $5 ; 15: add $9, $3, $5 - X"00655020", -- [0x00400028] add $10, $3, $5 ; 16: add $10, $3, $5 - X"00655820", -- [0x0040002c] add $11, $3, $5 ; 17: add $11, $3, $5 - X"00000000", -- [0x00400030] nop ; 18: sll $0, $0, 0 - X"00000000", -- [0x00400034] nop ; 19: sll $0, $0, 0 - X"08100001", -- [0x00400038] j 0x00400004 [main] ; 20: j main - X"00000000", -- [0x0040003c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400040] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400044] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400048] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040004c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400050] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400054] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400058] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040005c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400060] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400064] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400068] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040006c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400070] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400074] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400078] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040007c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400080] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400084] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400088] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040008c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400090] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400094] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400098] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040009c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000a0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000a4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000a8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000ac] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000b0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000b4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000b8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000bc] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000c0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000c4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000c8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000cc] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000d0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000d4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000d8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000dc] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000e0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000e4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000e8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000ec] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000f0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000f4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000f8] nop ; 21: sll $0, $0, 0 - X"00000000" -- [0x004000fc] nop ; 21: sll $0, $0, 0 - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test5.vhd b/lib/CPUs/MIPS/src/irom_test5.vhd deleted file mode 100644 index 490bdd9..0000000 --- a/lib/CPUs/MIPS/src/irom_test5.vhd +++ /dev/null @@ -1,122 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - - X"08100001", -- [0x00400000] j 0x00400004 [main] - X"3c018000", -- [0x00400004] lui $1, -32768 - X"3c020000", -- [0x00400008] lui $2, 0 - X"3c030000", -- [0x0040000c] lui $3, 0 - X"34420001", -- [0x00400010] ori $2, $2, 1 - X"34630003", -- [0x00400014] ori $3, $3, 3 - X"00010842", -- [0x00400018] srl $1, $1, 1 - X"00010840", -- [0x0040001c] sll $1, $1, 1 - X"00010843", -- [0x00400020] sra $1, $1, 1 - X"000108c3", -- [0x00400024] sra $1, $1, 3 - X"00612004", -- [0x00400028] sllv $4, $1, $3 - X"00412807", -- [0x0040002c] srav $5, $1, $2 - X"00613007", -- [0x00400030] srav $6, $1, $3 - X"3c1f0040", -- [0x00400034] lui $31, 64 - X"03e00008", -- [0x00400038] jr $31 - X"00000000", -- [0x0040003c] nop - X"00000000", -- [0x00400040] nop - X"00000000", -- [0x00400044] nop - X"00000000", -- [0x00400048] nop - X"00000000", -- [0x0040004c] nop - X"00000000", -- [0x00400050] nop - X"00000000", -- [0x00400054] nop - X"00000000", -- [0x00400058] nop - X"00000000", -- [0x0040005c] nop - X"00000000", -- [0x00400060] nop - X"00000000", -- [0x00400064] nop - X"00000000", -- [0x00400068] nop - X"00000000", -- [0x0040006c] nop - X"00000000", -- [0x00400070] nop - X"00000000", -- [0x00400074] nop - X"00000000", -- [0x00400078] nop - X"00000000", -- [0x0040007c] nop - X"00000000", -- [0x00400080] nop - X"00000000", -- [0x00400084] nop - X"00000000", -- [0x00400088] nop - X"00000000", -- [0x0040008c] nop - X"00000000", -- [0x00400090] nop - X"00000000", -- [0x00400094] nop - X"00000000", -- [0x00400098] nop - X"00000000", -- [0x0040009c] nop - X"00000000", -- [0x004000a0] nop - X"00000000", -- [0x004000a4] nop - X"00000000", -- [0x004000a8] nop - X"00000000", -- [0x004000ac] nop - X"00000000", -- [0x004000b0] nop - X"00000000", -- [0x004000b4] nop - X"00000000", -- [0x004000b8] nop - X"00000000", -- [0x004000bc] nop - X"00000000", -- [0x004000c0] nop - X"00000000", -- [0x004000c4] nop - X"00000000", -- [0x004000c8] nop - X"00000000", -- [0x004000cc] nop - X"00000000", -- [0x004000d0] nop - X"00000000", -- [0x004000d4] nop - X"00000000", -- [0x004000d8] nop - X"00000000", -- [0x004000dc] nop - X"00000000", -- [0x004000e0] nop - X"00000000", -- [0x004000e4] nop - X"00000000", -- [0x004000e8] nop - X"00000000", -- [0x004000ec] nop - X"00000000", -- [0x004000f0] nop - X"00000000", -- [0x004000f4] nop - X"00000000", -- [0x004000f8] nop - X"00000000" -- [0x004000fc] nop - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test6.vhd b/lib/CPUs/MIPS/src/irom_test6.vhd deleted file mode 100644 index 5231af8..0000000 --- a/lib/CPUs/MIPS/src/irom_test6.vhd +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"08100001", -- [0x00400000] j 0x00400004 [main] ; 5: j main - X"3c080000", -- [0x00400004] lui $8, 0 ; 7: lui $8, 0 - X"00000000", -- [0x00400008] nop ; 8: sll $0, $0, 0 - X"0c100009", -- [0x0040000c] jal 0x00400024 [subr1] ; 9: jal subr1 - X"3c010040", -- [0x00400010] lui $1, 64 [subr2] ; 10: la $2, subr2 - X"34220030", -- [0x00400014] ori $2, $1, 48 [subr2] - X"00407809", -- [0x00400018] jalr $15, $2 ; 11: jalr $15, $2 - X"00000000", -- [0x0040001c] nop ; 12: sll $0, $0, 0 - X"08100002", -- [0x00400020] j 0x00400008 [loop] ; 13: j loop - X"21080001", -- [0x00400024] addi $8, $8, 1 ; 15: addi $8, 1 - X"00000000", -- [0x00400028] nop ; 16: sll $0, $0, 0 - X"03e00008", -- [0x0040002c] jr $31 ; 17: jr $31 - X"21080010", -- [0x00400030] addi $8, $8, 16 ; 18: addi $8, 16 - X"00000000", -- [0x00400034] nop ; 19: sll $0, $0, 0 - X"01e00008", -- [0x00400038] jr $15 ; 20: jr $15 - X"00000000", -- [0x0040003c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400040] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400044] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400048] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040004c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400050] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400054] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400058] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040005c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400060] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400064] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400068] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040006c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400070] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400074] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400078] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040007c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400080] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400084] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400088] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040008c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400090] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400094] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400098] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040009c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000a0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000a4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000a8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000ac] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000b0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000b4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000b8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000bc] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000c0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000c4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000c8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000cc] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000d0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000d4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000d8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000dc] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000e0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000e4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000e8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000ec] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000f0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000f4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000f8] nop ; 21: sll $0, $0, 0 - X"00000000" -- [0x004000fc] nop ; 21: sll $0, $0, 0 - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test_addsub.vhd b/lib/CPUs/MIPS/src/irom_test_addsub.vhd deleted file mode 100644 index bbe764f..0000000 --- a/lib/CPUs/MIPS/src/irom_test_addsub.vhd +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"3c011234", -- [0x00400000] lui $1, 4660 - X"34225678", -- [0x00400004] ori $2, $1, 22136 - X"3c012345", -- [0x00400008] lui $1, 9029 - X"34236789", -- [0x0040000c] ori $3, $1, 26505 - X"3c018765", -- [0x00400010] lui $1, -30875 - X"34244321", -- [0x00400014] ori $4, $1, 17185 - X"3c019876", -- [0x00400018] lui $1, -26506 - X"34255432", -- [0x0040001c] ori $5, $1, 21554 - X"00000000", -- [0x00400020] nop - X"00427823", -- [0x00400024] subu $15, $2, $2 - X"00437823", -- [0x00400028] subu $15, $2, $3 - X"00447823", -- [0x0040002c] subu $15, $2, $4 - X"00457823", -- [0x00400030] subu $15, $2, $5 - X"00627823", -- [0x00400034] subu $15, $3, $2 - X"00637823", -- [0x00400038] subu $15, $3, $3 - X"00647823", -- [0x0040003c] subu $15, $3, $4 - X"00657823", -- [0x00400040] subu $15, $3, $5 - X"00827823", -- [0x00400044] subu $15, $4, $2 - X"00837823", -- [0x00400048] subu $15, $4, $3 - X"00847823", -- [0x0040004c] subu $15, $4, $4 - X"00857823", -- [0x00400050] subu $15, $4, $5 - X"00a27823", -- [0x00400054] subu $15, $5, $2 - X"00a37823", -- [0x00400058] subu $15, $5, $3 - X"00a47823", -- [0x0040005c] subu $15, $5, $4 - X"00a57823", -- [0x00400060] subu $15, $5, $5 - X"00000000", -- [0x00400064] nop - X"00427822", -- [0x00400068] sub $15, $2, $2 - X"00437822", -- [0x0040006c] sub $15, $2, $3 - X"00447822", -- [0x00400070] sub $15, $2, $4 - X"00457822", -- [0x00400074] sub $15, $2, $5 - X"00627822", -- [0x00400078] sub $15, $3, $2 - X"00637822", -- [0x0040007c] sub $15, $3, $3 - X"00647822", -- [0x00400080] sub $15, $3, $4 - X"00657822", -- [0x00400084] sub $15, $3, $5 - X"00827822", -- [0x00400088] sub $15, $4, $2 - X"00837822", -- [0x0040008c] sub $15, $4, $3 - X"00847822", -- [0x00400090] sub $15, $4, $4 - X"00857822", -- [0x00400094] sub $15, $4, $5 - X"00a27822", -- [0x00400098] sub $15, $5, $2 - X"00a37822", -- [0x0040009c] sub $15, $5, $3 - X"00a47822", -- [0x004000a0] sub $15, $5, $4 - X"00a57822", -- [0x004000a4] sub $15, $5, $5 - X"00000000", -- [0x004000a8] nop - X"08104000", -- [0x004000ac] j 0x00410000 [main] - X"00000000", -- [0x004000b0] nop - X"00000000", -- [0x004000b4] - X"00000000", -- [0x004000b8] - X"00000000", -- [0x004000bc] - X"00000000", -- [0x004000c0] - X"00000000", -- [0x004000c4] - X"00000000", -- [0x004000c8] - X"00000000", -- [0x004000cc] - X"00000000", -- [0x004000d0] - X"00000000", -- [0x004000d4] - X"00000000", -- [0x004000d8] - X"00000000", -- [0x004000dc] - X"00000000", -- [0x004000e0] - X"00000000", -- [0x004000e4] - X"00000000", -- [0x004000e8] - X"00000000", -- [0x004000ec] - X"00000000", -- [0x004000f0] - X"00000000", -- [0x004000f4] - X"00000000", -- [0x004000f8] - X"00000000" -- [0x004000fc] - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test_slt.vhd b/lib/CPUs/MIPS/src/irom_test_slt.vhd deleted file mode 100644 index 5fcf2fe..0000000 --- a/lib/CPUs/MIPS/src/irom_test_slt.vhd +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"3c011234", -- [0x00400000] lui $1, 4660 - X"34225678", -- [0x00400004] ori $2, $1, 22136 - X"3c012345", -- [0x00400008] lui $1, 9029 - X"34236789", -- [0x0040000c] ori $3, $1, 26505 - X"3c018765", -- [0x00400010] lui $1, -30875 - X"34244321", -- [0x00400014] ori $4, $1, 17185 - X"3c019876", -- [0x00400018] lui $1, -26506 - X"34255432", -- [0x0040001c] ori $5, $1, 21554 - X"3c081000", -- [0x00400020] lui $8, 4096 - X"00000000", -- [0x00400024] nop - X"0042782b", -- [0x00400028] sltu $15, $2, $2 - X"0043782b", -- [0x0040002c] sltu $15, $2, $3 - X"0044782b", -- [0x00400030] sltu $15, $2, $4 - X"0045782b", -- [0x00400034] sltu $15, $2, $5 - X"0062782b", -- [0x00400038] sltu $15, $3, $2 - X"0063782b", -- [0x0040003c] sltu $15, $3, $3 - X"0064782b", -- [0x00400040] sltu $15, $3, $4 - X"0065782b", -- [0x00400044] sltu $15, $3, $5 - X"0082782b", -- [0x00400048] sltu $15, $4, $2 - X"0083782b", -- [0x0040004c] sltu $15, $4, $3 - X"0084782b", -- [0x00400050] sltu $15, $4, $4 - X"0085782b", -- [0x00400054] sltu $15, $4, $5 - X"00a2782b", -- [0x00400058] sltu $15, $5, $2 - X"00a3782b", -- [0x0040005c] sltu $15, $5, $3 - X"00a4782b", -- [0x00400060] sltu $15, $5, $4 - X"00a5782b", -- [0x00400064] sltu $15, $5, $5 - X"00000000", -- [0x00400068] nop - X"0042782a", -- [0x0040006c] slt $15, $2, $2 - X"0043782a", -- [0x00400070] slt $15, $2, $3 - X"0044782a", -- [0x00400074] slt $15, $2, $4 - X"0045782a", -- [0x00400078] slt $15, $2, $5 - X"0062782a", -- [0x0040007c] slt $15, $3, $2 - X"0063782a", -- [0x00400080] slt $15, $3, $3 - X"0064782a", -- [0x00400084] slt $15, $3, $4 - X"0065782a", -- [0x00400088] slt $15, $3, $5 - X"0082782a", -- [0x0040008c] slt $15, $4, $2 - X"0083782a", -- [0x00400090] slt $15, $4, $3 - X"0084782a", -- [0x00400094] slt $15, $4, $4 - X"0085782a", -- [0x00400098] slt $15, $4, $5 - X"00a2782a", -- [0x0040009c] slt $15, $5, $2 - X"00a3782a", -- [0x004000a0] slt $15, $5, $3 - X"00a4782a", -- [0x004000a4] slt $15, $5, $4 - X"00a5782a", -- [0x004000a8] slt $15, $5, $5 - X"00000000", -- [0x004000ac] nop - X"08104000", -- [0x004000b0] j 0x00410000 [main] - X"00000000", -- [0x004000b4] nop - X"00000000", -- [0x004000b8] - X"00000000", -- [0x004000bc] - X"00000000", -- [0x004000c0] - X"00000000", -- [0x004000c4] - X"00000000", -- [0x004000c8] - X"00000000", -- [0x004000cc] - X"00000000", -- [0x004000d0] - X"00000000", -- [0x004000d4] - X"00000000", -- [0x004000d8] - X"00000000", -- [0x004000dc] - X"00000000", -- [0x004000e0] - X"00000000", -- [0x004000e4] - X"00000000", -- [0x004000e8] - X"00000000", -- [0x004000ec] - X"00000000", -- [0x004000f0] - X"00000000", -- [0x004000f4] - X"00000000", -- [0x004000f8] - X"00000000" -- [0x004000fc] - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test_slti.vhd b/lib/CPUs/MIPS/src/irom_test_slti.vhd deleted file mode 100644 index b87fd8a..0000000 --- a/lib/CPUs/MIPS/src/irom_test_slti.vhd +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"3c011234", -- [0x00400000] lui $1, 4660 - X"34225678", -- [0x00400004] ori $2, $1, 22136 - X"3c012345", -- [0x00400008] lui $1, 9029 - X"34236789", -- [0x0040000c] ori $3, $1, 26505 - X"3c018765", -- [0x00400010] lui $1, -30875 - X"34244321", -- [0x00400014] ori $4, $1, 17185 - X"3c019876", -- [0x00400018] lui $1, -26506 - X"34255432", -- [0x0040001c] ori $5, $1, 21554 - X"3c081000", -- [0x00400020] lui $8, 4096 - X"00000000", -- [0x00400024] nop - X"2c4f1234", -- [0x00400028] sltiu $15, $2, 4660 - X"2c4f2345", -- [0x0040002c] sltiu $15, $2, 9029 - X"2c4fedcc", -- [0x00400030] sltiu $15, $2, -4660 - X"2c4fdcbb", -- [0x00400034] sltiu $15, $2, -9029 - X"2c6f1234", -- [0x00400038] sltiu $15, $3, 4660 - X"2c6f2345", -- [0x0040003c] sltiu $15, $3, 9029 - X"2c6fedcc", -- [0x00400040] sltiu $15, $3, -4660 - X"2c6fdcbb", -- [0x00400044] sltiu $15, $3, -9029 - X"2c8f1234", -- [0x00400048] sltiu $15, $4, 4660 - X"2c8f2345", -- [0x0040004c] sltiu $15, $4, 9029 - X"2c8fedcc", -- [0x00400050] sltiu $15, $4, -4660 - X"2c8fdcbb", -- [0x00400054] sltiu $15, $4, -9029 - X"2caf1234", -- [0x00400058] sltiu $15, $5, 4660 - X"2caf2345", -- [0x0040005c] sltiu $15, $5, 9029 - X"2cafedcc", -- [0x00400060] sltiu $15, $5, -4660 - X"2cafdcbb", -- [0x00400064] sltiu $15, $5, -9029 - X"00000000", -- [0x00400068] nop - X"284f1234", -- [0x0040006c] slti $15, $2, 4660 - X"284f2345", -- [0x00400070] slti $15, $2, 9029 - X"284fedcc", -- [0x00400074] slti $15, $2, -4660 - X"284fdcbb", -- [0x00400078] slti $15, $2, -9029 - X"286f1234", -- [0x0040007c] slti $15, $3, 4660 - X"286f2345", -- [0x00400080] slti $15, $3, 9029 - X"286fedcc", -- [0x00400084] slti $15, $3, -4660 - X"286fdcbb", -- [0x00400088] slti $15, $3, -9029 - X"288f1234", -- [0x0040008c] slti $15, $4, 4660 - X"288f2345", -- [0x00400090] slti $15, $4, 9029 - X"288fedcc", -- [0x00400094] slti $15, $4, -4660 - X"288fdcbb", -- [0x00400098] slti $15, $4, -9029 - X"28af1234", -- [0x0040009c] slti $15, $5, 4660 - X"28af2345", -- [0x004000a0] slti $15, $5, 9029 - X"28afedcc", -- [0x004000a4] slti $15, $5, -4660 - X"28afdcbb", -- [0x004000a8] slti $15, $5, -9029 - X"00000000", -- [0x004000ac] nop - X"08104000", -- [0x004000b0] j 0x00410000 [main] - X"00000000", -- [0x004000b4] nop - X"00000000", -- [0x004000b8] - X"00000000", -- [0x004000bc] - X"00000000", -- [0x004000c0] - X"00000000", -- [0x004000c4] - X"00000000", -- [0x004000c8] - X"00000000", -- [0x004000cc] - X"00000000", -- [0x004000d0] - X"00000000", -- [0x004000d4] - X"00000000", -- [0x004000d8] - X"00000000", -- [0x004000dc] - X"00000000", -- [0x004000e0] - X"00000000", -- [0x004000e4] - X"00000000", -- [0x004000e8] - X"00000000", -- [0x004000ec] - X"00000000", -- [0x004000f0] - X"00000000", -- [0x004000f4] - X"00000000", -- [0x004000f8] - X"00000000" -- [0x004000fc] - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test_sub.vhd b/lib/CPUs/MIPS/src/irom_test_sub.vhd deleted file mode 100644 index bbe764f..0000000 --- a/lib/CPUs/MIPS/src/irom_test_sub.vhd +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"3c011234", -- [0x00400000] lui $1, 4660 - X"34225678", -- [0x00400004] ori $2, $1, 22136 - X"3c012345", -- [0x00400008] lui $1, 9029 - X"34236789", -- [0x0040000c] ori $3, $1, 26505 - X"3c018765", -- [0x00400010] lui $1, -30875 - X"34244321", -- [0x00400014] ori $4, $1, 17185 - X"3c019876", -- [0x00400018] lui $1, -26506 - X"34255432", -- [0x0040001c] ori $5, $1, 21554 - X"00000000", -- [0x00400020] nop - X"00427823", -- [0x00400024] subu $15, $2, $2 - X"00437823", -- [0x00400028] subu $15, $2, $3 - X"00447823", -- [0x0040002c] subu $15, $2, $4 - X"00457823", -- [0x00400030] subu $15, $2, $5 - X"00627823", -- [0x00400034] subu $15, $3, $2 - X"00637823", -- [0x00400038] subu $15, $3, $3 - X"00647823", -- [0x0040003c] subu $15, $3, $4 - X"00657823", -- [0x00400040] subu $15, $3, $5 - X"00827823", -- [0x00400044] subu $15, $4, $2 - X"00837823", -- [0x00400048] subu $15, $4, $3 - X"00847823", -- [0x0040004c] subu $15, $4, $4 - X"00857823", -- [0x00400050] subu $15, $4, $5 - X"00a27823", -- [0x00400054] subu $15, $5, $2 - X"00a37823", -- [0x00400058] subu $15, $5, $3 - X"00a47823", -- [0x0040005c] subu $15, $5, $4 - X"00a57823", -- [0x00400060] subu $15, $5, $5 - X"00000000", -- [0x00400064] nop - X"00427822", -- [0x00400068] sub $15, $2, $2 - X"00437822", -- [0x0040006c] sub $15, $2, $3 - X"00447822", -- [0x00400070] sub $15, $2, $4 - X"00457822", -- [0x00400074] sub $15, $2, $5 - X"00627822", -- [0x00400078] sub $15, $3, $2 - X"00637822", -- [0x0040007c] sub $15, $3, $3 - X"00647822", -- [0x00400080] sub $15, $3, $4 - X"00657822", -- [0x00400084] sub $15, $3, $5 - X"00827822", -- [0x00400088] sub $15, $4, $2 - X"00837822", -- [0x0040008c] sub $15, $4, $3 - X"00847822", -- [0x00400090] sub $15, $4, $4 - X"00857822", -- [0x00400094] sub $15, $4, $5 - X"00a27822", -- [0x00400098] sub $15, $5, $2 - X"00a37822", -- [0x0040009c] sub $15, $5, $3 - X"00a47822", -- [0x004000a0] sub $15, $5, $4 - X"00a57822", -- [0x004000a4] sub $15, $5, $5 - X"00000000", -- [0x004000a8] nop - X"08104000", -- [0x004000ac] j 0x00410000 [main] - X"00000000", -- [0x004000b0] nop - X"00000000", -- [0x004000b4] - X"00000000", -- [0x004000b8] - X"00000000", -- [0x004000bc] - X"00000000", -- [0x004000c0] - X"00000000", -- [0x004000c4] - X"00000000", -- [0x004000c8] - X"00000000", -- [0x004000cc] - X"00000000", -- [0x004000d0] - X"00000000", -- [0x004000d4] - X"00000000", -- [0x004000d8] - X"00000000", -- [0x004000dc] - X"00000000", -- [0x004000e0] - X"00000000", -- [0x004000e4] - X"00000000", -- [0x004000e8] - X"00000000", -- [0x004000ec] - X"00000000", -- [0x004000f0] - X"00000000", -- [0x004000f4] - X"00000000", -- [0x004000f8] - X"00000000" -- [0x004000fc] - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/mips_embedded.vhd b/lib/CPUs/MIPS/src/mips_embedded.vhd deleted file mode 100644 index 47d7bd7..0000000 --- a/lib/CPUs/MIPS/src/mips_embedded.vhd +++ /dev/null @@ -1,332 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - -entity mips_embedded is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - halt : in STD_LOGIC; - int : in unsigned(5 downto 0); - rxd : in STD_LOGIC; - txd : out STD_LOGIC; - dout : out word_t - ); -end mips_embedded; - -architecture rtl of mips_embedded is - - COMPONENT mips_top - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - int : in unsigned(5 downto 0); - mem_rdy : in STD_LOGIC; - mem_re : out STD_LOGIC; - mem_en : out STD_LOGIC; - mem_we : out unsigned(3 downto 0); - mem_din : in word_t; - mem_dout : out word_t; - mem_addr : out word_t - - ); - END COMPONENT; - - signal mem_din : word_t; - signal mem_dout : word_t; - signal mem_addr : word_t; - signal mem_re : std_logic; - signal mem_en : std_logic; - signal mem_we : unsigned(3 downto 0); - signal mem_rdy : std_logic; - - subtype tick_usec_t is natural range 0 to 99; - signal tick_usec : tick_usec_t; - signal cnt_usec : word_t; - signal cnt_sec : word_t; - signal cnt_usec_preset : word_t; - signal cnt_sec_preset : word_t; - signal cnt_usec_en : std_logic; - signal cnt_usec_we : std_logic; - signal cnt_sec_en : std_logic; - signal cnt_sec_we : std_logic; - - COMPONENT uart_tx - Port - ( - data_in : in std_logic_vector(7 downto 0); - write_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - serial_out : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - clk : in std_logic - ); - END COMPONENT; - - COMPONENT uart_rx - Port - ( - serial_in : in std_logic; - data_out : out std_logic_vector(7 downto 0); - read_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - buffer_data_present : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - clk : in std_logic - ); - END COMPONENT; - - signal baud_count : unsigned(7 downto 0); - signal en_16_x_baud : std_logic; - signal reg_we_uart_tx : std_logic; - signal tx_full : std_logic; - signal tx_half_full : std_logic; - signal reg_uart_tx : unsigned(7 downto 0); - signal reg_re_uart_rx : std_logic; - signal reg_uart_rx : std_logic_vector(7 downto 0); - signal rx_data_present : std_logic; - signal rx_full : std_logic; - signal rx_half_full : std_logic; - signal uart_status_port : unsigned(7 downto 0); - signal reg_uart_ctrl : unsigned(7 downto 0); - signal reg_uart_baud : unsigned(7 downto 0); - -begin - -registers_write: - process(clk) - begin - if rising_edge(clk) then - reg_we_uart_tx <= '0'; - cnt_usec_we <= '0'; - cnt_sec_we <= '0'; - if rst = '1' then - dout <= (others => '0'); - reg_uart_baud <= to_unsigned(53, 8); - reg_uart_ctrl <= to_unsigned(0, 8); - elsif mem_en = '1' then - case mem_addr(5 downto 2) is - - when "0000" => - if mem_we(0) = '1' then - dout(7 downto 0) <= mem_dout(7 downto 0); - end if; - if mem_we(1) = '1' then - dout(15 downto 8) <= mem_dout(15 downto 8); - end if; - if mem_we(2) = '1' then - dout(23 downto 16) <= mem_dout(23 downto 16); - end if; - if mem_we(3) = '1' then - dout(31 downto 24) <= mem_dout(31 downto 24); - end if; - - when "0001" => - if mem_we(0) = '1' then - reg_we_uart_tx <= '1'; - reg_uart_tx <= mem_dout(7 downto 0); - end if; - - when "0010" => - if mem_we(0) = '1' then - reg_uart_ctrl <= mem_dout(7 downto 0); - end if; - if mem_we(1) = '1' then - reg_uart_baud <= mem_dout(15 downto 8); - end if; - - when "0100" => - if mem_we(3) = '1' then - cnt_usec_we <= '1'; - cnt_usec_preset <= mem_dout; - end if; - - when "0101" => - if mem_we(3) = '1' then - cnt_sec_we <= '1'; - cnt_sec_preset <= mem_dout; - end if; - - when others => null; - end case; - end if; - end if; - end process; - -registers_read: - process(clk) - begin - if rising_edge(clk) then - reg_re_uart_rx <= '0'; - if mem_en = '1' then - mem_din <= (others => '0'); - case mem_addr(5 downto 2) is - - when "0000" => null; - - when "0001" => - reg_re_uart_rx <= '1'; - mem_din(7 downto 0) <= unsigned(reg_uart_rx); - - when "0010" => - mem_din(7 downto 0) <= uart_status_port; - mem_din(15 downto 8) <= reg_uart_baud; - - when "0100" => - mem_din <= cnt_usec; - - when "0101" => - mem_din <= cnt_sec; - - when others => null; - end case; - end if; - end if; - end process; - - mem_rdy <= not halt; - -inst_mips_top: mips_top - PORT MAP - ( - rst => rst, - clk => clk, - int => int, - mem_rdy => mem_rdy, - mem_en => mem_en, - mem_we => mem_we, - mem_din => mem_din, - mem_dout => mem_dout, - mem_addr => mem_addr - ); - -inst_uart_tx: uart_tx - port map - ( - data_in => std_logic_vector(reg_uart_tx), - write_buffer => reg_we_uart_tx, - reset_buffer => rst, - en_16_x_baud => en_16_x_baud, - serial_out => txd, - buffer_full => tx_full, - buffer_half_full => tx_half_full, - clk => clk - ); - -inst_uart_rx: uart_rx - port map - ( - serial_in => rxd, - data_out => reg_uart_rx, - read_buffer => reg_re_uart_rx, - reset_buffer => rst, - en_16_x_baud => en_16_x_baud, - buffer_data_present => rx_data_present, - buffer_full => rx_full, - buffer_half_full => rx_half_full, - clk => clk - ); - - uart_status_port <= (7 downto 5 => '0') & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full; - -tick_usec_timer: - process(clk) - begin - if clk'event and clk='1' then - cnt_usec_en <= '0'; - if rst = '1' then - tick_usec <= 0; - cnt_usec_en <= '0'; - elsif tick_usec = tick_usec_t'high then - tick_usec <= 0; - cnt_usec_en <= '1'; - else - tick_usec <= tick_usec + 1; - end if; - end if; - end process; - -cnt_usec_timer: - process(clk) - begin - if clk'event and clk='1' then - cnt_sec_en <= '0'; - if rst = '1' then - cnt_usec <= (others => '0'); - cnt_sec_en <= '0'; - elsif cnt_usec_we = '1' then - cnt_usec <= cnt_usec_preset; - elsif cnt_usec_en = '1' then - if cnt_usec = to_unsigned(1E6 - 1, word_t'length) then - cnt_usec <= (others => '0'); - cnt_sec_en <= '1'; - else - cnt_usec <= cnt_usec + 1; - end if; - end if; - end if; - end process; - -cnt_sec_timer: - process(clk) - begin - if clk'event and clk='1' then - if rst = '1' then - cnt_sec <= (others => '0'); - elsif cnt_sec_we = '1' then - cnt_sec <= cnt_sec_preset; - elsif cnt_sec_en = '1' then - cnt_sec <= cnt_sec + 1; - end if; - end if; - end process; - -baud_timer: - process(clk) - begin - if clk'event and clk='1' then - if rst = '1' then - baud_count <= (others => '0'); - elsif baud_count = reg_uart_baud then - baud_count <= (others => '0'); - en_16_x_baud <= '1'; - else - baud_count <= baud_count + 1; - en_16_x_baud <= '0'; - end if; - end if; - end process; - -end rtl; diff --git a/lib/CPUs/MIPS/src/mips_embedded_syn.vhd b/lib/CPUs/MIPS/src/mips_embedded_syn.vhd deleted file mode 100644 index 9de77e7..0000000 --- a/lib/CPUs/MIPS/src/mips_embedded_syn.vhd +++ /dev/null @@ -1,137 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: JIPS top file --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - -entity mips_embedded_syn is - Port - ( - sys_rst_n_in : in STD_LOGIC; - sys_clk_in : in STD_LOGIC; - sys_dip : in STD_LOGIC_VECTOR (7 downto 0); - sys_btn : in STD_LOGIC_VECTOR (8 downto 0); - sys_led : out STD_LOGIC_VECTOR (7 downto 0); - sys_rx : in STD_LOGIC; - sys_tx : out STD_LOGIC; - sys_error : out STD_LOGIC_VECTOR (1 downto 0) - ); - -end mips_embedded_syn; - -architecture struct of mips_embedded_syn is - - COMPONENT mips_embedded - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - halt : in STD_LOGIC; - int : in unsigned(5 downto 0); - rxd : in STD_LOGIC; - txd : out STD_LOGIC; - dout : out word_t - ); - END COMPONENT; - - signal dout : word_t; - signal rst : STD_LOGIC; - signal clk : STD_LOGIC; - signal halt : STD_LOGIC; - signal int : unsigned(5 downto 0); - signal btn_r : unsigned (8 downto 0); - signal dip_r : unsigned (7 downto 0); - -begin - -------------------------------------------------------------------- -inst_mips_embedded: mips_embedded - PORT MAP - ( - rst => rst, - clk => clk, - halt => halt, - int => int, - rxd => sys_rx, - txd => sys_tx, - dout => dout - ); - - clk <= sys_clk_in; - rst <= not sys_rst_n_in; - -ERR_LED_reg: - process(rst, clk) - begin - if rst = '1' then - sys_error <= (others => '1'); - elsif rising_edge(clk) then - sys_error <= STD_LOGIC_VECTOR(dout(31 downto 30)); - end if; - end process; - -LED_reg: - process(rst, clk) - begin - if rst = '1' then - sys_led <= (others => '0'); - elsif rising_edge(clk) then - sys_led <= STD_LOGIC_VECTOR(dout(7 downto 0)); - end if; - end process; - -DIP_reg: - process(rst, clk) - begin - if rst = '1' then - dip_r <= (others => '0'); - elsif rising_edge(clk) then - dip_r <= unsigned(sys_dip); - end if; - end process; - -BTN_reg: - process(rst, clk) - begin - if rst = '1' then - btn_r <= (others => '0'); - elsif rising_edge(clk) then - btn_r <= unsigned(sys_btn); - end if; - end process; - - halt <= btn_r(4) after 6.5 ns; - int(0) <= dip_r(0) and btn_r(3) after 1 ns; - int(1) <= dip_r(1) and btn_r(3) after 1 ns; - int(2) <= dip_r(2) and btn_r(3) after 1 ns; - int(3) <= dip_r(3) and btn_r(3) after 1 ns; - int(4) <= dip_r(4) and btn_r(3) after 1 ns; - int(5) <= dip_r(5) and btn_r(3) after 1 ns; - -------------------------------------------------------------------- - -end struct; diff --git a/lib/CPUs/MIPS/src/mips_muldiv.vhd b/lib/CPUs/MIPS/src/mips_muldiv.vhd deleted file mode 100644 index 34016d9..0000000 --- a/lib/CPUs/MIPS/src/mips_muldiv.vhd +++ /dev/null @@ -1,83 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity muldiv is - Port - ( - rst : in std_logic; - clk : in std_logic; - din_vld_hi : in std_logic; - din_vld_lo : in std_logic; - din_hi : in word_t; - din_lo : in word_t; - hilo_sel : in std_logic; - dout : out word_t - ); -end muldiv; - -architecture Behavioral of muldiv is - - signal reg_hi, reg_lo : word_t; - --------------------------------------------------------------------------- -begin - --------------------------------------------------------------------------- -proc_reg_out: - process(hilo_sel, reg_hi, reg_lo) - begin - if hilo_sel = '1' then - dout <= reg_hi; - else - dout <= reg_lo; - end if; - end process; - -proc_reg_in: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - reg_hi <= (others => '0'); - reg_lo <= (others => '0'); - elsif din_vld_hi = '1' then - if hilo_sel = '1' then - reg_hi <= din_hi; - else - reg_lo <= din_hi; - end if; - end if; - if din_vld_lo = '1' then - reg_lo <= din_lo; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/ram.vhd b/lib/CPUs/MIPS/src/ram.vhd deleted file mode 100644 index d054c72..0000000 --- a/lib/CPUs/MIPS/src/ram.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY ram IS - Generic - ( - word_addr_width : integer := 6 - ); - Port - ( - clk : in STD_LOGIC; - we : in unsigned(3 downto 0); - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - din : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END ram; - -ARCHITECTURE behavior OF ram IS - - constant depth : natural := 2**word_addr_width; - - type sram_t is array (0 to depth-1) of unsigned(7 downto 0); - - function sram_clear return sram_t is - - variable result : sram_t; - begin - for i in 0 to sram_t'length-1 loop - result(i) := (others => '0'); - end loop; - return result; - end sram_clear; - - signal sram0, sram1, sram2, sram3 : sram_t := sram_clear; - -BEGIN - - -SRAM_RW: - process(clk) - variable index : natural range 0 to depth-1; - begin - if rising_edge(clk) and ce = '1' then - index := to_integer(addr(word_addr_width+1 downto 2)); - if we(0) = '1' then - sram0(index)<= din(7 downto 0); - end if; - dout(7 downto 0) <= sram0(index); - end if; - end process; - - process(clk) - variable index : natural range 0 to depth-1; - begin - if rising_edge(clk) and ce = '1' then - index := to_integer(addr(word_addr_width+1 downto 2)); - if we(1) = '1' then - sram1(index)<= din(15 downto 8); - end if; - dout(15 downto 8) <= sram1(index); - end if; - end process; - - process(clk) - variable index : natural range 0 to depth-1; - begin - if rising_edge(clk) and ce = '1' then - index := to_integer(addr(word_addr_width+1 downto 2)); - if we(2) = '1' then - sram2(index)<= din(23 downto 16); - end if; - dout(23 downto 16) <= sram2(index); - end if; - end process; - - process(clk) - variable index : natural range 0 to depth-1; - begin - if rising_edge(clk) and ce = '1' then - index := to_integer(addr(word_addr_width+1 downto 2)); - if we(3) = '1' then - sram3(index)<= din(31 downto 24); - end if; - dout(31 downto 24) <= sram3(index); - end if; - end process; - -end behavior; diff --git a/lib/CPUs/MIPS/src/ram_ld.vhd b/lib/CPUs/MIPS/src/ram_ld.vhd deleted file mode 100644 index 7a36b13..0000000 --- a/lib/CPUs/MIPS/src/ram_ld.vhd +++ /dev/null @@ -1,177 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY ram IS - Generic - ( - word_addr_width : integer := 6 - ); - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - we : in unsigned(3 downto 0); - addr : in unsigned(31 downto 0); - din : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END ram; - -ARCHITECTURE behavior OF ram IS - - COMPONENT dpram_2w2r - Generic - ( - addr_width : integer; - data_width : integer - ); - Port - ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - - signal jtag_clk : STD_LOGIC; - signal jtag_we : unsigned(3 downto 0); - signal jtag_addr : unsigned (15 downto 0); - signal jtag_dout : unsigned (31 downto 0); - signal jtag_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - -BEGIN - -gen_sram: - for i in 0 to 3 generate - begin - inst_dpram_2w2r : dpram_2w2r - GENERIC MAP - ( - addr_width => word_addr_width, - data_width => 8 - ) - PORT MAP - ( - clk_a => clk, - en_a => ce, - we_a => we(i), - addr_a => addr(word_addr_width+1 downto 2), - din_a => din((i+1)*8-1 downto i*8), - dout_a => dout((i+1)*8-1 downto i*8), - - clk_b => jtag_clk, - en_b => jtag_we(i), - we_b => jtag_we(i), - addr_b => jtag_addr(word_addr_width-1 downto 0), - din_b => jtag_din((i+1)*8-1 downto i*8), - dout_b => jtag_dout((i+1)*8-1 downto i*8) - ); - end generate; - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_addr <= user_regi(user_regi'left downto jtag_dout'length); - jtag_din <= user_regi(jtag_dout'length-1 downto 0); - jtag_clk <= bs_update1; - jtag_we <= (3 downto 0 => bs_sel); - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_dout'length => '0') & jtag_dout; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end behavior; diff --git a/lib/CPUs/MIPS/src/ram_sim.vhd b/lib/CPUs/MIPS/src/ram_sim.vhd deleted file mode 100644 index 6d26672..0000000 --- a/lib/CPUs/MIPS/src/ram_sim.vhd +++ /dev/null @@ -1,88 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY ram IS - Generic - ( - word_addr_width : integer := 6 - ); - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - we : in unsigned(3 downto 0); - addr : in unsigned(31 downto 0); - din : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END ram; - -ARCHITECTURE behavior OF ram IS - - constant depth : natural := 2**word_addr_width; - - type sram_t is array (0 to depth-1) of unsigned(31 downto 0); - - function sram_clear return sram_t is - - variable result : sram_t; - begin - for i in 0 to sram_t'length-1 loop - result(i) := (others => '0'); - end loop; - return result; - end sram_clear; - - signal sram : sram_t := sram_clear; - -BEGIN - - -SRAM_RW: - process(clk) - variable index : natural range 0 to depth-1; - begin - if rising_edge(clk) and ce = '1' then - index := to_integer(addr(word_addr_width+1 downto 2)); - if we(0) = '1' then - sram(index)(7 downto 0) <= din(7 downto 0); - end if; - if we(1) = '1' then - sram(index)(15 downto 8) <= din(15 downto 8); - end if; - if we(2) = '1' then - sram(index)(23 downto 16) <= din(23 downto 16); - end if; - if we(3) = '1' then - sram(index)(31 downto 24) <= din(31 downto 24); - end if; - dout <= sram(index); - end if; - end process; - -end behavior; diff --git a/lib/CPUs/MIPS/src/rmd160_test.ROM_ld.vhd b/lib/CPUs/MIPS/src/rmd160_test.ROM_ld.vhd deleted file mode 100644 index b0c6fe3..0000000 --- a/lib/CPUs/MIPS/src/rmd160_test.ROM_ld.vhd +++ /dev/null @@ -1,4222 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY rom IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END rom; - -ARCHITECTURE data OF rom IS - - subtype word_t is unsigned(31 downto 0); - type word_array_t is array (0 to 4095) of word_t; - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : unsigned (15 downto 0); - signal jtag_ld_dout : unsigned (31 downto 0); - signal jtag_ld_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - - signal word_array : word_array_t := - ( - - X"401A6000", -- 00000000 - X"3C1B0040", -- 00000004 - X"035BD024", -- 00000008 - X"375A000C", -- 0000000C - X"409A6000", -- 00000010 - X"401A7800", -- 00000014 - X"00000000", -- 00000018 - X"409AF800", -- 0000001C - X"3C1D7FFF", -- 00000020 - X"37BDEFFC", -- 00000024 - X"3C1A0040", -- 00000028 - X"275A05B4", -- 0000002C - X"0340F809", -- 00000030 - X"42000010", -- 00000034 - X"00000000", -- 00000038 - X"00000000", -- 0000003C - X"00000000", -- 00000040 - X"00000000", -- 00000044 - X"00000000", -- 00000048 - X"00000000", -- 0000004C - X"00000000", -- 00000050 - X"00000000", -- 00000054 - X"00000000", -- 00000058 - X"00000000", -- 0000005C - X"00000000", -- 00000060 - X"00000000", -- 00000064 - X"00000000", -- 00000068 - X"00000000", -- 0000006C - X"00000000", -- 00000070 - X"00000000", -- 00000074 - X"00000000", -- 00000078 - X"00000000", -- 0000007C - X"00000000", -- 00000080 - X"00000000", -- 00000084 - X"00000000", -- 00000088 - X"00000000", -- 0000008C - X"00000000", -- 00000090 - X"00000000", -- 00000094 - X"00000000", -- 00000098 - X"00000000", -- 0000009C - X"00000000", -- 000000A0 - X"00000000", -- 000000A4 - X"00000000", -- 000000A8 - X"00000000", -- 000000AC - X"00000000", -- 000000B0 - X"00000000", -- 000000B4 - X"00000000", -- 000000B8 - X"00000000", -- 000000BC - X"00000000", -- 000000C0 - X"00000000", -- 000000C4 - X"00000000", -- 000000C8 - X"00000000", -- 000000CC - X"00000000", -- 000000D0 - X"00000000", -- 000000D4 - X"00000000", -- 000000D8 - X"00000000", -- 000000DC - X"00000000", -- 000000E0 - X"00000000", -- 000000E4 - X"00000000", -- 000000E8 - X"00000000", -- 000000EC - X"00000000", -- 000000F0 - X"00000000", -- 000000F4 - X"00000000", -- 000000F8 - X"00000000", -- 000000FC - X"00000000", -- 00000100 - X"00000000", -- 00000104 - X"00000000", -- 00000108 - X"00000000", -- 0000010C - X"00000000", -- 00000110 - X"00000000", -- 00000114 - X"00000000", -- 00000118 - X"00000000", -- 0000011C - X"00000000", -- 00000120 - X"00000000", -- 00000124 - X"00000000", -- 00000128 - X"00000000", -- 0000012C - X"00000000", -- 00000130 - X"00000000", -- 00000134 - X"00000000", -- 00000138 - X"00000000", -- 0000013C - X"00000000", -- 00000140 - X"00000000", -- 00000144 - X"00000000", -- 00000148 - X"00000000", -- 0000014C - X"00000000", -- 00000150 - X"00000000", -- 00000154 - X"00000000", -- 00000158 - X"00000000", -- 0000015C - X"00000000", -- 00000160 - X"00000000", -- 00000164 - X"00000000", -- 00000168 - X"00000000", -- 0000016C - X"00000000", -- 00000170 - X"00000000", -- 00000174 - X"00000000", -- 00000178 - X"00000000", -- 0000017C - X"3C010000", -- 00000180 - X"AC3D0018", -- 00000184 - X"3C1D0000", -- 00000188 - X"27BD0018", -- 0000018C - X"27BD0004", -- 00000190 - X"AFA80000", -- 00000194 - X"27BD0004", -- 00000198 - X"AFA90000", -- 0000019C - X"27BD0004", -- 000001A0 - X"AFAA0000", -- 000001A4 - X"27BD0004", -- 000001A8 - X"AFAB0000", -- 000001AC - X"27BD0004", -- 000001B0 - X"AFAC0000", -- 000001B4 - X"27BD0004", -- 000001B8 - X"AFBF0000", -- 000001BC - X"400A4000", -- 000001C0 - X"27BD0004", -- 000001C4 - X"AFAA0000", -- 000001C8 - X"400A6000", -- 000001CC - X"27BD0004", -- 000001D0 - X"AFAA0000", -- 000001D4 - X"400A6800", -- 000001D8 - X"27BD0004", -- 000001DC - X"AFAA0000", -- 000001E0 - X"000A5742", -- 000001E4 - X"314B0004", -- 000001E8 - X"400A7000", -- 000001EC - X"27BD0004", -- 000001F0 - X"AFAA0000", -- 000001F4 - X"014B5021", -- 000001F8 - X"27BD0004", -- 000001FC - X"AFAA0000", -- 00000200 - X"3C0B0000", -- 00000204 - X"256B0156", -- 00000208 - X"0C100126", -- 0000020C - X"00000000", -- 00000210 - X"3C0B0000", -- 00000214 - X"256B0118", -- 00000218 - X"0C100126", -- 0000021C - X"00000000", -- 00000220 - X"8FAA0000", -- 00000224 - X"27BDFFFC", -- 00000228 - X"0C1000DE", -- 0000022C - X"00000000", -- 00000230 - X"3C0B0000", -- 00000234 - X"256B0156", -- 00000238 - X"0C100126", -- 0000023C - X"00000000", -- 00000240 - X"3C0B0000", -- 00000244 - X"256B0126", -- 00000248 - X"0C100126", -- 0000024C - X"00000000", -- 00000250 - X"8FAA0000", -- 00000254 - X"27BDFFFC", -- 00000258 - X"0C1000DE", -- 0000025C - X"00000000", -- 00000260 - X"3C0B0000", -- 00000264 - X"256B0156", -- 00000268 - X"0C100126", -- 0000026C - X"00000000", -- 00000270 - X"3C0B0000", -- 00000274 - X"256B0132", -- 00000278 - X"0C100126", -- 0000027C - X"00000000", -- 00000280 - X"8FAA0000", -- 00000284 - X"27BDFFFC", -- 00000288 - X"0C1000DE", -- 0000028C - X"00000000", -- 00000290 - X"3C0B0000", -- 00000294 - X"256B0156", -- 00000298 - X"0C100126", -- 0000029C - X"00000000", -- 000002A0 - X"3C0B0000", -- 000002A4 - X"256B013E", -- 000002A8 - X"0C100126", -- 000002AC - X"00000000", -- 000002B0 - X"8FAA0000", -- 000002B4 - X"27BDFFFC", -- 000002B8 - X"0C1000DE", -- 000002BC - X"00000000", -- 000002C0 - X"3C0B0000", -- 000002C4 - X"256B0156", -- 000002C8 - X"0C100126", -- 000002CC - X"00000000", -- 000002D0 - X"3C0B0000", -- 000002D4 - X"256B014A", -- 000002D8 - X"0C100126", -- 000002DC - X"00000000", -- 000002E0 - X"8FAA0000", -- 000002E4 - X"27BDFFFC", -- 000002E8 - X"0C1000DE", -- 000002EC - X"00000000", -- 000002F0 - X"3C0B0000", -- 000002F4 - X"256B0156", -- 000002F8 - X"0C100126", -- 000002FC - X"00000000", -- 00000300 - X"401A6800", -- 00000304 - X"3C1B8000", -- 00000308 - X"001AD082", -- 0000030C - X"335A000F", -- 00000310 - X"035BD025", -- 00000314 - X"AF7A0000", -- 00000318 - X"401A6800", -- 0000031C - X"00000000", -- 00000320 - X"001AD202", -- 00000324 - X"335A0001", -- 00000328 - X"1740FFFB", -- 0000032C - X"00000000", -- 00000330 - X"401A7000", -- 00000334 - X"8FBF0000", -- 00000338 - X"27BDFFFC", -- 0000033C - X"8FAC0000", -- 00000340 - X"27BDFFFC", -- 00000344 - X"8FAB0000", -- 00000348 - X"27BDFFFC", -- 0000034C - X"8FAA0000", -- 00000350 - X"27BDFFFC", -- 00000354 - X"8FA90000", -- 00000358 - X"27BDFFFC", -- 0000035C - X"8FA80000", -- 00000360 - X"27BDFFFC", -- 00000364 - X"3C1D0000", -- 00000368 - X"8FBD0018", -- 0000036C - X"03400008", -- 00000370 - X"42000010", -- 00000374 - X"27BD0004", -- 00000378 - X"AFBF0000", -- 0000037C - X"27BD0004", -- 00000380 - X"AFAA0000", -- 00000384 - X"000A5402", -- 00000388 - X"0C1000ED", -- 0000038C - X"00000000", -- 00000390 - X"8FAA0000", -- 00000394 - X"27BDFFFC", -- 00000398 - X"0C1000ED", -- 0000039C - X"00000000", -- 000003A0 - X"8FBF0000", -- 000003A4 - X"27BDFFFC", -- 000003A8 - X"03E00008", -- 000003AC - X"00000000", -- 000003B0 - X"27BD0004", -- 000003B4 - X"AFBF0000", -- 000003B8 - X"27BD0004", -- 000003BC - X"AFAA0000", -- 000003C0 - X"000A5202", -- 000003C4 - X"0C1000FC", -- 000003C8 - X"00000000", -- 000003CC - X"8FAA0000", -- 000003D0 - X"27BDFFFC", -- 000003D4 - X"0C1000FC", -- 000003D8 - X"00000000", -- 000003DC - X"8FBF0000", -- 000003E0 - X"27BDFFFC", -- 000003E4 - X"03E00008", -- 000003E8 - X"00000000", -- 000003EC - X"27BD0004", -- 000003F0 - X"AFBF0000", -- 000003F4 - X"27BD0004", -- 000003F8 - X"AFAA0000", -- 000003FC - X"000A5102", -- 00000400 - X"0C10010B", -- 00000404 - X"00000000", -- 00000408 - X"8FAA0000", -- 0000040C - X"27BDFFFC", -- 00000410 - X"0C10010B", -- 00000414 - X"00000000", -- 00000418 - X"8FBF0000", -- 0000041C - X"27BDFFFC", -- 00000420 - X"03E00008", -- 00000424 - X"00000000", -- 00000428 - X"27BD0004", -- 0000042C - X"AFBF0000", -- 00000430 - X"27BD0004", -- 00000434 - X"AFAA0000", -- 00000438 - X"3C0C0000", -- 0000043C - X"258C0159", -- 00000440 - X"314A000F", -- 00000444 - X"018A6021", -- 00000448 - X"918A0000", -- 0000044C - X"0C10011C", -- 00000450 - X"00000000", -- 00000454 - X"8FAA0000", -- 00000458 - X"27BDFFFC", -- 0000045C - X"8FBF0000", -- 00000460 - X"27BDFFFC", -- 00000464 - X"03E00008", -- 00000468 - X"00000000", -- 0000046C - X"3C088000", -- 00000470 - X"35080008", -- 00000474 - X"91080000", -- 00000478 - X"3C098000", -- 0000047C - X"35290004", -- 00000480 - X"31080002", -- 00000484 - X"1500FFF9", -- 00000488 - X"00000000", -- 0000048C - X"03E00008", -- 00000490 - X"A12A0000", -- 00000494 - X"27BD0004", -- 00000498 - X"AFAB0000", -- 0000049C - X"27BD0004", -- 000004A0 - X"AFBF0000", -- 000004A4 - X"916A0000", -- 000004A8 - X"256B0001", -- 000004AC - X"19400005", -- 000004B0 - X"00000000", -- 000004B4 - X"0C10011C", -- 000004B8 - X"00000000", -- 000004BC - X"0810012A", -- 000004C0 - X"00000000", -- 000004C4 - X"8FBF0000", -- 000004C8 - X"27BDFFFC", -- 000004CC - X"8FAB0000", -- 000004D0 - X"27BDFFFC", -- 000004D4 - X"03E00008", -- 000004D8 - X"00000000", -- 000004DC - X"3C028000", -- 000004E0 - X"00042600", -- 000004E4 - X"00042603", -- 000004E8 - X"34450004", -- 000004EC - X"34430008", -- 000004F0 - X"90620000", -- 000004F4 - X"00000000", -- 000004F8 - X"30420002", -- 000004FC - X"1440FFFC", -- 00000500 - X"00000000", -- 00000504 - X"03E00008", -- 00000508 - X"A0A40000", -- 0000050C - X"27BDFFE0", -- 00000510 - X"AFB10014", -- 00000514 - X"AFB00010", -- 00000518 - X"AFBF0018", -- 0000051C - X"00808021", -- 00000520 - X"80840000", -- 00000524 - X"08100150", -- 00000528 - X"02008821", -- 0000052C - X"0C100138", -- 00000530 - X"26100001", -- 00000534 - X"82040000", -- 00000538 - X"00000000", -- 0000053C - X"1480FFFB", -- 00000540 - X"02111023", -- 00000544 - X"8FBF0018", -- 00000548 - X"8FB10014", -- 0000054C - X"8FB00010", -- 00000550 - X"03E00008", -- 00000554 - X"27BD0020", -- 00000558 - X"27BDFFE0", -- 0000055C - X"AFB10014", -- 00000560 - X"AFB00010", -- 00000564 - X"AFBF0018", -- 00000568 - X"00808021", -- 0000056C - X"24110007", -- 00000570 - X"00101F02", -- 00000574 - X"2C62000A", -- 00000578 - X"2631FFFF", -- 0000057C - X"00108100", -- 00000580 - X"14400002", -- 00000584 - X"24640030", -- 00000588 - X"24640037", -- 0000058C - X"0C100138", -- 00000590 - X"00000000", -- 00000594 - X"0621FFF7", -- 00000598 - X"00101F02", -- 0000059C - X"8FBF0018", -- 000005A0 - X"8FB10014", -- 000005A4 - X"8FB00010", -- 000005A8 - X"03E00008", -- 000005AC - X"27BD0020", -- 000005B0 - X"3C020000", -- 000005B4 - X"8C420000", -- 000005B8 - X"3C030000", -- 000005BC - X"8C630004", -- 000005C0 - X"27BDFFB8", -- 000005C4 - X"AFA20028", -- 000005C8 - X"AFA3002C", -- 000005CC - X"3C020000", -- 000005D0 - X"8C420008", -- 000005D4 - X"3C030000", -- 000005D8 - X"8C63000C", -- 000005DC - X"AFA20030", -- 000005E0 - X"AFA30034", -- 000005E4 - X"3C020000", -- 000005E8 - X"8C420010", -- 000005EC - X"3C030000", -- 000005F0 - X"8C630014", -- 000005F4 - X"3C058000", -- 000005F8 - X"AFA20038", -- 000005FC - X"AFA3003C", -- 00000600 - X"34A60009", -- 00000604 - X"24020035", -- 00000608 - X"34A50008", -- 0000060C - X"24030055", -- 00000610 - X"A0C20000", -- 00000614 - X"27A40010", -- 00000618 - X"A0A30000", -- 0000061C - X"AFBF0040", -- 00000620 - X"AFA00010", -- 00000624 - X"AFA00014", -- 00000628 - X"AFA00018", -- 0000062C - X"AFA0001C", -- 00000630 - X"0C100193", -- 00000634 - X"AFA00020", -- 00000638 - X"0C100144", -- 0000063C - X"27A40028", -- 00000640 - X"08100191", -- 00000644 - X"00000000", -- 00000648 - X"3C02C3D2", -- 0000064C - X"3442E1F0", -- 00000650 - X"AC820010", -- 00000654 - X"3C036745", -- 00000658 - X"3C02EFCD", -- 0000065C - X"34632301", -- 00000660 - X"3442AB89", -- 00000664 - X"AC830000", -- 00000668 - X"AC820004", -- 0000066C - X"3C0398BA", -- 00000670 - X"3C021032", -- 00000674 - X"3463DCFE", -- 00000678 - X"34425476", -- 0000067C - X"AC830008", -- 00000680 - X"03E00008", -- 00000684 - X"AC82000C", -- 00000688 - X"27BDFF80", -- 0000068C - X"AFB30064", -- 00000690 - X"8C93000C", -- 00000694 - X"AFB40068", -- 00000698 - X"8C980004", -- 0000069C - X"8C940008", -- 000006A0 - X"AFBE0078", -- 000006A4 - X"AFB70074", -- 000006A8 - X"AFB60070", -- 000006AC - X"AFB5006C", -- 000006B0 - X"AFB20060", -- 000006B4 - X"AFB1005C", -- 000006B8 - X"AFB00058", -- 000006BC - X"00131027", -- 000006C0 - X"8CA60014", -- 000006C4 - X"8CA70000", -- 000006C8 - X"8C950000", -- 000006CC - X"03141826", -- 000006D0 - X"00541025", -- 000006D4 - X"00731826", -- 000006D8 - X"00581026", -- 000006DC - X"00671821", -- 000006E0 - X"02A08821", -- 000006E4 - X"00461021", -- 000006E8 - X"3C0B50A2", -- 000006EC - X"356B8BE6", -- 000006F0 - X"02A3A821", -- 000006F4 - X"00511021", -- 000006F8 - X"004B8821", -- 000006FC - X"8C990010", -- 00000700 - X"AFA6000C", -- 00000704 - X"00151D42", -- 00000708 - X"00144582", -- 0000070C - X"00143280", -- 00000710 - X"001512C0", -- 00000714 - X"00C8B825", -- 00000718 - X"00431025", -- 0000071C - X"00113E02", -- 00000720 - X"00111A00", -- 00000724 - X"0059A821", -- 00000728 - X"00671825", -- 0000072C - X"00171027", -- 00000730 - X"00798821", -- 00000734 - X"8CA80038", -- 00000738 - X"8CA60004", -- 0000073C - X"02B81826", -- 00000740 - X"00581025", -- 00000744 - X"00771826", -- 00000748 - X"00511026", -- 0000074C - X"0320F021", -- 00000750 - X"00661821", -- 00000754 - X"00481021", -- 00000758 - X"0323C821", -- 0000075C - X"005E1021", -- 00000760 - X"004BF021", -- 00000764 - X"AFA80024", -- 00000768 - X"00191C82", -- 0000076C - X"00184582", -- 00000770 - X"00183280", -- 00000774 - X"00191380", -- 00000778 - X"00C8B025", -- 0000077C - X"00431025", -- 00000780 - X"001E3DC2", -- 00000784 - X"001E1A40", -- 00000788 - X"0053C821", -- 0000078C - X"00671825", -- 00000790 - X"00161027", -- 00000794 - X"0073F021", -- 00000798 - X"8CA70008", -- 0000079C - X"8CA8001C", -- 000007A0 - X"03351826", -- 000007A4 - X"00511025", -- 000007A8 - X"00761826", -- 000007AC - X"005E1026", -- 000007B0 - X"02609021", -- 000007B4 - X"00671821", -- 000007B8 - X"00481021", -- 000007BC - X"02639821", -- 000007C0 - X"00521021", -- 000007C4 - X"004B9021", -- 000007C8 - X"AFA70000", -- 000007CC - X"00113582", -- 000007D0 - X"00133C42", -- 000007D4 - X"00131BC0", -- 000007D8 - X"00111280", -- 000007DC - X"00468825", -- 000007E0 - X"00671825", -- 000007E4 - X"001215C2", -- 000007E8 - X"00123240", -- 000007EC - X"00779821", -- 000007F0 - X"00C23025", -- 000007F4 - X"00153D82", -- 000007F8 - X"00111027", -- 000007FC - X"00151A80", -- 00000800 - X"00D79021", -- 00000804 - X"0067A825", -- 00000808 - X"8CA60000", -- 0000080C - X"8CA7000C", -- 00000810 - X"02791826", -- 00000814 - X"005E1025", -- 00000818 - X"00751826", -- 0000081C - X"00521026", -- 00000820 - X"00671821", -- 00000824 - X"00461021", -- 00000828 - X"02E3A021", -- 0000082C - X"00571021", -- 00000830 - X"004BB821", -- 00000834 - X"AFA60008", -- 00000838 - X"00143D02", -- 0000083C - X"001E3582", -- 00000840 - X"00141B00", -- 00000844 - X"001E1280", -- 00000848 - X"0046F025", -- 0000084C - X"00671825", -- 00000850 - X"00171542", -- 00000854 - X"001732C0", -- 00000858 - X"0076A021", -- 0000085C - X"00C23025", -- 00000860 - X"00193D82", -- 00000864 - X"001E1027", -- 00000868 - X"00191A80", -- 0000086C - X"00D6B821", -- 00000870 - X"0067C825", -- 00000874 - X"8CA60010", -- 00000878 - X"AFA80014", -- 0000087C - X"02931826", -- 00000880 - X"8CA80024", -- 00000884 - X"00521025", -- 00000888 - X"00791826", -- 0000088C - X"00571026", -- 00000890 - X"00661821", -- 00000894 - X"00481021", -- 00000898 - X"02C3C021", -- 0000089C - X"00561021", -- 000008A0 - X"004BB021", -- 000008A4 - X"00183EC2", -- 000008A8 - X"00123582", -- 000008AC - X"00181940", -- 000008B0 - X"00121280", -- 000008B4 - X"00469025", -- 000008B8 - X"00671825", -- 000008BC - X"001614C2", -- 000008C0 - X"00163340", -- 000008C4 - X"0075C021", -- 000008C8 - X"00C23025", -- 000008CC - X"00133D82", -- 000008D0 - X"00121027", -- 000008D4 - X"00131A80", -- 000008D8 - X"00D1B021", -- 000008DC - X"00679825", -- 000008E0 - X"00571025", -- 000008E4 - X"8FA70000", -- 000008E8 - X"AFA80010", -- 000008EC - X"03141826", -- 000008F0 - X"8CA80014", -- 000008F4 - X"00561026", -- 000008F8 - X"00731826", -- 000008FC - X"00471021", -- 00000900 - X"00681821", -- 00000904 - X"00511021", -- 00000908 - X"004B8821", -- 0000090C - X"02A3A821", -- 00000910 - X"00173582", -- 00000914 - X"00171280", -- 00000918 - X"0046B825", -- 0000091C - X"AFA7001C", -- 00000920 - X"00111442", -- 00000924 - X"00153E02", -- 00000928 - X"00151A00", -- 0000092C - X"001133C0", -- 00000930 - X"00671825", -- 00000934 - X"00C23025", -- 00000938 - X"00143D82", -- 0000093C - X"00141280", -- 00000940 - X"0047A025", -- 00000944 - X"8CA2002C", -- 00000948 - X"0079A821", -- 0000094C - X"00171827", -- 00000950 - X"AFA2002C", -- 00000954 - X"00DE8821", -- 00000958 - X"8FA7002C", -- 0000095C - X"8CA60018", -- 00000960 - X"02B81026", -- 00000964 - X"00761825", -- 00000968 - X"00541026", -- 0000096C - X"00711826", -- 00000970 - X"00461021", -- 00000974 - X"00671821", -- 00000978 - X"0322C821", -- 0000097C - X"007E1821", -- 00000980 - X"006BF021", -- 00000984 - X"00193E42", -- 00000988 - X"00163582", -- 0000098C - X"001919C0", -- 00000990 - X"00161280", -- 00000994 - X"0046B025", -- 00000998 - X"00671825", -- 0000099C - X"001E1442", -- 000009A0 - X"001E33C0", -- 000009A4 - X"0073C821", -- 000009A8 - X"00C23025", -- 000009AC - X"00183D82", -- 000009B0 - X"00161027", -- 000009B4 - X"00181A80", -- 000009B8 - X"00D2F021", -- 000009BC - X"0067C025", -- 000009C0 - X"8CA80010", -- 000009C4 - X"8CA6001C", -- 000009C8 - X"03351826", -- 000009CC - X"00511025", -- 000009D0 - X"00781826", -- 000009D4 - X"005E1026", -- 000009D8 - X"00661821", -- 000009DC - X"00481021", -- 000009E0 - X"02639821", -- 000009E4 - X"00521021", -- 000009E8 - X"004B9021", -- 000009EC - X"00133DC2", -- 000009F0 - X"00113582", -- 000009F4 - X"00131A40", -- 000009F8 - X"00111280", -- 000009FC - X"00468825", -- 00000A00 - X"00671825", -- 00000A04 - X"001216C2", -- 00000A08 - X"00123140", -- 00000A0C - X"00749821", -- 00000A10 - X"00C23025", -- 00000A14 - X"00153D82", -- 00000A18 - X"00111827", -- 00000A1C - X"00151280", -- 00000A20 - X"00D79021", -- 00000A24 - X"0047A825", -- 00000A28 - X"AFA80004", -- 00000A2C - X"8CA70034", -- 00000A30 - X"8CA80020", -- 00000A34 - X"02791026", -- 00000A38 - X"007E1825", -- 00000A3C - X"00551026", -- 00000A40 - X"00721826", -- 00000A44 - X"00481021", -- 00000A48 - X"00671821", -- 00000A4C - X"0282A021", -- 00000A50 - X"00771821", -- 00000A54 - X"006BB821", -- 00000A58 - X"AFA70034", -- 00000A5C - X"001E3582", -- 00000A60 - X"00143D42", -- 00000A64 - X"00141AC0", -- 00000A68 - X"001E1280", -- 00000A6C - X"0046F025", -- 00000A70 - X"00671825", -- 00000A74 - X"00171642", -- 00000A78 - X"001731C0", -- 00000A7C - X"0078A021", -- 00000A80 - X"00C23025", -- 00000A84 - X"00193D82", -- 00000A88 - X"001E1827", -- 00000A8C - X"00191280", -- 00000A90 - X"8CAC0018", -- 00000A94 - X"00D6B821", -- 00000A98 - X"0047C825", -- 00000A9C - X"8CA60024", -- 00000AA0 - X"02931026", -- 00000AA4 - X"00721825", -- 00000AA8 - X"00591026", -- 00000AAC - X"00771826", -- 00000AB0 - X"00461021", -- 00000AB4 - X"006C1821", -- 00000AB8 - X"0302C021", -- 00000ABC - X"00761821", -- 00000AC0 - X"006BB021", -- 00000AC4 - X"00183CC2", -- 00000AC8 - X"00123582", -- 00000ACC - X"00181B40", -- 00000AD0 - X"00121280", -- 00000AD4 - X"00469025", -- 00000AD8 - X"00671825", -- 00000ADC - X"00161642", -- 00000AE0 - X"001631C0", -- 00000AE4 - X"0075C021", -- 00000AE8 - X"00C23025", -- 00000AEC - X"00133D82", -- 00000AF0 - X"00121827", -- 00000AF4 - X"00131280", -- 00000AF8 - X"00D1B021", -- 00000AFC - X"00479825", -- 00000B00 - X"8CA80028", -- 00000B04 - X"8CA7003C", -- 00000B08 - X"03141026", -- 00000B0C - X"00771825", -- 00000B10 - X"00531026", -- 00000B14 - X"00761826", -- 00000B18 - X"00481021", -- 00000B1C - X"00671821", -- 00000B20 - X"02A2A821", -- 00000B24 - X"00711821", -- 00000B28 - X"AFA70030", -- 00000B2C - X"006B8821", -- 00000B30 - X"00153C82", -- 00000B34 - X"00173582", -- 00000B38 - X"00151B80", -- 00000B3C - X"00171280", -- 00000B40 - X"0046B825", -- 00000B44 - X"00671825", -- 00000B48 - X"00111602", -- 00000B4C - X"00113200", -- 00000B50 - X"0079A821", -- 00000B54 - X"00C23025", -- 00000B58 - X"00143D82", -- 00000B5C - X"00171827", -- 00000B60 - X"00141280", -- 00000B64 - X"8CAD0020", -- 00000B68 - X"00DE8821", -- 00000B6C - X"0047A025", -- 00000B70 - X"8CA6002C", -- 00000B74 - X"02B81026", -- 00000B78 - X"00761825", -- 00000B7C - X"00541026", -- 00000B80 - X"00711826", -- 00000B84 - X"00461021", -- 00000B88 - X"006D1821", -- 00000B8C - X"0322C821", -- 00000B90 - X"007E1821", -- 00000B94 - X"006BF021", -- 00000B98 - X"00193C42", -- 00000B9C - X"00163582", -- 00000BA0 - X"00191BC0", -- 00000BA4 - X"00161280", -- 00000BA8 - X"0046B025", -- 00000BAC - X"00671825", -- 00000BB0 - X"001E1542", -- 00000BB4 - X"001E32C0", -- 00000BB8 - X"0073C821", -- 00000BBC - X"00C23025", -- 00000BC0 - X"00183D82", -- 00000BC4 - X"00161027", -- 00000BC8 - X"00181A80", -- 00000BCC - X"00D2F021", -- 00000BD0 - X"0067C025", -- 00000BD4 - X"8CA80030", -- 00000BD8 - X"8CA70004", -- 00000BDC - X"03351826", -- 00000BE0 - X"00511025", -- 00000BE4 - X"00781826", -- 00000BE8 - X"005E1026", -- 00000BEC - X"00681821", -- 00000BF0 - X"00471021", -- 00000BF4 - X"02639821", -- 00000BF8 - X"00521021", -- 00000BFC - X"AFA70028", -- 00000C00 - X"004B9021", -- 00000C04 - X"00133E82", -- 00000C08 - X"00113582", -- 00000C0C - X"00131980", -- 00000C10 - X"00111280", -- 00000C14 - X"00468825", -- 00000C18 - X"00671825", -- 00000C1C - X"00121482", -- 00000C20 - X"00123380", -- 00000C24 - X"00749821", -- 00000C28 - X"00C23025", -- 00000C2C - X"00153D82", -- 00000C30 - X"00111027", -- 00000C34 - X"00151A80", -- 00000C38 - X"00D79021", -- 00000C3C - X"0067A825", -- 00000C40 - X"8CA60028", -- 00000C44 - X"8CA70034", -- 00000C48 - X"02791826", -- 00000C4C - X"005E1025", -- 00000C50 - X"00751826", -- 00000C54 - X"00521026", -- 00000C58 - X"00671821", -- 00000C5C - X"00461021", -- 00000C60 - X"0283A021", -- 00000C64 - X"00571021", -- 00000C68 - X"AFA60020", -- 00000C6C - X"004BB821", -- 00000C70 - X"00143E42", -- 00000C74 - X"001E3582", -- 00000C78 - X"001419C0", -- 00000C7C - X"001E1280", -- 00000C80 - X"0046F025", -- 00000C84 - X"00671825", -- 00000C88 - X"00171482", -- 00000C8C - X"00173380", -- 00000C90 - X"0078A021", -- 00000C94 - X"00C23025", -- 00000C98 - X"00193D82", -- 00000C9C - X"001E1827", -- 00000CA0 - X"00191280", -- 00000CA4 - X"8CB0000C", -- 00000CA8 - X"00D6B821", -- 00000CAC - X"0047C825", -- 00000CB0 - X"8CA80038", -- 00000CB4 - X"02931026", -- 00000CB8 - X"00721825", -- 00000CBC - X"00591026", -- 00000CC0 - X"00771826", -- 00000CC4 - X"00481021", -- 00000CC8 - X"00701821", -- 00000CCC - X"0302C021", -- 00000CD0 - X"00761821", -- 00000CD4 - X"006BB021", -- 00000CD8 - X"00183DC2", -- 00000CDC - X"00181A40", -- 00000CE0 - X"00671825", -- 00000CE4 - X"00123582", -- 00000CE8 - X"00121280", -- 00000CEC - X"0075C021", -- 00000CF0 - X"00469025", -- 00000CF4 - X"00133D82", -- 00000CF8 - X"00161502", -- 00000CFC - X"00163300", -- 00000D00 - X"00131A80", -- 00000D04 - X"00679825", -- 00000D08 - X"00C23025", -- 00000D0C - X"8CA7003C", -- 00000D10 - X"03141826", -- 00000D14 - X"00121027", -- 00000D18 - X"00D1B021", -- 00000D1C - X"00571025", -- 00000D20 - X"8CA60030", -- 00000D24 - X"00731826", -- 00000D28 - X"00671821", -- 00000D2C - X"00561026", -- 00000D30 - X"02A3A821", -- 00000D34 - X"00461021", -- 00000D38 - X"AFA60018", -- 00000D3C - X"00151E02", -- 00000D40 - X"00511021", -- 00000D44 - X"00153200", -- 00000D48 - X"004B8821", -- 00000D4C - X"00C33025", -- 00000D50 - X"00173D82", -- 00000D54 - X"00171280", -- 00000D58 - X"0047B825", -- 00000D5C - X"00D9A821", -- 00000D60 - X"00114682", -- 00000D64 - X"00111980", -- 00000D68 - X"00143D82", -- 00000D6C - X"00141280", -- 00000D70 - X"0047A025", -- 00000D74 - X"00681825", -- 00000D78 - X"00153027", -- 00000D7C - X"007E8821", -- 00000D80 - X"8CA8001C", -- 00000D84 - X"00D43024", -- 00000D88 - X"02B81024", -- 00000D8C - X"00173827", -- 00000D90 - X"00F63824", -- 00000D94 - X"02371824", -- 00000D98 - X"00461025", -- 00000D9C - X"00671825", -- 00000DA0 - X"00481021", -- 00000DA4 - X"3C0B5A82", -- 00000DA8 - X"356B7999", -- 00000DAC - X"00591021", -- 00000DB0 - X"006C1821", -- 00000DB4 - X"3C0A5C4D", -- 00000DB8 - X"354AD124", -- 00000DBC - X"004BC821", -- 00000DC0 - X"007E1821", -- 00000DC4 - X"006AF021", -- 00000DC8 - X"00194642", -- 00000DCC - X"001919C0", -- 00000DD0 - X"001E4DC2", -- 00000DD4 - X"00681825", -- 00000DD8 - X"00163D82", -- 00000DDC - X"001E3240", -- 00000DE0 - X"00161280", -- 00000DE4 - X"0073C821", -- 00000DE8 - X"0047B025", -- 00000DEC - X"00C93025", -- 00000DF0 - X"00181D82", -- 00000DF4 - X"00181280", -- 00000DF8 - X"00D2F021", -- 00000DFC - X"0043C025", -- 00000E00 - X"00193027", -- 00000E04 - X"00D83024", -- 00000E08 - X"03351024", -- 00000E0C - X"00163827", -- 00000E10 - X"00F13824", -- 00000E14 - X"03D61824", -- 00000E18 - X"00461025", -- 00000E1C - X"8FA6002C", -- 00000E20 - X"00671825", -- 00000E24 - X"8CA70010", -- 00000E28 - X"00661821", -- 00000E2C - X"00721821", -- 00000E30 - X"00471021", -- 00000E34 - X"006A9021", -- 00000E38 - X"00531021", -- 00000E3C - X"004B9821", -- 00000E40 - X"00123CC2", -- 00000E44 - X"00113582", -- 00000E48 - X"00121B40", -- 00000E4C - X"00111280", -- 00000E50 - X"00468825", -- 00000E54 - X"00671825", -- 00000E58 - X"00133682", -- 00000E5C - X"00131180", -- 00000E60 - X"00779021", -- 00000E64 - X"00461025", -- 00000E68 - X"00113027", -- 00000E6C - X"00549821", -- 00000E70 - X"00DE3024", -- 00000E74 - X"02511024", -- 00000E78 - X"00153D82", -- 00000E7C - X"00151A80", -- 00000E80 - X"00461025", -- 00000E84 - X"0067A825", -- 00000E88 - X"00501021", -- 00000E8C - X"00131827", -- 00000E90 - X"8CA80034", -- 00000E94 - X"00751824", -- 00000E98 - X"02793024", -- 00000E9C - X"00571021", -- 00000EA0 - X"004AB821", -- 00000EA4 - X"00C33025", -- 00000EA8 - X"00C83021", -- 00000EAC - X"001E3D82", -- 00000EB0 - X"00174442", -- 00000EB4 - X"00171BC0", -- 00000EB8 - X"001E1280", -- 00000EBC - X"0047F025", -- 00000EC0 - X"00681825", -- 00000EC4 - X"00D43021", -- 00000EC8 - X"0076B821", -- 00000ECC - X"00CBA021", -- 00000ED0 - X"001E1027", -- 00000ED4 - X"00143E02", -- 00000ED8 - X"00521024", -- 00000EDC - X"02FE1824", -- 00000EE0 - X"00143200", -- 00000EE4 - X"00C73025", -- 00000EE8 - X"00621825", -- 00000EEC - X"00193D82", -- 00000EF0 - X"00191280", -- 00000EF4 - X"0047C825", -- 00000EF8 - X"8FA20014", -- 00000EFC - X"00D8A021", -- 00000F00 - X"00621821", -- 00000F04 - X"00761821", -- 00000F08 - X"00141027", -- 00000F0C - X"006AB021", -- 00000F10 - X"00591024", -- 00000F14 - X"8CA30004", -- 00000F18 - X"02933024", -- 00000F1C - X"00C23025", -- 00000F20 - X"00164642", -- 00000F24 - X"00C33021", -- 00000F28 - X"00123D82", -- 00000F2C - X"001619C0", -- 00000F30 - X"00121280", -- 00000F34 - X"00479025", -- 00000F38 - X"00681825", -- 00000F3C - X"0071B021", -- 00000F40 - X"00123827", -- 00000F44 - X"00F73824", -- 00000F48 - X"02D21824", -- 00000F4C - X"00D83021", -- 00000F50 - X"00CBC021", -- 00000F54 - X"00671825", -- 00000F58 - X"8FA70008", -- 00000F5C - X"001834C2", -- 00000F60 - X"00181340", -- 00000F64 - X"00461025", -- 00000F68 - X"00671821", -- 00000F6C - X"0055C021", -- 00000F70 - X"00133582", -- 00000F74 - X"00131280", -- 00000F78 - X"00711821", -- 00000F7C - X"00469825", -- 00000F80 - X"006A8821", -- 00000F84 - X"00181027", -- 00000F88 - X"00531024", -- 00000F8C - X"03141824", -- 00000F90 - X"00114502", -- 00000F94 - X"00113B00", -- 00000F98 - X"00E83825", -- 00000F9C - X"00621825", -- 00000FA0 - X"8CA80028", -- 00000FA4 - X"00173582", -- 00000FA8 - X"00171280", -- 00000FAC - X"0046B825", -- 00000FB0 - X"00FE8821", -- 00000FB4 - X"00681821", -- 00000FB8 - X"00173027", -- 00000FBC - X"00D63024", -- 00000FC0 - X"02371024", -- 00000FC4 - X"00751821", -- 00000FC8 - X"006BA821", -- 00000FCC - X"00461025", -- 00000FD0 - X"8FA60034", -- 00000FD4 - X"00153D42", -- 00000FD8 - X"00151AC0", -- 00000FDC - X"00671825", -- 00000FE0 - X"00461021", -- 00000FE4 - X"0079A821", -- 00000FE8 - X"005E1021", -- 00000FEC - X"00143582", -- 00000FF0 - X"00141A80", -- 00000FF4 - X"0066A025", -- 00000FF8 - X"004AF021", -- 00000FFC - X"00153827", -- 00001000 - X"00F43824", -- 00001004 - X"001E4E02", -- 00001008 - X"02B83024", -- 0000100C - X"00164582", -- 00001010 - X"001E1A00", -- 00001014 - X"00161280", -- 00001018 - X"0048B025", -- 0000101C - X"00691825", -- 00001020 - X"00C73025", -- 00001024 - X"0072F021", -- 00001028 - X"00CC3021", -- 0000102C - X"00161827", -- 00001030 - X"8FA8000C", -- 00001034 - X"00711824", -- 00001038 - X"03D61024", -- 0000103C - X"00D93021", -- 00001040 - X"00CBC821", -- 00001044 - X"00431025", -- 00001048 - X"00193DC2", -- 0000104C - X"00481021", -- 00001050 - X"00191A40", -- 00001054 - X"00671825", -- 00001058 - X"00521021", -- 0000105C - X"0073C821", -- 00001060 - X"004A9021", -- 00001064 - X"00181D82", -- 00001068 - X"00181280", -- 0000106C - X"0043C025", -- 00001070 - X"00113582", -- 00001074 - X"00191827", -- 00001078 - X"00111280", -- 0000107C - X"00468825", -- 00001080 - X"001245C2", -- 00001084 - X"00781824", -- 00001088 - X"03351024", -- 0000108C - X"00123A40", -- 00001090 - X"00E83825", -- 00001094 - X"00431025", -- 00001098 - X"8CA3003C", -- 0000109C - X"00F79021", -- 000010A0 - X"00113027", -- 000010A4 - X"00DE3024", -- 000010A8 - X"00431021", -- 000010AC - X"02511824", -- 000010B0 - X"00661825", -- 000010B4 - X"8FA60020", -- 000010B8 - X"00531021", -- 000010BC - X"004B9821", -- 000010C0 - X"00661821", -- 000010C4 - X"00771821", -- 000010C8 - X"00133642", -- 000010CC - X"001311C0", -- 000010D0 - X"006AB821", -- 000010D4 - X"00461025", -- 000010D8 - X"00549821", -- 000010DC - X"00174D42", -- 000010E0 - X"00154582", -- 000010E4 - X"001E3D82", -- 000010E8 - X"00171AC0", -- 000010EC - X"00153280", -- 000010F0 - X"001E1280", -- 000010F4 - X"0047F025", -- 000010F8 - X"00C8A825", -- 000010FC - X"00691825", -- 00001100 - X"00131027", -- 00001104 - X"0076B821", -- 00001108 - X"00551024", -- 0000110C - X"02791824", -- 00001110 - X"001E3027", -- 00001114 - X"8FA80024", -- 00001118 - X"00D23024", -- 0000111C - X"00621825", -- 00001120 - X"02FE1024", -- 00001124 - X"00461025", -- 00001128 - X"00701821", -- 0000112C - X"00741821", -- 00001130 - X"00481021", -- 00001134 - X"006BA021", -- 00001138 - X"00561021", -- 0000113C - X"004AB021", -- 00001140 - X"00141C42", -- 00001144 - X"001433C0", -- 00001148 - X"00C33025", -- 0000114C - X"00164642", -- 00001150 - X"00123D82", -- 00001154 - X"001619C0", -- 00001158 - X"00121280", -- 0000115C - X"00479025", -- 00001160 - X"00D8A021", -- 00001164 - X"00681825", -- 00001168 - X"00193D82", -- 0000116C - X"00191280", -- 00001170 - X"0047C825", -- 00001174 - X"0071B021", -- 00001178 - X"00143027", -- 0000117C - X"00123827", -- 00001180 - X"00D93024", -- 00001184 - X"00F73824", -- 00001188 - X"02931024", -- 0000118C - X"02D21824", -- 00001190 - X"00461025", -- 00001194 - X"00671825", -- 00001198 - X"8CA60030", -- 0000119C - X"8FA70030", -- 000011A0 - X"00461021", -- 000011A4 - X"00671821", -- 000011A8 - X"00581021", -- 000011AC - X"00711821", -- 000011B0 - X"004BC021", -- 000011B4 - X"006A8821", -- 000011B8 - X"00184642", -- 000011BC - X"00114E42", -- 000011C0 - X"00173D82", -- 000011C4 - X"001819C0", -- 000011C8 - X"001131C0", -- 000011CC - X"00171280", -- 000011D0 - X"0047B825", -- 000011D4 - X"00681825", -- 000011D8 - X"00C93025", -- 000011DC - X"0075C021", -- 000011E0 - X"00DE8821", -- 000011E4 - X"00131D82", -- 000011E8 - X"00173827", -- 000011EC - X"00131280", -- 000011F0 - X"00439825", -- 000011F4 - X"00F63824", -- 000011F8 - X"02371824", -- 000011FC - X"00183027", -- 00001200 - X"8CA80000", -- 00001204 - X"00D33024", -- 00001208 - X"03141024", -- 0000120C - X"00671825", -- 00001210 - X"00461025", -- 00001214 - X"006D1821", -- 00001218 - X"007E1821", -- 0000121C - X"00481021", -- 00001220 - X"006AF021", -- 00001224 - X"00551021", -- 00001228 - X"004BA821", -- 0000122C - X"001E3D02", -- 00001230 - X"00163582", -- 00001234 - X"001E1B00", -- 00001238 - X"00161280", -- 0000123C - X"0046B025", -- 00001240 - X"00671825", -- 00001244 - X"00153502", -- 00001248 - X"00151300", -- 0000124C - X"0072F021", -- 00001250 - X"00461025", -- 00001254 - X"00163027", -- 00001258 - X"0059A821", -- 0000125C - X"00D13024", -- 00001260 - X"03D61024", -- 00001264 - X"00143D82", -- 00001268 - X"00141A80", -- 0000126C - X"00461025", -- 00001270 - X"8FA60018", -- 00001274 - X"0067A025", -- 00001278 - X"00151827", -- 0000127C - X"8CA70024", -- 00001280 - X"00741824", -- 00001284 - X"00461021", -- 00001288 - X"02B83024", -- 0000128C - X"00C33025", -- 00001290 - X"00521021", -- 00001294 - X"004A9021", -- 00001298 - X"00C73021", -- 0000129C - X"00124642", -- 000012A0 - X"00D93021", -- 000012A4 - X"00113D82", -- 000012A8 - X"001219C0", -- 000012AC - X"00111280", -- 000012B0 - X"00478825", -- 000012B4 - X"00CBC821", -- 000012B8 - X"00681825", -- 000012BC - X"00779021", -- 000012C0 - X"00193C42", -- 000012C4 - X"001933C0", -- 000012C8 - X"00111027", -- 000012CC - X"00C73025", -- 000012D0 - X"005E1024", -- 000012D4 - X"02511824", -- 000012D8 - X"00D3C821", -- 000012DC - X"8FA80004", -- 000012E0 - X"00621825", -- 000012E4 - X"00183D82", -- 000012E8 - X"00181280", -- 000012EC - X"0047C025", -- 000012F0 - X"00191027", -- 000012F4 - X"00581024", -- 000012F8 - X"03353024", -- 000012FC - X"00681821", -- 00001300 - X"00771821", -- 00001304 - X"00C23025", -- 00001308 - X"8CA20014", -- 0000130C - X"006AB821", -- 00001310 - X"00174682", -- 00001314 - X"00C23021", -- 00001318 - X"001E3D82", -- 0000131C - X"00171980", -- 00001320 - X"001E1280", -- 00001324 - X"0047F025", -- 00001328 - X"00681825", -- 0000132C - X"0076B821", -- 00001330 - X"00D33021", -- 00001334 - X"001E3827", -- 00001338 - X"00CB9821", -- 0000133C - X"00F23824", -- 00001340 - X"02FE1824", -- 00001344 - X"001335C2", -- 00001348 - X"00131240", -- 0000134C - X"00671825", -- 00001350 - X"8FA70010", -- 00001354 - X"00461025", -- 00001358 - X"00549821", -- 0000135C - X"00153582", -- 00001360 - X"00671821", -- 00001364 - X"00151280", -- 00001368 - X"0046A825", -- 0000136C - X"00761821", -- 00001370 - X"00131027", -- 00001374 - X"006AB021", -- 00001378 - X"00551024", -- 0000137C - X"02791824", -- 00001380 - X"00164442", -- 00001384 - X"00621825", -- 00001388 - X"00123582", -- 0000138C - X"00163BC0", -- 00001390 - X"00121280", -- 00001394 - X"00469025", -- 00001398 - X"00E83825", -- 0000139C - X"8FA80000", -- 000013A0 - X"00F1B021", -- 000013A4 - X"00123027", -- 000013A8 - X"00D73024", -- 000013AC - X"02D21024", -- 000013B0 - X"00681821", -- 000013B4 - X"00741821", -- 000013B8 - X"00461025", -- 000013BC - X"8FA60028", -- 000013C0 - X"006BA021", -- 000013C4 - X"00143D42", -- 000013C8 - X"00141AC0", -- 000013CC - X"00461021", -- 000013D0 - X"00671825", -- 000013D4 - X"00511021", -- 000013D8 - X"0078A021", -- 000013DC - X"004A8821", -- 000013E0 - X"00193582", -- 000013E4 - X"00191A80", -- 000013E8 - X"0066C825", -- 000013EC - X"00114CC2", -- 000013F0 - X"00143827", -- 000013F4 - X"00174582", -- 000013F8 - X"00111B40", -- 000013FC - X"00171280", -- 00001400 - X"0048B825", -- 00001404 - X"00F93824", -- 00001408 - X"02933024", -- 0000140C - X"00691825", -- 00001410 - X"007E8821", -- 00001414 - X"00C73025", -- 00001418 - X"00171827", -- 0000141C - X"8CA70038", -- 00001420 - X"8FA8001C", -- 00001424 - X"00761824", -- 00001428 - X"02371024", -- 0000142C - X"00C73021", -- 00001430 - X"00431025", -- 00001434 - X"00D83021", -- 00001438 - X"00481021", -- 0000143C - X"00CBC021", -- 00001440 - X"005E1021", -- 00001444 - X"004AF021", -- 00001448 - X"00183E42", -- 0000144C - X"001819C0", -- 00001450 - X"00133582", -- 00001454 - X"00131280", -- 00001458 - X"00469825", -- 0000145C - X"00671825", -- 00001460 - X"001E32C0", -- 00001464 - X"001E3D42", -- 00001468 - X"0075C021", -- 0000146C - X"00C73025", -- 00001470 - X"00D2F021", -- 00001474 - X"00181827", -- 00001478 - X"00163D82", -- 0000147C - X"00163280", -- 00001480 - X"00C7B025", -- 00001484 - X"00731824", -- 00001488 - X"8CA6002C", -- 0000148C - X"03141024", -- 00001490 - X"00431025", -- 00001494 - X"00111827", -- 00001498 - X"8FA70030", -- 0000149C - X"007E1825", -- 000014A0 - X"00461021", -- 000014A4 - X"00551021", -- 000014A8 - X"00761826", -- 000014AC - X"004BA821", -- 000014B0 - X"00671821", -- 000014B4 - X"3C0A6D70", -- 000014B8 - X"354A3EF3", -- 000014BC - X"001534C2", -- 000014C0 - X"00721821", -- 000014C4 - X"00151340", -- 000014C8 - X"006A9021", -- 000014CC - X"00461025", -- 000014D0 - X"0059A821", -- 000014D4 - X"001245C2", -- 000014D8 - X"00143582", -- 000014DC - X"00121A40", -- 000014E0 - X"00141280", -- 000014E4 - X"0046A025", -- 000014E8 - X"00681825", -- 000014EC - X"00153827", -- 000014F0 - X"00779021", -- 000014F4 - X"00F44024", -- 000014F8 - X"02B81824", -- 000014FC - X"00114D82", -- 00001500 - X"001E1027", -- 00001504 - X"00113280", -- 00001508 - X"00C98825", -- 0000150C - X"00681825", -- 00001510 - X"8FA6000C", -- 00001514 - X"00521025", -- 00001518 - X"00511026", -- 0000151C - X"006D1821", -- 00001520 - X"00791821", -- 00001524 - X"00461021", -- 00001528 - X"006BC821", -- 0000152C - X"00571021", -- 00001530 - X"004AB821", -- 00001534 - X"00191D02", -- 00001538 - X"00191300", -- 0000153C - X"00431025", -- 00001540 - X"00173642", -- 00001544 - X"001719C0", -- 00001548 - X"0053C821", -- 0000154C - X"00661825", -- 00001550 - X"00181280", -- 00001554 - X"00183582", -- 00001558 - X"0076B821", -- 0000155C - X"0046C025", -- 00001560 - X"00F93825", -- 00001564 - X"001E3582", -- 00001568 - X"00121027", -- 0000156C - X"001E1A80", -- 00001570 - X"0066F025", -- 00001574 - X"00F83826", -- 00001578 - X"8FA30028", -- 0000157C - X"00571025", -- 00001580 - X"005E1026", -- 00001584 - X"00F03821", -- 00001588 - X"3C096ED9", -- 0000158C - X"3529EBA1", -- 00001590 - X"00F33821", -- 00001594 - X"00431021", -- 00001598 - X"00E99821", -- 0000159C - X"00561021", -- 000015A0 - X"004AB021", -- 000015A4 - X"00131D42", -- 000015A8 - X"001312C0", -- 000015AC - X"00431025", -- 000015B0 - X"00163442", -- 000015B4 - X"00161BC0", -- 000015B8 - X"00549821", -- 000015BC - X"00661825", -- 000015C0 - X"00153D82", -- 000015C4 - X"00151280", -- 000015C8 - X"0071B021", -- 000015CC - X"0047A825", -- 000015D0 - X"00193027", -- 000015D4 - X"00123D82", -- 000015D8 - X"00121A80", -- 000015DC - X"00679025", -- 000015E0 - X"00D33025", -- 000015E4 - X"8CA70028", -- 000015E8 - X"00171027", -- 000015EC - X"00D53026", -- 000015F0 - X"00561025", -- 000015F4 - X"00521026", -- 000015F8 - X"00C73021", -- 000015FC - X"00D43021", -- 00001600 - X"00501021", -- 00001604 - X"00C9A021", -- 00001608 - X"00511021", -- 0000160C - X"004A8821", -- 00001610 - X"00141CC2", -- 00001614 - X"00141340", -- 00001618 - X"00431025", -- 0000161C - X"00113542", -- 00001620 - X"00111AC0", -- 00001624 - X"0058A021", -- 00001628 - X"00661825", -- 0000162C - X"00193D82", -- 00001630 - X"00133027", -- 00001634 - X"00191280", -- 00001638 - X"007E8821", -- 0000163C - X"0047C825", -- 00001640 - X"8CA80038", -- 00001644 - X"00D43025", -- 00001648 - X"00173D82", -- 0000164C - X"00161027", -- 00001650 - X"00171A80", -- 00001654 - X"0067B825", -- 00001658 - X"00D93026", -- 0000165C - X"8FA30014", -- 00001660 - X"00511025", -- 00001664 - X"00571026", -- 00001668 - X"00C83021", -- 0000166C - X"00D83021", -- 00001670 - X"00431021", -- 00001674 - X"00C9C021", -- 00001678 - X"005E1021", -- 0000167C - X"004AF021", -- 00001680 - X"00181E82", -- 00001684 - X"00181180", -- 00001688 - X"00431025", -- 0000168C - X"001E3602", -- 00001690 - X"001E1A00", -- 00001694 - X"0055C021", -- 00001698 - X"00661825", -- 0000169C - X"00133D82", -- 000016A0 - X"00131280", -- 000016A4 - X"0072F021", -- 000016A8 - X"00479825", -- 000016AC - X"00143027", -- 000016B0 - X"00163D82", -- 000016B4 - X"00161A80", -- 000016B8 - X"0067B025", -- 000016BC - X"00D83025", -- 000016C0 - X"8CA70010", -- 000016C4 - X"00111027", -- 000016C8 - X"00D33026", -- 000016CC - X"005E1025", -- 000016D0 - X"00561026", -- 000016D4 - X"00C73021", -- 000016D8 - X"00D53021", -- 000016DC - X"00481021", -- 000016E0 - X"00C9A821", -- 000016E4 - X"00521021", -- 000016E8 - X"004A9021", -- 000016EC - X"00151E42", -- 000016F0 - X"001511C0", -- 000016F4 - X"00431025", -- 000016F8 - X"00123682", -- 000016FC - X"00121980", -- 00001700 - X"0059A821", -- 00001704 - X"00661825", -- 00001708 - X"00143D82", -- 0000170C - X"00141280", -- 00001710 - X"00779021", -- 00001714 - X"0047A025", -- 00001718 - X"00183027", -- 0000171C - X"00113D82", -- 00001720 - X"00111A80", -- 00001724 - X"00678825", -- 00001728 - X"00D53025", -- 0000172C - X"8CA30024", -- 00001730 - X"001E1027", -- 00001734 - X"00D43026", -- 00001738 - X"00521025", -- 0000173C - X"00511026", -- 00001740 - X"00C33021", -- 00001744 - X"00D93021", -- 00001748 - X"004C1021", -- 0000174C - X"00C9C821", -- 00001750 - X"00571021", -- 00001754 - X"004AB821", -- 00001758 - X"00191C82", -- 0000175C - X"00191380", -- 00001760 - X"00431025", -- 00001764 - X"00173682", -- 00001768 - X"00171980", -- 0000176C - X"0053C821", -- 00001770 - X"00661825", -- 00001774 - X"00183D82", -- 00001778 - X"00181280", -- 0000177C - X"0076B821", -- 00001780 - X"0047C025", -- 00001784 - X"00153027", -- 00001788 - X"001E3D82", -- 0000178C - X"001E1A80", -- 00001790 - X"0067F025", -- 00001794 - X"00D93025", -- 00001798 - X"8CA7003C", -- 0000179C - X"00121027", -- 000017A0 - X"8FA80010", -- 000017A4 - X"00D83026", -- 000017A8 - X"00571025", -- 000017AC - X"005E1026", -- 000017B0 - X"00C73021", -- 000017B4 - X"00D33021", -- 000017B8 - X"00481021", -- 000017BC - X"00C99821", -- 000017C0 - X"00561021", -- 000017C4 - X"004AB021", -- 000017C8 - X"00131DC2", -- 000017CC - X"00131240", -- 000017D0 - X"00431025", -- 000017D4 - X"00163482", -- 000017D8 - X"00161B80", -- 000017DC - X"00549821", -- 000017E0 - X"00661825", -- 000017E4 - X"00153D82", -- 000017E8 - X"00193027", -- 000017EC - X"00151280", -- 000017F0 - X"0071B021", -- 000017F4 - X"0047A825", -- 000017F8 - X"00D33025", -- 000017FC - X"00123D82", -- 00001800 - X"00171027", -- 00001804 - X"00121A80", -- 00001808 - X"00679025", -- 0000180C - X"00D53026", -- 00001810 - X"8FA7002C", -- 00001814 - X"00561025", -- 00001818 - X"00521026", -- 0000181C - X"00CD3021", -- 00001820 - X"00D43021", -- 00001824 - X"00471021", -- 00001828 - X"00C9A021", -- 0000182C - X"00511021", -- 00001830 - X"004A8821", -- 00001834 - X"00141CC2", -- 00001838 - X"00141340", -- 0000183C - X"00431025", -- 00001840 - X"00113502", -- 00001844 - X"00111B00", -- 00001848 - X"0058A021", -- 0000184C - X"00661825", -- 00001850 - X"00193D82", -- 00001854 - X"00133027", -- 00001858 - X"00191280", -- 0000185C - X"007E8821", -- 00001860 - X"0047C825", -- 00001864 - X"8CA80004", -- 00001868 - X"00D43025", -- 0000186C - X"00173D82", -- 00001870 - X"00161027", -- 00001874 - X"00171A80", -- 00001878 - X"0067B825", -- 0000187C - X"00D93026", -- 00001880 - X"00511025", -- 00001884 - X"00571026", -- 00001888 - X"00C83021", -- 0000188C - X"00D83021", -- 00001890 - X"004D1021", -- 00001894 - X"00C9C021", -- 00001898 - X"005E1021", -- 0000189C - X"004AF021", -- 000018A0 - X"00181C42", -- 000018A4 - X"001813C0", -- 000018A8 - X"00431025", -- 000018AC - X"001E34C2", -- 000018B0 - X"001E1B40", -- 000018B4 - X"0055C021", -- 000018B8 - X"00661825", -- 000018BC - X"00133D82", -- 000018C0 - X"00131280", -- 000018C4 - X"0072F021", -- 000018C8 - X"00479825", -- 000018CC - X"00143027", -- 000018D0 - X"00163D82", -- 000018D4 - X"00161A80", -- 000018D8 - X"0067B025", -- 000018DC - X"00D83025", -- 000018E0 - X"8FA30000", -- 000018E4 - X"00111027", -- 000018E8 - X"8FA70018", -- 000018EC - X"00D33026", -- 000018F0 - X"005E1025", -- 000018F4 - X"00561026", -- 000018F8 - X"00C33021", -- 000018FC - X"00D53021", -- 00001900 - X"00471021", -- 00001904 - X"00C9A821", -- 00001908 - X"00521021", -- 0000190C - X"004A9021", -- 00001910 - X"00151C82", -- 00001914 - X"00151380", -- 00001918 - X"00431025", -- 0000191C - X"001236C2", -- 00001920 - X"00121940", -- 00001924 - X"0059A821", -- 00001928 - X"00661825", -- 0000192C - X"00143D82", -- 00001930 - X"00183027", -- 00001934 - X"00141280", -- 00001938 - X"00779021", -- 0000193C - X"0047A025", -- 00001940 - X"8CA8001C", -- 00001944 - X"00D53025", -- 00001948 - X"00113D82", -- 0000194C - X"001E1027", -- 00001950 - X"00111A80", -- 00001954 - X"00678825", -- 00001958 - X"00D43026", -- 0000195C - X"8FA3001C", -- 00001960 - X"00521025", -- 00001964 - X"00511026", -- 00001968 - X"00C83021", -- 0000196C - X"00D93021", -- 00001970 - X"00431021", -- 00001974 - X"00C9C821", -- 00001978 - X"00571021", -- 0000197C - X"004AB821", -- 00001980 - X"00191E02", -- 00001984 - X"00191200", -- 00001988 - X"00431025", -- 0000198C - X"00173482", -- 00001990 - X"00171B80", -- 00001994 - X"0053C821", -- 00001998 - X"00661825", -- 0000199C - X"00183D82", -- 000019A0 - X"00181280", -- 000019A4 - X"0076B821", -- 000019A8 - X"0047C025", -- 000019AC - X"00153027", -- 000019B0 - X"001E3D82", -- 000019B4 - X"001E1A80", -- 000019B8 - X"0067F025", -- 000019BC - X"00D93025", -- 000019C0 - X"8CA70000", -- 000019C4 - X"00121027", -- 000019C8 - X"8FA80020", -- 000019CC - X"00D83026", -- 000019D0 - X"00571025", -- 000019D4 - X"005E1026", -- 000019D8 - X"00C73021", -- 000019DC - X"00D33021", -- 000019E0 - X"00481021", -- 000019E4 - X"00C99821", -- 000019E8 - X"00561021", -- 000019EC - X"004AB021", -- 000019F0 - X"00131CC2", -- 000019F4 - X"00131340", -- 000019F8 - X"00431025", -- 000019FC - X"001634C2", -- 00001A00 - X"00161B40", -- 00001A04 - X"00549821", -- 00001A08 - X"00661825", -- 00001A0C - X"00153D82", -- 00001A10 - X"00193027", -- 00001A14 - X"00151280", -- 00001A18 - X"0071B021", -- 00001A1C - X"0047A825", -- 00001A20 - X"00D33025", -- 00001A24 - X"00123D82", -- 00001A28 - X"00171027", -- 00001A2C - X"00121A80", -- 00001A30 - X"00679025", -- 00001A34 - X"00D53026", -- 00001A38 - X"8FA70008", -- 00001A3C - X"00561025", -- 00001A40 - X"00521026", -- 00001A44 - X"00CC3021", -- 00001A48 - X"00D43021", -- 00001A4C - X"00471021", -- 00001A50 - X"00C9A021", -- 00001A54 - X"00511021", -- 00001A58 - X"004A8821", -- 00001A5C - X"00141E82", -- 00001A60 - X"00141180", -- 00001A64 - X"00431025", -- 00001A68 - X"001134C2", -- 00001A6C - X"00111B40", -- 00001A70 - X"0058A021", -- 00001A74 - X"8CA80010", -- 00001A78 - X"00661825", -- 00001A7C - X"00193D82", -- 00001A80 - X"00191280", -- 00001A84 - X"007E8821", -- 00001A88 - X"0047C825", -- 00001A8C - X"00133027", -- 00001A90 - X"00173D82", -- 00001A94 - X"00171A80", -- 00001A98 - X"AFA80038", -- 00001A9C - X"0067B825", -- 00001AA0 - X"00D43025", -- 00001AA4 - X"8CA30034", -- 00001AA8 - X"00161027", -- 00001AAC - X"00D93026", -- 00001AB0 - X"00511025", -- 00001AB4 - X"00571026", -- 00001AB8 - X"00C33021", -- 00001ABC - X"00D83021", -- 00001AC0 - X"00481021", -- 00001AC4 - X"00C9C021", -- 00001AC8 - X"005E1021", -- 00001ACC - X"004AF021", -- 00001AD0 - X"00181EC2", -- 00001AD4 - X"00181140", -- 00001AD8 - X"00431025", -- 00001ADC - X"001E3642", -- 00001AE0 - X"001E19C0", -- 00001AE4 - X"0055C021", -- 00001AE8 - X"00661825", -- 00001AEC - X"00133D82", -- 00001AF0 - X"00131280", -- 00001AF4 - X"0072F021", -- 00001AF8 - X"00479825", -- 00001AFC - X"00143027", -- 00001B00 - X"00163D82", -- 00001B04 - X"00111027", -- 00001B08 - X"00161A80", -- 00001B0C - X"0067B025", -- 00001B10 - X"8FA80034", -- 00001B14 - X"8CA7002C", -- 00001B18 - X"00D83025", -- 00001B1C - X"005E1025", -- 00001B20 - X"00D33026", -- 00001B24 - X"00561026", -- 00001B28 - X"00C73021", -- 00001B2C - X"00481021", -- 00001B30 - X"00D53021", -- 00001B34 - X"00521021", -- 00001B38 - X"00C9A821", -- 00001B3C - X"004A9021", -- 00001B40 - X"00151D02", -- 00001B44 - X"00123EC2", -- 00001B48 - X"00151300", -- 00001B4C - X"00123140", -- 00001B50 - X"00431025", -- 00001B54 - X"00C73025", -- 00001B58 - X"00141A80", -- 00001B5C - X"00143D82", -- 00001B60 - X"00D79021", -- 00001B64 - X"0059A821", -- 00001B68 - X"0067A025", -- 00001B6C - X"00181027", -- 00001B70 - X"00113582", -- 00001B74 - X"00111A80", -- 00001B78 - X"00668825", -- 00001B7C - X"00551025", -- 00001B80 - X"8CA30014", -- 00001B84 - X"00541026", -- 00001B88 - X"00123027", -- 00001B8C - X"00D13024", -- 00001B90 - X"00431021", -- 00001B94 - X"025E1824", -- 00001B98 - X"00661825", -- 00001B9C - X"00591021", -- 00001BA0 - X"006D1821", -- 00001BA4 - X"3C0B7A6D", -- 00001BA8 - X"356B76E9", -- 00001BAC - X"0049C821", -- 00001BB0 - X"00771821", -- 00001BB4 - X"006BB821", -- 00001BB8 - X"00193642", -- 00001BBC - X"001911C0", -- 00001BC0 - X"00461025", -- 00001BC4 - X"00174442", -- 00001BC8 - X"001733C0", -- 00001BCC - X"0053C821", -- 00001BD0 - X"00C83025", -- 00001BD4 - X"00183D82", -- 00001BD8 - X"00181280", -- 00001BDC - X"00D6B821", -- 00001BE0 - X"0047C025", -- 00001BE4 - X"00151827", -- 00001BE8 - X"001E3582", -- 00001BEC - X"001E1280", -- 00001BF0 - X"0046F025", -- 00001BF4 - X"00791825", -- 00001BF8 - X"8CA60030", -- 00001BFC - X"00781826", -- 00001C00 - X"00661821", -- 00001C04 - X"00173027", -- 00001C08 - X"00DE3024", -- 00001C0C - X"02F21024", -- 00001C10 - X"00731821", -- 00001C14 - X"00461025", -- 00001C18 - X"00699821", -- 00001C1C - X"004C1021", -- 00001C20 - X"001346C2", -- 00001C24 - X"00153D82", -- 00001C28 - X"00133140", -- 00001C2C - X"00151A80", -- 00001C30 - X"00561021", -- 00001C34 - X"0067A825", -- 00001C38 - X"00C83025", -- 00001C3C - X"004BB021", -- 00001C40 - X"00D49821", -- 00001C44 - X"00163EC2", -- 00001C48 - X"00153027", -- 00001C4C - X"00161140", -- 00001C50 - X"00D93024", -- 00001C54 - X"02751824", -- 00001C58 - X"00471025", -- 00001C5C - X"8CA70004", -- 00001C60 - X"00661825", -- 00001C64 - X"0051B021", -- 00001C68 - X"00671821", -- 00001C6C - X"00123582", -- 00001C70 - X"00121280", -- 00001C74 - X"3C0A8F1B", -- 00001C78 - X"354ABCDC", -- 00001C7C - X"00469025", -- 00001C80 - X"00741821", -- 00001C84 - X"00161027", -- 00001C88 - X"006AA021", -- 00001C8C - X"00521024", -- 00001C90 - X"02D71824", -- 00001C94 - X"00144542", -- 00001C98 - X"00621825", -- 00001C9C - X"00193582", -- 00001CA0 - X"00143AC0", -- 00001CA4 - X"00191280", -- 00001CA8 - X"0046C825", -- 00001CAC - X"00E83825", -- 00001CB0 - X"8FA80038", -- 00001CB4 - X"00F8A021", -- 00001CB8 - X"00193027", -- 00001CBC - X"00D33024", -- 00001CC0 - X"02991024", -- 00001CC4 - X"00681821", -- 00001CC8 - X"00711821", -- 00001CCC - X"00461025", -- 00001CD0 - X"8CA60024", -- 00001CD4 - X"006B8821", -- 00001CD8 - X"00113E02", -- 00001CDC - X"00111A00", -- 00001CE0 - X"00461021", -- 00001CE4 - X"00671825", -- 00001CE8 - X"00581021", -- 00001CEC - X"007E8821", -- 00001CF0 - X"004AC021", -- 00001CF4 - X"00173582", -- 00001CF8 - X"8CA20004", -- 00001CFC - X"00171A80", -- 00001D00 - X"0066B825", -- 00001D04 - X"00184D02", -- 00001D08 - X"00181B00", -- 00001D0C - X"AFA2003C", -- 00001D10 - X"00691825", -- 00001D14 - X"00113827", -- 00001D18 - X"0075C021", -- 00001D1C - X"00F73824", -- 00001D20 - X"8FA3003C", -- 00001D24 - X"02363024", -- 00001D28 - X"00134582", -- 00001D2C - X"00131280", -- 00001D30 - X"00C73025", -- 00001D34 - X"00489825", -- 00001D38 - X"00C33021", -- 00001D3C - X"00DE3021", -- 00001D40 - X"00131827", -- 00001D44 - X"00CBF021", -- 00001D48 - X"00741824", -- 00001D4C - X"8CA6002C", -- 00001D50 - X"03131024", -- 00001D54 - X"00431025", -- 00001D58 - X"00461021", -- 00001D5C - X"001E1AC0", -- 00001D60 - X"001E3542", -- 00001D64 - X"00661825", -- 00001D68 - X"00551021", -- 00001D6C - X"0072F021", -- 00001D70 - X"004AA821", -- 00001D74 - X"00161D82", -- 00001D78 - X"00161280", -- 00001D7C - X"0043B025", -- 00001D80 - X"00154482", -- 00001D84 - X"00143582", -- 00001D88 - X"00153B80", -- 00001D8C - X"001E1827", -- 00001D90 - X"00141280", -- 00001D94 - X"0046A025", -- 00001D98 - X"00E83825", -- 00001D9C - X"00761824", -- 00001DA0 - X"03D11024", -- 00001DA4 - X"00F9A821", -- 00001DA8 - X"00431025", -- 00001DAC - X"00143027", -- 00001DB0 - X"8CA70028", -- 00001DB4 - X"00D83024", -- 00001DB8 - X"02B41824", -- 00001DBC - X"00501021", -- 00001DC0 - X"00661825", -- 00001DC4 - X"00521021", -- 00001DC8 - X"004B9021", -- 00001DCC - X"00671821", -- 00001DD0 - X"00123482", -- 00001DD4 - X"00791821", -- 00001DD8 - X"00121380", -- 00001DDC - X"006AC821", -- 00001DE0 - X"00461025", -- 00001DE4 - X"00579021", -- 00001DE8 - X"00194C42", -- 00001DEC - X"00183D82", -- 00001DF0 - X"00114582", -- 00001DF4 - X"00191BC0", -- 00001DF8 - X"00181280", -- 00001DFC - X"00113280", -- 00001E00 - X"0047C025", -- 00001E04 - X"00C88825", -- 00001E08 - X"00691825", -- 00001E0C - X"00121027", -- 00001E10 - X"0073C821", -- 00001E14 - X"00511024", -- 00001E18 - X"025E1824", -- 00001E1C - X"00183027", -- 00001E20 - X"8FA8002C", -- 00001E24 - X"00D53024", -- 00001E28 - X"00621825", -- 00001E2C - X"03381024", -- 00001E30 - X"00461025", -- 00001E34 - X"8CA60000", -- 00001E38 - X"00681821", -- 00001E3C - X"00771821", -- 00001E40 - X"00461021", -- 00001E44 - X"006BB821", -- 00001E48 - X"00531021", -- 00001E4C - X"004A9821", -- 00001E50 - X"00171C82", -- 00001E54 - X"00173380", -- 00001E58 - X"00C33025", -- 00001E5C - X"00134482", -- 00001E60 - X"00153D82", -- 00001E64 - X"00131B80", -- 00001E68 - X"00151280", -- 00001E6C - X"00D6B821", -- 00001E70 - X"0047A825", -- 00001E74 - X"00681825", -- 00001E78 - X"001E3D82", -- 00001E7C - X"001E1280", -- 00001E80 - X"00749821", -- 00001E84 - X"0047F025", -- 00001E88 - X"00153027", -- 00001E8C - X"00173827", -- 00001E90 - X"8FA80030", -- 00001E94 - X"00D93024", -- 00001E98 - X"00FE3824", -- 00001E9C - X"02751024", -- 00001EA0 - X"02F21824", -- 00001EA4 - X"00461025", -- 00001EA8 - X"00671825", -- 00001EAC - X"00681821", -- 00001EB0 - X"004D1021", -- 00001EB4 - X"00541021", -- 00001EB8 - X"00761821", -- 00001EBC - X"004AA021", -- 00001EC0 - X"006BB021", -- 00001EC4 - X"00144442", -- 00001EC8 - X"00164E82", -- 00001ECC - X"00193D82", -- 00001ED0 - X"001433C0", -- 00001ED4 - X"00161980", -- 00001ED8 - X"00191280", -- 00001EDC - X"0047C825", -- 00001EE0 - X"00C83025", -- 00001EE4 - X"00691825", -- 00001EE8 - X"0071B021", -- 00001EEC - X"00D8A021", -- 00001EF0 - X"00121D82", -- 00001EF4 - X"00193827", -- 00001EF8 - X"00121280", -- 00001EFC - X"00439025", -- 00001F00 - X"8CA80030", -- 00001F04 - X"00F33824", -- 00001F08 - X"02991824", -- 00001F0C - X"00163027", -- 00001F10 - X"00D23024", -- 00001F14 - X"02D71024", -- 00001F18 - X"00671825", -- 00001F1C - X"8CA70000", -- 00001F20 - X"00461025", -- 00001F24 - X"00681821", -- 00001F28 - X"00781821", -- 00001F2C - X"00471021", -- 00001F30 - X"006AC021", -- 00001F34 - X"00511021", -- 00001F38 - X"004B8821", -- 00001F3C - X"AFA70040", -- 00001F40 - X"00133582", -- 00001F44 - X"00183DC2", -- 00001F48 - X"00181A40", -- 00001F4C - X"00131280", -- 00001F50 - X"00469825", -- 00001F54 - X"00671825", -- 00001F58 - X"00113482", -- 00001F5C - X"00111380", -- 00001F60 - X"0075C021", -- 00001F64 - X"00461025", -- 00001F68 - X"00133827", -- 00001F6C - X"00173582", -- 00001F70 - X"00171A80", -- 00001F74 - X"005E8821", -- 00001F78 - X"0066B825", -- 00001F7C - X"00F43824", -- 00001F80 - X"8CA30010", -- 00001F84 - X"03131024", -- 00001F88 - X"00471025", -- 00001F8C - X"00113027", -- 00001F90 - X"8CAF0014", -- 00001F94 - X"00D73024", -- 00001F98 - X"00431021", -- 00001F9C - X"02361824", -- 00001FA0 - X"00551021", -- 00001FA4 - X"00661825", -- 00001FA8 - X"004AA821", -- 00001FAC - X"006F1821", -- 00001FB0 - X"00154602", -- 00001FB4 - X"007E1821", -- 00001FB8 - X"00143D82", -- 00001FBC - X"00153200", -- 00001FC0 - X"00141280", -- 00001FC4 - X"0047A025", -- 00001FC8 - X"00C83025", -- 00001FCC - X"006BF021", -- 00001FD0 - X"00D9A821", -- 00001FD4 - X"001E1E82", -- 00001FD8 - X"00141027", -- 00001FDC - X"001E3180", -- 00001FE0 - X"00C33025", -- 00001FE4 - X"00581024", -- 00001FE8 - X"02B41824", -- 00001FEC - X"00621825", -- 00001FF0 - X"00163D82", -- 00001FF4 - X"00161280", -- 00001FF8 - X"00D2F021", -- 00001FFC - X"0047B025", -- 00002000 - X"8CA60034", -- 00002004 - X"8CA70030", -- 00002008 - X"001E1027", -- 0000200C - X"AFA70044", -- 00002010 - X"00561024", -- 00002014 - X"00661821", -- 00002018 - X"03D13024", -- 0000201C - X"00791821", -- 00002020 - X"00C23025", -- 00002024 - X"8FA20044", -- 00002028 - X"006AC821", -- 0000202C - X"001945C2", -- 00002030 - X"00183D82", -- 00002034 - X"00C23021", -- 00002038 - X"00191A40", -- 0000203C - X"00181280", -- 00002040 - X"0047C025", -- 00002044 - X"00681825", -- 00002048 - X"00D23021", -- 0000204C - X"0073C821", -- 00002050 - X"00CB9021", -- 00002054 - X"00183827", -- 00002058 - X"00F53824", -- 0000205C - X"001235C2", -- 00002060 - X"03381024", -- 00002064 - X"00121A40", -- 00002068 - X"00661825", -- 0000206C - X"00471025", -- 00002070 - X"00779021", -- 00002074 - X"00501021", -- 00002078 - X"00113582", -- 0000207C - X"00111A80", -- 00002080 - X"00668825", -- 00002084 - X"00531021", -- 00002088 - X"00121827", -- 0000208C - X"004A9821", -- 00002090 - X"00711824", -- 00002094 - X"025E3024", -- 00002098 - X"8CAE0008", -- 0000209C - X"00134482", -- 000020A0 - X"00C33025", -- 000020A4 - X"00133B80", -- 000020A8 - X"00151D82", -- 000020AC - X"00151280", -- 000020B0 - X"0043A825", -- 000020B4 - X"00E83825", -- 000020B8 - X"00F49821", -- 000020BC - X"00151827", -- 000020C0 - X"00CE3021", -- 000020C4 - X"8CA7001C", -- 000020C8 - X"00791824", -- 000020CC - X"02751024", -- 000020D0 - X"00D73021", -- 000020D4 - X"00CBB821", -- 000020D8 - X"00431025", -- 000020DC - X"00173502", -- 000020E0 - X"00171B00", -- 000020E4 - X"00471021", -- 000020E8 - X"00661825", -- 000020EC - X"00541021", -- 000020F0 - X"0076B821", -- 000020F4 - X"004AA021", -- 000020F8 - X"001E3582", -- 000020FC - X"001E1A80", -- 00002100 - X"0066F025", -- 00002104 - X"00144EC2", -- 00002108 - X"00173827", -- 0000210C - X"00194582", -- 00002110 - X"00141940", -- 00002114 - X"00191280", -- 00002118 - X"0048C825", -- 0000211C - X"00FE3824", -- 00002120 - X"8FA80034", -- 00002124 - X"02F23024", -- 00002128 - X"00691825", -- 0000212C - X"0078A021", -- 00002130 - X"00C73025", -- 00002134 - X"00191827", -- 00002138 - X"00731824", -- 0000213C - X"02991024", -- 00002140 - X"00C83021", -- 00002144 - X"00D63021", -- 00002148 - X"00431025", -- 0000214C - X"8CA3003C", -- 00002150 - X"00CBB021", -- 00002154 - X"001635C2", -- 00002158 - X"00431021", -- 0000215C - X"00161A40", -- 00002160 - X"00661825", -- 00002164 - X"00581021", -- 00002168 - X"0071B021", -- 0000216C - X"004AC021", -- 00002170 - X"00121D82", -- 00002174 - X"00121280", -- 00002178 - X"00439025", -- 0000217C - X"00184682", -- 00002180 - X"00131D82", -- 00002184 - X"00183980", -- 00002188 - X"00163027", -- 0000218C - X"00131280", -- 00002190 - X"00439825", -- 00002194 - X"00E83825", -- 00002198 - X"00D23024", -- 0000219C - X"8CA80024", -- 000021A0 - X"02D71824", -- 000021A4 - X"00661825", -- 000021A8 - X"00681821", -- 000021AC - X"00F5C021", -- 000021B0 - X"00133027", -- 000021B4 - X"00711821", -- 000021B8 - X"006B8821", -- 000021BC - X"00D43024", -- 000021C0 - X"8CA30038", -- 000021C4 - X"03131024", -- 000021C8 - X"00461025", -- 000021CC - X"00431021", -- 000021D0 - X"00113502", -- 000021D4 - X"00551021", -- 000021D8 - X"00111B00", -- 000021DC - X"004AA821", -- 000021E0 - X"AFA80048", -- 000021E4 - X"00661825", -- 000021E8 - X"00174582", -- 000021EC - X"00173280", -- 000021F0 - X"007E8821", -- 000021F4 - X"00C8B825", -- 000021F8 - X"00154E02", -- 000021FC - X"8CA6001C", -- 00002200 - X"00143D82", -- 00002204 - X"00151A00", -- 00002208 - X"00141280", -- 0000220C - X"0047A025", -- 00002210 - X"00691825", -- 00002214 - X"00111027", -- 00002218 - X"AFA6004C", -- 0000221C - X"0079A821", -- 00002220 - X"8FA7004C", -- 00002224 - X"00571024", -- 00002228 - X"02361824", -- 0000222C - X"00143027", -- 00002230 - X"00D83024", -- 00002234 - X"00621825", -- 00002238 - X"02B41024", -- 0000223C - X"00461025", -- 00002240 - X"00671821", -- 00002244 - X"007E1821", -- 00002248 - X"004F1021", -- 0000224C - X"006BF021", -- 00002250 - X"00591021", -- 00002254 - X"004AC821", -- 00002258 - X"001E1EC2", -- 0000225C - X"001E3140", -- 00002260 - X"00C33025", -- 00002264 - X"00194682", -- 00002268 - X"00183D82", -- 0000226C - X"00191980", -- 00002270 - X"00181280", -- 00002274 - X"00D2F021", -- 00002278 - X"0047C025", -- 0000227C - X"00681825", -- 00002280 - X"00163D82", -- 00002284 - X"00161280", -- 00002288 - X"0073C821", -- 0000228C - X"0047B025", -- 00002290 - X"00183027", -- 00002294 - X"001E3827", -- 00002298 - X"8CA80028", -- 0000229C - X"00D53024", -- 000022A0 - X"00F63824", -- 000022A4 - X"03381024", -- 000022A8 - X"03D11824", -- 000022AC - X"00461025", -- 000022B0 - X"00671825", -- 000022B4 - X"00681821", -- 000022B8 - X"004C1021", -- 000022BC - X"00531021", -- 000022C0 - X"00721821", -- 000022C4 - X"004A9821", -- 000022C8 - X"006B9021", -- 000022CC - X"AFA80050", -- 000022D0 - X"00124C42", -- 000022D4 - X"001346C2", -- 000022D8 - X"00153D82", -- 000022DC - X"00133140", -- 000022E0 - X"00121BC0", -- 000022E4 - X"00151280", -- 000022E8 - X"0047A825", -- 000022EC - X"00C83025", -- 000022F0 - X"00691825", -- 000022F4 - X"00779021", -- 000022F8 - X"00D49821", -- 000022FC - X"00113D82", -- 00002300 - X"00151827", -- 00002304 - X"00111280", -- 00002308 - X"00478825", -- 0000230C - X"00791824", -- 00002310 - X"02751024", -- 00002314 - X"00123027", -- 00002318 - X"8CA70038", -- 0000231C - X"00D13024", -- 00002320 - X"00431025", -- 00002324 - X"025E1824", -- 00002328 - X"00661825", -- 0000232C - X"004E1021", -- 00002330 - X"00541021", -- 00002334 - X"00671821", -- 00002338 - X"004AA021", -- 0000233C - X"00771821", -- 00002340 - X"00192D82", -- 00002344 - X"00191280", -- 00002348 - X"0045C825", -- 0000234C - X"006BB821", -- 00002350 - X"00141502", -- 00002354 - X"00142B00", -- 00002358 - X"00A22825", -- 0000235C - X"00173602", -- 00002360 - X"00171200", -- 00002364 - X"00461025", -- 00002368 - X"00B8A021", -- 0000236C - X"0056B821", -- 00002370 - X"00191827", -- 00002374 - X"001E2D82", -- 00002378 - X"001E1280", -- 0000237C - X"0045F025", -- 00002380 - X"00731825", -- 00002384 - X"8FA20004", -- 00002388 - X"8FA60044", -- 0000238C - X"02F22826", -- 00002390 - X"00741826", -- 00002394 - X"00621821", -- 00002398 - X"00BE2826", -- 0000239C - X"3C08A953", -- 000023A0 - X"3508FD4E", -- 000023A4 - X"00A62821", -- 000023A8 - X"00781821", -- 000023AC - X"0068C021", -- 000023B0 - X"02C5B021", -- 000023B4 - X"00133582", -- 000023B8 - X"00131280", -- 000023BC - X"00469825", -- 000023C0 - X"00182A40", -- 000023C4 - X"001815C2", -- 000023C8 - X"00163602", -- 000023CC - X"00161A00", -- 000023D0 - X"00A22825", -- 000023D4 - X"00661825", -- 000023D8 - X"00B5C021", -- 000023DC - X"0071B021", -- 000023E0 - X"00131027", -- 000023E4 - X"00122D82", -- 000023E8 - X"00121A80", -- 000023EC - X"00659025", -- 000023F0 - X"00541025", -- 000023F4 - X"8FA30008", -- 000023F8 - X"00581026", -- 000023FC - X"8FA50030", -- 00002400 - X"00431021", -- 00002404 - X"02D71826", -- 00002408 - X"00721826", -- 0000240C - X"00651821", -- 00002410 - X"00551021", -- 00002414 - X"0048A821", -- 00002418 - X"02238821", -- 0000241C - X"00142D82", -- 00002420 - X"00141280", -- 00002424 - X"0045A025", -- 00002428 - X"001136C2", -- 0000242C - X"00151442", -- 00002430 - X"00152BC0", -- 00002434 - X"00111940", -- 00002438 - X"00A22825", -- 0000243C - X"00661825", -- 00002440 - X"00141027", -- 00002444 - X"00B9A821", -- 00002448 - X"007E8821", -- 0000244C - X"00581025", -- 00002450 - X"00172D82", -- 00002454 - X"00171A80", -- 00002458 - X"0065B825", -- 0000245C - X"00551026", -- 00002460 - X"8FA50050", -- 00002464 - X"02361826", -- 00002468 - X"00771826", -- 0000246C - X"004F1021", -- 00002470 - X"00651821", -- 00002474 - X"00591021", -- 00002478 - X"0048C821", -- 0000247C - X"03C3F021", -- 00002480 - X"00182D82", -- 00002484 - X"00181280", -- 00002488 - X"0045C025", -- 0000248C - X"001E3502", -- 00002490 - X"001916C2", -- 00002494 - X"00192940", -- 00002498 - X"001E1B00", -- 0000249C - X"00A22825", -- 000024A0 - X"00661825", -- 000024A4 - X"00181027", -- 000024A8 - X"00B3C821", -- 000024AC - X"0072F021", -- 000024B0 - X"8FA60010", -- 000024B4 - X"00551025", -- 000024B8 - X"00162D82", -- 000024BC - X"00161A80", -- 000024C0 - X"0065B025", -- 000024C4 - X"00591026", -- 000024C8 - X"8FA50038", -- 000024CC - X"03D11826", -- 000024D0 - X"00461021", -- 000024D4 - X"00761826", -- 000024D8 - X"00651821", -- 000024DC - X"00531021", -- 000024E0 - X"00489821", -- 000024E4 - X"02439021", -- 000024E8 - X"00152D82", -- 000024EC - X"00151280", -- 000024F0 - X"0045A825", -- 000024F4 - X"001235C2", -- 000024F8 - X"00131542", -- 000024FC - X"00132AC0", -- 00002500 - X"00121A40", -- 00002504 - X"00A22825", -- 00002508 - X"00661825", -- 0000250C - X"00151027", -- 00002510 - X"00B49821", -- 00002514 - X"00779021", -- 00002518 - X"8FA60014", -- 0000251C - X"00591025", -- 00002520 - X"00112D82", -- 00002524 - X"00111A80", -- 00002528 - X"00658825", -- 0000252C - X"00531026", -- 00002530 - X"8FA5003C", -- 00002534 - X"025E1826", -- 00002538 - X"00461021", -- 0000253C - X"00711826", -- 00002540 - X"00651821", -- 00002544 - X"00541021", -- 00002548 - X"0048A021", -- 0000254C - X"02E3B821", -- 00002550 - X"00192D82", -- 00002554 - X"00191280", -- 00002558 - X"0045C825", -- 0000255C - X"00173502", -- 00002560 - X"00141682", -- 00002564 - X"00142980", -- 00002568 - X"00171B00", -- 0000256C - X"00A22825", -- 00002570 - X"00661825", -- 00002574 - X"00191027", -- 00002578 - X"00B8A021", -- 0000257C - X"0076B821", -- 00002580 - X"8FA60018", -- 00002584 - X"00531025", -- 00002588 - X"001E2D82", -- 0000258C - X"001E1A80", -- 00002590 - X"0065F025", -- 00002594 - X"00541026", -- 00002598 - X"02F21826", -- 0000259C - X"00461021", -- 000025A0 - X"007E1826", -- 000025A4 - X"00581021", -- 000025A8 - X"006F1821", -- 000025AC - X"0048C021", -- 000025B0 - X"02C3B021", -- 000025B4 - X"00132D82", -- 000025B8 - X"00131280", -- 000025BC - X"00459825", -- 000025C0 - X"001636C2", -- 000025C4 - X"00181602", -- 000025C8 - X"00182A00", -- 000025CC - X"00161940", -- 000025D0 - X"00A22825", -- 000025D4 - X"00661825", -- 000025D8 - X"00131027", -- 000025DC - X"00B5C021", -- 000025E0 - X"0071B021", -- 000025E4 - X"00541025", -- 000025E8 - X"00122D82", -- 000025EC - X"00121A80", -- 000025F0 - X"00659025", -- 000025F4 - X"00581026", -- 000025F8 - X"02D71826", -- 000025FC - X"00721826", -- 00002600 - X"004E1021", -- 00002604 - X"00551021", -- 00002608 - X"006D1821", -- 0000260C - X"0048A821", -- 00002610 - X"02238821", -- 00002614 - X"00142D82", -- 00002618 - X"00141280", -- 0000261C - X"0045A025", -- 00002620 - X"00113482", -- 00002624 - X"001514C2", -- 00002628 - X"00152B40", -- 0000262C - X"00111B80", -- 00002630 - X"00A22825", -- 00002634 - X"00661825", -- 00002638 - X"00B9A821", -- 0000263C - X"007E8821", -- 00002640 - X"00141027", -- 00002644 - X"00172D82", -- 00002648 - X"00171A80", -- 0000264C - X"0065B825", -- 00002650 - X"00581025", -- 00002654 - X"8FA50020", -- 00002658 - X"8FA6004C", -- 0000265C - X"02361826", -- 00002660 - X"00551026", -- 00002664 - X"00451021", -- 00002668 - X"00771826", -- 0000266C - X"00661821", -- 00002670 - X"00591021", -- 00002674 - X"0048C821", -- 00002678 - X"03C3F021", -- 0000267C - X"00182D82", -- 00002680 - X"00181280", -- 00002684 - X"0045C025", -- 00002688 - X"001E3682", -- 0000268C - X"00191502", -- 00002690 - X"00192B00", -- 00002694 - X"001E1980", -- 00002698 - X"00A22825", -- 0000269C - X"00661825", -- 000026A0 - X"00181027", -- 000026A4 - X"00B3C821", -- 000026A8 - X"0072F021", -- 000026AC - X"00551025", -- 000026B0 - X"00162D82", -- 000026B4 - X"00161A80", -- 000026B8 - X"0065B025", -- 000026BC - X"00591026", -- 000026C0 - X"03D11826", -- 000026C4 - X"00471021", -- 000026C8 - X"00761826", -- 000026CC - X"00531021", -- 000026D0 - X"006C1821", -- 000026D4 - X"00489821", -- 000026D8 - X"02439021", -- 000026DC - X"00152D82", -- 000026E0 - X"00151280", -- 000026E4 - X"0045A825", -- 000026E8 - X"00123602", -- 000026EC - X"001316C2", -- 000026F0 - X"00132940", -- 000026F4 - X"00121A00", -- 000026F8 - X"00A22825", -- 000026FC - X"00661825", -- 00002700 - X"00B49821", -- 00002704 - X"00779021", -- 00002708 - X"00151027", -- 0000270C - X"00112D82", -- 00002710 - X"00111A80", -- 00002714 - X"00658825", -- 00002718 - X"00591025", -- 0000271C - X"8FA50028", -- 00002720 - X"025E1826", -- 00002724 - X"00531026", -- 00002728 - X"00451021", -- 0000272C - X"00711826", -- 00002730 - X"00541021", -- 00002734 - X"006E1821", -- 00002738 - X"0048A021", -- 0000273C - X"02E3B821", -- 00002740 - X"00192D82", -- 00002744 - X"00191280", -- 00002748 - X"0045C825", -- 0000274C - X"001734C2", -- 00002750 - X"00141502", -- 00002754 - X"00142B00", -- 00002758 - X"00171B40", -- 0000275C - X"00A22825", -- 00002760 - X"00661825", -- 00002764 - X"00191027", -- 00002768 - X"00B8A021", -- 0000276C - X"0076B821", -- 00002770 - X"00531025", -- 00002774 - X"001E2D82", -- 00002778 - X"001E1A80", -- 0000277C - X"0065F025", -- 00002780 - X"8FA60034", -- 00002784 - X"02F21826", -- 00002788 - X"00541026", -- 0000278C - X"00501021", -- 00002790 - X"007E1826", -- 00002794 - X"00661821", -- 00002798 - X"00581021", -- 0000279C - X"0048C021", -- 000027A0 - X"02C3B021", -- 000027A4 - X"00132D82", -- 000027A8 - X"00131280", -- 000027AC - X"00459825", -- 000027B0 - X"00163682", -- 000027B4 - X"001814C2", -- 000027B8 - X"00182B40", -- 000027BC - X"00161980", -- 000027C0 - X"00A22825", -- 000027C4 - X"00661825", -- 000027C8 - X"00131027", -- 000027CC - X"00B5C021", -- 000027D0 - X"0071B021", -- 000027D4 - X"00541025", -- 000027D8 - X"00122D82", -- 000027DC - X"00121A80", -- 000027E0 - X"00659025", -- 000027E4 - X"00581026", -- 000027E8 - X"02D71826", -- 000027EC - X"00721826", -- 000027F0 - X"004D1021", -- 000027F4 - X"00671821", -- 000027F8 - X"00551021", -- 000027FC - X"0048A821", -- 00002800 - X"02238821", -- 00002804 - X"00142D82", -- 00002808 - X"00141280", -- 0000280C - X"0045A025", -- 00002810 - X"001136C2", -- 00002814 - X"00151482", -- 00002818 - X"00152B80", -- 0000281C - X"00111940", -- 00002820 - X"00A22825", -- 00002824 - X"00661825", -- 00002828 - X"00141027", -- 0000282C - X"00B9A821", -- 00002830 - X"007E8821", -- 00002834 - X"8FA7002C", -- 00002838 - X"00581025", -- 0000283C - X"00172D82", -- 00002840 - X"00171A80", -- 00002844 - X"0065B825", -- 00002848 - X"00551026", -- 0000284C - X"8FA50040", -- 00002850 - X"02361826", -- 00002854 - X"00471021", -- 00002858 - X"00771826", -- 0000285C - X"00651821", -- 00002860 - X"00591021", -- 00002864 - X"0048C821", -- 00002868 - X"03C3F021", -- 0000286C - X"00182D82", -- 00002870 - X"00181280", -- 00002874 - X"0045C025", -- 00002878 - X"001E3442", -- 0000287C - X"00191542", -- 00002880 - X"00192AC0", -- 00002884 - X"001E1BC0", -- 00002888 - X"00A22825", -- 0000288C - X"00661825", -- 00002890 - X"00181027", -- 00002894 - X"00B3C821", -- 00002898 - X"0072F021", -- 0000289C - X"00551025", -- 000028A0 - X"00162D82", -- 000028A4 - X"00161A80", -- 000028A8 - X"0065B025", -- 000028AC - X"00591026", -- 000028B0 - X"03D11826", -- 000028B4 - X"00761826", -- 000028B8 - X"004C1021", -- 000028BC - X"00701821", -- 000028C0 - X"00531021", -- 000028C4 - X"00489821", -- 000028C8 - X"02439021", -- 000028CC - X"00152D82", -- 000028D0 - X"00151280", -- 000028D4 - X"0045A825", -- 000028D8 - X"001234C2", -- 000028DC - X"00131602", -- 000028E0 - X"00132A00", -- 000028E4 - X"00121B40", -- 000028E8 - X"00A22825", -- 000028EC - X"00661825", -- 000028F0 - X"00151027", -- 000028F4 - X"00B49821", -- 000028F8 - X"00779021", -- 000028FC - X"8FA60030", -- 00002900 - X"00591025", -- 00002904 - X"00112D82", -- 00002908 - X"00111A80", -- 0000290C - X"00658825", -- 00002910 - X"8FA70048", -- 00002914 - X"025E1826", -- 00002918 - X"00531026", -- 0000291C - X"00461021", -- 00002920 - X"00711826", -- 00002924 - X"00671821", -- 00002928 - X"00541021", -- 0000292C - X"0048A021", -- 00002930 - X"02E3B821", -- 00002934 - X"00192D82", -- 00002938 - X"00191280", -- 0000293C - X"0045C825", -- 00002940 - X"00141EC2", -- 00002944 - X"00173542", -- 00002948 - X"00142940", -- 0000294C - X"001712C0", -- 00002950 - X"00A32825", -- 00002954 - X"00461025", -- 00002958 - X"00B8A021", -- 0000295C - X"0056B821", -- 00002960 - X"001E2D82", -- 00002964 - X"001E1280", -- 00002968 - X"00191827", -- 0000296C - X"0045F025", -- 00002970 - X"00731825", -- 00002974 - X"8FA20034", -- 00002978 - X"00741826", -- 0000297C - X"00621821", -- 00002980 - X"00781821", -- 00002984 - X"0068C021", -- 00002988 - X"02F21026", -- 0000298C - X"8FA3002C", -- 00002990 - X"8C860008", -- 00002994 - X"00133D82", -- 00002998 - X"00132A80", -- 0000299C - X"00A79825", -- 000029A0 - X"005E1026", -- 000029A4 - X"00431021", -- 000029A8 - X"00D33021", -- 000029AC - X"02C2B021", -- 000029B0 - X"00DE3021", -- 000029B4 - X"00181682", -- 000029B8 - X"00182980", -- 000029BC - X"00161D42", -- 000029C0 - X"8C8A0004", -- 000029C4 - X"8C87000C", -- 000029C8 - X"8C880000", -- 000029CC - X"00A22825", -- 000029D0 - X"00164AC0", -- 000029D4 - X"AC860004", -- 000029D8 - X"8C860010", -- 000029DC - X"01234825", -- 000029E0 - X"00B5C021", -- 000029E4 - X"00121D82", -- 000029E8 - X"00121280", -- 000029EC - X"0131B021", -- 000029F0 - X"01545021", -- 000029F4 - X"00D53021", -- 000029F8 - X"00439025", -- 000029FC - X"00F93821", -- 00002A00 - X"01184021", -- 00002A04 - X"024A9021", -- 00002A08 - X"00F13821", -- 00002A0C - X"00D63021", -- 00002A10 - X"01174021", -- 00002A14 - X"AC920000", -- 00002A18 - X"AC870008", -- 00002A1C - X"AC86000C", -- 00002A20 - X"AC880010", -- 00002A24 - X"8FBE0078", -- 00002A28 - X"8FB70074", -- 00002A2C - X"8FB60070", -- 00002A30 - X"8FB5006C", -- 00002A34 - X"8FB40068", -- 00002A38 - X"8FB30064", -- 00002A3C - X"8FB20060", -- 00002A40 - X"8FB1005C", -- 00002A44 - X"8FB00058", -- 00002A48 - X"03E00008", -- 00002A4C - X"27BD0080", -- 00002A50 - X"27BDFF98", -- 00002A54 - X"AFB10054", -- 00002A58 - X"27B10010", -- 00002A5C - X"AFB40060", -- 00002A60 - X"AFB20058", -- 00002A64 - X"AFB00050", -- 00002A68 - X"00C09021", -- 00002A6C - X"0080A021", -- 00002A70 - X"24060040", -- 00002A74 - X"00A08021", -- 00002A78 - X"02202021", -- 00002A7C - X"00002821", -- 00002A80 - X"AFB3005C", -- 00002A84 - X"AFBF0064", -- 00002A88 - X"0C100AEB", -- 00002A8C - X"00E09821", -- 00002A90 - X"3247003F", -- 00002A94 - X"10E0000F", -- 00002A98 - X"00003021", -- 00002A9C - X"00062882", -- 00002AA0 - X"00052880", -- 00002AA4 - X"92040000", -- 00002AA8 - X"00B12821", -- 00002AAC - X"30C20003", -- 00002AB0 - X"000210C0", -- 00002AB4 - X"8CA30000", -- 00002AB8 - X"00442004", -- 00002ABC - X"24C60001", -- 00002AC0 - X"00641826", -- 00002AC4 - X"00C7102B", -- 00002AC8 - X"ACA30000", -- 00002ACC - X"1440FFF3", -- 00002AD0 - X"26100001", -- 00002AD4 - X"3245003C", -- 00002AD8 - X"32430003", -- 00002ADC - X"00B12821", -- 00002AE0 - X"000318C0", -- 00002AE4 - X"24630007", -- 00002AE8 - X"8CA40000", -- 00002AEC - X"24020001", -- 00002AF0 - X"00621004", -- 00002AF4 - X"00822026", -- 00002AF8 - X"2CE30038", -- 00002AFC - X"10600012", -- 00002B00 - X"ACA40000", -- 00002B04 - X"001318C0", -- 00002B08 - X"00121742", -- 00002B0C - X"00431025", -- 00002B10 - X"02802021", -- 00002B14 - X"001218C0", -- 00002B18 - X"02202821", -- 00002B1C - X"AFA30048", -- 00002B20 - X"0C1001A3", -- 00002B24 - X"AFA2004C", -- 00002B28 - X"8FBF0064", -- 00002B2C - X"8FB40060", -- 00002B30 - X"8FB3005C", -- 00002B34 - X"8FB20058", -- 00002B38 - X"8FB10054", -- 00002B3C - X"8FB00050", -- 00002B40 - X"03E00008", -- 00002B44 - X"27BD0068", -- 00002B48 - X"02802021", -- 00002B4C - X"0C1001A3", -- 00002B50 - X"02202821", -- 00002B54 - X"02202021", -- 00002B58 - X"00002821", -- 00002B5C - X"0C100AEB", -- 00002B60 - X"24060040", -- 00002B64 - X"001318C0", -- 00002B68 - X"00121742", -- 00002B6C - X"00431025", -- 00002B70 - X"02802021", -- 00002B74 - X"001218C0", -- 00002B78 - X"02202821", -- 00002B7C - X"AFA30048", -- 00002B80 - X"0C1001A3", -- 00002B84 - X"AFA2004C", -- 00002B88 - X"8FBF0064", -- 00002B8C - X"8FB40060", -- 00002B90 - X"8FB3005C", -- 00002B94 - X"8FB20058", -- 00002B98 - X"8FB10054", -- 00002B9C - X"8FB00050", -- 00002BA0 - X"03E00008", -- 00002BA4 - X"27BD0068", -- 00002BA8 - X"2CC20010", -- 00002BAC - X"14400027", -- 00002BB0 - X"00801821", -- 00002BB4 - X"30870003", -- 00002BB8 - X"10E00009", -- 00002BBC - X"2CE20004", -- 00002BC0 - X"08100AF7", -- 00002BC4 - X"00000000", -- 00002BC8 - X"A0650000", -- 00002BCC - X"2CE20004", -- 00002BD0 - X"24C6FFFF", -- 00002BD4 - X"24630001", -- 00002BD8 - X"1440FFFB", -- 00002BDC - X"24E70001", -- 00002BE0 - X"30A500FF", -- 00002BE4 - X"00603821", -- 00002BE8 - X"10A00005", -- 00002BEC - X"00A04021", -- 00002BF0 - X"00051200", -- 00002BF4 - X"00A24025", -- 00002BF8 - X"00081C00", -- 00002BFC - X"01034025", -- 00002C00 - X"000610C2", -- 00002C04 - X"08100B07", -- 00002C08 - X"30C60007", -- 00002C0C - X"ACE80000", -- 00002C10 - X"ACE80004", -- 00002C14 - X"24E70008", -- 00002C18 - X"1440FFFC", -- 00002C1C - X"2442FFFF", -- 00002C20 - X"2CC20004", -- 00002C24 - X"14400004", -- 00002C28 - X"00000000", -- 00002C2C - X"ACE80000", -- 00002C30 - X"24C6FFFC", -- 00002C34 - X"24E70004", -- 00002C38 - X"10C00006", -- 00002C3C - X"00E01821", -- 00002C40 - X"A0650000", -- 00002C44 - X"24C6FFFF", -- 00002C48 - X"24630001", -- 00002C4C - X"14C0FFFC", -- 00002C50 - X"00000000", -- 00002C54 - X"03E00008", -- 00002C58 - X"00801021", -- 00002C5C - X"00000000", -- 00002C60 - X"00000000", -- 00002C64 - X"00000000", -- 00002C68 - X"00000000", -- 00002C6C - X"00000000", -- 00002C70 - X"00000000", -- 00002C74 - X"00000000", -- 00002C78 - X"00000000", -- 00002C7C - X"00000000", -- 00002C80 - X"00000000", -- 00002C84 - X"00000000", -- 00002C88 - X"00000000", -- 00002C8C - X"00000000", -- 00002C90 - X"00000000", -- 00002C94 - X"00000000", -- 00002C98 - X"00000000", -- 00002C9C - X"00000000", -- 00002CA0 - X"00000000", -- 00002CA4 - X"00000000", -- 00002CA8 - X"00000000", -- 00002CAC - X"00000000", -- 00002CB0 - X"00000000", -- 00002CB4 - X"00000000", -- 00002CB8 - X"00000000", -- 00002CBC - X"00000000", -- 00002CC0 - X"00000000", -- 00002CC4 - X"00000000", -- 00002CC8 - X"00000000", -- 00002CCC - X"00000000", -- 00002CD0 - X"00000000", -- 00002CD4 - X"00000000", -- 00002CD8 - X"00000000", -- 00002CDC - X"00000000", -- 00002CE0 - X"00000000", -- 00002CE4 - X"00000000", -- 00002CE8 - X"00000000", -- 00002CEC - X"00000000", -- 00002CF0 - X"00000000", -- 00002CF4 - X"00000000", -- 00002CF8 - X"00000000", -- 00002CFC - X"00000000", -- 00002D00 - X"00000000", -- 00002D04 - X"00000000", -- 00002D08 - X"00000000", -- 00002D0C - X"00000000", -- 00002D10 - X"00000000", -- 00002D14 - X"00000000", -- 00002D18 - X"00000000", -- 00002D1C - X"00000000", -- 00002D20 - X"00000000", -- 00002D24 - X"00000000", -- 00002D28 - X"00000000", -- 00002D2C - X"00000000", -- 00002D30 - X"00000000", -- 00002D34 - X"00000000", -- 00002D38 - X"00000000", -- 00002D3C - X"00000000", -- 00002D40 - X"00000000", -- 00002D44 - X"00000000", -- 00002D48 - X"00000000", -- 00002D4C - X"00000000", -- 00002D50 - X"00000000", -- 00002D54 - X"00000000", -- 00002D58 - X"00000000", -- 00002D5C - X"00000000", -- 00002D60 - X"00000000", -- 00002D64 - X"00000000", -- 00002D68 - X"00000000", -- 00002D6C - X"00000000", -- 00002D70 - X"00000000", -- 00002D74 - X"00000000", -- 00002D78 - X"00000000", -- 00002D7C - X"00000000", -- 00002D80 - X"00000000", -- 00002D84 - X"00000000", -- 00002D88 - X"00000000", -- 00002D8C - X"00000000", -- 00002D90 - X"00000000", -- 00002D94 - X"00000000", -- 00002D98 - X"00000000", -- 00002D9C - X"00000000", -- 00002DA0 - X"00000000", -- 00002DA4 - X"00000000", -- 00002DA8 - X"00000000", -- 00002DAC - X"00000000", -- 00002DB0 - X"00000000", -- 00002DB4 - X"00000000", -- 00002DB8 - X"00000000", -- 00002DBC - X"00000000", -- 00002DC0 - X"00000000", -- 00002DC4 - X"00000000", -- 00002DC8 - X"00000000", -- 00002DCC - X"00000000", -- 00002DD0 - X"00000000", -- 00002DD4 - X"00000000", -- 00002DD8 - X"00000000", -- 00002DDC - X"00000000", -- 00002DE0 - X"00000000", -- 00002DE4 - X"00000000", -- 00002DE8 - X"00000000", -- 00002DEC - X"00000000", -- 00002DF0 - X"00000000", -- 00002DF4 - X"00000000", -- 00002DF8 - X"00000000", -- 00002DFC - X"00000000", -- 00002E00 - X"00000000", -- 00002E04 - X"00000000", -- 00002E08 - X"00000000", -- 00002E0C - X"00000000", -- 00002E10 - X"00000000", -- 00002E14 - X"00000000", -- 00002E18 - X"00000000", -- 00002E1C - X"00000000", -- 00002E20 - X"00000000", -- 00002E24 - X"00000000", -- 00002E28 - X"00000000", -- 00002E2C - X"00000000", -- 00002E30 - X"00000000", -- 00002E34 - X"00000000", -- 00002E38 - X"00000000", -- 00002E3C - X"00000000", -- 00002E40 - X"00000000", -- 00002E44 - X"00000000", -- 00002E48 - X"00000000", -- 00002E4C - X"00000000", -- 00002E50 - X"00000000", -- 00002E54 - X"00000000", -- 00002E58 - X"00000000", -- 00002E5C - X"00000000", -- 00002E60 - X"00000000", -- 00002E64 - X"00000000", -- 00002E68 - X"00000000", -- 00002E6C - X"00000000", -- 00002E70 - X"00000000", -- 00002E74 - X"00000000", -- 00002E78 - X"00000000", -- 00002E7C - X"00000000", -- 00002E80 - X"00000000", -- 00002E84 - X"00000000", -- 00002E88 - X"00000000", -- 00002E8C - X"00000000", -- 00002E90 - X"00000000", -- 00002E94 - X"00000000", -- 00002E98 - X"00000000", -- 00002E9C - X"00000000", -- 00002EA0 - X"00000000", -- 00002EA4 - X"00000000", -- 00002EA8 - X"00000000", -- 00002EAC - X"00000000", -- 00002EB0 - X"00000000", -- 00002EB4 - X"00000000", -- 00002EB8 - X"00000000", -- 00002EBC - X"00000000", -- 00002EC0 - X"00000000", -- 00002EC4 - X"00000000", -- 00002EC8 - X"00000000", -- 00002ECC - X"00000000", -- 00002ED0 - X"00000000", -- 00002ED4 - X"00000000", -- 00002ED8 - X"00000000", -- 00002EDC - X"00000000", -- 00002EE0 - X"00000000", -- 00002EE4 - X"00000000", -- 00002EE8 - X"00000000", -- 00002EEC - X"00000000", -- 00002EF0 - X"00000000", -- 00002EF4 - X"00000000", -- 00002EF8 - X"00000000", -- 00002EFC - X"00000000", -- 00002F00 - X"00000000", -- 00002F04 - X"00000000", -- 00002F08 - X"00000000", -- 00002F0C - X"00000000", -- 00002F10 - X"00000000", -- 00002F14 - X"00000000", -- 00002F18 - X"00000000", -- 00002F1C - X"00000000", -- 00002F20 - X"00000000", -- 00002F24 - X"00000000", -- 00002F28 - X"00000000", -- 00002F2C - X"00000000", -- 00002F30 - X"00000000", -- 00002F34 - X"00000000", -- 00002F38 - X"00000000", -- 00002F3C - X"00000000", -- 00002F40 - X"00000000", -- 00002F44 - X"00000000", -- 00002F48 - X"00000000", -- 00002F4C - X"00000000", -- 00002F50 - X"00000000", -- 00002F54 - X"00000000", -- 00002F58 - X"00000000", -- 00002F5C - X"00000000", -- 00002F60 - X"00000000", -- 00002F64 - X"00000000", -- 00002F68 - X"00000000", -- 00002F6C - X"00000000", -- 00002F70 - X"00000000", -- 00002F74 - X"00000000", -- 00002F78 - X"00000000", -- 00002F7C - X"00000000", -- 00002F80 - X"00000000", -- 00002F84 - X"00000000", -- 00002F88 - X"00000000", -- 00002F8C - X"00000000", -- 00002F90 - X"00000000", -- 00002F94 - X"00000000", -- 00002F98 - X"00000000", -- 00002F9C - X"00000000", -- 00002FA0 - X"00000000", -- 00002FA4 - X"00000000", -- 00002FA8 - X"00000000", -- 00002FAC - X"00000000", -- 00002FB0 - X"00000000", -- 00002FB4 - X"00000000", -- 00002FB8 - X"00000000", -- 00002FBC - X"00000000", -- 00002FC0 - X"00000000", -- 00002FC4 - X"00000000", -- 00002FC8 - X"00000000", -- 00002FCC - X"00000000", -- 00002FD0 - X"00000000", -- 00002FD4 - X"00000000", -- 00002FD8 - X"00000000", -- 00002FDC - X"00000000", -- 00002FE0 - X"00000000", -- 00002FE4 - X"00000000", -- 00002FE8 - X"00000000", -- 00002FEC - X"00000000", -- 00002FF0 - X"00000000", -- 00002FF4 - X"00000000", -- 00002FF8 - X"00000000", -- 00002FFC - X"00000000", -- 00003000 - X"00000000", -- 00003004 - X"00000000", -- 00003008 - X"00000000", -- 0000300C - X"00000000", -- 00003010 - X"00000000", -- 00003014 - X"00000000", -- 00003018 - X"00000000", -- 0000301C - X"00000000", -- 00003020 - X"00000000", -- 00003024 - X"00000000", -- 00003028 - X"00000000", -- 0000302C - X"00000000", -- 00003030 - X"00000000", -- 00003034 - X"00000000", -- 00003038 - X"00000000", -- 0000303C - X"00000000", -- 00003040 - X"00000000", -- 00003044 - X"00000000", -- 00003048 - X"00000000", -- 0000304C - X"00000000", -- 00003050 - X"00000000", -- 00003054 - X"00000000", -- 00003058 - X"00000000", -- 0000305C - X"00000000", -- 00003060 - X"00000000", -- 00003064 - X"00000000", -- 00003068 - X"00000000", -- 0000306C - X"00000000", -- 00003070 - X"00000000", -- 00003074 - X"00000000", -- 00003078 - X"00000000", -- 0000307C - X"00000000", -- 00003080 - X"00000000", -- 00003084 - X"00000000", -- 00003088 - X"00000000", -- 0000308C - X"00000000", -- 00003090 - X"00000000", -- 00003094 - X"00000000", -- 00003098 - X"00000000", -- 0000309C - X"00000000", -- 000030A0 - X"00000000", -- 000030A4 - X"00000000", -- 000030A8 - X"00000000", -- 000030AC - X"00000000", -- 000030B0 - X"00000000", -- 000030B4 - X"00000000", -- 000030B8 - X"00000000", -- 000030BC - X"00000000", -- 000030C0 - X"00000000", -- 000030C4 - X"00000000", -- 000030C8 - X"00000000", -- 000030CC - X"00000000", -- 000030D0 - X"00000000", -- 000030D4 - X"00000000", -- 000030D8 - X"00000000", -- 000030DC - X"00000000", -- 000030E0 - X"00000000", -- 000030E4 - X"00000000", -- 000030E8 - X"00000000", -- 000030EC - X"00000000", -- 000030F0 - X"00000000", -- 000030F4 - X"00000000", -- 000030F8 - X"00000000", -- 000030FC - X"00000000", -- 00003100 - X"00000000", -- 00003104 - X"00000000", -- 00003108 - X"00000000", -- 0000310C - X"00000000", -- 00003110 - X"00000000", -- 00003114 - X"00000000", -- 00003118 - X"00000000", -- 0000311C - X"00000000", -- 00003120 - X"00000000", -- 00003124 - X"00000000", -- 00003128 - X"00000000", -- 0000312C - X"00000000", -- 00003130 - X"00000000", -- 00003134 - X"00000000", -- 00003138 - X"00000000", -- 0000313C - X"00000000", -- 00003140 - X"00000000", -- 00003144 - X"00000000", -- 00003148 - X"00000000", -- 0000314C - X"00000000", -- 00003150 - X"00000000", -- 00003154 - X"00000000", -- 00003158 - X"00000000", -- 0000315C - X"00000000", -- 00003160 - X"00000000", -- 00003164 - X"00000000", -- 00003168 - X"00000000", -- 0000316C - X"00000000", -- 00003170 - X"00000000", -- 00003174 - X"00000000", -- 00003178 - X"00000000", -- 0000317C - X"00000000", -- 00003180 - X"00000000", -- 00003184 - X"00000000", -- 00003188 - X"00000000", -- 0000318C - X"00000000", -- 00003190 - X"00000000", -- 00003194 - X"00000000", -- 00003198 - X"00000000", -- 0000319C - X"00000000", -- 000031A0 - X"00000000", -- 000031A4 - X"00000000", -- 000031A8 - X"00000000", -- 000031AC - X"00000000", -- 000031B0 - X"00000000", -- 000031B4 - X"00000000", -- 000031B8 - X"00000000", -- 000031BC - X"00000000", -- 000031C0 - X"00000000", -- 000031C4 - X"00000000", -- 000031C8 - X"00000000", -- 000031CC - X"00000000", -- 000031D0 - X"00000000", -- 000031D4 - X"00000000", -- 000031D8 - X"00000000", -- 000031DC - X"00000000", -- 000031E0 - X"00000000", -- 000031E4 - X"00000000", -- 000031E8 - X"00000000", -- 000031EC - X"00000000", -- 000031F0 - X"00000000", -- 000031F4 - X"00000000", -- 000031F8 - X"00000000", -- 000031FC - X"00000000", -- 00003200 - X"00000000", -- 00003204 - X"00000000", -- 00003208 - X"00000000", -- 0000320C - X"00000000", -- 00003210 - X"00000000", -- 00003214 - X"00000000", -- 00003218 - X"00000000", -- 0000321C - X"00000000", -- 00003220 - X"00000000", -- 00003224 - X"00000000", -- 00003228 - X"00000000", -- 0000322C - X"00000000", -- 00003230 - X"00000000", -- 00003234 - X"00000000", -- 00003238 - X"00000000", -- 0000323C - X"00000000", -- 00003240 - X"00000000", -- 00003244 - X"00000000", -- 00003248 - X"00000000", -- 0000324C - X"00000000", -- 00003250 - X"00000000", -- 00003254 - X"00000000", -- 00003258 - X"00000000", -- 0000325C - X"00000000", -- 00003260 - X"00000000", -- 00003264 - X"00000000", -- 00003268 - X"00000000", -- 0000326C - X"00000000", -- 00003270 - X"00000000", -- 00003274 - X"00000000", -- 00003278 - X"00000000", -- 0000327C - X"00000000", -- 00003280 - X"00000000", -- 00003284 - X"00000000", -- 00003288 - X"00000000", -- 0000328C - X"00000000", -- 00003290 - X"00000000", -- 00003294 - X"00000000", -- 00003298 - X"00000000", -- 0000329C - X"00000000", -- 000032A0 - X"00000000", -- 000032A4 - X"00000000", -- 000032A8 - X"00000000", -- 000032AC - X"00000000", -- 000032B0 - X"00000000", -- 000032B4 - X"00000000", -- 000032B8 - X"00000000", -- 000032BC - X"00000000", -- 000032C0 - X"00000000", -- 000032C4 - X"00000000", -- 000032C8 - X"00000000", -- 000032CC - X"00000000", -- 000032D0 - X"00000000", -- 000032D4 - X"00000000", -- 000032D8 - X"00000000", -- 000032DC - X"00000000", -- 000032E0 - X"00000000", -- 000032E4 - X"00000000", -- 000032E8 - X"00000000", -- 000032EC - X"00000000", -- 000032F0 - X"00000000", -- 000032F4 - X"00000000", -- 000032F8 - X"00000000", -- 000032FC - X"00000000", -- 00003300 - X"00000000", -- 00003304 - X"00000000", -- 00003308 - X"00000000", -- 0000330C - X"00000000", -- 00003310 - X"00000000", -- 00003314 - X"00000000", -- 00003318 - X"00000000", -- 0000331C - X"00000000", -- 00003320 - X"00000000", -- 00003324 - X"00000000", -- 00003328 - X"00000000", -- 0000332C - X"00000000", -- 00003330 - X"00000000", -- 00003334 - X"00000000", -- 00003338 - X"00000000", -- 0000333C - X"00000000", -- 00003340 - X"00000000", -- 00003344 - X"00000000", -- 00003348 - X"00000000", -- 0000334C - X"00000000", -- 00003350 - X"00000000", -- 00003354 - X"00000000", -- 00003358 - X"00000000", -- 0000335C - X"00000000", -- 00003360 - X"00000000", -- 00003364 - X"00000000", -- 00003368 - X"00000000", -- 0000336C - X"00000000", -- 00003370 - X"00000000", -- 00003374 - X"00000000", -- 00003378 - X"00000000", -- 0000337C - X"00000000", -- 00003380 - X"00000000", -- 00003384 - X"00000000", -- 00003388 - X"00000000", -- 0000338C - X"00000000", -- 00003390 - X"00000000", -- 00003394 - X"00000000", -- 00003398 - X"00000000", -- 0000339C - X"00000000", -- 000033A0 - X"00000000", -- 000033A4 - X"00000000", -- 000033A8 - X"00000000", -- 000033AC - X"00000000", -- 000033B0 - X"00000000", -- 000033B4 - X"00000000", -- 000033B8 - X"00000000", -- 000033BC - X"00000000", -- 000033C0 - X"00000000", -- 000033C4 - X"00000000", -- 000033C8 - X"00000000", -- 000033CC - X"00000000", -- 000033D0 - X"00000000", -- 000033D4 - X"00000000", -- 000033D8 - X"00000000", -- 000033DC - X"00000000", -- 000033E0 - X"00000000", -- 000033E4 - X"00000000", -- 000033E8 - X"00000000", -- 000033EC - X"00000000", -- 000033F0 - X"00000000", -- 000033F4 - X"00000000", -- 000033F8 - X"00000000", -- 000033FC - X"00000000", -- 00003400 - X"00000000", -- 00003404 - X"00000000", -- 00003408 - X"00000000", -- 0000340C - X"00000000", -- 00003410 - X"00000000", -- 00003414 - X"00000000", -- 00003418 - X"00000000", -- 0000341C - X"00000000", -- 00003420 - X"00000000", -- 00003424 - X"00000000", -- 00003428 - X"00000000", -- 0000342C - X"00000000", -- 00003430 - X"00000000", -- 00003434 - X"00000000", -- 00003438 - X"00000000", -- 0000343C - X"00000000", -- 00003440 - X"00000000", -- 00003444 - X"00000000", -- 00003448 - X"00000000", -- 0000344C - X"00000000", -- 00003450 - X"00000000", -- 00003454 - X"00000000", -- 00003458 - X"00000000", -- 0000345C - X"00000000", -- 00003460 - X"00000000", -- 00003464 - X"00000000", -- 00003468 - X"00000000", -- 0000346C - X"00000000", -- 00003470 - X"00000000", -- 00003474 - X"00000000", -- 00003478 - X"00000000", -- 0000347C - X"00000000", -- 00003480 - X"00000000", -- 00003484 - X"00000000", -- 00003488 - X"00000000", -- 0000348C - X"00000000", -- 00003490 - X"00000000", -- 00003494 - X"00000000", -- 00003498 - X"00000000", -- 0000349C - X"00000000", -- 000034A0 - X"00000000", -- 000034A4 - X"00000000", -- 000034A8 - X"00000000", -- 000034AC - X"00000000", -- 000034B0 - X"00000000", -- 000034B4 - X"00000000", -- 000034B8 - X"00000000", -- 000034BC - X"00000000", -- 000034C0 - X"00000000", -- 000034C4 - X"00000000", -- 000034C8 - X"00000000", -- 000034CC - X"00000000", -- 000034D0 - X"00000000", -- 000034D4 - X"00000000", -- 000034D8 - X"00000000", -- 000034DC - X"00000000", -- 000034E0 - X"00000000", -- 000034E4 - X"00000000", -- 000034E8 - X"00000000", -- 000034EC - X"00000000", -- 000034F0 - X"00000000", -- 000034F4 - X"00000000", -- 000034F8 - X"00000000", -- 000034FC - X"00000000", -- 00003500 - X"00000000", -- 00003504 - X"00000000", -- 00003508 - X"00000000", -- 0000350C - X"00000000", -- 00003510 - X"00000000", -- 00003514 - X"00000000", -- 00003518 - X"00000000", -- 0000351C - X"00000000", -- 00003520 - X"00000000", -- 00003524 - X"00000000", -- 00003528 - X"00000000", -- 0000352C - X"00000000", -- 00003530 - X"00000000", -- 00003534 - X"00000000", -- 00003538 - X"00000000", -- 0000353C - X"00000000", -- 00003540 - X"00000000", -- 00003544 - X"00000000", -- 00003548 - X"00000000", -- 0000354C - X"00000000", -- 00003550 - X"00000000", -- 00003554 - X"00000000", -- 00003558 - X"00000000", -- 0000355C - X"00000000", -- 00003560 - X"00000000", -- 00003564 - X"00000000", -- 00003568 - X"00000000", -- 0000356C - X"00000000", -- 00003570 - X"00000000", -- 00003574 - X"00000000", -- 00003578 - X"00000000", -- 0000357C - X"00000000", -- 00003580 - X"00000000", -- 00003584 - X"00000000", -- 00003588 - X"00000000", -- 0000358C - X"00000000", -- 00003590 - X"00000000", -- 00003594 - X"00000000", -- 00003598 - X"00000000", -- 0000359C - X"00000000", -- 000035A0 - X"00000000", -- 000035A4 - X"00000000", -- 000035A8 - X"00000000", -- 000035AC - X"00000000", -- 000035B0 - X"00000000", -- 000035B4 - X"00000000", -- 000035B8 - X"00000000", -- 000035BC - X"00000000", -- 000035C0 - X"00000000", -- 000035C4 - X"00000000", -- 000035C8 - X"00000000", -- 000035CC - X"00000000", -- 000035D0 - X"00000000", -- 000035D4 - X"00000000", -- 000035D8 - X"00000000", -- 000035DC - X"00000000", -- 000035E0 - X"00000000", -- 000035E4 - X"00000000", -- 000035E8 - X"00000000", -- 000035EC - X"00000000", -- 000035F0 - X"00000000", -- 000035F4 - X"00000000", -- 000035F8 - X"00000000", -- 000035FC - X"00000000", -- 00003600 - X"00000000", -- 00003604 - X"00000000", -- 00003608 - X"00000000", -- 0000360C - X"00000000", -- 00003610 - X"00000000", -- 00003614 - X"00000000", -- 00003618 - X"00000000", -- 0000361C - X"00000000", -- 00003620 - X"00000000", -- 00003624 - X"00000000", -- 00003628 - X"00000000", -- 0000362C - X"00000000", -- 00003630 - X"00000000", -- 00003634 - X"00000000", -- 00003638 - X"00000000", -- 0000363C - X"00000000", -- 00003640 - X"00000000", -- 00003644 - X"00000000", -- 00003648 - X"00000000", -- 0000364C - X"00000000", -- 00003650 - X"00000000", -- 00003654 - X"00000000", -- 00003658 - X"00000000", -- 0000365C - X"00000000", -- 00003660 - X"00000000", -- 00003664 - X"00000000", -- 00003668 - X"00000000", -- 0000366C - X"00000000", -- 00003670 - X"00000000", -- 00003674 - X"00000000", -- 00003678 - X"00000000", -- 0000367C - X"00000000", -- 00003680 - X"00000000", -- 00003684 - X"00000000", -- 00003688 - X"00000000", -- 0000368C - X"00000000", -- 00003690 - X"00000000", -- 00003694 - X"00000000", -- 00003698 - X"00000000", -- 0000369C - X"00000000", -- 000036A0 - X"00000000", -- 000036A4 - X"00000000", -- 000036A8 - X"00000000", -- 000036AC - X"00000000", -- 000036B0 - X"00000000", -- 000036B4 - X"00000000", -- 000036B8 - X"00000000", -- 000036BC - X"00000000", -- 000036C0 - X"00000000", -- 000036C4 - X"00000000", -- 000036C8 - X"00000000", -- 000036CC - X"00000000", -- 000036D0 - X"00000000", -- 000036D4 - X"00000000", -- 000036D8 - X"00000000", -- 000036DC - X"00000000", -- 000036E0 - X"00000000", -- 000036E4 - X"00000000", -- 000036E8 - X"00000000", -- 000036EC - X"00000000", -- 000036F0 - X"00000000", -- 000036F4 - X"00000000", -- 000036F8 - X"00000000", -- 000036FC - X"00000000", -- 00003700 - X"00000000", -- 00003704 - X"00000000", -- 00003708 - X"00000000", -- 0000370C - X"00000000", -- 00003710 - X"00000000", -- 00003714 - X"00000000", -- 00003718 - X"00000000", -- 0000371C - X"00000000", -- 00003720 - X"00000000", -- 00003724 - X"00000000", -- 00003728 - X"00000000", -- 0000372C - X"00000000", -- 00003730 - X"00000000", -- 00003734 - X"00000000", -- 00003738 - X"00000000", -- 0000373C - X"00000000", -- 00003740 - X"00000000", -- 00003744 - X"00000000", -- 00003748 - X"00000000", -- 0000374C - X"00000000", -- 00003750 - X"00000000", -- 00003754 - X"00000000", -- 00003758 - X"00000000", -- 0000375C - X"00000000", -- 00003760 - X"00000000", -- 00003764 - X"00000000", -- 00003768 - X"00000000", -- 0000376C - X"00000000", -- 00003770 - X"00000000", -- 00003774 - X"00000000", -- 00003778 - X"00000000", -- 0000377C - X"00000000", -- 00003780 - X"00000000", -- 00003784 - X"00000000", -- 00003788 - X"00000000", -- 0000378C - X"00000000", -- 00003790 - X"00000000", -- 00003794 - X"00000000", -- 00003798 - X"00000000", -- 0000379C - X"00000000", -- 000037A0 - X"00000000", -- 000037A4 - X"00000000", -- 000037A8 - X"00000000", -- 000037AC - X"00000000", -- 000037B0 - X"00000000", -- 000037B4 - X"00000000", -- 000037B8 - X"00000000", -- 000037BC - X"00000000", -- 000037C0 - X"00000000", -- 000037C4 - X"00000000", -- 000037C8 - X"00000000", -- 000037CC - X"00000000", -- 000037D0 - X"00000000", -- 000037D4 - X"00000000", -- 000037D8 - X"00000000", -- 000037DC - X"00000000", -- 000037E0 - X"00000000", -- 000037E4 - X"00000000", -- 000037E8 - X"00000000", -- 000037EC - X"00000000", -- 000037F0 - X"00000000", -- 000037F4 - X"00000000", -- 000037F8 - X"00000000", -- 000037FC - X"00000000", -- 00003800 - X"00000000", -- 00003804 - X"00000000", -- 00003808 - X"00000000", -- 0000380C - X"00000000", -- 00003810 - X"00000000", -- 00003814 - X"00000000", -- 00003818 - X"00000000", -- 0000381C - X"00000000", -- 00003820 - X"00000000", -- 00003824 - X"00000000", -- 00003828 - X"00000000", -- 0000382C - X"00000000", -- 00003830 - X"00000000", -- 00003834 - X"00000000", -- 00003838 - X"00000000", -- 0000383C - X"00000000", -- 00003840 - X"00000000", -- 00003844 - X"00000000", -- 00003848 - X"00000000", -- 0000384C - X"00000000", -- 00003850 - X"00000000", -- 00003854 - X"00000000", -- 00003858 - X"00000000", -- 0000385C - X"00000000", -- 00003860 - X"00000000", -- 00003864 - X"00000000", -- 00003868 - X"00000000", -- 0000386C - X"00000000", -- 00003870 - X"00000000", -- 00003874 - X"00000000", -- 00003878 - X"00000000", -- 0000387C - X"00000000", -- 00003880 - X"00000000", -- 00003884 - X"00000000", -- 00003888 - X"00000000", -- 0000388C - X"00000000", -- 00003890 - X"00000000", -- 00003894 - X"00000000", -- 00003898 - X"00000000", -- 0000389C - X"00000000", -- 000038A0 - X"00000000", -- 000038A4 - X"00000000", -- 000038A8 - X"00000000", -- 000038AC - X"00000000", -- 000038B0 - X"00000000", -- 000038B4 - X"00000000", -- 000038B8 - X"00000000", -- 000038BC - X"00000000", -- 000038C0 - X"00000000", -- 000038C4 - X"00000000", -- 000038C8 - X"00000000", -- 000038CC - X"00000000", -- 000038D0 - X"00000000", -- 000038D4 - X"00000000", -- 000038D8 - X"00000000", -- 000038DC - X"00000000", -- 000038E0 - X"00000000", -- 000038E4 - X"00000000", -- 000038E8 - X"00000000", -- 000038EC - X"00000000", -- 000038F0 - X"00000000", -- 000038F4 - X"00000000", -- 000038F8 - X"00000000", -- 000038FC - X"00000000", -- 00003900 - X"00000000", -- 00003904 - X"00000000", -- 00003908 - X"00000000", -- 0000390C - X"00000000", -- 00003910 - X"00000000", -- 00003914 - X"00000000", -- 00003918 - X"00000000", -- 0000391C - X"00000000", -- 00003920 - X"00000000", -- 00003924 - X"00000000", -- 00003928 - X"00000000", -- 0000392C - X"00000000", -- 00003930 - X"00000000", -- 00003934 - X"00000000", -- 00003938 - X"00000000", -- 0000393C - X"00000000", -- 00003940 - X"00000000", -- 00003944 - X"00000000", -- 00003948 - X"00000000", -- 0000394C - X"00000000", -- 00003950 - X"00000000", -- 00003954 - X"00000000", -- 00003958 - X"00000000", -- 0000395C - X"00000000", -- 00003960 - X"00000000", -- 00003964 - X"00000000", -- 00003968 - X"00000000", -- 0000396C - X"00000000", -- 00003970 - X"00000000", -- 00003974 - X"00000000", -- 00003978 - X"00000000", -- 0000397C - X"00000000", -- 00003980 - X"00000000", -- 00003984 - X"00000000", -- 00003988 - X"00000000", -- 0000398C - X"00000000", -- 00003990 - X"00000000", -- 00003994 - X"00000000", -- 00003998 - X"00000000", -- 0000399C - X"00000000", -- 000039A0 - X"00000000", -- 000039A4 - X"00000000", -- 000039A8 - X"00000000", -- 000039AC - X"00000000", -- 000039B0 - X"00000000", -- 000039B4 - X"00000000", -- 000039B8 - X"00000000", -- 000039BC - X"00000000", -- 000039C0 - X"00000000", -- 000039C4 - X"00000000", -- 000039C8 - X"00000000", -- 000039CC - X"00000000", -- 000039D0 - X"00000000", -- 000039D4 - X"00000000", -- 000039D8 - X"00000000", -- 000039DC - X"00000000", -- 000039E0 - X"00000000", -- 000039E4 - X"00000000", -- 000039E8 - X"00000000", -- 000039EC - X"00000000", -- 000039F0 - X"00000000", -- 000039F4 - X"00000000", -- 000039F8 - X"00000000", -- 000039FC - X"00000000", -- 00003A00 - X"00000000", -- 00003A04 - X"00000000", -- 00003A08 - X"00000000", -- 00003A0C - X"00000000", -- 00003A10 - X"00000000", -- 00003A14 - X"00000000", -- 00003A18 - X"00000000", -- 00003A1C - X"00000000", -- 00003A20 - X"00000000", -- 00003A24 - X"00000000", -- 00003A28 - X"00000000", -- 00003A2C - X"00000000", -- 00003A30 - X"00000000", -- 00003A34 - X"00000000", -- 00003A38 - X"00000000", -- 00003A3C - X"00000000", -- 00003A40 - X"00000000", -- 00003A44 - X"00000000", -- 00003A48 - X"00000000", -- 00003A4C - X"00000000", -- 00003A50 - X"00000000", -- 00003A54 - X"00000000", -- 00003A58 - X"00000000", -- 00003A5C - X"00000000", -- 00003A60 - X"00000000", -- 00003A64 - X"00000000", -- 00003A68 - X"00000000", -- 00003A6C - X"00000000", -- 00003A70 - X"00000000", -- 00003A74 - X"00000000", -- 00003A78 - X"00000000", -- 00003A7C - X"00000000", -- 00003A80 - X"00000000", -- 00003A84 - X"00000000", -- 00003A88 - X"00000000", -- 00003A8C - X"00000000", -- 00003A90 - X"00000000", -- 00003A94 - X"00000000", -- 00003A98 - X"00000000", -- 00003A9C - X"00000000", -- 00003AA0 - X"00000000", -- 00003AA4 - X"00000000", -- 00003AA8 - X"00000000", -- 00003AAC - X"00000000", -- 00003AB0 - X"00000000", -- 00003AB4 - X"00000000", -- 00003AB8 - X"00000000", -- 00003ABC - X"00000000", -- 00003AC0 - X"00000000", -- 00003AC4 - X"00000000", -- 00003AC8 - X"00000000", -- 00003ACC - X"00000000", -- 00003AD0 - X"00000000", -- 00003AD4 - X"00000000", -- 00003AD8 - X"00000000", -- 00003ADC - X"00000000", -- 00003AE0 - X"00000000", -- 00003AE4 - X"00000000", -- 00003AE8 - X"00000000", -- 00003AEC - X"00000000", -- 00003AF0 - X"00000000", -- 00003AF4 - X"00000000", -- 00003AF8 - X"00000000", -- 00003AFC - X"00000000", -- 00003B00 - X"00000000", -- 00003B04 - X"00000000", -- 00003B08 - X"00000000", -- 00003B0C - X"00000000", -- 00003B10 - X"00000000", -- 00003B14 - X"00000000", -- 00003B18 - X"00000000", -- 00003B1C - X"00000000", -- 00003B20 - X"00000000", -- 00003B24 - X"00000000", -- 00003B28 - X"00000000", -- 00003B2C - X"00000000", -- 00003B30 - X"00000000", -- 00003B34 - X"00000000", -- 00003B38 - X"00000000", -- 00003B3C - X"00000000", -- 00003B40 - X"00000000", -- 00003B44 - X"00000000", -- 00003B48 - X"00000000", -- 00003B4C - X"00000000", -- 00003B50 - X"00000000", -- 00003B54 - X"00000000", -- 00003B58 - X"00000000", -- 00003B5C - X"00000000", -- 00003B60 - X"00000000", -- 00003B64 - X"00000000", -- 00003B68 - X"00000000", -- 00003B6C - X"00000000", -- 00003B70 - X"00000000", -- 00003B74 - X"00000000", -- 00003B78 - X"00000000", -- 00003B7C - X"00000000", -- 00003B80 - X"00000000", -- 00003B84 - X"00000000", -- 00003B88 - X"00000000", -- 00003B8C - X"00000000", -- 00003B90 - X"00000000", -- 00003B94 - X"00000000", -- 00003B98 - X"00000000", -- 00003B9C - X"00000000", -- 00003BA0 - X"00000000", -- 00003BA4 - X"00000000", -- 00003BA8 - X"00000000", -- 00003BAC - X"00000000", -- 00003BB0 - X"00000000", -- 00003BB4 - X"00000000", -- 00003BB8 - X"00000000", -- 00003BBC - X"00000000", -- 00003BC0 - X"00000000", -- 00003BC4 - X"00000000", -- 00003BC8 - X"00000000", -- 00003BCC - X"00000000", -- 00003BD0 - X"00000000", -- 00003BD4 - X"00000000", -- 00003BD8 - X"00000000", -- 00003BDC - X"00000000", -- 00003BE0 - X"00000000", -- 00003BE4 - X"00000000", -- 00003BE8 - X"00000000", -- 00003BEC - X"00000000", -- 00003BF0 - X"00000000", -- 00003BF4 - X"00000000", -- 00003BF8 - X"00000000", -- 00003BFC - X"00000000", -- 00003C00 - X"00000000", -- 00003C04 - X"00000000", -- 00003C08 - X"00000000", -- 00003C0C - X"00000000", -- 00003C10 - X"00000000", -- 00003C14 - X"00000000", -- 00003C18 - X"00000000", -- 00003C1C - X"00000000", -- 00003C20 - X"00000000", -- 00003C24 - X"00000000", -- 00003C28 - X"00000000", -- 00003C2C - X"00000000", -- 00003C30 - X"00000000", -- 00003C34 - X"00000000", -- 00003C38 - X"00000000", -- 00003C3C - X"00000000", -- 00003C40 - X"00000000", -- 00003C44 - X"00000000", -- 00003C48 - X"00000000", -- 00003C4C - X"00000000", -- 00003C50 - X"00000000", -- 00003C54 - X"00000000", -- 00003C58 - X"00000000", -- 00003C5C - X"00000000", -- 00003C60 - X"00000000", -- 00003C64 - X"00000000", -- 00003C68 - X"00000000", -- 00003C6C - X"00000000", -- 00003C70 - X"00000000", -- 00003C74 - X"00000000", -- 00003C78 - X"00000000", -- 00003C7C - X"00000000", -- 00003C80 - X"00000000", -- 00003C84 - X"00000000", -- 00003C88 - X"00000000", -- 00003C8C - X"00000000", -- 00003C90 - X"00000000", -- 00003C94 - X"00000000", -- 00003C98 - X"00000000", -- 00003C9C - X"00000000", -- 00003CA0 - X"00000000", -- 00003CA4 - X"00000000", -- 00003CA8 - X"00000000", -- 00003CAC - X"00000000", -- 00003CB0 - X"00000000", -- 00003CB4 - X"00000000", -- 00003CB8 - X"00000000", -- 00003CBC - X"00000000", -- 00003CC0 - X"00000000", -- 00003CC4 - X"00000000", -- 00003CC8 - X"00000000", -- 00003CCC - X"00000000", -- 00003CD0 - X"00000000", -- 00003CD4 - X"00000000", -- 00003CD8 - X"00000000", -- 00003CDC - X"00000000", -- 00003CE0 - X"00000000", -- 00003CE4 - X"00000000", -- 00003CE8 - X"00000000", -- 00003CEC - X"00000000", -- 00003CF0 - X"00000000", -- 00003CF4 - X"00000000", -- 00003CF8 - X"00000000", -- 00003CFC - X"00000000", -- 00003D00 - X"00000000", -- 00003D04 - X"00000000", -- 00003D08 - X"00000000", -- 00003D0C - X"00000000", -- 00003D10 - X"00000000", -- 00003D14 - X"00000000", -- 00003D18 - X"00000000", -- 00003D1C - X"00000000", -- 00003D20 - X"00000000", -- 00003D24 - X"00000000", -- 00003D28 - X"00000000", -- 00003D2C - X"00000000", -- 00003D30 - X"00000000", -- 00003D34 - X"00000000", -- 00003D38 - X"00000000", -- 00003D3C - X"00000000", -- 00003D40 - X"00000000", -- 00003D44 - X"00000000", -- 00003D48 - X"00000000", -- 00003D4C - X"00000000", -- 00003D50 - X"00000000", -- 00003D54 - X"00000000", -- 00003D58 - X"00000000", -- 00003D5C - X"00000000", -- 00003D60 - X"00000000", -- 00003D64 - X"00000000", -- 00003D68 - X"00000000", -- 00003D6C - X"00000000", -- 00003D70 - X"00000000", -- 00003D74 - X"00000000", -- 00003D78 - X"00000000", -- 00003D7C - X"00000000", -- 00003D80 - X"00000000", -- 00003D84 - X"00000000", -- 00003D88 - X"00000000", -- 00003D8C - X"00000000", -- 00003D90 - X"00000000", -- 00003D94 - X"00000000", -- 00003D98 - X"00000000", -- 00003D9C - X"00000000", -- 00003DA0 - X"00000000", -- 00003DA4 - X"00000000", -- 00003DA8 - X"00000000", -- 00003DAC - X"00000000", -- 00003DB0 - X"00000000", -- 00003DB4 - X"00000000", -- 00003DB8 - X"00000000", -- 00003DBC - X"00000000", -- 00003DC0 - X"00000000", -- 00003DC4 - X"00000000", -- 00003DC8 - X"00000000", -- 00003DCC - X"00000000", -- 00003DD0 - X"00000000", -- 00003DD4 - X"00000000", -- 00003DD8 - X"00000000", -- 00003DDC - X"00000000", -- 00003DE0 - X"00000000", -- 00003DE4 - X"00000000", -- 00003DE8 - X"00000000", -- 00003DEC - X"00000000", -- 00003DF0 - X"00000000", -- 00003DF4 - X"00000000", -- 00003DF8 - X"00000000", -- 00003DFC - X"00000000", -- 00003E00 - X"00000000", -- 00003E04 - X"00000000", -- 00003E08 - X"00000000", -- 00003E0C - X"00000000", -- 00003E10 - X"00000000", -- 00003E14 - X"00000000", -- 00003E18 - X"00000000", -- 00003E1C - X"00000000", -- 00003E20 - X"00000000", -- 00003E24 - X"00000000", -- 00003E28 - X"00000000", -- 00003E2C - X"00000000", -- 00003E30 - X"00000000", -- 00003E34 - X"00000000", -- 00003E38 - X"00000000", -- 00003E3C - X"00000000", -- 00003E40 - X"00000000", -- 00003E44 - X"00000000", -- 00003E48 - X"00000000", -- 00003E4C - X"00000000", -- 00003E50 - X"00000000", -- 00003E54 - X"00000000", -- 00003E58 - X"00000000", -- 00003E5C - X"00000000", -- 00003E60 - X"00000000", -- 00003E64 - X"00000000", -- 00003E68 - X"00000000", -- 00003E6C - X"00000000", -- 00003E70 - X"00000000", -- 00003E74 - X"00000000", -- 00003E78 - X"00000000", -- 00003E7C - X"00000000", -- 00003E80 - X"00000000", -- 00003E84 - X"00000000", -- 00003E88 - X"00000000", -- 00003E8C - X"00000000", -- 00003E90 - X"00000000", -- 00003E94 - X"00000000", -- 00003E98 - X"00000000", -- 00003E9C - X"00000000", -- 00003EA0 - X"00000000", -- 00003EA4 - X"00000000", -- 00003EA8 - X"00000000", -- 00003EAC - X"00000000", -- 00003EB0 - X"00000000", -- 00003EB4 - X"00000000", -- 00003EB8 - X"00000000", -- 00003EBC - X"00000000", -- 00003EC0 - X"00000000", -- 00003EC4 - X"00000000", -- 00003EC8 - X"00000000", -- 00003ECC - X"00000000", -- 00003ED0 - X"00000000", -- 00003ED4 - X"00000000", -- 00003ED8 - X"00000000", -- 00003EDC - X"00000000", -- 00003EE0 - X"00000000", -- 00003EE4 - X"00000000", -- 00003EE8 - X"00000000", -- 00003EEC - X"00000000", -- 00003EF0 - X"00000000", -- 00003EF4 - X"00000000", -- 00003EF8 - X"00000000", -- 00003EFC - X"00000000", -- 00003F00 - X"00000000", -- 00003F04 - X"00000000", -- 00003F08 - X"00000000", -- 00003F0C - X"00000000", -- 00003F10 - X"00000000", -- 00003F14 - X"00000000", -- 00003F18 - X"00000000", -- 00003F1C - X"00000000", -- 00003F20 - X"00000000", -- 00003F24 - X"00000000", -- 00003F28 - X"00000000", -- 00003F2C - X"00000000", -- 00003F30 - X"00000000", -- 00003F34 - X"00000000", -- 00003F38 - X"00000000", -- 00003F3C - X"00000000", -- 00003F40 - X"00000000", -- 00003F44 - X"00000000", -- 00003F48 - X"00000000", -- 00003F4C - X"00000000", -- 00003F50 - X"00000000", -- 00003F54 - X"00000000", -- 00003F58 - X"00000000", -- 00003F5C - X"00000000", -- 00003F60 - X"00000000", -- 00003F64 - X"00000000", -- 00003F68 - X"00000000", -- 00003F6C - X"00000000", -- 00003F70 - X"00000000", -- 00003F74 - X"00000000", -- 00003F78 - X"00000000", -- 00003F7C - X"00000000", -- 00003F80 - X"00000000", -- 00003F84 - X"00000000", -- 00003F88 - X"00000000", -- 00003F8C - X"00000000", -- 00003F90 - X"00000000", -- 00003F94 - X"00000000", -- 00003F98 - X"00000000", -- 00003F9C - X"00000000", -- 00003FA0 - X"00000000", -- 00003FA4 - X"00000000", -- 00003FA8 - X"00000000", -- 00003FAC - X"00000000", -- 00003FB0 - X"00000000", -- 00003FB4 - X"00000000", -- 00003FB8 - X"00000000", -- 00003FBC - X"00000000", -- 00003FC0 - X"00000000", -- 00003FC4 - X"00000000", -- 00003FC8 - X"00000000", -- 00003FCC - X"00000000", -- 00003FD0 - X"00000000", -- 00003FD4 - X"00000000", -- 00003FD8 - X"00000000", -- 00003FDC - X"00000000", -- 00003FE0 - X"00000000", -- 00003FE4 - X"00000000", -- 00003FE8 - X"00000000", -- 00003FEC - X"00000000", -- 00003FF0 - X"00000000", -- 00003FF4 - X"00000000", -- 00003FF8 - X"00000000" -- 00003FFC - ); - -begin - -PROM_READ: - process(clk) - begin - if rising_edge(clk) and ce = '1' then - dout <= word_array(to_integer(addr(13 downto 2))); - end if; - end process; - - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length); - jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout; - - end if; - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - word_array(to_integer(jtag_ld_addr(11 downto 0))) <= jtag_ld_din; - else - jtag_ld_dout <= word_array(to_integer(jtag_ld_addr(11 downto 0))); - end if; - end if; - end process; - -end data; diff --git a/lib/CPUs/MIPS/src/tb_eval_muldiv.vhd b/lib/CPUs/MIPS/src/tb_eval_muldiv.vhd deleted file mode 100644 index e4bbef2..0000000 --- a/lib/CPUs/MIPS/src/tb_eval_muldiv.vhd +++ /dev/null @@ -1,156 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.mips_types.all; -use work.mips_instr.all; - -ENTITY tb_eval_muldiv IS -END tb_eval_muldiv; - -ARCHITECTURE behavior OF tb_eval_muldiv IS - - constant CLK_PERIOD : time := 10 ns; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal ce : std_logic := '0'; - signal mul_divn : std_logic := '1'; - signal op_valid : std_logic := '0'; - signal op1_in : word_t := (others => '-'); - signal op2_in : word_t := (others => '-'); - signal result : unsigned (2*word_t'length-1 downto 0); - signal res_valid : std_logic; - signal busy : std_logic; - signal result_reg : unsigned (2*word_t'length-1 downto 0); - subtype pp_t is unsigned (39 downto 0); - - signal pp0, pp1, pp2, pp3 : pp_t; - - signal signed_mul : std_logic := '1'; - signal sign1 : std_logic; - signal sign2 : std_logic; - signal cy : std_logic; - -BEGIN - - sign1 <= signed_mul and op1_in(op1_in'left); - sign2 <= signed_mul and op2_in(op1_in'left); - cy <= sign1; - - pp0 <= op1_in * op2_in(7 downto 0); - pp1 <= op1_in * op2_in(15 downto 8); - pp2 <= op1_in * op2_in(23 downto 16); - pp3 <= op1_in * op2_in(31 downto 24); - - result <= ((63 downto 40 => '0') & pp0) - + ((63 downto 48 => '0') & pp1 & (7 downto 0 => '0')) - + ((63 downto 56 => '0') & pp2 & (15 downto 0 => '0')) - + (pp3 & (23 downto 0 => '0')); - - result_reg <= (63 downto 0 => sign1) xor (result + ((63 downto 0 => sign1) and X"0000_0000_0000_0000")); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - wait until rising_edge(clk); - rst <= '0'; - wait for 10*CLK_PERIOD; - - wait until rising_edge(clk); - ce <= '1'; - - wait for 10*CLK_PERIOD; - op1_in <= X"FFFF_FFFA"; -- (-6) - op2_in <= X"0000_0005"; -- (+5) - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait for 10*CLK_PERIOD; - op1_in <= X"0000_0006"; -- (+6) - op2_in <= X"FFFF_FFFB"; -- (-5) - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait for 10*CLK_PERIOD; - op1_in <= X"1234_5678"; - op2_in <= X"8765_4321"; - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait for 10*CLK_PERIOD; - op1_in <= X"8765_4321"; - op2_in <= X"1234_5678"; - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait for 10*CLK_PERIOD; - op1_in <= X"1234_5678"; - op2_in <= X"1234_5678"; - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait for 10*CLK_PERIOD; - op1_in <= X"8765_4321"; - op2_in <= X"8765_4321"; - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait for 10*CLK_PERIOD; - op1_in <= X"789A_BCDE"; - op2_in <= X"8765_4321"; - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait for 10*CLK_PERIOD; - op1_in <= X"8765_4321"; - op2_in <= X"789A_BCDE"; - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait; - - end process; - -END; diff --git a/lib/CPUs/MIPS/src/tb_mips_embedded.vhd b/lib/CPUs/MIPS/src/tb_mips_embedded.vhd deleted file mode 100644 index cbae0b7..0000000 --- a/lib/CPUs/MIPS/src/tb_mips_embedded.vhd +++ /dev/null @@ -1,82 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.mips_types.all; - -ENTITY tb_mips_embedded IS -END tb_mips_embedded; - -ARCHITECTURE behavior OF tb_mips_embedded IS - - COMPONENT mips_embedded - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - halt : in STD_LOGIC; - dout : out word_t - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal halt : std_logic := '0'; - signal dout : word_t; - -BEGIN - -uut: mips_embedded - PORT MAP( - rst => rst, - clk => clk, - halt => halt, - dout => dout - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -STIMULUS: process - begin - - wait for 3*CLK_PERIOD; - wait until rising_edge(clk); - rst <= '0'; - - wait; - - end process; - -END; diff --git a/lib/CPUs/MIPS/src/tb_mips_embedded_syn.vhd b/lib/CPUs/MIPS/src/tb_mips_embedded_syn.vhd deleted file mode 100644 index ac471b4..0000000 --- a/lib/CPUs/MIPS/src/tb_mips_embedded_syn.vhd +++ /dev/null @@ -1,123 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -ENTITY tb_mips_embedded_syn IS -END tb_mips_embedded_syn; - -ARCHITECTURE behavior OF tb_mips_embedded_syn IS - - COMPONENT mips_embedded_syn - Port - ( - sys_rst_n_in : in STD_LOGIC; - sys_clk_in : in STD_LOGIC; - sys_dip : in STD_LOGIC_VECTOR (7 downto 0); - sys_btn : in STD_LOGIC_VECTOR (8 downto 0); - sys_led : out STD_LOGIC_VECTOR (7 downto 0); - sys_rx : in STD_LOGIC; - sys_tx : out STD_LOGIC; - sys_error : out STD_LOGIC_VECTOR (1 downto 0) - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10.0 ns; - - signal sys_rst_n_in : std_logic := '0'; - signal sys_clk_in : std_logic := '1'; - signal sys_led : STD_LOGIC_VECTOR (7 downto 0); - signal sys_btn : STD_LOGIC_VECTOR (8 downto 0) := "000000000"; - signal sys_dip : STD_LOGIC_VECTOR (7 downto 0) := "10001001"; - signal sys_error : STD_LOGIC_VECTOR (1 downto 0); - signal sys_rx : std_logic := '1'; - signal sys_tx : std_logic; - -BEGIN - -uut: mips_embedded_syn - PORT MAP - ( - sys_rst_n_in => sys_rst_n_in, - sys_clk_in => sys_clk_in, - sys_btn => sys_btn, - sys_dip => sys_dip, - sys_led => sys_led, - sys_rx => sys_rx, - sys_tx => sys_tx, - sys_error => sys_error - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - sys_clk_in <= not sys_clk_in; - end process; - -STIMULUS1: process - begin - - wait for 3*CLK_PERIOD; - wait until rising_edge(sys_clk_in); - sys_rst_n_in <= '1'; - - - --- wait for 9994999*CLK_PERIOD; --- for i in 1 to 10000 loop --- wait for 100*CLK_PERIOD; --- sys_btn(3) <= '1'; --- wait for 10*CLK_PERIOD; --- sys_btn(3) <= '0'; --- end loop; - - wait until rising_edge(sys_clk_in) and now = 38980 ns; - sys_btn <= "000001000"; - wait until rising_edge(sys_clk_in); - sys_btn <= "000000000"; - - wait; - - end process; - -STIMULUS2: process - begin - - - wait for 9999999*CLK_PERIOD; - for i in 1 to 10000 loop - wait for 137*CLK_PERIOD; - sys_btn(4) <= '1'; - wait for 21*CLK_PERIOD; - sys_btn(4) <= '0'; - end loop; - - wait; - - end process; - -END; diff --git a/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd b/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd deleted file mode 100644 index 8235438..0000000 --- a/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd +++ /dev/null @@ -1,308 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; - -ENTITY tb_mips_muldiv IS -END tb_mips_muldiv; - -ARCHITECTURE behavior OF tb_mips_muldiv IS - - COMPONENT muldiv is - Port - ( - rst : in std_logic; - clk : in std_logic; - hilo_we : in std_logic; - din_hi : in word_t; - din_lo : in word_t; - mul_divn : in std_logic; - s_un : in std_logic; - start : in std_logic; - hilo_sel : in std_logic; - busy : out std_logic; - dout : out word_t - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - signal ENABLE_FAIL_REPORT : boolean := true; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal busy : std_logic; - signal mul_divn : std_logic := '0'; - signal s_un : std_logic := '1'; - signal hilo_we : std_logic := '0'; - signal start : std_logic := '0'; - signal din_hi : word_t := (others => '-'); - signal din_lo : word_t := (others => '-'); - signal ref_hi : word_t := (others => '-'); - signal ref_lo : word_t := (others => '-'); - signal dout : word_t; - signal hilo_sel : std_logic := '0'; - signal result : unsigned (2*word_t'length-1 downto 0); - signal ref_result : unsigned (2*word_t'length-1 downto 0); - - type word_array_t is array (natural range <>) of word_t; - - constant operands : word_array_t(0 to 63) := - ( - X"00000000", - X"00000001", - X"00000010", - X"00000100", - X"00001000", - X"00010000", - X"00100000", - X"01000000", - X"10000000", - X"0000000F", - X"000000FF", - X"00000FFF", - X"0000FFFF", - X"000FFFFF", - X"00FFFFFF", - X"0FFFFFFF", - X"12345678", - X"23456789", - X"7FFFFFFF", - X"80000000", - X"A541B3B9", - X"80000001", - X"80000010", - X"80000100", - X"80001000", - X"80010000", - X"80100000", - X"81000000", - X"87654321", - X"98765432", - X"FFFFFFFF", - X"FFFFFFFE", - X"FFFFFFFD", - X"FFFFFFFB", - X"FFFFFFF7", - X"FFFFFFEF", - X"FFFFFFDF", - X"FFFFFFBF", - X"FFFFFF7F", - X"FFFFFEFF", - X"FFFFFDFF", - X"FFFFFBFF", - X"FFFFF7FF", - X"FFFFEFFF", - X"FFFFDFFF", - X"FFFFBFFF", - X"FFFF7FFF", - X"FFFEFFFF", - X"FFFDFFFF", - X"FFFBFFFF", - X"FFF7FFFF", - X"FFEFFFFF", - X"FFDFFFFF", - X"FFBFFFFF", - X"FF7FFFFF", - X"FEFFFFFF", - X"FDFFFFFF", - X"FBFFFFFF", - X"F7FFFFFF", - X"EFFFFFFF", - X"DFFFFFFF", - X"BFFFFFFF", - X"CFFFFFFF", - X"7FFFFFFF" - ); - -BEGIN - -uut: muldiv - PORT MAP( - rst => rst, - clk => clk, - hilo_we => hilo_we, - din_hi => din_hi, - din_lo => din_lo, - mul_divn => mul_divn, - s_un => s_un, - start => start, - hilo_sel => hilo_sel, - busy => busy, - dout => dout - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -REF_GEN: process - variable tmp : unsigned (2*word_t'length-1 downto 0); - variable tmp2 : unsigned (word_t'length-1 downto 0); - begin - if mul_divn = '0' then - wait until rising_edge(clk) and start = '1'; - ref_lo <= din_lo; - ref_hi <= din_hi; - wait until rising_edge(clk) and busy = '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - if s_un = '1' then - tmp := unsigned(signed(result(31 downto 0)) * signed(ref_lo)); - tmp2 := unsigned(signed(tmp(31 downto 0)) + signed(result(63 downto 32))); - ref_result <= X"00000000" & tmp2(31 downto 0); - else - tmp := result(31 downto 0) * ref_lo; - tmp2 := tmp(31 downto 0) + result(63 downto 32); - ref_result <= X"00000000" & tmp2(31 downto 0); - end if; - wait until rising_edge(clk); - - if ref_lo /= X"00000000" then - if ENABLE_FAIL_REPORT then - assert ref_hi = ref_result(31 downto 0) report "Error on divison" severity failure; - end if; - end if; - else - wait until rising_edge(clk) and start = '1'; - wait until rising_edge(clk) and busy = '0'; - if s_un = '1' then - ref_result <= unsigned(signed(din_hi) * signed(din_lo)); - else - ref_result <= unsigned(din_hi) * unsigned(din_lo); - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - if ENABLE_FAIL_REPORT then - assert ref_result = result report "Error on multiplication" severity failure; - end if; - end if; - - end process; - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - wait until rising_edge(clk); - rst <= '0'; - wait for 2*CLK_PERIOD; - - mul_divn <= '0'; - s_un <= '0'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - result(31 downto 0) <= dout; - hilo_sel <= '1'; - wait until rising_edge(clk); - result(63 downto 32) <= dout; - wait for 2*CLK_PERIOD; - end loop; - end loop; - - s_un <= '1'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - result(31 downto 0) <= dout; - hilo_sel <= '1'; - wait until rising_edge(clk); - result(63 downto 32) <= dout; - wait for 2*CLK_PERIOD; - end loop; - end loop; - - mul_divn <= '1'; - s_un <= '0'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - result(31 downto 0) <= dout; - hilo_sel <= '1'; - wait until rising_edge(clk); - result(63 downto 32) <= dout; - end loop; - end loop; - - s_un <= '1'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - result(31 downto 0) <= dout; - hilo_sel <= '1'; - wait until rising_edge(clk); - result(63 downto 32) <= dout; - end loop; - end loop; - - wait; - - end process; - -END; diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd deleted file mode 100644 index 0bf5fed..0000000 --- a/lib/CPUs/MIPS/src/tb_mips_top.vhd +++ /dev/null @@ -1,174 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.mips_types.all; -use work.mips_instr.all; - -ENTITY tb_mips_top IS -END tb_mips_top; - -ARCHITECTURE behavior OF tb_mips_top IS - - COMPONENT mips_top - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - halt : in STD_LOGIC; - imem_din : in unsigned (WORD_WIDTH-1 downto 0); - imem_addr : out unsigned (WORD_WIDTH-1 downto 0); - dmem_we : out STD_LOGIC; - dmem_re : out STD_LOGIC; - dmem_din : in unsigned (WORD_WIDTH-1 downto 0); - dmem_dout : out unsigned (WORD_WIDTH-1 downto 0); - dmem_addr : out unsigned (WORD_WIDTH-1 downto 0) - - ); - END COMPONENT; - - COMPONENT rom - Port - ( - clk : in STD_LOGIC; - addr : in word_t; - dout : out word_t - ); - END COMPONENT; - - COMPONENT ram - Generic - ( - word_addr_width : integer - ); - Port - ( - clk : in STD_LOGIC; - we : in STD_LOGIC; - addr : in word_t; - din : in word_t; - dout : out word_t - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal cpu_halt : std_logic; - signal irom_data : word_t := (others => '-'); - signal irom_addr : word_t; - signal dmem_din : word_t := (others => '-'); - signal dmem_dout : word_t; - signal dmem_addr : word_t; - signal dmem_we : std_logic; - signal dmem_re : std_logic; - -BEGIN - -uut: mips_top - PORT MAP( - rst => rst, - clk => clk, - halt => cpu_halt, - imem_din => irom_data, - imem_addr => irom_addr, - dmem_we => dmem_we, - dmem_re => dmem_re, - dmem_din => dmem_din, - dmem_dout => dmem_dout, - dmem_addr => dmem_addr - ); - -inst_rom: rom - PORT MAP - ( - clk => clk, - addr => irom_addr, - dout => irom_data - ); - -inst_ram: ram - GENERIC MAP - ( - word_addr_width => 6 - ) - PORT MAP - ( - clk => clk, - we => dmem_we, - addr => dmem_addr, - din => dmem_dout, - dout => dmem_din - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -HLT_GEN: - process(rst, clk) - subtype cnt_t is natural range 0 to 2; - variable cnt : cnt_t; - begin - if rst = '1' then - cnt := cnt_t'high; - cpu_halt <= '0'; - elsif rising_edge(clk) then - cpu_halt <= '0'; - if cnt /= 0 then - cnt := cnt - 1; - else - cnt := cnt_t'high; - cpu_halt <= '1'; - end if; - end if; - end process; - -STIMULUS: process - - begin - --- for i in 0 to instr_name_array'length-1 loop --- fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i)); --- end loop; - - wait for 3*CLK_PERIOD; - wait until rising_edge(clk); - rst <= '0'; - wait for 2*CLK_PERIOD; - --- assert false report "Test finished" severity error; - wait; - - end process; - -END; diff --git a/lib/CPUs/MIPS/src/testbench.ROM_ld.vhd b/lib/CPUs/MIPS/src/testbench.ROM_ld.vhd deleted file mode 100644 index f46253b..0000000 --- a/lib/CPUs/MIPS/src/testbench.ROM_ld.vhd +++ /dev/null @@ -1,4222 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY icache IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END icache; - -ARCHITECTURE data OF icache IS - - subtype word_t is unsigned(31 downto 0); - type word_array_t is array (0 to 4095) of word_t; - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : unsigned (15 downto 0); - signal jtag_ld_dout : unsigned (31 downto 0); - signal jtag_ld_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - - signal word_array : word_array_t := - ( - - X"3C1A1040", -- 00000000 - X"375A040C", -- 00000004 - X"409A6000", -- 00000008 - X"241A0000", -- 0000000C - X"409A6800", -- 00000010 - X"401A7800", -- 00000014 - X"00000000", -- 00000018 - X"409AF800", -- 0000001C - X"3C1A0040", -- 00000020 - X"275A04F4", -- 00000024 - X"03400008", -- 00000028 - X"42000010", -- 0000002C - X"00000000", -- 00000030 - X"00000000", -- 00000034 - X"00000000", -- 00000038 - X"00000000", -- 0000003C - X"00000000", -- 00000040 - X"00000000", -- 00000044 - X"00000000", -- 00000048 - X"00000000", -- 0000004C - X"00000000", -- 00000050 - X"00000000", -- 00000054 - X"00000000", -- 00000058 - X"00000000", -- 0000005C - X"00000000", -- 00000060 - X"00000000", -- 00000064 - X"00000000", -- 00000068 - X"00000000", -- 0000006C - X"00000000", -- 00000070 - X"00000000", -- 00000074 - X"00000000", -- 00000078 - X"00000000", -- 0000007C - X"00000000", -- 00000080 - X"00000000", -- 00000084 - X"00000000", -- 00000088 - X"00000000", -- 0000008C - X"00000000", -- 00000090 - X"00000000", -- 00000094 - X"00000000", -- 00000098 - X"00000000", -- 0000009C - X"00000000", -- 000000A0 - X"00000000", -- 000000A4 - X"00000000", -- 000000A8 - X"00000000", -- 000000AC - X"00000000", -- 000000B0 - X"00000000", -- 000000B4 - X"00000000", -- 000000B8 - X"00000000", -- 000000BC - X"00000000", -- 000000C0 - X"00000000", -- 000000C4 - X"00000000", -- 000000C8 - X"00000000", -- 000000CC - X"00000000", -- 000000D0 - X"00000000", -- 000000D4 - X"00000000", -- 000000D8 - X"00000000", -- 000000DC - X"00000000", -- 000000E0 - X"00000000", -- 000000E4 - X"00000000", -- 000000E8 - X"00000000", -- 000000EC - X"00000000", -- 000000F0 - X"00000000", -- 000000F4 - X"00000000", -- 000000F8 - X"00000000", -- 000000FC - X"00000000", -- 00000100 - X"00000000", -- 00000104 - X"00000000", -- 00000108 - X"00000000", -- 0000010C - X"00000000", -- 00000110 - X"00000000", -- 00000114 - X"00000000", -- 00000118 - X"00000000", -- 0000011C - X"00000000", -- 00000120 - X"00000000", -- 00000124 - X"00000000", -- 00000128 - X"00000000", -- 0000012C - X"00000000", -- 00000130 - X"00000000", -- 00000134 - X"00000000", -- 00000138 - X"00000000", -- 0000013C - X"00000000", -- 00000140 - X"00000000", -- 00000144 - X"00000000", -- 00000148 - X"00000000", -- 0000014C - X"00000000", -- 00000150 - X"00000000", -- 00000154 - X"00000000", -- 00000158 - X"00000000", -- 0000015C - X"00000000", -- 00000160 - X"00000000", -- 00000164 - X"00000000", -- 00000168 - X"00000000", -- 0000016C - X"00000000", -- 00000170 - X"00000000", -- 00000174 - X"00000000", -- 00000178 - X"00000000", -- 0000017C - X"3C010000", -- 00000180 - X"AC3D09A0", -- 00000184 - X"3C1D0000", -- 00000188 - X"27BD09A0", -- 0000018C - X"27BD0004", -- 00000190 - X"AFA80000", -- 00000194 - X"27BD0004", -- 00000198 - X"AFA90000", -- 0000019C - X"27BD0004", -- 000001A0 - X"AFAA0000", -- 000001A4 - X"27BD0004", -- 000001A8 - X"AFAB0000", -- 000001AC - X"27BD0004", -- 000001B0 - X"AFAC0000", -- 000001B4 - X"27BD0004", -- 000001B8 - X"AFBF0000", -- 000001BC - X"400A4000", -- 000001C0 - X"27BD0004", -- 000001C4 - X"AFAA0000", -- 000001C8 - X"400A6000", -- 000001CC - X"27BD0004", -- 000001D0 - X"AFAA0000", -- 000001D4 - X"400A6800", -- 000001D8 - X"27BD0004", -- 000001DC - X"AFAA0000", -- 000001E0 - X"000A5742", -- 000001E4 - X"314B0004", -- 000001E8 - X"400A7000", -- 000001EC - X"27BD0004", -- 000001F0 - X"AFAA0000", -- 000001F4 - X"014B5021", -- 000001F8 - X"27BD0004", -- 000001FC - X"AFAA0000", -- 00000200 - X"3C1A8000", -- 00000204 - X"275A0009", -- 00000208 - X"241B000D", -- 0000020C - X"A35B0000", -- 00000210 - X"3C0B0000", -- 00000214 - X"256B0ADE", -- 00000218 - X"0C10012B", -- 0000021C - X"00000000", -- 00000220 - X"3C0B0000", -- 00000224 - X"256B0AA0", -- 00000228 - X"0C10012B", -- 0000022C - X"00000000", -- 00000230 - X"8FAA0000", -- 00000234 - X"27BDFFFC", -- 00000238 - X"0C1000E3", -- 0000023C - X"00000000", -- 00000240 - X"3C0B0000", -- 00000244 - X"256B0ADE", -- 00000248 - X"0C10012B", -- 0000024C - X"00000000", -- 00000250 - X"3C0B0000", -- 00000254 - X"256B0AAE", -- 00000258 - X"0C10012B", -- 0000025C - X"00000000", -- 00000260 - X"8FAA0000", -- 00000264 - X"27BDFFFC", -- 00000268 - X"0C1000E3", -- 0000026C - X"00000000", -- 00000270 - X"3C0B0000", -- 00000274 - X"256B0ADE", -- 00000278 - X"0C10012B", -- 0000027C - X"00000000", -- 00000280 - X"3C0B0000", -- 00000284 - X"256B0ABA", -- 00000288 - X"0C10012B", -- 0000028C - X"00000000", -- 00000290 - X"8FAA0000", -- 00000294 - X"27BDFFFC", -- 00000298 - X"0C1000E3", -- 0000029C - X"00000000", -- 000002A0 - X"3C0B0000", -- 000002A4 - X"256B0ADE", -- 000002A8 - X"0C10012B", -- 000002AC - X"00000000", -- 000002B0 - X"3C0B0000", -- 000002B4 - X"256B0AC6", -- 000002B8 - X"0C10012B", -- 000002BC - X"00000000", -- 000002C0 - X"8FAA0000", -- 000002C4 - X"27BDFFFC", -- 000002C8 - X"0C1000E3", -- 000002CC - X"00000000", -- 000002D0 - X"3C0B0000", -- 000002D4 - X"256B0ADE", -- 000002D8 - X"0C10012B", -- 000002DC - X"00000000", -- 000002E0 - X"3C0B0000", -- 000002E4 - X"256B0AD2", -- 000002E8 - X"0C10012B", -- 000002EC - X"00000000", -- 000002F0 - X"8FAA0000", -- 000002F4 - X"27BDFFFC", -- 000002F8 - X"0C1000E3", -- 000002FC - X"00000000", -- 00000300 - X"3C0B0000", -- 00000304 - X"256B0ADE", -- 00000308 - X"0C10012B", -- 0000030C - X"00000000", -- 00000310 - X"401A6800", -- 00000314 - X"3C1B8000", -- 00000318 - X"277B0000", -- 0000031C - X"001AD082", -- 00000320 - X"335A000F", -- 00000324 - X"035BD025", -- 00000328 - X"AF7A0000", -- 0000032C - X"401A6800", -- 00000330 - X"00000000", -- 00000334 - X"001AD202", -- 00000338 - X"335A00FF", -- 0000033C - X"1740FFFB", -- 00000340 - X"00000000", -- 00000344 - X"401A7000", -- 00000348 - X"8FBF0000", -- 0000034C - X"27BDFFFC", -- 00000350 - X"8FAC0000", -- 00000354 - X"27BDFFFC", -- 00000358 - X"8FAB0000", -- 0000035C - X"27BDFFFC", -- 00000360 - X"8FAA0000", -- 00000364 - X"27BDFFFC", -- 00000368 - X"8FA90000", -- 0000036C - X"27BDFFFC", -- 00000370 - X"8FA80000", -- 00000374 - X"27BDFFFC", -- 00000378 - X"3C1D0000", -- 0000037C - X"8FBD09A0", -- 00000380 - X"03400008", -- 00000384 - X"42000010", -- 00000388 - X"27BD0004", -- 0000038C - X"AFBF0000", -- 00000390 - X"27BD0004", -- 00000394 - X"AFAA0000", -- 00000398 - X"000A5402", -- 0000039C - X"0C1000F2", -- 000003A0 - X"00000000", -- 000003A4 - X"8FAA0000", -- 000003A8 - X"27BDFFFC", -- 000003AC - X"0C1000F2", -- 000003B0 - X"00000000", -- 000003B4 - X"8FBF0000", -- 000003B8 - X"27BDFFFC", -- 000003BC - X"03E00008", -- 000003C0 - X"00000000", -- 000003C4 - X"27BD0004", -- 000003C8 - X"AFBF0000", -- 000003CC - X"27BD0004", -- 000003D0 - X"AFAA0000", -- 000003D4 - X"000A5202", -- 000003D8 - X"0C100101", -- 000003DC - X"00000000", -- 000003E0 - X"8FAA0000", -- 000003E4 - X"27BDFFFC", -- 000003E8 - X"0C100101", -- 000003EC - X"00000000", -- 000003F0 - X"8FBF0000", -- 000003F4 - X"27BDFFFC", -- 000003F8 - X"03E00008", -- 000003FC - X"00000000", -- 00000400 - X"27BD0004", -- 00000404 - X"AFBF0000", -- 00000408 - X"27BD0004", -- 0000040C - X"AFAA0000", -- 00000410 - X"000A5102", -- 00000414 - X"0C100110", -- 00000418 - X"00000000", -- 0000041C - X"8FAA0000", -- 00000420 - X"27BDFFFC", -- 00000424 - X"0C100110", -- 00000428 - X"00000000", -- 0000042C - X"8FBF0000", -- 00000430 - X"27BDFFFC", -- 00000434 - X"03E00008", -- 00000438 - X"00000000", -- 0000043C - X"27BD0004", -- 00000440 - X"AFBF0000", -- 00000444 - X"27BD0004", -- 00000448 - X"AFAA0000", -- 0000044C - X"3C0C0000", -- 00000450 - X"258C0AE1", -- 00000454 - X"314A000F", -- 00000458 - X"018A6021", -- 0000045C - X"918A0000", -- 00000460 - X"0C100121", -- 00000464 - X"00000000", -- 00000468 - X"8FAA0000", -- 0000046C - X"27BDFFFC", -- 00000470 - X"8FBF0000", -- 00000474 - X"27BDFFFC", -- 00000478 - X"03E00008", -- 0000047C - X"00000000", -- 00000480 - X"3C088000", -- 00000484 - X"25080008", -- 00000488 - X"91080000", -- 0000048C - X"3C098000", -- 00000490 - X"25290004", -- 00000494 - X"31080002", -- 00000498 - X"1500FFF9", -- 0000049C - X"00000000", -- 000004A0 - X"03E00008", -- 000004A4 - X"A12A0000", -- 000004A8 - X"27BD0004", -- 000004AC - X"AFAB0000", -- 000004B0 - X"27BD0004", -- 000004B4 - X"AFBF0000", -- 000004B8 - X"916A0000", -- 000004BC - X"256B0001", -- 000004C0 - X"19400005", -- 000004C4 - X"00000000", -- 000004C8 - X"0C100121", -- 000004CC - X"00000000", -- 000004D0 - X"0810012F", -- 000004D4 - X"00000000", -- 000004D8 - X"8FBF0000", -- 000004DC - X"27BDFFFC", -- 000004E0 - X"8FAB0000", -- 000004E4 - X"27BDFFFC", -- 000004E8 - X"03E00008", -- 000004EC - X"00000000", -- 000004F0 - X"3C1A8000", -- 000004F4 - X"275A0009", -- 000004F8 - X"241B000D", -- 000004FC - X"A35B0000", -- 00000500 - X"3C1D8000", -- 00000504 - X"27BDEFFC", -- 00000508 - X"3C1A0040", -- 0000050C - X"275A0D90", -- 00000510 - X"0340F809", -- 00000514 - X"00000000", -- 00000518 - X"08100146", -- 0000051C - X"00000000", -- 00000520 - X"3C028000", -- 00000524 - X"34440004", -- 00000528 - X"34430008", -- 0000052C - X"90620000", -- 00000530 - X"00000000", -- 00000534 - X"30420010", -- 00000538 - X"1040FFFC", -- 0000053C - X"00000000", -- 00000540 - X"90820000", -- 00000544 - X"00000000", -- 00000548 - X"00021600", -- 0000054C - X"03E00008", -- 00000550 - X"00021603", -- 00000554 - X"3C028000", -- 00000558 - X"00042600", -- 0000055C - X"00042603", -- 00000560 - X"34450004", -- 00000564 - X"34430008", -- 00000568 - X"90620000", -- 0000056C - X"00000000", -- 00000570 - X"30420002", -- 00000574 - X"1440FFFC", -- 00000578 - X"00000000", -- 0000057C - X"03E00008", -- 00000580 - X"A0A40000", -- 00000584 - X"3C028000", -- 00000588 - X"34420014", -- 0000058C - X"8C420000", -- 00000590 - X"10800005", -- 00000594 - X"00000000", -- 00000598 - X"AC80000C", -- 0000059C - X"AC820000", -- 000005A0 - X"AC800004", -- 000005A4 - X"AC800008", -- 000005A8 - X"03E00008", -- 000005AC - X"00000000", -- 000005B0 - X"3C028000", -- 000005B4 - X"34450014", -- 000005B8 - X"10800007", -- 000005BC - X"34430010", -- 000005C0 - X"8CA20000", -- 000005C4 - X"00000000", -- 000005C8 - X"AC820000", -- 000005CC - X"8C630000", -- 000005D0 - X"00000000", -- 000005D4 - X"AC830004", -- 000005D8 - X"03E00008", -- 000005DC - X"00001021", -- 000005E0 - X"27BDFFD8", -- 000005E4 - X"AFB20020", -- 000005E8 - X"AFB1001C", -- 000005EC - X"AFB00018", -- 000005F0 - X"AFBF0024", -- 000005F4 - X"8C850004", -- 000005F8 - X"3C06000F", -- 000005FC - X"00808021", -- 00000600 - X"3C028000", -- 00000604 - X"34C64240", -- 00000608 - X"27A40010", -- 0000060C - X"34520014", -- 00000610 - X"0C1003B1", -- 00000614 - X"34510010", -- 00000618 - X"12000009", -- 0000061C - X"00000000", -- 00000620 - X"8FA20014", -- 00000624 - X"00000000", -- 00000628 - X"AE220000", -- 0000062C - X"8E030000", -- 00000630 - X"8FA20010", -- 00000634 - X"00000000", -- 00000638 - X"00621821", -- 0000063C - X"AE430000", -- 00000640 - X"8FBF0024", -- 00000644 - X"8FB20020", -- 00000648 - X"8FB1001C", -- 0000064C - X"8FB00018", -- 00000650 - X"00001021", -- 00000654 - X"03E00008", -- 00000658 - X"27BD0028", -- 0000065C - X"8F820988", -- 00000660 - X"00000000", -- 00000664 - X"14400004", -- 00000668 - X"00441821", -- 0000066C - X"3C028000", -- 00000670 - X"2442EFFC", -- 00000674 - X"00441821", -- 00000678 - X"03E00008", -- 0000067C - X"AF830988", -- 00000680 - X"24022000", -- 00000684 - X"ACA20004", -- 00000688 - X"03E00008", -- 0000068C - X"00001021", -- 00000690 - X"03E00008", -- 00000694 - X"00001021", -- 00000698 - X"03E00008", -- 0000069C - X"2402FFFF", -- 000006A0 - X"03E00008", -- 000006A4 - X"2402FFFF", -- 000006A8 - X"03E00008", -- 000006AC - X"00001021", -- 000006B0 - X"27BDFFE0", -- 000006B4 - X"AFB20018", -- 000006B8 - X"AFB10014", -- 000006BC - X"AFB00010", -- 000006C0 - X"AFBF001C", -- 000006C4 - X"00C09021", -- 000006C8 - X"00A08021", -- 000006CC - X"18C00007", -- 000006D0 - X"00008821", -- 000006D4 - X"82040000", -- 000006D8 - X"0C100156", -- 000006DC - X"26310001", -- 000006E0 - X"0232102A", -- 000006E4 - X"1440FFFB", -- 000006E8 - X"26100001", -- 000006EC - X"02201021", -- 000006F0 - X"8FBF001C", -- 000006F4 - X"8FB20018", -- 000006F8 - X"8FB10014", -- 000006FC - X"8FB00010", -- 00000700 - X"03E00008", -- 00000704 - X"27BD0020", -- 00000708 - X"03E00008", -- 0000070C - X"24020001", -- 00000710 - X"27BDFFE0", -- 00000714 - X"AFB10014", -- 00000718 - X"AFB00010", -- 0000071C - X"AFBF0018", -- 00000720 - X"00808021", -- 00000724 - X"80840000", -- 00000728 - X"081001D1", -- 0000072C - X"02008821", -- 00000730 - X"0C100156", -- 00000734 - X"26100001", -- 00000738 - X"82040000", -- 0000073C - X"00000000", -- 00000740 - X"1480FFFB", -- 00000744 - X"02111023", -- 00000748 - X"8FBF0018", -- 0000074C - X"8FB10014", -- 00000750 - X"8FB00010", -- 00000754 - X"03E00008", -- 00000758 - X"27BD0020", -- 0000075C - X"27BDFFE0", -- 00000760 - X"AFB00010", -- 00000764 - X"00048600", -- 00000768 - X"AFB10014", -- 0000076C - X"AFBF0018", -- 00000770 - X"00108603", -- 00000774 - X"24110001", -- 00000778 - X"00101103", -- 0000077C - X"3045000F", -- 00000780 - X"00101100", -- 00000784 - X"00028600", -- 00000788 - X"2CA3000A", -- 0000078C - X"2631FFFF", -- 00000790 - X"00108603", -- 00000794 - X"14600002", -- 00000798 - X"24A40030", -- 0000079C - X"24A40037", -- 000007A0 - X"0C100156", -- 000007A4 - X"00000000", -- 000007A8 - X"0621FFF4", -- 000007AC - X"00101103", -- 000007B0 - X"8FBF0018", -- 000007B4 - X"8FB10014", -- 000007B8 - X"8FB00010", -- 000007BC - X"03E00008", -- 000007C0 - X"27BD0020", -- 000007C4 - X"27BDFFE0", -- 000007C8 - X"AFB10014", -- 000007CC - X"AFB00010", -- 000007D0 - X"AFBF0018", -- 000007D4 - X"00808021", -- 000007D8 - X"24110003", -- 000007DC - X"00102603", -- 000007E0 - X"0C1001D8", -- 000007E4 - X"2631FFFF", -- 000007E8 - X"0621FFFC", -- 000007EC - X"00108200", -- 000007F0 - X"8FBF0018", -- 000007F4 - X"8FB10014", -- 000007F8 - X"8FB00010", -- 000007FC - X"03E00008", -- 00000800 - X"27BD0020", -- 00000804 - X"24080002", -- 00000808 - X"0107102A", -- 0000080C - X"ACC40000", -- 00000810 - X"1040000A", -- 00000814 - X"ACC50004", -- 00000818 - X"24C60008", -- 0000081C - X"8CC2FFF8", -- 00000820 - X"8CC3FFFC", -- 00000824 - X"25080001", -- 00000828 - X"00431021", -- 0000082C - X"0107202A", -- 00000830 - X"ACC20000", -- 00000834 - X"1480FFF9", -- 00000838 - X"24C60004", -- 0000083C - X"03E00008", -- 00000840 - X"01001021", -- 00000844 - X"40026000", -- 00000848 - X"03E00008", -- 0000084C - X"00000000", -- 00000850 - X"40027800", -- 00000854 - X"03E00008", -- 00000858 - X"00000000", -- 0000085C - X"3C020000", -- 00000860 - X"8C420098", -- 00000864 - X"27BDFFC0", -- 00000868 - X"3C030000", -- 0000086C - X"8C63009C", -- 00000870 - X"AFA20010", -- 00000874 - X"3C020000", -- 00000878 - X"8C4200A0", -- 0000087C - X"AFA30014", -- 00000880 - X"AFA20018", -- 00000884 - X"3C030000", -- 00000888 - X"8C6300A4", -- 0000088C - X"3C020000", -- 00000890 - X"8C4200A8", -- 00000894 - X"AFA3001C", -- 00000898 - X"AFA20020", -- 0000089C - X"3C030000", -- 000008A0 - X"8C6300AC", -- 000008A4 - X"3C020000", -- 000008A8 - X"8C4200B0", -- 000008AC - X"AFA30024", -- 000008B0 - X"AFBF0038", -- 000008B4 - X"AFB10034", -- 000008B8 - X"AFB00030", -- 000008BC - X"0C100212", -- 000008C0 - X"AFA20028", -- 000008C4 - X"3C040000", -- 000008C8 - X"2484003C", -- 000008CC - X"0C1001C5", -- 000008D0 - X"00408821", -- 000008D4 - X"0C1001F2", -- 000008D8 - X"02202021", -- 000008DC - X"3C040000", -- 000008E0 - X"0C1001C5", -- 000008E4 - X"24840078", -- 000008E8 - X"0C100215", -- 000008EC - X"00000000", -- 000008F0 - X"00028203", -- 000008F4 - X"321000FF", -- 000008F8 - X"3C040000", -- 000008FC - X"24840048", -- 00000900 - X"0C1001C5", -- 00000904 - X"00408821", -- 00000908 - X"00101880", -- 0000090C - X"2610FFFF", -- 00000910 - X"2E100006", -- 00000914 - X"3C040000", -- 00000918 - X"24840054", -- 0000091C - X"12000012", -- 00000920 - X"03A31021", -- 00000924 - X"8C440010", -- 00000928 - X"0C1001C5", -- 0000092C - X"00000000", -- 00000930 - X"3C040000", -- 00000934 - X"0C1001C5", -- 00000938 - X"2484005C", -- 0000093C - X"00112600", -- 00000940 - X"0C1001D8", -- 00000944 - X"00042603", -- 00000948 - X"3C040000", -- 0000094C - X"0C1001C5", -- 00000950 - X"24840078", -- 00000954 - X"8FBF0038", -- 00000958 - X"8FB10034", -- 0000095C - X"8FB00030", -- 00000960 - X"03E00008", -- 00000964 - X"27BD0040", -- 00000968 - X"0C1001C5", -- 0000096C - X"00000000", -- 00000970 - X"3C040000", -- 00000974 - X"0C1001C5", -- 00000978 - X"24840078", -- 0000097C - X"8FBF0038", -- 00000980 - X"8FB10034", -- 00000984 - X"8FB00030", -- 00000988 - X"03E00008", -- 0000098C - X"27BD0040", -- 00000990 - X"27BDFFE8", -- 00000994 - X"24040080", -- 00000998 - X"AFBF0014", -- 0000099C - X"0C1003D6", -- 000009A0 - X"AFB00010", -- 000009A4 - X"00402021", -- 000009A8 - X"3C025555", -- 000009AC - X"3C03AAAA", -- 000009B0 - X"34455555", -- 000009B4 - X"3466AAAA", -- 000009B8 - X"2407FFFF", -- 000009BC - X"AC800000", -- 000009C0 - X"AC850004", -- 000009C4 - X"AC860008", -- 000009C8 - X"AC87000C", -- 000009CC - X"8C830000", -- 000009D0 - X"3C028000", -- 000009D4 - X"14600005", -- 000009D8 - X"34500010", -- 000009DC - X"8C820004", -- 000009E0 - X"00000000", -- 000009E4 - X"10450008", -- 000009E8 - X"00000000", -- 000009EC - X"0C1003DA", -- 000009F0 - X"00000000", -- 000009F4 - X"02001021", -- 000009F8 - X"8FBF0014", -- 000009FC - X"8FB00010", -- 00000A00 - X"03E00008", -- 00000A04 - X"27BD0018", -- 00000A08 - X"8C820008", -- 00000A0C - X"00000000", -- 00000A10 - X"1446FFF6", -- 00000A14 - X"00000000", -- 00000A18 - X"8C82000C", -- 00000A1C - X"00000000", -- 00000A20 - X"1447FFF2", -- 00000A24 - X"00801821", -- 00000A28 - X"00002821", -- 00000A2C - X"3C078000", -- 00000A30 - X"2406001F", -- 00000A34 - X"00051043", -- 00000A38 - X"24C6FFFF", -- 00000A3C - X"AC650000", -- 00000A40 - X"24630004", -- 00000A44 - X"04C1FFFB", -- 00000A48 - X"00472825", -- 00000A4C - X"00801821", -- 00000A50 - X"00002821", -- 00000A54 - X"00003021", -- 00000A58 - X"0810029D", -- 00000A5C - X"3C088000", -- 00000A60 - X"24C60001", -- 00000A64 - X"28C20020", -- 00000A68 - X"10400005", -- 00000A6C - X"00E82825", -- 00000A70 - X"8C620000", -- 00000A74 - X"00053843", -- 00000A78 - X"1045FFF9", -- 00000A7C - X"24630004", -- 00000A80 - X"24020020", -- 00000A84 - X"14C2FFD9", -- 00000A88 - X"00801821", -- 00000A8C - X"00002821", -- 00000A90 - X"2406001F", -- 00000A94 - X"00051040", -- 00000A98 - X"24C6FFFF", -- 00000A9C - X"AC650000", -- 00000AA0 - X"24630004", -- 00000AA4 - X"04C1FFFB", -- 00000AA8 - X"34450001", -- 00000AAC - X"00801821", -- 00000AB0 - X"00002821", -- 00000AB4 - X"081002B4", -- 00000AB8 - X"00003021", -- 00000ABC - X"24C60001", -- 00000AC0 - X"28C20020", -- 00000AC4 - X"10400005", -- 00000AC8 - X"34E50001", -- 00000ACC - X"8C620000", -- 00000AD0 - X"00053840", -- 00000AD4 - X"1045FFF9", -- 00000AD8 - X"24630004", -- 00000ADC - X"24020020", -- 00000AE0 - X"14C2FFC2", -- 00000AE4 - X"00801821", -- 00000AE8 - X"24050001", -- 00000AEC - X"2406001F", -- 00000AF0 - X"24C6FFFF", -- 00000AF4 - X"AC650000", -- 00000AF8 - X"24630004", -- 00000AFC - X"04C1FFFC", -- 00000B00 - X"00052840", -- 00000B04 - X"00801821", -- 00000B08 - X"24050001", -- 00000B0C - X"081002CA", -- 00000B10 - X"00003021", -- 00000B14 - X"24C60001", -- 00000B18 - X"28C20020", -- 00000B1C - X"10400005", -- 00000B20 - X"00052840", -- 00000B24 - X"8C620000", -- 00000B28 - X"00000000", -- 00000B2C - X"1045FFF9", -- 00000B30 - X"24630004", -- 00000B34 - X"24020020", -- 00000B38 - X"14C2FFAC", -- 00000B3C - X"00801821", -- 00000B40 - X"2405FFFE", -- 00000B44 - X"2406001F", -- 00000B48 - X"00051040", -- 00000B4C - X"24C6FFFF", -- 00000B50 - X"AC650000", -- 00000B54 - X"24630004", -- 00000B58 - X"04C1FFFB", -- 00000B5C - X"34450001", -- 00000B60 - X"00801821", -- 00000B64 - X"2405FFFE", -- 00000B68 - X"081002E1", -- 00000B6C - X"00003021", -- 00000B70 - X"24C60001", -- 00000B74 - X"28C20020", -- 00000B78 - X"10400005", -- 00000B7C - X"34E50001", -- 00000B80 - X"8C620000", -- 00000B84 - X"00053840", -- 00000B88 - X"1045FFF9", -- 00000B8C - X"24630004", -- 00000B90 - X"24020020", -- 00000B94 - X"14C2FF95", -- 00000B98 - X"00000000", -- 00000B9C - X"0810027C", -- 00000BA0 - X"00008021", -- 00000BA4 - X"27BDFF88", -- 00000BA8 - X"3C02AAAA", -- 00000BAC - X"AFB3006C", -- 00000BB0 - X"AFB20068", -- 00000BB4 - X"AFB00060", -- 00000BB8 - X"AFBF0070", -- 00000BBC - X"AFB10064", -- 00000BC0 - X"3450AAAA", -- 00000BC4 - X"00009821", -- 00000BC8 - X"00002021", -- 00000BCC - X"27B20010", -- 00000BD0 - X"02401021", -- 00000BD4 - X"24060013", -- 00000BD8 - X"24C6FFFF", -- 00000BDC - X"AC500000", -- 00000BE0 - X"04C1FFFD", -- 00000BE4 - X"24420004", -- 00000BE8 - X"02041026", -- 00000BEC - X"24910001", -- 00000BF0 - X"2442FFFF", -- 00000BF4 - X"02202821", -- 00000BF8 - X"27A60010", -- 00000BFC - X"24070014", -- 00000C00 - X"0C100202", -- 00000C04 - X"00028040", -- 00000C08 - X"24070002", -- 00000C0C - X"26450008", -- 00000C10 - X"08100309", -- 00000C14 - X"24060011", -- 00000C18 - X"04C0000A", -- 00000C1C - X"00000000", -- 00000C20 - X"8CA20000", -- 00000C24 - X"8CA3FFFC", -- 00000C28 - X"8CA4FFF8", -- 00000C2C - X"00431023", -- 00000C30 - X"24C6FFFF", -- 00000C34 - X"1482FFF8", -- 00000C38 - X"24A50004", -- 00000C3C - X"04C1FFF8", -- 00000C40 - X"24E70001", -- 00000C44 - X"24060014", -- 00000C48 - X"10E6000F", -- 00000C4C - X"00000000", -- 00000C50 - X"2A220003", -- 00000C54 - X"1440FFDE", -- 00000C58 - X"02202021", -- 00000C5C - X"24020003", -- 00000C60 - X"1662000B", -- 00000C64 - X"00001821", -- 00000C68 - X"8FBF0070", -- 00000C6C - X"8FB3006C", -- 00000C70 - X"8FB20068", -- 00000C74 - X"8FB10064", -- 00000C78 - X"8FB00060", -- 00000C7C - X"00601021", -- 00000C80 - X"03E00008", -- 00000C84 - X"27BD0078", -- 00000C88 - X"08100315", -- 00000C8C - X"26730001", -- 00000C90 - X"3C028000", -- 00000C94 - X"34430011", -- 00000C98 - X"8FBF0070", -- 00000C9C - X"8FB3006C", -- 00000CA0 - X"8FB20068", -- 00000CA4 - X"8FB10064", -- 00000CA8 - X"8FB00060", -- 00000CAC - X"00601021", -- 00000CB0 - X"03E00008", -- 00000CB4 - X"27BD0078", -- 00000CB8 - X"3C041970", -- 00000CBC - X"27BDFFD0", -- 00000CC0 - X"34841031", -- 00000CC4 - X"AFB30024", -- 00000CC8 - X"AFBF0028", -- 00000CCC - X"AFB20020", -- 00000CD0 - X"AFB1001C", -- 00000CD4 - X"AFB00018", -- 00000CD8 - X"0C100897", -- 00000CDC - X"00009821", -- 00000CE0 - X"0810033D", -- 00000CE4 - X"24120001", -- 00000CE8 - X"10800022", -- 00000CEC - X"00000000", -- 00000CF0 - X"0C10089C", -- 00000CF4 - X"26520001", -- 00000CF8 - X"00021C00", -- 00000CFC - X"00021200", -- 00000D00 - X"0C10089C", -- 00000D04 - X"00438026", -- 00000D08 - X"0C10089C", -- 00000D0C - X"00508826", -- 00000D10 - X"00021C00", -- 00000D14 - X"00021200", -- 00000D18 - X"0C10089C", -- 00000D1C - X"00438026", -- 00000D20 - X"00508026", -- 00000D24 - X"27A40010", -- 00000D28 - X"02202821", -- 00000D2C - X"0C1003B1", -- 00000D30 - X"02003021", -- 00000D34 - X"8FA30010", -- 00000D38 - X"8FA20014", -- 00000D3C - X"00700018", -- 00000D40 - X"00001812", -- 00000D44 - X"00431021", -- 00000D48 - X"1051FFE7", -- 00000D4C - X"2A4403E8", -- 00000D50 - X"3C028000", -- 00000D54 - X"34420012", -- 00000D58 - X"8FBF0028", -- 00000D5C - X"8FB30024", -- 00000D60 - X"8FB20020", -- 00000D64 - X"8FB1001C", -- 00000D68 - X"8FB00018", -- 00000D6C - X"03E00008", -- 00000D70 - X"27BD0030", -- 00000D74 - X"26730001", -- 00000D78 - X"2A620064", -- 00000D7C - X"1440FFDC", -- 00000D80 - X"24120001", -- 00000D84 - X"08100357", -- 00000D88 - X"00001021", -- 00000D8C - X"27BDFFD0", -- 00000D90 - X"AFB30024", -- 00000D94 - X"AFB20020", -- 00000D98 - X"AFB1001C", -- 00000D9C - X"AFBF0028", -- 00000DA0 - X"0C100218", -- 00000DA4 - X"AFB00018", -- 00000DA8 - X"3C023FFF", -- 00000DAC - X"3453FFFF", -- 00000DB0 - X"3C128000", -- 00000DB4 - X"08100399", -- 00000DB8 - X"00008821", -- 00000DBC - X"0C1002EA", -- 00000DC0 - X"00000000", -- 00000DC4 - X"0440002B", -- 00000DC8 - X"00408021", -- 00000DCC - X"0C10032F", -- 00000DD0 - X"00000000", -- 00000DD4 - X"3C040000", -- 00000DD8 - X"24840064", -- 00000DDC - X"04400025", -- 00000DE0 - X"00408021", -- 00000DE4 - X"0C1001C5", -- 00000DE8 - X"00000000", -- 00000DEC - X"0C1001F2", -- 00000DF0 - X"02202021", -- 00000DF4 - X"3C040000", -- 00000DF8 - X"24840070", -- 00000DFC - X"0C1001C5", -- 00000E00 - X"26310001", -- 00000E04 - X"0C1008CE", -- 00000E08 - X"00002021", -- 00000E0C - X"27A40010", -- 00000E10 - X"0C1003D1", -- 00000E14 - X"AFA20010", -- 00000E18 - X"80440008", -- 00000E1C - X"0C1001D8", -- 00000E20 - X"00408021", -- 00000E24 - X"3C040000", -- 00000E28 - X"0C1001C5", -- 00000E2C - X"2484007C", -- 00000E30 - X"82040004", -- 00000E34 - X"0C1001D8", -- 00000E38 - X"00000000", -- 00000E3C - X"3C040000", -- 00000E40 - X"0C1001C5", -- 00000E44 - X"2484007C", -- 00000E48 - X"82040000", -- 00000E4C - X"0C1001D8", -- 00000E50 - X"00000000", -- 00000E54 - X"3C040000", -- 00000E58 - X"0C1001C5", -- 00000E5C - X"24840078", -- 00000E60 - X"02331024", -- 00000E64 - X"0C100265", -- 00000E68 - X"AE420000", -- 00000E6C - X"0441FFD3", -- 00000E70 - X"00408021", -- 00000E74 - X"3C024000", -- 00000E78 - X"02221025", -- 00000E7C - X"3C040000", -- 00000E80 - X"24840080", -- 00000E84 - X"0C1001C5", -- 00000E88 - X"AE420000", -- 00000E8C - X"0C1001F2", -- 00000E90 - X"02002021", -- 00000E94 - X"3C040000", -- 00000E98 - X"0C1001C5", -- 00000E9C - X"24840094", -- 00000EA0 - X"8FBF0028", -- 00000EA4 - X"8FB30024", -- 00000EA8 - X"8FB20020", -- 00000EAC - X"8FB1001C", -- 00000EB0 - X"8FB00018", -- 00000EB4 - X"24020001", -- 00000EB8 - X"03E00008", -- 00000EBC - X"27BD0030", -- 00000EC0 - X"14C00002", -- 00000EC4 - X"00A6001A", -- 00000EC8 - X"0007000D", -- 00000ECC - X"27BDFFF8", -- 00000ED0 - X"00001010", -- 00000ED4 - X"00001812", -- 00000ED8 - X"04A0000D", -- 00000EDC - X"00803821", -- 00000EE0 - X"00463023", -- 00000EE4 - X"0440000D", -- 00000EE8 - X"24640001", -- 00000EEC - X"AFA20004", -- 00000EF0 - X"AFA30000", -- 00000EF4 - X"8FA40000", -- 00000EF8 - X"8FA30004", -- 00000EFC - X"00E01021", -- 00000F00 - X"27BD0008", -- 00000F04 - X"ACE30004", -- 00000F08 - X"03E00008", -- 00000F0C - X"ACE40000", -- 00000F10 - X"00463021", -- 00000F14 - X"1840FFF5", -- 00000F18 - X"2464FFFF", -- 00000F1C - X"AFA40000", -- 00000F20 - X"AFA60004", -- 00000F24 - X"8FA40000", -- 00000F28 - X"8FA30004", -- 00000F2C - X"00E01021", -- 00000F30 - X"27BD0008", -- 00000F34 - X"ACE30004", -- 00000F38 - X"03E00008", -- 00000F3C - X"ACE40000", -- 00000F40 - X"8F85096C", -- 00000F44 - X"081003D4", -- 00000F48 - X"24A5007C", -- 00000F4C - X"081006BE", -- 00000F50 - X"24060001", -- 00000F54 - X"00802821", -- 00000F58 - X"8F84096C", -- 00000F5C - X"081003DE", -- 00000F60 - X"00000000", -- 00000F64 - X"00802821", -- 00000F68 - X"8F84096C", -- 00000F6C - X"08100938", -- 00000F70 - X"00000000", -- 00000F74 - X"24A6000B", -- 00000F78 - X"27BDFFC8", -- 00000F7C - X"2CC20017", -- 00000F80 - X"AFB20018", -- 00000F84 - X"AFB10014", -- 00000F88 - X"AFBF0034", -- 00000F8C - X"AFBE0030", -- 00000F90 - X"AFB7002C", -- 00000F94 - X"AFB60028", -- 00000F98 - X"AFB50024", -- 00000F9C - X"AFB40020", -- 00000FA0 - X"AFB3001C", -- 00000FA4 - X"AFB00010", -- 00000FA8 - X"00809021", -- 00000FAC - X"14400005", -- 00000FB0 - X"24110010", -- 00000FB4 - X"2402FFF8", -- 00000FB8 - X"00C28824", -- 00000FBC - X"06200004", -- 00000FC0 - X"2402000C", -- 00000FC4 - X"0225102B", -- 00000FC8 - X"10400010", -- 00000FCC - X"2402000C", -- 00000FD0 - X"00001821", -- 00000FD4 - X"AE420000", -- 00000FD8 - X"8FBF0034", -- 00000FDC - X"8FBE0030", -- 00000FE0 - X"8FB7002C", -- 00000FE4 - X"8FB60028", -- 00000FE8 - X"8FB50024", -- 00000FEC - X"8FB40020", -- 00000FF0 - X"8FB3001C", -- 00000FF4 - X"8FB20018", -- 00000FF8 - X"8FB10014", -- 00000FFC - X"8FB00010", -- 00001000 - X"00601021", -- 00001004 - X"03E00008", -- 00001008 - X"27BD0038", -- 0000100C - X"0C100893", -- 00001010 - X"02402021", -- 00001014 - X"2E2201F8", -- 00001018 - X"10400024", -- 0000101C - X"00111A42", -- 00001020 - X"3C020000", -- 00001024 - X"24420520", -- 00001028 - X"02223021", -- 0000102C - X"8CD0000C", -- 00001030 - X"00000000", -- 00001034 - X"12060059", -- 00001038 - X"001140C2", -- 0000103C - X"8E030004", -- 00001040 - X"2402FFFC", -- 00001044 - X"00622024", -- 00001048 - X"02042021", -- 0000104C - X"8C820004", -- 00001050 - X"8E07000C", -- 00001054 - X"8E060008", -- 00001058 - X"34420001", -- 0000105C - X"ACE60008", -- 00001060 - X"AC820004", -- 00001064 - X"ACC7000C", -- 00001068 - X"02402021", -- 0000106C - X"0C100895", -- 00001070 - X"00000000", -- 00001074 - X"26030008", -- 00001078 - X"8FBF0034", -- 0000107C - X"8FBE0030", -- 00001080 - X"8FB7002C", -- 00001084 - X"8FB60028", -- 00001088 - X"8FB50024", -- 0000108C - X"8FB40020", -- 00001090 - X"8FB3001C", -- 00001094 - X"8FB20018", -- 00001098 - X"8FB10014", -- 0000109C - X"8FB00010", -- 000010A0 - X"00601021", -- 000010A4 - X"03E00008", -- 000010A8 - X"27BD0038", -- 000010AC - X"1060000C", -- 000010B0 - X"001140C2", -- 000010B4 - X"2C620005", -- 000010B8 - X"1440003F", -- 000010BC - X"00111182", -- 000010C0 - X"2C620015", -- 000010C4 - X"14400006", -- 000010C8 - X"2468005B", -- 000010CC - X"2C620055", -- 000010D0 - X"10400162", -- 000010D4 - X"2C620155", -- 000010D8 - X"00111302", -- 000010DC - X"2448006E", -- 000010E0 - X"000810C0", -- 000010E4 - X"3C040000", -- 000010E8 - X"24840520", -- 000010EC - X"00441821", -- 000010F0 - X"8C70000C", -- 000010F4 - X"00000000", -- 000010F8 - X"1203000F", -- 000010FC - X"00000000", -- 00001100 - X"2406FFFC", -- 00001104 - X"8E020004", -- 00001108 - X"00000000", -- 0000110C - X"00462024", -- 00001110 - X"00912823", -- 00001114 - X"28A20010", -- 00001118 - X"10400102", -- 0000111C - X"00000000", -- 00001120 - X"04A10102", -- 00001124 - X"00000000", -- 00001128 - X"8E10000C", -- 0000112C - X"00000000", -- 00001130 - X"1603FFF4", -- 00001134 - X"00000000", -- 00001138 - X"25080001", -- 0000113C - X"3C100000", -- 00001140 - X"8E100530", -- 00001144 - X"3C0C0000", -- 00001148 - X"258C0528", -- 0000114C - X"120C0032", -- 00001150 - X"2403FFFC", -- 00001154 - X"8E020004", -- 00001158 - X"00000000", -- 0000115C - X"00432024", -- 00001160 - X"00912823", -- 00001164 - X"28A20010", -- 00001168 - X"10400073", -- 0000116C - X"00000000", -- 00001170 - X"AD8C000C", -- 00001174 - X"04A00012", -- 00001178 - X"AD8C0008", -- 0000117C - X"02041821", -- 00001180 - X"8C620004", -- 00001184 - X"02402021", -- 00001188 - X"34420001", -- 0000118C - X"0C100895", -- 00001190 - X"AC620004", -- 00001194 - X"0810041F", -- 00001198 - X"26030008", -- 0000119C - X"26060008", -- 000011A0 - X"8CD0000C", -- 000011A4 - X"00000000", -- 000011A8 - X"1606FFA4", -- 000011AC - X"25080002", -- 000011B0 - X"08100450", -- 000011B4 - X"00000000", -- 000011B8 - X"08100439", -- 000011BC - X"24480038", -- 000011C0 - X"2C820200", -- 000011C4 - X"104000E2", -- 000011C8 - X"00042A42", -- 000011CC - X"000418C2", -- 000011D0 - X"3C050000", -- 000011D4 - X"24A50520", -- 000011D8 - X"04600155", -- 000011DC - X"00602021", -- 000011E0 - X"000310C0", -- 000011E4 - X"00453821", -- 000011E8 - X"00042083", -- 000011EC - X"3C020000", -- 000011F0 - X"8C420524", -- 000011F4 - X"24030001", -- 000011F8 - X"8CE60008", -- 000011FC - X"00831804", -- 00001200 - X"00431025", -- 00001204 - X"AE07000C", -- 00001208 - X"AE060008", -- 0000120C - X"ACA20004", -- 00001210 - X"ACD0000C", -- 00001214 - X"ACF00008", -- 00001218 - X"0500010E", -- 0000121C - X"01001021", -- 00001220 - X"00021083", -- 00001224 - X"3C0A0000", -- 00001228 - X"8D4A0524", -- 0000122C - X"24030001", -- 00001230 - X"00433804", -- 00001234 - X"0147202B", -- 00001238 - X"1480004C", -- 0000123C - X"01471024", -- 00001240 - X"1440000A", -- 00001244 - X"2402FFFC", -- 00001248 - X"00073840", -- 0000124C - X"01021024", -- 00001250 - X"01471824", -- 00001254 - X"14600005", -- 00001258 - X"24480004", -- 0000125C - X"00073840", -- 00001260 - X"01471024", -- 00001264 - X"1040FFFD", -- 00001268 - X"25080004", -- 0000126C - X"3C030000", -- 00001270 - X"24630520", -- 00001274 - X"000810C0", -- 00001278 - X"00433021", -- 0000127C - X"01005821", -- 00001280 - X"00C01821", -- 00001284 - X"8C70000C", -- 00001288 - X"00000000", -- 0000128C - X"1203000F", -- 00001290 - X"00000000", -- 00001294 - X"2409FFFC", -- 00001298 - X"8E020004", -- 0000129C - X"00000000", -- 000012A0 - X"00492024", -- 000012A4 - X"00912823", -- 000012A8 - X"28A20010", -- 000012AC - X"104000CD", -- 000012B0 - X"00000000", -- 000012B4 - X"04A100DE", -- 000012B8 - X"00000000", -- 000012BC - X"8E10000C", -- 000012C0 - X"00000000", -- 000012C4 - X"1603FFF4", -- 000012C8 - X"00000000", -- 000012CC - X"25080001", -- 000012D0 - X"31020003", -- 000012D4 - X"1440FFEB", -- 000012D8 - X"24630008", -- 000012DC - X"31620003", -- 000012E0 - X"24C6FFF8", -- 000012E4 - X"10400132", -- 000012E8 - X"256BFFFF", -- 000012EC - X"8CC20008", -- 000012F0 - X"00000000", -- 000012F4 - X"1046FFFA", -- 000012F8 - X"31620003", -- 000012FC - X"00073840", -- 00001300 - X"0147102B", -- 00001304 - X"14400019", -- 00001308 - X"00000000", -- 0000130C - X"10E00017", -- 00001310 - X"01471024", -- 00001314 - X"081004CB", -- 00001318 - X"00000000", -- 0000131C - X"00073840", -- 00001320 - X"01471024", -- 00001324 - X"25080004", -- 00001328 - X"1040FFFC", -- 0000132C - X"00000000", -- 00001330 - X"0810049C", -- 00001334 - X"00000000", -- 00001338 - X"02114021", -- 0000133C - X"34A40001", -- 00001340 - X"36230001", -- 00001344 - X"01051021", -- 00001348 - X"AE030004", -- 0000134C - X"AD040004", -- 00001350 - X"02402021", -- 00001354 - X"AD88000C", -- 00001358 - X"AD880008", -- 0000135C - X"AC450000", -- 00001360 - X"AD0C0008", -- 00001364 - X"0810041C", -- 00001368 - X"AD0C000C", -- 0000136C - X"3C130000", -- 00001370 - X"8E730528", -- 00001374 - X"2403FFFC", -- 00001378 - X"8E620004", -- 0000137C - X"00000000", -- 00001380 - X"0043B024", -- 00001384 - X"02D1202B", -- 00001388 - X"14800004", -- 0000138C - X"02D12823", -- 00001390 - X"28A20010", -- 00001394 - X"10400028", -- 00001398 - X"02712021", -- 0000139C - X"8F820994", -- 000013A0 - X"241EFFFF", -- 000013A4 - X"02221821", -- 000013A8 - X"8F820970", -- 000013AC - X"02C0B821", -- 000013B0 - X"0276A021", -- 000013B4 - X"105E0004", -- 000013B8 - X"24750010", -- 000013BC - X"2463100F", -- 000013C0 - X"2402F000", -- 000013C4 - X"0062A824", -- 000013C8 - X"02402021", -- 000013CC - X"0C1008B8", -- 000013D0 - X"02A02821", -- 000013D4 - X"105E0008", -- 000013D8 - X"00408021", -- 000013DC - X"0054102B", -- 000013E0 - X"1040001F", -- 000013E4 - X"00000000", -- 000013E8 - X"3C020000", -- 000013EC - X"24420520", -- 000013F0 - X"1262001B", -- 000013F4 - X"00000000", -- 000013F8 - X"3C130000", -- 000013FC - X"8E730528", -- 00001400 - X"00000000", -- 00001404 - X"8E620004", -- 00001408 - X"2403FFFC", -- 0000140C - X"00431024", -- 00001410 - X"0051202B", -- 00001414 - X"14800004", -- 00001418 - X"00512823", -- 0000141C - X"28A20010", -- 00001420 - X"10400005", -- 00001424 - X"02712021", -- 00001428 - X"0C100895", -- 0000142C - X"02402021", -- 00001430 - X"081003F7", -- 00001434 - X"00001821", -- 00001438 - X"34A30001", -- 0000143C - X"36220001", -- 00001440 - X"AE620004", -- 00001444 - X"3C010000", -- 00001448 - X"AC240528", -- 0000144C - X"AC830004", -- 00001450 - X"0C100895", -- 00001454 - X"02402021", -- 00001458 - X"081003F7", -- 0000145C - X"26630008", -- 00001460 - X"3C020000", -- 00001464 - X"8C420AF4", -- 00001468 - X"121400C7", -- 0000146C - X"00552021", -- 00001470 - X"8F830970", -- 00001474 - X"2402FFFF", -- 00001478 - X"106200BF", -- 0000147C - X"02141023", -- 00001480 - X"00821021", -- 00001484 - X"3C010000", -- 00001488 - X"AC220AF4", -- 0000148C - X"32030007", -- 00001490 - X"10600004", -- 00001494 - X"0000A021", -- 00001498 - X"24020008", -- 0000149C - X"0043A023", -- 000014A0 - X"02148021", -- 000014A4 - X"02151021", -- 000014A8 - X"30420FFF", -- 000014AC - X"24031000", -- 000014B0 - X"00621823", -- 000014B4 - X"0283A021", -- 000014B8 - X"02402021", -- 000014BC - X"0C1008B8", -- 000014C0 - X"02802821", -- 000014C4 - X"00401821", -- 000014C8 - X"2402FFFF", -- 000014CC - X"106200C2", -- 000014D0 - X"00000000", -- 000014D4 - X"3C020000", -- 000014D8 - X"8C420AF4", -- 000014DC - X"00701823", -- 000014E0 - X"00741821", -- 000014E4 - X"00541021", -- 000014E8 - X"3C040000", -- 000014EC - X"24840520", -- 000014F0 - X"3C010000", -- 000014F4 - X"AC220AF4", -- 000014F8 - X"3C010000", -- 000014FC - X"AC300528", -- 00001500 - X"126400B1", -- 00001504 - X"34650001", -- 00001508 - X"2EC20010", -- 0000150C - X"10400065", -- 00001510 - X"26C3FFF4", -- 00001514 - X"24020001", -- 00001518 - X"02009821", -- 0000151C - X"08100502", -- 00001520 - X"AE020004", -- 00001524 - X"0810044F", -- 00001528 - X"2508FFFF", -- 0000152C - X"02041821", -- 00001530 - X"8C620004", -- 00001534 - X"8E07000C", -- 00001538 - X"8E060008", -- 0000153C - X"34420001", -- 00001540 - X"ACE60008", -- 00001544 - X"AC620004", -- 00001548 - X"0810041B", -- 0000154C - X"ACC7000C", -- 00001550 - X"10A00006", -- 00001554 - X"000418C2", -- 00001558 - X"2CA20005", -- 0000155C - X"10400049", -- 00001560 - X"2CA20015", -- 00001564 - X"00041182", -- 00001568 - X"24430038", -- 0000156C - X"000310C0", -- 00001570 - X"3C050000", -- 00001574 - X"24A50520", -- 00001578 - X"00453821", -- 0000157C - X"8CE60008", -- 00001580 - X"00000000", -- 00001584 - X"10C7006C", -- 00001588 - X"00000000", -- 0000158C - X"8CC20004", -- 00001590 - X"2403FFFC", -- 00001594 - X"00431024", -- 00001598 - X"0082102B", -- 0000159C - X"1040000B", -- 000015A0 - X"00000000", -- 000015A4 - X"8CC60008", -- 000015A8 - X"00000000", -- 000015AC - X"10C70007", -- 000015B0 - X"00000000", -- 000015B4 - X"8CC20004", -- 000015B8 - X"00000000", -- 000015BC - X"00431024", -- 000015C0 - X"0082102B", -- 000015C4 - X"1440FFF7", -- 000015C8 - X"00000000", -- 000015CC - X"8CC7000C", -- 000015D0 - X"AE060008", -- 000015D4 - X"AE07000C", -- 000015D8 - X"ACF00008", -- 000015DC - X"08100487", -- 000015E0 - X"ACD0000C", -- 000015E4 - X"02114021", -- 000015E8 - X"8E07000C", -- 000015EC - X"8E060008", -- 000015F0 - X"36230001", -- 000015F4 - X"34A40001", -- 000015F8 - X"01051021", -- 000015FC - X"ACE60008", -- 00001600 - X"AE030004", -- 00001604 - X"ACC7000C", -- 00001608 - X"AD040004", -- 0000160C - X"AD880008", -- 00001610 - X"AD88000C", -- 00001614 - X"AC450000", -- 00001618 - X"AD0C0008", -- 0000161C - X"02402021", -- 00001620 - X"0C100895", -- 00001624 - X"AD0C000C", -- 00001628 - X"0810041F", -- 0000162C - X"26030008", -- 00001630 - X"02041821", -- 00001634 - X"8C620004", -- 00001638 - X"8E07000C", -- 0000163C - X"8E060008", -- 00001640 - X"34420001", -- 00001644 - X"AC620004", -- 00001648 - X"ACE60008", -- 0000164C - X"0810041B", -- 00001650 - X"ACC7000C", -- 00001654 - X"08100489", -- 00001658 - X"25020003", -- 0000165C - X"10400004", -- 00001660 - X"2C620555", -- 00001664 - X"001113C2", -- 00001668 - X"08100439", -- 0000166C - X"24480077", -- 00001670 - X"1040FE9B", -- 00001674 - X"2408007E", -- 00001678 - X"00111482", -- 0000167C - X"08100439", -- 00001680 - X"2448007C", -- 00001684 - X"1440FFB9", -- 00001688 - X"24A3005B", -- 0000168C - X"2CA20055", -- 00001690 - X"10400054", -- 00001694 - X"2CA20155", -- 00001698 - X"00041302", -- 0000169C - X"0810055C", -- 000016A0 - X"2443006E", -- 000016A4 - X"2402FFF8", -- 000016A8 - X"0062B824", -- 000016AC - X"02772021", -- 000016B0 - X"24030005", -- 000016B4 - X"AE050004", -- 000016B8 - X"AC830008", -- 000016BC - X"AC830004", -- 000016C0 - X"8E620004", -- 000016C4 - X"2EE30010", -- 000016C8 - X"30420001", -- 000016CC - X"00571025", -- 000016D0 - X"10600012", -- 000016D4 - X"AE620004", -- 000016D8 - X"3C130000", -- 000016DC - X"8E730528", -- 000016E0 - X"3C030000", -- 000016E4 - X"8C630AF4", -- 000016E8 - X"8F820990", -- 000016EC - X"00000000", -- 000016F0 - X"0043102B", -- 000016F4 - X"10400002", -- 000016F8 - X"00000000", -- 000016FC - X"AF830990", -- 00001700 - X"8F82098C", -- 00001704 - X"00000000", -- 00001708 - X"0043102B", -- 0000170C - X"1040FF3D", -- 00001710 - X"00000000", -- 00001714 - X"08100502", -- 00001718 - X"AF83098C", -- 0000171C - X"26650008", -- 00001720 - X"0C100938", -- 00001724 - X"02402021", -- 00001728 - X"081005B7", -- 0000172C - X"00000000", -- 00001730 - X"08100479", -- 00001734 - X"24640003", -- 00001738 - X"0460002F", -- 0000173C - X"00601021", -- 00001740 - X"00021083", -- 00001744 - X"3C040000", -- 00001748 - X"8C840524", -- 0000174C - X"24030001", -- 00001750 - X"00431804", -- 00001754 - X"00832025", -- 00001758 - X"3C020000", -- 0000175C - X"24420520", -- 00001760 - X"AE07000C", -- 00001764 - X"AE060008", -- 00001768 - X"AC440004", -- 0000176C - X"ACD0000C", -- 00001770 - X"08100487", -- 00001774 - X"ACF00008", -- 00001778 - X"3C010000", -- 0000177C - X"AC240AF4", -- 00001780 - X"08100524", -- 00001784 - X"AF900970", -- 00001788 - X"32020FFF", -- 0000178C - X"1440FF38", -- 00001790 - X"02B71821", -- 00001794 - X"3C130000", -- 00001798 - X"8E730528", -- 0000179C - X"34620001", -- 000017A0 - X"3C010000", -- 000017A4 - X"AC240AF4", -- 000017A8 - X"081005B9", -- 000017AC - X"AE620004", -- 000017B0 - X"00071027", -- 000017B4 - X"01421024", -- 000017B8 - X"3C010000", -- 000017BC - X"AC220524", -- 000017C0 - X"081004C0", -- 000017C4 - X"00405021", -- 000017C8 - X"3C130000", -- 000017CC - X"8E730528", -- 000017D0 - X"081005B9", -- 000017D4 - X"AE050004", -- 000017D8 - X"0000A021", -- 000017DC - X"08100536", -- 000017E0 - X"02001821", -- 000017E4 - X"10400006", -- 000017E8 - X"2CA20555", -- 000017EC - X"000413C2", -- 000017F0 - X"0810055C", -- 000017F4 - X"24430077", -- 000017F8 - X"081005D1", -- 000017FC - X"24620003", -- 00001800 - X"1040FF5A", -- 00001804 - X"2403007E", -- 00001808 - X"00041482", -- 0000180C - X"0810055C", -- 00001810 - X"2443007C", -- 00001814 - X"27BDFFE8", -- 00001818 - X"AFB00010", -- 0000181C - X"AFBF0014", -- 00001820 - X"0C100A23", -- 00001824 - X"00808021", -- 00001828 - X"00405821", -- 0000182C - X"2A0207B2", -- 00001830 - X"14400086", -- 00001834 - X"00002021", -- 00001838 - X"2602F84E", -- 0000183C - X"000218C0", -- 00001840 - X"00621821", -- 00001844 - X"000318C0", -- 00001848 - X"00621821", -- 0000184C - X"00032080", -- 00001850 - X"2606F84F", -- 00001854 - X"00641021", -- 00001858 - X"04C000A2", -- 0000185C - X"AD700004", -- 00001860 - X"3C0451EB", -- 00001864 - X"3484851F", -- 00001868 - X"2607F893", -- 0000186C - X"00E40018", -- 00001870 - X"2603F9BF", -- 00001874 - X"000347C3", -- 00001878 - X"00063083", -- 0000187C - X"00073FC3", -- 00001880 - X"00463021", -- 00001884 - X"3C029249", -- 00001888 - X"34592493", -- 0000188C - X"320E0003", -- 00001890 - X"01604821", -- 00001894 - X"240C0001", -- 00001898 - X"00002810", -- 0000189C - X"00052943", -- 000018A0 - X"00A72823", -- 000018A4 - X"00640018", -- 000018A8 - X"00C53023", -- 000018AC - X"00001810", -- 000018B0 - X"000319C3", -- 000018B4 - X"00681823", -- 000018B8 - X"02040018", -- 000018BC - X"00C36821", -- 000018C0 - X"00002010", -- 000018C4 - X"000479C3", -- 000018C8 - X"0004C143", -- 000018CC - X"81230008", -- 000018D0 - X"2402004A", -- 000018D4 - X"10620062", -- 000018D8 - X"24020044", -- 000018DC - X"10620044", -- 000018E0 - X"00002021", -- 000018E4 - X"15C00009", -- 000018E8 - X"00102FC3", -- 000018EC - X"03051823", -- 000018F0 - X"00031040", -- 000018F4 - X"00431021", -- 000018F8 - X"000210C0", -- 000018FC - X"00431021", -- 00001900 - X"00021080", -- 00001904 - X"1602006B", -- 00001908 - X"00000000", -- 0000190C - X"01E51823", -- 00001910 - X"00031040", -- 00001914 - X"00431021", -- 00001918 - X"000210C0", -- 0000191C - X"00431021", -- 00001920 - X"00021100", -- 00001924 - X"12020063", -- 00001928 - X"00000000", -- 0000192C - X"00041040", -- 00001930 - X"8D25000C", -- 00001934 - X"00441021", -- 00001938 - X"24080001", -- 0000193C - X"00021100", -- 00001940 - X"3C030000", -- 00001944 - X"246300B8", -- 00001948 - X"0105202A", -- 0000194C - X"00435021", -- 00001950 - X"10800008", -- 00001954 - X"01A03821", -- 00001958 - X"01402021", -- 0000195C - X"8C820000", -- 00001960 - X"25080001", -- 00001964 - X"0105182A", -- 00001968 - X"00E23821", -- 0000196C - X"1460FFFB", -- 00001970 - X"24840004", -- 00001974 - X"24E40004", -- 00001978 - X"00990018", -- 0000197C - X"00042FC3", -- 00001980 - X"8D260014", -- 00001984 - X"00001810", -- 00001988 - X"00641821", -- 0000198C - X"00031883", -- 00001990 - X"00651823", -- 00001994 - X"000310C0", -- 00001998 - X"00431023", -- 0000199C - X"00821823", -- 000019A0 - X"00C33023", -- 000019A4 - X"04C00051", -- 000019A8 - X"00000000", -- 000019AC - X"8D240010", -- 000019B0 - X"00081880", -- 000019B4 - X"000410C0", -- 000019B8 - X"00441023", -- 000019BC - X"006A1821", -- 000019C0 - X"00461021", -- 000019C4 - X"8C65FFFC", -- 000019C8 - X"2444FFF9", -- 000019CC - X"0085182A", -- 000019D0 - X"14600005", -- 000019D4 - X"00000000", -- 000019D8 - X"2484FFF9", -- 000019DC - X"0085102A", -- 000019E0 - X"1040FFFD", -- 000019E4 - X"00000000", -- 000019E8 - X"08100680", -- 000019EC - X"00E43821", -- 000019F0 - X"8D220014", -- 000019F4 - X"00000000", -- 000019F8 - X"004D3821", -- 000019FC - X"00071840", -- 00001A00 - X"00671821", -- 00001A04 - X"00032100", -- 00001A08 - X"00832023", -- 00001A0C - X"00041100", -- 00001A10 - X"8D250018", -- 00001A14 - X"00441023", -- 00001A18 - X"8D230020", -- 00001A1C - X"000211C0", -- 00001A20 - X"00451021", -- 00001A24 - X"00431021", -- 00001A28 - X"258CFFFF", -- 00001A2C - X"AD22001C", -- 00001A30 - X"0581FFA6", -- 00001A34 - X"2529001C", -- 00001A38 - X"8D62001C", -- 00001A3C - X"8D630038", -- 00001A40 - X"24040001", -- 00001A44 - X"0043102A", -- 00001A48 - X"AD620000", -- 00001A4C - X"8FBF0014", -- 00001A50 - X"8FB00010", -- 00001A54 - X"00801021", -- 00001A58 - X"03E00008", -- 00001A5C - X"27BD0018", -- 00001A60 - X"8D220014", -- 00001A64 - X"00003021", -- 00001A68 - X"004D2021", -- 00001A6C - X"11C00013", -- 00001A70 - X"00102FC3", -- 00001A74 - X"01E51823", -- 00001A78 - X"00031040", -- 00001A7C - X"00431021", -- 00001A80 - X"000210C0", -- 00001A84 - X"00431021", -- 00001A88 - X"00021100", -- 00001A8C - X"1602FFDB", -- 00001A90 - X"00863821", -- 00001A94 - X"8D220014", -- 00001A98 - X"00000000", -- 00001A9C - X"2842003C", -- 00001AA0 - X"14400002", -- 00001AA4 - X"00000000", -- 00001AA8 - X"24060001", -- 00001AAC - X"08100680", -- 00001AB0 - X"00863821", -- 00001AB4 - X"0810064C", -- 00001AB8 - X"24040001", -- 00001ABC - X"03051823", -- 00001AC0 - X"00031040", -- 00001AC4 - X"00431021", -- 00001AC8 - X"000210C0", -- 00001ACC - X"00431021", -- 00001AD0 - X"00021080", -- 00001AD4 - X"1602FFEF", -- 00001AD8 - X"01E51823", -- 00001ADC - X"081006A0", -- 00001AE0 - X"00031040", -- 00001AE4 - X"08100619", -- 00001AE8 - X"2606F852", -- 00001AEC - X"0810066C", -- 00001AF0 - X"24C60007", -- 00001AF4 - X"27BDFFD0", -- 00001AF8 - X"AFB50024", -- 00001AFC - X"AFB40020", -- 00001B00 - X"AFB3001C", -- 00001B04 - X"0080A021", -- 00001B08 - X"AFB10014", -- 00001B0C - X"AFBF0028", -- 00001B10 - X"00A08821", -- 00001B14 - X"AFB20018", -- 00001B18 - X"AFB00010", -- 00001B1C - X"0C100A23", -- 00001B20 - X"00C0A821", -- 00001B24 - X"00409821", -- 00001B28 - X"8E850000", -- 00001B2C - X"3C02C22E", -- 00001B30 - X"34424507", -- 00001B34 - X"00A20018", -- 00001B38 - X"000527C3", -- 00001B3C - X"00001010", -- 00001B40 - X"00451021", -- 00001B44 - X"00021403", -- 00001B48 - X"00444823", -- 00001B4C - X"00091840", -- 00001B50 - X"00691821", -- 00001B54 - X"00032100", -- 00001B58 - X"00832023", -- 00001B5C - X"00041100", -- 00001B60 - X"00441023", -- 00001B64 - X"000211C0", -- 00001B68 - X"00A24023", -- 00001B6C - X"05000091", -- 00001B70 - X"3C020001", -- 00001B74 - X"3445517F", -- 00001B78 - X"00A8182A", -- 00001B7C - X"10600007", -- 00001B80 - X"3C02FFFE", -- 00001B84 - X"3444AE80", -- 00001B88 - X"00A01821", -- 00001B8C - X"01044021", -- 00001B90 - X"0068102A", -- 00001B94 - X"1440FFFD", -- 00001B98 - X"25290001", -- 00001B9C - X"3C0391A2", -- 00001BA0 - X"3463B3C5", -- 00001BA4 - X"01030018", -- 00001BA8 - X"000827C3", -- 00001BAC - X"25250004", -- 00001BB0 - X"00053FC3", -- 00001BB4 - X"00001810", -- 00001BB8 - X"00681821", -- 00001BBC - X"00031AC3", -- 00001BC0 - X"00642023", -- 00001BC4 - X"000410C0", -- 00001BC8 - X"00441023", -- 00001BCC - X"00021140", -- 00001BD0 - X"00441021", -- 00001BD4 - X"00021100", -- 00001BD8 - X"3C038888", -- 00001BDC - X"01024023", -- 00001BE0 - X"34638889", -- 00001BE4 - X"01030018", -- 00001BE8 - X"AE240008", -- 00001BEC - X"3C049249", -- 00001BF0 - X"34842493", -- 00001BF4 - X"000837C3", -- 00001BF8 - X"00001810", -- 00001BFC - X"00681821", -- 00001C00 - X"00031943", -- 00001C04 - X"00A40018", -- 00001C08 - X"00661823", -- 00001C0C - X"00031100", -- 00001C10 - X"00431023", -- 00001C14 - X"00021080", -- 00001C18 - X"01021023", -- 00001C1C - X"AE220000", -- 00001C20 - X"00002010", -- 00001C24 - X"00852021", -- 00001C28 - X"00042083", -- 00001C2C - X"00872023", -- 00001C30 - X"000410C0", -- 00001C34 - X"00441023", -- 00001C38 - X"00A22823", -- 00001C3C - X"04A0008B", -- 00001C40 - X"AE230004", -- 00001C44 - X"AE250018", -- 00001C48 - X"05200060", -- 00001C4C - X"241007B2", -- 00001C50 - X"27860978", -- 00001C54 - X"32020003", -- 00001C58 - X"001027C3", -- 00001C5C - X"1440000E", -- 00001C60 - X"00002821", -- 00001C64 - X"3C0351EB", -- 00001C68 - X"3463851F", -- 00001C6C - X"02030018", -- 00001C70 - X"00001810", -- 00001C74 - X"00031943", -- 00001C78 - X"00641823", -- 00001C7C - X"00031040", -- 00001C80 - X"00431021", -- 00001C84 - X"000210C0", -- 00001C88 - X"00431021", -- 00001C8C - X"00021080", -- 00001C90 - X"16020017", -- 00001C94 - X"00000000", -- 00001C98 - X"3C0351EB", -- 00001C9C - X"3463851F", -- 00001CA0 - X"02030018", -- 00001CA4 - X"00001810", -- 00001CA8 - X"000319C3", -- 00001CAC - X"00641823", -- 00001CB0 - X"00031040", -- 00001CB4 - X"00431021", -- 00001CB8 - X"000210C0", -- 00001CBC - X"00431021", -- 00001CC0 - X"00021100", -- 00001CC4 - X"1202000A", -- 00001CC8 - X"00051080", -- 00001CCC - X"00461021", -- 00001CD0 - X"8C420000", -- 00001CD4 - X"00000000", -- 00001CD8 - X"0122182A", -- 00001CDC - X"1460000D", -- 00001CE0 - X"00000000", -- 00001CE4 - X"01224823", -- 00001CE8 - X"08100716", -- 00001CEC - X"26100001", -- 00001CF0 - X"24050001", -- 00001CF4 - X"00051080", -- 00001CF8 - X"00461021", -- 00001CFC - X"8C420000", -- 00001D00 - X"00000000", -- 00001D04 - X"0122182A", -- 00001D08 - X"1060FFF7", -- 00001D0C - X"01224823", -- 00001D10 - X"01224821", -- 00001D14 - X"00051040", -- 00001D18 - X"00451021", -- 00001D1C - X"00021100", -- 00001D20 - X"2603F894", -- 00001D24 - X"3C040000", -- 00001D28 - X"248400B8", -- 00001D2C - X"AE230014", -- 00001D30 - X"00449021", -- 00001D34 - X"AE29001C", -- 00001D38 - X"AE200010", -- 00001D3C - X"8E420000", -- 00001D40 - X"0810075F", -- 00001D44 - X"0122102A", -- 00001D48 - X"8E220010", -- 00001D4C - X"00000000", -- 00001D50 - X"24440001", -- 00001D54 - X"00021080", -- 00001D58 - X"00521021", -- 00001D5C - X"00041880", -- 00001D60 - X"8C450000", -- 00001D64 - X"00721821", -- 00001D68 - X"AE240010", -- 00001D6C - X"8C620000", -- 00001D70 - X"01254823", -- 00001D74 - X"0122102A", -- 00001D78 - X"1040FFF3", -- 00001D7C - X"25220001", -- 00001D80 - X"12A0003D", -- 00001D84 - X"AE22000C", -- 00001D88 - X"02201021", -- 00001D8C - X"AE200020", -- 00001D90 - X"8FBF0028", -- 00001D94 - X"8FB50024", -- 00001D98 - X"8FB40020", -- 00001D9C - X"8FB3001C", -- 00001DA0 - X"8FB20018", -- 00001DA4 - X"8FB10014", -- 00001DA8 - X"8FB00010", -- 00001DAC - X"03E00008", -- 00001DB0 - X"27BD0030", -- 00001DB4 - X"34425180", -- 00001DB8 - X"01024021", -- 00001DBC - X"0500FFFE", -- 00001DC0 - X"2529FFFF", -- 00001DC4 - X"081006DE", -- 00001DC8 - X"3C020001", -- 00001DCC - X"3C0251EB", -- 00001DD0 - X"3447851F", -- 00001DD4 - X"27860978", -- 00001DD8 - X"2610FFFF", -- 00001DDC - X"32020003", -- 00001DE0 - X"00002821", -- 00001DE4 - X"1440000C", -- 00001DE8 - X"001027C3", -- 00001DEC - X"02070018", -- 00001DF0 - X"00001810", -- 00001DF4 - X"00031943", -- 00001DF8 - X"00641823", -- 00001DFC - X"00031040", -- 00001E00 - X"00431021", -- 00001E04 - X"000210C0", -- 00001E08 - X"00431021", -- 00001E0C - X"00021080", -- 00001E10 - X"1602000C", -- 00001E14 - X"00000000", -- 00001E18 - X"02070018", -- 00001E1C - X"00001810", -- 00001E20 - X"000319C3", -- 00001E24 - X"00641823", -- 00001E28 - X"00031040", -- 00001E2C - X"00431021", -- 00001E30 - X"000210C0", -- 00001E34 - X"00431021", -- 00001E38 - X"00021100", -- 00001E3C - X"16020003", -- 00001E40 - X"00051080", -- 00001E44 - X"24050001", -- 00001E48 - X"00051080", -- 00001E4C - X"00461021", -- 00001E50 - X"8C430000", -- 00001E54 - X"00000000", -- 00001E58 - X"01234821", -- 00001E5C - X"0520FFDE", -- 00001E60 - X"00051040", -- 00001E64 - X"08100748", -- 00001E68 - X"00451021", -- 00001E6C - X"24A20007", -- 00001E70 - X"08100713", -- 00001E74 - X"AE220018", -- 00001E78 - X"0C1008E6", -- 00001E7C - X"00000000", -- 00001E80 - X"8F82099C", -- 00001E84 - X"00000000", -- 00001E88 - X"1040001B", -- 00001E8C - X"00000000", -- 00001E90 - X"8E620004", -- 00001E94 - X"00000000", -- 00001E98 - X"10500005", -- 00001E9C - X"00000000", -- 00001EA0 - X"0C100606", -- 00001EA4 - X"02002021", -- 00001EA8 - X"1040008C", -- 00001EAC - X"2402FFFF", -- 00001EB0 - X"8E620000", -- 00001EB4 - X"00000000", -- 00001EB8 - X"10400080", -- 00001EBC - X"00000000", -- 00001EC0 - X"8E840000", -- 00001EC4 - X"8E62001C", -- 00001EC8 - X"00000000", -- 00001ECC - X"0082102A", -- 00001ED0 - X"14400007", -- 00001ED4 - X"00001821", -- 00001ED8 - X"8E620038", -- 00001EDC - X"00000000", -- 00001EE0 - X"0082102A", -- 00001EE4 - X"10400002", -- 00001EE8 - X"00000000", -- 00001EEC - X"24030001", -- 00001EF0 - X"081007C0", -- 00001EF4 - X"AE230020", -- 00001EF8 - X"AE200020", -- 00001EFC - X"8E230020", -- 00001F00 - X"24020001", -- 00001F04 - X"10620068", -- 00001F08 - X"00000000", -- 00001F0C - X"8E690020", -- 00001F10 - X"3C0491A2", -- 00001F14 - X"3484B3C5", -- 00001F18 - X"01240018", -- 00001F1C - X"00091FC3", -- 00001F20 - X"8E270000", -- 00001F24 - X"8E280004", -- 00001F28 - X"8E260008", -- 00001F2C - X"00002010", -- 00001F30 - X"00892021", -- 00001F34 - X"000422C3", -- 00001F38 - X"00832023", -- 00001F3C - X"000410C0", -- 00001F40 - X"00441023", -- 00001F44 - X"00021140", -- 00001F48 - X"00441021", -- 00001F4C - X"00021100", -- 00001F50 - X"3C038888", -- 00001F54 - X"01224823", -- 00001F58 - X"34638889", -- 00001F5C - X"01230018", -- 00001F60 - X"00092FC3", -- 00001F64 - X"00C43023", -- 00001F68 - X"00C02021", -- 00001F6C - X"00001810", -- 00001F70 - X"00691821", -- 00001F74 - X"00031943", -- 00001F78 - X"00651823", -- 00001F7C - X"00031100", -- 00001F80 - X"00431023", -- 00001F84 - X"00021080", -- 00001F88 - X"01221023", -- 00001F8C - X"00E22823", -- 00001F90 - X"01034023", -- 00001F94 - X"28A2003C", -- 00001F98 - X"1440003F", -- 00001F9C - X"01001821", -- 00001FA0 - X"25080001", -- 00001FA4 - X"24A2FFC4", -- 00001FA8 - X"01001821", -- 00001FAC - X"AE220000", -- 00001FB0 - X"2862003C", -- 00001FB4 - X"14400034", -- 00001FB8 - X"00000000", -- 00001FBC - X"24860001", -- 00001FC0 - X"2463FFC4", -- 00001FC4 - X"00C02021", -- 00001FC8 - X"AE230004", -- 00001FCC - X"28820018", -- 00001FD0 - X"14400027", -- 00001FD4 - X"00000000", -- 00001FD8 - X"8E220018", -- 00001FDC - X"8E23001C", -- 00001FE0 - X"24450001", -- 00001FE4 - X"24630001", -- 00001FE8 - X"28A20007", -- 00001FEC - X"14400031", -- 00001FF0 - X"AE23001C", -- 00001FF4 - X"AE200018", -- 00001FF8 - X"8E22000C", -- 00001FFC - X"8E260010", -- 00002000 - X"24450001", -- 00002004 - X"2484FFE8", -- 00002008 - X"00061080", -- 0000200C - X"AE240008", -- 00002010 - X"00521021", -- 00002014 - X"AE25000C", -- 00002018 - X"8C420000", -- 0000201C - X"00000000", -- 00002020 - X"0045182A", -- 00002024 - X"10600006", -- 00002028 - X"00A21823", -- 0000202C - X"24C40001", -- 00002030 - X"2402000C", -- 00002034 - X"1082004E", -- 00002038 - X"AE23000C", -- 0000203C - X"AE240010", -- 00002040 - X"0C1008E8", -- 00002044 - X"00000000", -- 00002048 - X"02201021", -- 0000204C - X"8FBF0028", -- 00002050 - X"8FB50024", -- 00002054 - X"8FB40020", -- 00002058 - X"8FB3001C", -- 0000205C - X"8FB20018", -- 00002060 - X"8FB10014", -- 00002064 - X"8FB00010", -- 00002068 - X"03E00008", -- 0000206C - X"27BD0030", -- 00002070 - X"04800023", -- 00002074 - X"00000000", -- 00002078 - X"0C1008E8", -- 0000207C - X"AE260008", -- 00002080 - X"08100814", -- 00002084 - X"02201021", -- 00002088 - X"04600019", -- 0000208C - X"2462003C", -- 00002090 - X"081007F4", -- 00002094 - X"AE280004", -- 00002098 - X"04A00012", -- 0000209C - X"00000000", -- 000020A0 - X"081007ED", -- 000020A4 - X"AE250000", -- 000020A8 - X"8E69003C", -- 000020AC - X"081007C6", -- 000020B0 - X"3C0491A2", -- 000020B4 - X"081007FF", -- 000020B8 - X"AE250018", -- 000020BC - X"8E840000", -- 000020C0 - X"8E62001C", -- 000020C4 - X"00000000", -- 000020C8 - X"0082102A", -- 000020CC - X"1040FF87", -- 000020D0 - X"00001821", -- 000020D4 - X"081007B7", -- 000020D8 - X"00000000", -- 000020DC - X"081007C0", -- 000020E0 - X"AE220020", -- 000020E4 - X"2508FFFF", -- 000020E8 - X"081007EB", -- 000020EC - X"24A2003C", -- 000020F0 - X"2486FFFF", -- 000020F4 - X"00C02021", -- 000020F8 - X"081007F4", -- 000020FC - X"AE220004", -- 00002100 - X"8E220018", -- 00002104 - X"8E23001C", -- 00002108 - X"2445FFFF", -- 0000210C - X"04A00024", -- 00002110 - X"2466FFFF", -- 00002114 - X"AE250018", -- 00002118 - X"8E22000C", -- 0000211C - X"24830018", -- 00002120 - X"2442FFFF", -- 00002124 - X"AE230008", -- 00002128 - X"14400019", -- 0000212C - X"AE22000C", -- 00002130 - X"8E220010", -- 00002134 - X"00000000", -- 00002138 - X"2444FFFF", -- 0000213C - X"0480001B", -- 00002140 - X"00000000", -- 00002144 - X"AE240010", -- 00002148 - X"AE26001C", -- 0000214C - X"8E220010", -- 00002150 - X"00000000", -- 00002154 - X"00021080", -- 00002158 - X"00521021", -- 0000215C - X"8C430000", -- 00002160 - X"0C1008E8", -- 00002164 - X"AE23000C", -- 00002168 - X"08100814", -- 0000216C - X"02201021", -- 00002170 - X"8E220014", -- 00002174 - X"AE200010", -- 00002178 - X"24420001", -- 0000217C - X"AE220014", -- 00002180 - X"0C1008E8", -- 00002184 - X"AE20001C", -- 00002188 - X"08100814", -- 0000218C - X"02201021", -- 00002190 - X"0C1008E8", -- 00002194 - X"AE26001C", -- 00002198 - X"08100814", -- 0000219C - X"02201021", -- 000021A0 - X"24020006", -- 000021A4 - X"08100847", -- 000021A8 - X"AE220018", -- 000021AC - X"8E220014", -- 000021B0 - X"00003021", -- 000021B4 - X"2444FFFF", -- 000021B8 - X"30830003", -- 000021BC - X"2402000B", -- 000021C0 - X"AE220010", -- 000021C4 - X"AE240014", -- 000021C8 - X"1460000E", -- 000021CC - X"00042FC3", -- 000021D0 - X"3C0351EB", -- 000021D4 - X"3463851F", -- 000021D8 - X"00830018", -- 000021DC - X"00001810", -- 000021E0 - X"00031943", -- 000021E4 - X"00651823", -- 000021E8 - X"00031040", -- 000021EC - X"00431021", -- 000021F0 - X"000210C0", -- 000021F4 - X"00431021", -- 000021F8 - X"00021080", -- 000021FC - X"1482000E", -- 00002200 - X"00000000", -- 00002204 - X"3C0351EB", -- 00002208 - X"3463851F", -- 0000220C - X"00830018", -- 00002210 - X"00001810", -- 00002214 - X"000319C3", -- 00002218 - X"00651823", -- 0000221C - X"00031040", -- 00002220 - X"00431021", -- 00002224 - X"000210C0", -- 00002228 - X"00431021", -- 0000222C - X"00021100", -- 00002230 - X"14820002", -- 00002234 - X"00000000", -- 00002238 - X"24060001", -- 0000223C - X"24C2016D", -- 00002240 - X"08100854", -- 00002244 - X"AE22001C", -- 00002248 - X"03E00008", -- 0000224C - X"00000000", -- 00002250 - X"03E00008", -- 00002254 - X"00000000", -- 00002258 - X"8F82096C", -- 0000225C - X"00002821", -- 00002260 - X"AC4400A8", -- 00002264 - X"03E00008", -- 00002268 - X"AC4500AC", -- 0000226C - X"8F88096C", -- 00002270 - X"3C045851", -- 00002274 - X"8D0600A8", -- 00002278 - X"3484F42D", -- 0000227C - X"00C40018", -- 00002280 - X"3C054C95", -- 00002284 - X"34A57F2D", -- 00002288 - X"8D0700AC", -- 0000228C - X"00002012", -- 00002290 - X"00000000", -- 00002294 - X"00000000", -- 00002298 - X"00C50019", -- 0000229C - X"00001810", -- 000022A0 - X"00832021", -- 000022A4 - X"00001012", -- 000022A8 - X"24420001", -- 000022AC - X"2C460001", -- 000022B0 - X"00E50018", -- 000022B4 - X"AD0200A8", -- 000022B8 - X"3C027FFF", -- 000022BC - X"3442FFFF", -- 000022C0 - X"00002812", -- 000022C4 - X"00851821", -- 000022C8 - X"00661821", -- 000022CC - X"00032002", -- 000022D0 - X"00441024", -- 000022D4 - X"03E00008", -- 000022D8 - X"AD0300AC", -- 000022DC - X"27BDFFE8", -- 000022E0 - X"AFB00010", -- 000022E4 - X"00808021", -- 000022E8 - X"00A02021", -- 000022EC - X"AFBF0014", -- 000022F0 - X"0C100198", -- 000022F4 - X"AF800B1C", -- 000022F8 - X"00401821", -- 000022FC - X"2402FFFF", -- 00002300 - X"10620006", -- 00002304 - X"00000000", -- 00002308 - X"8FBF0014", -- 0000230C - X"8FB00010", -- 00002310 - X"00601021", -- 00002314 - X"03E00008", -- 00002318 - X"27BD0018", -- 0000231C - X"8F820B1C", -- 00002320 - X"00000000", -- 00002324 - X"1040FFF8", -- 00002328 - X"00000000", -- 0000232C - X"081008C3", -- 00002330 - X"AE020000", -- 00002334 - X"27BDFFE0", -- 00002338 - X"AFB00018", -- 0000233C - X"00808021", -- 00002340 - X"8F84096C", -- 00002344 - X"27A50010", -- 00002348 - X"AFBF001C", -- 0000234C - X"0C100A08", -- 00002350 - X"00003021", -- 00002354 - X"04400007", -- 00002358 - X"2403FFFF", -- 0000235C - X"1200000A", -- 00002360 - X"00000000", -- 00002364 - X"8FA20010", -- 00002368 - X"00000000", -- 0000236C - X"AE020000", -- 00002370 - X"00401821", -- 00002374 - X"8FBF001C", -- 00002378 - X"8FB00018", -- 0000237C - X"00601021", -- 00002380 - X"03E00008", -- 00002384 - X"27BD0020", -- 00002388 - X"8FA20010", -- 0000238C - X"081008DE", -- 00002390 - X"00401821", -- 00002394 - X"03E00008", -- 00002398 - X"00000000", -- 0000239C - X"03E00008", -- 000023A0 - X"00000000", -- 000023A4 - X"27BDFFE0", -- 000023A8 - X"AFB20018", -- 000023AC - X"AFB10014", -- 000023B0 - X"AFB00010", -- 000023B4 - X"00809021", -- 000023B8 - X"AFBF001C", -- 000023BC - X"0C100893", -- 000023C0 - X"00A08021", -- 000023C4 - X"3C020000", -- 000023C8 - X"8C420528", -- 000023CC - X"02402021", -- 000023D0 - X"8C430004", -- 000023D4 - X"2402FFFC", -- 000023D8 - X"00628824", -- 000023DC - X"02308023", -- 000023E0 - X"26100FEF", -- 000023E4 - X"00108302", -- 000023E8 - X"2610FFFF", -- 000023EC - X"00108300", -- 000023F0 - X"2A021000", -- 000023F4 - X"14400009", -- 000023F8 - X"00002821", -- 000023FC - X"0C1008B8", -- 00002400 - X"00000000", -- 00002404 - X"3C030000", -- 00002408 - X"8C630528", -- 0000240C - X"02402021", -- 00002410 - X"00711821", -- 00002414 - X"1062000A", -- 00002418 - X"00102823", -- 0000241C - X"0C100895", -- 00002420 - X"00000000", -- 00002424 - X"00001021", -- 00002428 - X"8FBF001C", -- 0000242C - X"8FB20018", -- 00002430 - X"8FB10014", -- 00002434 - X"8FB00010", -- 00002438 - X"03E00008", -- 0000243C - X"27BD0020", -- 00002440 - X"0C1008B8", -- 00002444 - X"02402021", -- 00002448 - X"02301823", -- 0000244C - X"34660001", -- 00002450 - X"2403FFFF", -- 00002454 - X"02402021", -- 00002458 - X"1043000F", -- 0000245C - X"00002821", -- 00002460 - X"3C030000", -- 00002464 - X"8C630528", -- 00002468 - X"00000000", -- 0000246C - X"AC660004", -- 00002470 - X"3C020000", -- 00002474 - X"8C420AF4", -- 00002478 - X"00000000", -- 0000247C - X"00501023", -- 00002480 - X"3C010000", -- 00002484 - X"AC220AF4", -- 00002488 - X"0C100895", -- 0000248C - X"02402021", -- 00002490 - X"0810090B", -- 00002494 - X"24020001", -- 00002498 - X"0C1008B8", -- 0000249C - X"00000000", -- 000024A0 - X"3C050000", -- 000024A4 - X"8CA50528", -- 000024A8 - X"00401821", -- 000024AC - X"00458823", -- 000024B0 - X"2A220010", -- 000024B4 - X"02402021", -- 000024B8 - X"1440FFD8", -- 000024BC - X"36260001", -- 000024C0 - X"8F820970", -- 000024C4 - X"00000000", -- 000024C8 - X"00621023", -- 000024CC - X"3C010000", -- 000024D0 - X"AC220AF4", -- 000024D4 - X"08100908", -- 000024D8 - X"ACA60004", -- 000024DC - X"27BDFFE0", -- 000024E0 - X"AFB10014", -- 000024E4 - X"AFB00010", -- 000024E8 - X"AFBF0018", -- 000024EC - X"00A08021", -- 000024F0 - X"10A0003C", -- 000024F4 - X"00808821", -- 000024F8 - X"0C100893", -- 000024FC - X"00000000", -- 00002500 - X"260BFFF8", -- 00002504 - X"8D640004", -- 00002508 - X"2402FFFE", -- 0000250C - X"00824824", -- 00002510 - X"01693021", -- 00002514 - X"8CC30004", -- 00002518 - X"2402FFFC", -- 0000251C - X"00625024", -- 00002520 - X"3C020000", -- 00002524 - X"8C420528", -- 00002528 - X"3C0C0000", -- 0000252C - X"258C0520", -- 00002530 - X"10460053", -- 00002534 - X"30820001", -- 00002538 - X"ACCA0004", -- 0000253C - X"1440000D", -- 00002540 - X"00002021", -- 00002544 - X"8E05FFF8", -- 00002548 - X"3C020000", -- 0000254C - X"24420528", -- 00002550 - X"01655823", -- 00002554 - X"8D630008", -- 00002558 - X"00000000", -- 0000255C - X"10620087", -- 00002560 - X"01254821", -- 00002564 - X"8D68000C", -- 00002568 - X"00000000", -- 0000256C - X"AD030008", -- 00002570 - X"AC68000C", -- 00002574 - X"00CA1821", -- 00002578 - X"8C620004", -- 0000257C - X"00000000", -- 00002580 - X"30420001", -- 00002584 - X"1440000D", -- 00002588 - X"35220001", -- 0000258C - X"1480001A", -- 00002590 - X"012A4821", -- 00002594 - X"8CC30008", -- 00002598 - X"3C020000", -- 0000259C - X"24420528", -- 000025A0 - X"10620070", -- 000025A4 - X"00000000", -- 000025A8 - X"8CC8000C", -- 000025AC - X"00000000", -- 000025B0 - X"AD030008", -- 000025B4 - X"AC68000C", -- 000025B8 - X"35220001", -- 000025BC - X"01691821", -- 000025C0 - X"AD620004", -- 000025C4 - X"10800012", -- 000025C8 - X"AC690000", -- 000025CC - X"02202021", -- 000025D0 - X"8FBF0018", -- 000025D4 - X"8FB10014", -- 000025D8 - X"8FB00010", -- 000025DC - X"08100895", -- 000025E0 - X"27BD0020", -- 000025E4 - X"8FBF0018", -- 000025E8 - X"8FB10014", -- 000025EC - X"8FB00010", -- 000025F0 - X"03E00008", -- 000025F4 - X"27BD0020", -- 000025F8 - X"8CC30008", -- 000025FC - X"8CC8000C", -- 00002600 - X"00000000", -- 00002604 - X"AD030008", -- 00002608 - X"0810096F", -- 0000260C - X"AC68000C", -- 00002610 - X"2D220200", -- 00002614 - X"1040002F", -- 00002618 - X"00092242", -- 0000261C - X"000918C2", -- 00002620 - X"3C050000", -- 00002624 - X"24A50520", -- 00002628 - X"0460005E", -- 0000262C - X"00602021", -- 00002630 - X"000310C0", -- 00002634 - X"00454021", -- 00002638 - X"00042083", -- 0000263C - X"3C020000", -- 00002640 - X"8C420524", -- 00002644 - X"24030001", -- 00002648 - X"8D070008", -- 0000264C - X"00831804", -- 00002650 - X"00431025", -- 00002654 - X"AD68000C", -- 00002658 - X"AD670008", -- 0000265C - X"ACA20004", -- 00002660 - X"ACEB000C", -- 00002664 - X"AD0B0008", -- 00002668 - X"02202021", -- 0000266C - X"8FBF0018", -- 00002670 - X"8FB10014", -- 00002674 - X"8FB00010", -- 00002678 - X"08100895", -- 0000267C - X"27BD0020", -- 00002680 - X"14400009", -- 00002684 - X"012A4821", -- 00002688 - X"8E05FFF8", -- 0000268C - X"00000000", -- 00002690 - X"01655823", -- 00002694 - X"8D68000C", -- 00002698 - X"8D670008", -- 0000269C - X"01254821", -- 000026A0 - X"AD070008", -- 000026A4 - X"ACE8000C", -- 000026A8 - X"8F820974", -- 000026AC - X"35230001", -- 000026B0 - X"0122102B", -- 000026B4 - X"AD8B0008", -- 000026B8 - X"1440FFC4", -- 000026BC - X"AD630004", -- 000026C0 - X"8F850994", -- 000026C4 - X"0C1008EA", -- 000026C8 - X"02202021", -- 000026CC - X"08100975", -- 000026D0 - X"02202021", -- 000026D4 - X"1480001D", -- 000026D8 - X"000918C2", -- 000026DC - X"000310C0", -- 000026E0 - X"004C4021", -- 000026E4 - X"8D070008", -- 000026E8 - X"00000000", -- 000026EC - X"10E8002F", -- 000026F0 - X"00000000", -- 000026F4 - X"8CE20004", -- 000026F8 - X"2403FFFC", -- 000026FC - X"00431024", -- 00002700 - X"0122102B", -- 00002704 - X"1040000B", -- 00002708 - X"00000000", -- 0000270C - X"8CE70008", -- 00002710 - X"00000000", -- 00002714 - X"10E80007", -- 00002718 - X"00000000", -- 0000271C - X"8CE20004", -- 00002720 - X"00000000", -- 00002724 - X"00431024", -- 00002728 - X"0122102B", -- 0000272C - X"1440FFF7", -- 00002730 - X"00000000", -- 00002734 - X"8CE8000C", -- 00002738 - X"AD670008", -- 0000273C - X"AD68000C", -- 00002740 - X"AD0B0008", -- 00002744 - X"0810099B", -- 00002748 - X"ACEB000C", -- 0000274C - X"2C820005", -- 00002750 - X"1040000C", -- 00002754 - X"2C820015", -- 00002758 - X"00091182", -- 0000275C - X"081009B8", -- 00002760 - X"24430038", -- 00002764 - X"24040001", -- 00002768 - X"AC6B000C", -- 0000276C - X"AC6B0008", -- 00002770 - X"AD63000C", -- 00002774 - X"0810096F", -- 00002778 - X"AD630008", -- 0000277C - X"0810095E", -- 00002780 - X"24040001", -- 00002784 - X"1440FFD5", -- 00002788 - X"2483005B", -- 0000278C - X"2C820055", -- 00002790 - X"10400016", -- 00002794 - X"2C820155", -- 00002798 - X"00091302", -- 0000279C - X"081009B8", -- 000027A0 - X"2443006E", -- 000027A4 - X"0810098D", -- 000027A8 - X"24640003", -- 000027AC - X"04600014", -- 000027B0 - X"00601021", -- 000027B4 - X"00021083", -- 000027B8 - X"3C040000", -- 000027BC - X"8C840524", -- 000027C0 - X"24030001", -- 000027C4 - X"00431804", -- 000027C8 - X"00832025", -- 000027CC - X"3C020000", -- 000027D0 - X"24420520", -- 000027D4 - X"AD68000C", -- 000027D8 - X"AD670008", -- 000027DC - X"AC440004", -- 000027E0 - X"ACEB000C", -- 000027E4 - X"0810099B", -- 000027E8 - X"AD0B0008", -- 000027EC - X"10400006", -- 000027F0 - X"2C820555", -- 000027F4 - X"000913C2", -- 000027F8 - X"081009B8", -- 000027FC - X"24430077", -- 00002800 - X"081009EE", -- 00002804 - X"24620003", -- 00002808 - X"1040FFB4", -- 0000280C - X"2403007E", -- 00002810 - X"00091482", -- 00002814 - X"081009B8", -- 00002818 - X"2443007C", -- 0000281C - X"27BDFFE8", -- 00002820 - X"AFB00010", -- 00002824 - X"00808021", -- 00002828 - X"00A02021", -- 0000282C - X"00C02821", -- 00002830 - X"AFBF0014", -- 00002834 - X"0C10016D", -- 00002838 - X"AF800B1C", -- 0000283C - X"00401821", -- 00002840 - X"2402FFFF", -- 00002844 - X"10620006", -- 00002848 - X"00000000", -- 0000284C - X"8FBF0014", -- 00002850 - X"8FB00010", -- 00002854 - X"00601021", -- 00002858 - X"03E00008", -- 0000285C - X"27BD0018", -- 00002860 - X"8F820B1C", -- 00002864 - X"00000000", -- 00002868 - X"1040FFF8", -- 0000286C - X"00000000", -- 00002870 - X"AE020000", -- 00002874 - X"8FBF0014", -- 00002878 - X"8FB00010", -- 0000287C - X"00601021", -- 00002880 - X"03E00008", -- 00002884 - X"27BD0018", -- 00002888 - X"3C020000", -- 0000288C - X"03E00008", -- 00002890 - X"24420928", -- 00002894 - X"27BDFFE0", -- 00002898 - X"AFB10014", -- 0000289C - X"AFB00010", -- 000028A0 - X"AFBF0018", -- 000028A4 - X"8CA20000", -- 000028A8 - X"00A08821", -- 000028AC - X"00808021", -- 000028B0 - X"14400008", -- 000028B4 - X"00402821", -- 000028B8 - X"02002021", -- 000028BC - X"02202821", -- 000028C0 - X"8FBF0018", -- 000028C4 - X"8FB10014", -- 000028C8 - X"8FB00010", -- 000028CC - X"08100938", -- 000028D0 - X"27BD0020", -- 000028D4 - X"0C100A26", -- 000028D8 - X"00000000", -- 000028DC - X"02002021", -- 000028E0 - X"02202821", -- 000028E4 - X"8FBF0018", -- 000028E8 - X"8FB10014", -- 000028EC - X"8FB00010", -- 000028F0 - X"08100938", -- 000028F4 - X"27BD0020", -- 000028F8 - X"8F82096C", -- 000028FC - X"27BDFFE0", -- 00002900 - X"AFB10014", -- 00002904 - X"AFBF001C", -- 00002908 - X"AFB20018", -- 0000290C - X"AFB00010", -- 00002910 - X"1082001F", -- 00002914 - X"00808821", -- 00002918 - X"8C85004C", -- 0000291C - X"00000000", -- 00002920 - X"14A00021", -- 00002924 - X"00000000", -- 00002928 - X"8E250040", -- 0000292C - X"00000000", -- 00002930 - X"14A00035", -- 00002934 - X"00000000", -- 00002938 - X"8E250148", -- 0000293C - X"00000000", -- 00002940 - X"10A0000B", -- 00002944 - X"00000000", -- 00002948 - X"2632014C", -- 0000294C - X"10B20008", -- 00002950 - X"00000000", -- 00002954 - X"08100A5B", -- 00002958 - X"00A08021", -- 0000295C - X"8E100000", -- 00002960 - X"0C100938", -- 00002964 - X"02202021", -- 00002968 - X"1650FFFC", -- 0000296C - X"02002821", -- 00002970 - X"8E250054", -- 00002974 - X"00000000", -- 00002978 - X"14A00036", -- 0000297C - X"00000000", -- 00002980 - X"8E220038", -- 00002984 - X"00000000", -- 00002988 - X"14400023", -- 0000298C - X"00000000", -- 00002990 - X"8FBF001C", -- 00002994 - X"8FB20018", -- 00002998 - X"8FB10014", -- 0000299C - X"8FB00010", -- 000029A0 - X"03E00008", -- 000029A4 - X"27BD0020", -- 000029A8 - X"00009021", -- 000029AC - X"00121080", -- 000029B0 - X"00451021", -- 000029B4 - X"8C500000", -- 000029B8 - X"00000000", -- 000029BC - X"12000008", -- 000029C0 - X"00000000", -- 000029C4 - X"02002821", -- 000029C8 - X"8E100000", -- 000029CC - X"0C100938", -- 000029D0 - X"02202021", -- 000029D4 - X"1600FFFC", -- 000029D8 - X"02002821", -- 000029DC - X"8E25004C", -- 000029E0 - X"26520001", -- 000029E4 - X"2A42000F", -- 000029E8 - X"1440FFF1", -- 000029EC - X"00121080", -- 000029F0 - X"0C100938", -- 000029F4 - X"02202021", -- 000029F8 - X"8E250040", -- 000029FC - X"00000000", -- 00002A00 - X"10A0FFCD", -- 00002A04 - X"00000000", -- 00002A08 - X"0C100938", -- 00002A0C - X"02202021", -- 00002A10 - X"08100A4F", -- 00002A14 - X"00000000", -- 00002A18 - X"8E22003C", -- 00002A1C - X"00000000", -- 00002A20 - X"0040F809", -- 00002A24 - X"02202021", -- 00002A28 - X"8E2502E0", -- 00002A2C - X"00000000", -- 00002A30 - X"10A0FFD7", -- 00002A34 - X"00000000", -- 00002A38 - X"02202021", -- 00002A3C - X"8FBF001C", -- 00002A40 - X"8FB20018", -- 00002A44 - X"8FB10014", -- 00002A48 - X"8FB00010", -- 00002A4C - X"08100A26", -- 00002A50 - X"27BD0020", -- 00002A54 - X"0C100938", -- 00002A58 - X"02202021", -- 00002A5C - X"08100A61", -- 00002A60 - X"00000000", -- 00002A64 - X"27BDFFD8", -- 00002A68 - X"AFB3001C", -- 00002A6C - X"AFBF0020", -- 00002A70 - X"AFB20018", -- 00002A74 - X"AFB10014", -- 00002A78 - X"AFB00010", -- 00002A7C - X"10800028", -- 00002A80 - X"00809821", -- 00002A84 - X"8E720148", -- 00002A88 - X"00000000", -- 00002A8C - X"12400012", -- 00002A90 - X"00000000", -- 00002A94 - X"8E510004", -- 00002A98 - X"00000000", -- 00002A9C - X"2631FFFF", -- 00002AA0 - X"06200009", -- 00002AA4 - X"00111080", -- 00002AA8 - X"00521021", -- 00002AAC - X"24500008", -- 00002AB0 - X"8E020000", -- 00002AB4 - X"00000000", -- 00002AB8 - X"0040F809", -- 00002ABC - X"2631FFFF", -- 00002AC0 - X"0621FFFB", -- 00002AC4 - X"2610FFFC", -- 00002AC8 - X"8E520000", -- 00002ACC - X"00000000", -- 00002AD0 - X"1640FFF0", -- 00002AD4 - X"00000000", -- 00002AD8 - X"8E79003C", -- 00002ADC - X"00000000", -- 00002AE0 - X"17200008", -- 00002AE4 - X"02602021", -- 00002AE8 - X"8FBF0020", -- 00002AEC - X"8FB3001C", -- 00002AF0 - X"8FB20018", -- 00002AF4 - X"8FB10014", -- 00002AF8 - X"8FB00010", -- 00002AFC - X"03E00008", -- 00002B00 - X"27BD0028", -- 00002B04 - X"8FBF0020", -- 00002B08 - X"8FB3001C", -- 00002B0C - X"8FB20018", -- 00002B10 - X"8FB10014", -- 00002B14 - X"8FB00010", -- 00002B18 - X"03200008", -- 00002B1C - X"27BD0028", -- 00002B20 - X"8F93096C", -- 00002B24 - X"08100AA2", -- 00002B28 - X"00000000", -- 00002B2C - X"00000000", -- 00002B30 - X"00000000", -- 00002B34 - X"00000000", -- 00002B38 - X"00000000", -- 00002B3C - X"00000000", -- 00002B40 - X"00000000", -- 00002B44 - X"00000000", -- 00002B48 - X"00000000", -- 00002B4C - X"00000000", -- 00002B50 - X"00000000", -- 00002B54 - X"00000000", -- 00002B58 - X"00000000", -- 00002B5C - X"00000000", -- 00002B60 - X"00000000", -- 00002B64 - X"00000000", -- 00002B68 - X"00000000", -- 00002B6C - X"00000000", -- 00002B70 - X"00000000", -- 00002B74 - X"00000000", -- 00002B78 - X"00000000", -- 00002B7C - X"00000000", -- 00002B80 - X"00000000", -- 00002B84 - X"00000000", -- 00002B88 - X"00000000", -- 00002B8C - X"00000000", -- 00002B90 - X"00000000", -- 00002B94 - X"00000000", -- 00002B98 - X"00000000", -- 00002B9C - X"00000000", -- 00002BA0 - X"00000000", -- 00002BA4 - X"00000000", -- 00002BA8 - X"00000000", -- 00002BAC - X"00000000", -- 00002BB0 - X"00000000", -- 00002BB4 - X"00000000", -- 00002BB8 - X"00000000", -- 00002BBC - X"00000000", -- 00002BC0 - X"00000000", -- 00002BC4 - X"00000000", -- 00002BC8 - X"00000000", -- 00002BCC - X"00000000", -- 00002BD0 - X"00000000", -- 00002BD4 - X"00000000", -- 00002BD8 - X"00000000", -- 00002BDC - X"00000000", -- 00002BE0 - X"00000000", -- 00002BE4 - X"00000000", -- 00002BE8 - X"00000000", -- 00002BEC - X"00000000", -- 00002BF0 - X"00000000", -- 00002BF4 - X"00000000", -- 00002BF8 - X"00000000", -- 00002BFC - X"00000000", -- 00002C00 - X"00000000", -- 00002C04 - X"00000000", -- 00002C08 - X"00000000", -- 00002C0C - X"00000000", -- 00002C10 - X"00000000", -- 00002C14 - X"00000000", -- 00002C18 - X"00000000", -- 00002C1C - X"00000000", -- 00002C20 - X"00000000", -- 00002C24 - X"00000000", -- 00002C28 - X"00000000", -- 00002C2C - X"00000000", -- 00002C30 - X"00000000", -- 00002C34 - X"00000000", -- 00002C38 - X"00000000", -- 00002C3C - X"00000000", -- 00002C40 - X"00000000", -- 00002C44 - X"00000000", -- 00002C48 - X"00000000", -- 00002C4C - X"00000000", -- 00002C50 - X"00000000", -- 00002C54 - X"00000000", -- 00002C58 - X"00000000", -- 00002C5C - X"00000000", -- 00002C60 - X"00000000", -- 00002C64 - X"00000000", -- 00002C68 - X"00000000", -- 00002C6C - X"00000000", -- 00002C70 - X"00000000", -- 00002C74 - X"00000000", -- 00002C78 - X"00000000", -- 00002C7C - X"00000000", -- 00002C80 - X"00000000", -- 00002C84 - X"00000000", -- 00002C88 - X"00000000", -- 00002C8C - X"00000000", -- 00002C90 - X"00000000", -- 00002C94 - X"00000000", -- 00002C98 - X"00000000", -- 00002C9C - X"00000000", -- 00002CA0 - X"00000000", -- 00002CA4 - X"00000000", -- 00002CA8 - X"00000000", -- 00002CAC - X"00000000", -- 00002CB0 - X"00000000", -- 00002CB4 - X"00000000", -- 00002CB8 - X"00000000", -- 00002CBC - X"00000000", -- 00002CC0 - X"00000000", -- 00002CC4 - X"00000000", -- 00002CC8 - X"00000000", -- 00002CCC - X"00000000", -- 00002CD0 - X"00000000", -- 00002CD4 - X"00000000", -- 00002CD8 - X"00000000", -- 00002CDC - X"00000000", -- 00002CE0 - X"00000000", -- 00002CE4 - X"00000000", -- 00002CE8 - X"00000000", -- 00002CEC - X"00000000", -- 00002CF0 - X"00000000", -- 00002CF4 - X"00000000", -- 00002CF8 - X"00000000", -- 00002CFC - X"00000000", -- 00002D00 - X"00000000", -- 00002D04 - X"00000000", -- 00002D08 - X"00000000", -- 00002D0C - X"00000000", -- 00002D10 - X"00000000", -- 00002D14 - X"00000000", -- 00002D18 - X"00000000", -- 00002D1C - X"00000000", -- 00002D20 - X"00000000", -- 00002D24 - X"00000000", -- 00002D28 - X"00000000", -- 00002D2C - X"00000000", -- 00002D30 - X"00000000", -- 00002D34 - X"00000000", -- 00002D38 - X"00000000", -- 00002D3C - X"00000000", -- 00002D40 - X"00000000", -- 00002D44 - X"00000000", -- 00002D48 - X"00000000", -- 00002D4C - X"00000000", -- 00002D50 - X"00000000", -- 00002D54 - X"00000000", -- 00002D58 - X"00000000", -- 00002D5C - X"00000000", -- 00002D60 - X"00000000", -- 00002D64 - X"00000000", -- 00002D68 - X"00000000", -- 00002D6C - X"00000000", -- 00002D70 - X"00000000", -- 00002D74 - X"00000000", -- 00002D78 - X"00000000", -- 00002D7C - X"00000000", -- 00002D80 - X"00000000", -- 00002D84 - X"00000000", -- 00002D88 - X"00000000", -- 00002D8C - X"00000000", -- 00002D90 - X"00000000", -- 00002D94 - X"00000000", -- 00002D98 - X"00000000", -- 00002D9C - X"00000000", -- 00002DA0 - X"00000000", -- 00002DA4 - X"00000000", -- 00002DA8 - X"00000000", -- 00002DAC - X"00000000", -- 00002DB0 - X"00000000", -- 00002DB4 - X"00000000", -- 00002DB8 - X"00000000", -- 00002DBC - X"00000000", -- 00002DC0 - X"00000000", -- 00002DC4 - X"00000000", -- 00002DC8 - X"00000000", -- 00002DCC - X"00000000", -- 00002DD0 - X"00000000", -- 00002DD4 - X"00000000", -- 00002DD8 - X"00000000", -- 00002DDC - X"00000000", -- 00002DE0 - X"00000000", -- 00002DE4 - X"00000000", -- 00002DE8 - X"00000000", -- 00002DEC - X"00000000", -- 00002DF0 - X"00000000", -- 00002DF4 - X"00000000", -- 00002DF8 - X"00000000", -- 00002DFC - X"00000000", -- 00002E00 - X"00000000", -- 00002E04 - X"00000000", -- 00002E08 - X"00000000", -- 00002E0C - X"00000000", -- 00002E10 - X"00000000", -- 00002E14 - X"00000000", -- 00002E18 - X"00000000", -- 00002E1C - X"00000000", -- 00002E20 - X"00000000", -- 00002E24 - X"00000000", -- 00002E28 - X"00000000", -- 00002E2C - X"00000000", -- 00002E30 - X"00000000", -- 00002E34 - X"00000000", -- 00002E38 - X"00000000", -- 00002E3C - X"00000000", -- 00002E40 - X"00000000", -- 00002E44 - X"00000000", -- 00002E48 - X"00000000", -- 00002E4C - X"00000000", -- 00002E50 - X"00000000", -- 00002E54 - X"00000000", -- 00002E58 - X"00000000", -- 00002E5C - X"00000000", -- 00002E60 - X"00000000", -- 00002E64 - X"00000000", -- 00002E68 - X"00000000", -- 00002E6C - X"00000000", -- 00002E70 - X"00000000", -- 00002E74 - X"00000000", -- 00002E78 - X"00000000", -- 00002E7C - X"00000000", -- 00002E80 - X"00000000", -- 00002E84 - X"00000000", -- 00002E88 - X"00000000", -- 00002E8C - X"00000000", -- 00002E90 - X"00000000", -- 00002E94 - X"00000000", -- 00002E98 - X"00000000", -- 00002E9C - X"00000000", -- 00002EA0 - X"00000000", -- 00002EA4 - X"00000000", -- 00002EA8 - X"00000000", -- 00002EAC - X"00000000", -- 00002EB0 - X"00000000", -- 00002EB4 - X"00000000", -- 00002EB8 - X"00000000", -- 00002EBC - X"00000000", -- 00002EC0 - X"00000000", -- 00002EC4 - X"00000000", -- 00002EC8 - X"00000000", -- 00002ECC - X"00000000", -- 00002ED0 - X"00000000", -- 00002ED4 - X"00000000", -- 00002ED8 - X"00000000", -- 00002EDC - X"00000000", -- 00002EE0 - X"00000000", -- 00002EE4 - X"00000000", -- 00002EE8 - X"00000000", -- 00002EEC - X"00000000", -- 00002EF0 - X"00000000", -- 00002EF4 - X"00000000", -- 00002EF8 - X"00000000", -- 00002EFC - X"00000000", -- 00002F00 - X"00000000", -- 00002F04 - X"00000000", -- 00002F08 - X"00000000", -- 00002F0C - X"00000000", -- 00002F10 - X"00000000", -- 00002F14 - X"00000000", -- 00002F18 - X"00000000", -- 00002F1C - X"00000000", -- 00002F20 - X"00000000", -- 00002F24 - X"00000000", -- 00002F28 - X"00000000", -- 00002F2C - X"00000000", -- 00002F30 - X"00000000", -- 00002F34 - X"00000000", -- 00002F38 - X"00000000", -- 00002F3C - X"00000000", -- 00002F40 - X"00000000", -- 00002F44 - X"00000000", -- 00002F48 - X"00000000", -- 00002F4C - X"00000000", -- 00002F50 - X"00000000", -- 00002F54 - X"00000000", -- 00002F58 - X"00000000", -- 00002F5C - X"00000000", -- 00002F60 - X"00000000", -- 00002F64 - X"00000000", -- 00002F68 - X"00000000", -- 00002F6C - X"00000000", -- 00002F70 - X"00000000", -- 00002F74 - X"00000000", -- 00002F78 - X"00000000", -- 00002F7C - X"00000000", -- 00002F80 - X"00000000", -- 00002F84 - X"00000000", -- 00002F88 - X"00000000", -- 00002F8C - X"00000000", -- 00002F90 - X"00000000", -- 00002F94 - X"00000000", -- 00002F98 - X"00000000", -- 00002F9C - X"00000000", -- 00002FA0 - X"00000000", -- 00002FA4 - X"00000000", -- 00002FA8 - X"00000000", -- 00002FAC - X"00000000", -- 00002FB0 - X"00000000", -- 00002FB4 - X"00000000", -- 00002FB8 - X"00000000", -- 00002FBC - X"00000000", -- 00002FC0 - X"00000000", -- 00002FC4 - X"00000000", -- 00002FC8 - X"00000000", -- 00002FCC - X"00000000", -- 00002FD0 - X"00000000", -- 00002FD4 - X"00000000", -- 00002FD8 - X"00000000", -- 00002FDC - X"00000000", -- 00002FE0 - X"00000000", -- 00002FE4 - X"00000000", -- 00002FE8 - X"00000000", -- 00002FEC - X"00000000", -- 00002FF0 - X"00000000", -- 00002FF4 - X"00000000", -- 00002FF8 - X"00000000", -- 00002FFC - X"00000000", -- 00003000 - X"00000000", -- 00003004 - X"00000000", -- 00003008 - X"00000000", -- 0000300C - X"00000000", -- 00003010 - X"00000000", -- 00003014 - X"00000000", -- 00003018 - X"00000000", -- 0000301C - X"00000000", -- 00003020 - X"00000000", -- 00003024 - X"00000000", -- 00003028 - X"00000000", -- 0000302C - X"00000000", -- 00003030 - X"00000000", -- 00003034 - X"00000000", -- 00003038 - X"00000000", -- 0000303C - X"00000000", -- 00003040 - X"00000000", -- 00003044 - X"00000000", -- 00003048 - X"00000000", -- 0000304C - X"00000000", -- 00003050 - X"00000000", -- 00003054 - X"00000000", -- 00003058 - X"00000000", -- 0000305C - X"00000000", -- 00003060 - X"00000000", -- 00003064 - X"00000000", -- 00003068 - X"00000000", -- 0000306C - X"00000000", -- 00003070 - X"00000000", -- 00003074 - X"00000000", -- 00003078 - X"00000000", -- 0000307C - X"00000000", -- 00003080 - X"00000000", -- 00003084 - X"00000000", -- 00003088 - X"00000000", -- 0000308C - X"00000000", -- 00003090 - X"00000000", -- 00003094 - X"00000000", -- 00003098 - X"00000000", -- 0000309C - X"00000000", -- 000030A0 - X"00000000", -- 000030A4 - X"00000000", -- 000030A8 - X"00000000", -- 000030AC - X"00000000", -- 000030B0 - X"00000000", -- 000030B4 - X"00000000", -- 000030B8 - X"00000000", -- 000030BC - X"00000000", -- 000030C0 - X"00000000", -- 000030C4 - X"00000000", -- 000030C8 - X"00000000", -- 000030CC - X"00000000", -- 000030D0 - X"00000000", -- 000030D4 - X"00000000", -- 000030D8 - X"00000000", -- 000030DC - X"00000000", -- 000030E0 - X"00000000", -- 000030E4 - X"00000000", -- 000030E8 - X"00000000", -- 000030EC - X"00000000", -- 000030F0 - X"00000000", -- 000030F4 - X"00000000", -- 000030F8 - X"00000000", -- 000030FC - X"00000000", -- 00003100 - X"00000000", -- 00003104 - X"00000000", -- 00003108 - X"00000000", -- 0000310C - X"00000000", -- 00003110 - X"00000000", -- 00003114 - X"00000000", -- 00003118 - X"00000000", -- 0000311C - X"00000000", -- 00003120 - X"00000000", -- 00003124 - X"00000000", -- 00003128 - X"00000000", -- 0000312C - X"00000000", -- 00003130 - X"00000000", -- 00003134 - X"00000000", -- 00003138 - X"00000000", -- 0000313C - X"00000000", -- 00003140 - X"00000000", -- 00003144 - X"00000000", -- 00003148 - X"00000000", -- 0000314C - X"00000000", -- 00003150 - X"00000000", -- 00003154 - X"00000000", -- 00003158 - X"00000000", -- 0000315C - X"00000000", -- 00003160 - X"00000000", -- 00003164 - X"00000000", -- 00003168 - X"00000000", -- 0000316C - X"00000000", -- 00003170 - X"00000000", -- 00003174 - X"00000000", -- 00003178 - X"00000000", -- 0000317C - X"00000000", -- 00003180 - X"00000000", -- 00003184 - X"00000000", -- 00003188 - X"00000000", -- 0000318C - X"00000000", -- 00003190 - X"00000000", -- 00003194 - X"00000000", -- 00003198 - X"00000000", -- 0000319C - X"00000000", -- 000031A0 - X"00000000", -- 000031A4 - X"00000000", -- 000031A8 - X"00000000", -- 000031AC - X"00000000", -- 000031B0 - X"00000000", -- 000031B4 - X"00000000", -- 000031B8 - X"00000000", -- 000031BC - X"00000000", -- 000031C0 - X"00000000", -- 000031C4 - X"00000000", -- 000031C8 - X"00000000", -- 000031CC - X"00000000", -- 000031D0 - X"00000000", -- 000031D4 - X"00000000", -- 000031D8 - X"00000000", -- 000031DC - X"00000000", -- 000031E0 - X"00000000", -- 000031E4 - X"00000000", -- 000031E8 - X"00000000", -- 000031EC - X"00000000", -- 000031F0 - X"00000000", -- 000031F4 - X"00000000", -- 000031F8 - X"00000000", -- 000031FC - X"00000000", -- 00003200 - X"00000000", -- 00003204 - X"00000000", -- 00003208 - X"00000000", -- 0000320C - X"00000000", -- 00003210 - X"00000000", -- 00003214 - X"00000000", -- 00003218 - X"00000000", -- 0000321C - X"00000000", -- 00003220 - X"00000000", -- 00003224 - X"00000000", -- 00003228 - X"00000000", -- 0000322C - X"00000000", -- 00003230 - X"00000000", -- 00003234 - X"00000000", -- 00003238 - X"00000000", -- 0000323C - X"00000000", -- 00003240 - X"00000000", -- 00003244 - X"00000000", -- 00003248 - X"00000000", -- 0000324C - X"00000000", -- 00003250 - X"00000000", -- 00003254 - X"00000000", -- 00003258 - X"00000000", -- 0000325C - X"00000000", -- 00003260 - X"00000000", -- 00003264 - X"00000000", -- 00003268 - X"00000000", -- 0000326C - X"00000000", -- 00003270 - X"00000000", -- 00003274 - X"00000000", -- 00003278 - X"00000000", -- 0000327C - X"00000000", -- 00003280 - X"00000000", -- 00003284 - X"00000000", -- 00003288 - X"00000000", -- 0000328C - X"00000000", -- 00003290 - X"00000000", -- 00003294 - X"00000000", -- 00003298 - X"00000000", -- 0000329C - X"00000000", -- 000032A0 - X"00000000", -- 000032A4 - X"00000000", -- 000032A8 - X"00000000", -- 000032AC - X"00000000", -- 000032B0 - X"00000000", -- 000032B4 - X"00000000", -- 000032B8 - X"00000000", -- 000032BC - X"00000000", -- 000032C0 - X"00000000", -- 000032C4 - X"00000000", -- 000032C8 - X"00000000", -- 000032CC - X"00000000", -- 000032D0 - X"00000000", -- 000032D4 - X"00000000", -- 000032D8 - X"00000000", -- 000032DC - X"00000000", -- 000032E0 - X"00000000", -- 000032E4 - X"00000000", -- 000032E8 - X"00000000", -- 000032EC - X"00000000", -- 000032F0 - X"00000000", -- 000032F4 - X"00000000", -- 000032F8 - X"00000000", -- 000032FC - X"00000000", -- 00003300 - X"00000000", -- 00003304 - X"00000000", -- 00003308 - X"00000000", -- 0000330C - X"00000000", -- 00003310 - X"00000000", -- 00003314 - X"00000000", -- 00003318 - X"00000000", -- 0000331C - X"00000000", -- 00003320 - X"00000000", -- 00003324 - X"00000000", -- 00003328 - X"00000000", -- 0000332C - X"00000000", -- 00003330 - X"00000000", -- 00003334 - X"00000000", -- 00003338 - X"00000000", -- 0000333C - X"00000000", -- 00003340 - X"00000000", -- 00003344 - X"00000000", -- 00003348 - X"00000000", -- 0000334C - X"00000000", -- 00003350 - X"00000000", -- 00003354 - X"00000000", -- 00003358 - X"00000000", -- 0000335C - X"00000000", -- 00003360 - X"00000000", -- 00003364 - X"00000000", -- 00003368 - X"00000000", -- 0000336C - X"00000000", -- 00003370 - X"00000000", -- 00003374 - X"00000000", -- 00003378 - X"00000000", -- 0000337C - X"00000000", -- 00003380 - X"00000000", -- 00003384 - X"00000000", -- 00003388 - X"00000000", -- 0000338C - X"00000000", -- 00003390 - X"00000000", -- 00003394 - X"00000000", -- 00003398 - X"00000000", -- 0000339C - X"00000000", -- 000033A0 - X"00000000", -- 000033A4 - X"00000000", -- 000033A8 - X"00000000", -- 000033AC - X"00000000", -- 000033B0 - X"00000000", -- 000033B4 - X"00000000", -- 000033B8 - X"00000000", -- 000033BC - X"00000000", -- 000033C0 - X"00000000", -- 000033C4 - X"00000000", -- 000033C8 - X"00000000", -- 000033CC - X"00000000", -- 000033D0 - X"00000000", -- 000033D4 - X"00000000", -- 000033D8 - X"00000000", -- 000033DC - X"00000000", -- 000033E0 - X"00000000", -- 000033E4 - X"00000000", -- 000033E8 - X"00000000", -- 000033EC - X"00000000", -- 000033F0 - X"00000000", -- 000033F4 - X"00000000", -- 000033F8 - X"00000000", -- 000033FC - X"00000000", -- 00003400 - X"00000000", -- 00003404 - X"00000000", -- 00003408 - X"00000000", -- 0000340C - X"00000000", -- 00003410 - X"00000000", -- 00003414 - X"00000000", -- 00003418 - X"00000000", -- 0000341C - X"00000000", -- 00003420 - X"00000000", -- 00003424 - X"00000000", -- 00003428 - X"00000000", -- 0000342C - X"00000000", -- 00003430 - X"00000000", -- 00003434 - X"00000000", -- 00003438 - X"00000000", -- 0000343C - X"00000000", -- 00003440 - X"00000000", -- 00003444 - X"00000000", -- 00003448 - X"00000000", -- 0000344C - X"00000000", -- 00003450 - X"00000000", -- 00003454 - X"00000000", -- 00003458 - X"00000000", -- 0000345C - X"00000000", -- 00003460 - X"00000000", -- 00003464 - X"00000000", -- 00003468 - X"00000000", -- 0000346C - X"00000000", -- 00003470 - X"00000000", -- 00003474 - X"00000000", -- 00003478 - X"00000000", -- 0000347C - X"00000000", -- 00003480 - X"00000000", -- 00003484 - X"00000000", -- 00003488 - X"00000000", -- 0000348C - X"00000000", -- 00003490 - X"00000000", -- 00003494 - X"00000000", -- 00003498 - X"00000000", -- 0000349C - X"00000000", -- 000034A0 - X"00000000", -- 000034A4 - X"00000000", -- 000034A8 - X"00000000", -- 000034AC - X"00000000", -- 000034B0 - X"00000000", -- 000034B4 - X"00000000", -- 000034B8 - X"00000000", -- 000034BC - X"00000000", -- 000034C0 - X"00000000", -- 000034C4 - X"00000000", -- 000034C8 - X"00000000", -- 000034CC - X"00000000", -- 000034D0 - X"00000000", -- 000034D4 - X"00000000", -- 000034D8 - X"00000000", -- 000034DC - X"00000000", -- 000034E0 - X"00000000", -- 000034E4 - X"00000000", -- 000034E8 - X"00000000", -- 000034EC - X"00000000", -- 000034F0 - X"00000000", -- 000034F4 - X"00000000", -- 000034F8 - X"00000000", -- 000034FC - X"00000000", -- 00003500 - X"00000000", -- 00003504 - X"00000000", -- 00003508 - X"00000000", -- 0000350C - X"00000000", -- 00003510 - X"00000000", -- 00003514 - X"00000000", -- 00003518 - X"00000000", -- 0000351C - X"00000000", -- 00003520 - X"00000000", -- 00003524 - X"00000000", -- 00003528 - X"00000000", -- 0000352C - X"00000000", -- 00003530 - X"00000000", -- 00003534 - X"00000000", -- 00003538 - X"00000000", -- 0000353C - X"00000000", -- 00003540 - X"00000000", -- 00003544 - X"00000000", -- 00003548 - X"00000000", -- 0000354C - X"00000000", -- 00003550 - X"00000000", -- 00003554 - X"00000000", -- 00003558 - X"00000000", -- 0000355C - X"00000000", -- 00003560 - X"00000000", -- 00003564 - X"00000000", -- 00003568 - X"00000000", -- 0000356C - X"00000000", -- 00003570 - X"00000000", -- 00003574 - X"00000000", -- 00003578 - X"00000000", -- 0000357C - X"00000000", -- 00003580 - X"00000000", -- 00003584 - X"00000000", -- 00003588 - X"00000000", -- 0000358C - X"00000000", -- 00003590 - X"00000000", -- 00003594 - X"00000000", -- 00003598 - X"00000000", -- 0000359C - X"00000000", -- 000035A0 - X"00000000", -- 000035A4 - X"00000000", -- 000035A8 - X"00000000", -- 000035AC - X"00000000", -- 000035B0 - X"00000000", -- 000035B4 - X"00000000", -- 000035B8 - X"00000000", -- 000035BC - X"00000000", -- 000035C0 - X"00000000", -- 000035C4 - X"00000000", -- 000035C8 - X"00000000", -- 000035CC - X"00000000", -- 000035D0 - X"00000000", -- 000035D4 - X"00000000", -- 000035D8 - X"00000000", -- 000035DC - X"00000000", -- 000035E0 - X"00000000", -- 000035E4 - X"00000000", -- 000035E8 - X"00000000", -- 000035EC - X"00000000", -- 000035F0 - X"00000000", -- 000035F4 - X"00000000", -- 000035F8 - X"00000000", -- 000035FC - X"00000000", -- 00003600 - X"00000000", -- 00003604 - X"00000000", -- 00003608 - X"00000000", -- 0000360C - X"00000000", -- 00003610 - X"00000000", -- 00003614 - X"00000000", -- 00003618 - X"00000000", -- 0000361C - X"00000000", -- 00003620 - X"00000000", -- 00003624 - X"00000000", -- 00003628 - X"00000000", -- 0000362C - X"00000000", -- 00003630 - X"00000000", -- 00003634 - X"00000000", -- 00003638 - X"00000000", -- 0000363C - X"00000000", -- 00003640 - X"00000000", -- 00003644 - X"00000000", -- 00003648 - X"00000000", -- 0000364C - X"00000000", -- 00003650 - X"00000000", -- 00003654 - X"00000000", -- 00003658 - X"00000000", -- 0000365C - X"00000000", -- 00003660 - X"00000000", -- 00003664 - X"00000000", -- 00003668 - X"00000000", -- 0000366C - X"00000000", -- 00003670 - X"00000000", -- 00003674 - X"00000000", -- 00003678 - X"00000000", -- 0000367C - X"00000000", -- 00003680 - X"00000000", -- 00003684 - X"00000000", -- 00003688 - X"00000000", -- 0000368C - X"00000000", -- 00003690 - X"00000000", -- 00003694 - X"00000000", -- 00003698 - X"00000000", -- 0000369C - X"00000000", -- 000036A0 - X"00000000", -- 000036A4 - X"00000000", -- 000036A8 - X"00000000", -- 000036AC - X"00000000", -- 000036B0 - X"00000000", -- 000036B4 - X"00000000", -- 000036B8 - X"00000000", -- 000036BC - X"00000000", -- 000036C0 - X"00000000", -- 000036C4 - X"00000000", -- 000036C8 - X"00000000", -- 000036CC - X"00000000", -- 000036D0 - X"00000000", -- 000036D4 - X"00000000", -- 000036D8 - X"00000000", -- 000036DC - X"00000000", -- 000036E0 - X"00000000", -- 000036E4 - X"00000000", -- 000036E8 - X"00000000", -- 000036EC - X"00000000", -- 000036F0 - X"00000000", -- 000036F4 - X"00000000", -- 000036F8 - X"00000000", -- 000036FC - X"00000000", -- 00003700 - X"00000000", -- 00003704 - X"00000000", -- 00003708 - X"00000000", -- 0000370C - X"00000000", -- 00003710 - X"00000000", -- 00003714 - X"00000000", -- 00003718 - X"00000000", -- 0000371C - X"00000000", -- 00003720 - X"00000000", -- 00003724 - X"00000000", -- 00003728 - X"00000000", -- 0000372C - X"00000000", -- 00003730 - X"00000000", -- 00003734 - X"00000000", -- 00003738 - X"00000000", -- 0000373C - X"00000000", -- 00003740 - X"00000000", -- 00003744 - X"00000000", -- 00003748 - X"00000000", -- 0000374C - X"00000000", -- 00003750 - X"00000000", -- 00003754 - X"00000000", -- 00003758 - X"00000000", -- 0000375C - X"00000000", -- 00003760 - X"00000000", -- 00003764 - X"00000000", -- 00003768 - X"00000000", -- 0000376C - X"00000000", -- 00003770 - X"00000000", -- 00003774 - X"00000000", -- 00003778 - X"00000000", -- 0000377C - X"00000000", -- 00003780 - X"00000000", -- 00003784 - X"00000000", -- 00003788 - X"00000000", -- 0000378C - X"00000000", -- 00003790 - X"00000000", -- 00003794 - X"00000000", -- 00003798 - X"00000000", -- 0000379C - X"00000000", -- 000037A0 - X"00000000", -- 000037A4 - X"00000000", -- 000037A8 - X"00000000", -- 000037AC - X"00000000", -- 000037B0 - X"00000000", -- 000037B4 - X"00000000", -- 000037B8 - X"00000000", -- 000037BC - X"00000000", -- 000037C0 - X"00000000", -- 000037C4 - X"00000000", -- 000037C8 - X"00000000", -- 000037CC - X"00000000", -- 000037D0 - X"00000000", -- 000037D4 - X"00000000", -- 000037D8 - X"00000000", -- 000037DC - X"00000000", -- 000037E0 - X"00000000", -- 000037E4 - X"00000000", -- 000037E8 - X"00000000", -- 000037EC - X"00000000", -- 000037F0 - X"00000000", -- 000037F4 - X"00000000", -- 000037F8 - X"00000000", -- 000037FC - X"00000000", -- 00003800 - X"00000000", -- 00003804 - X"00000000", -- 00003808 - X"00000000", -- 0000380C - X"00000000", -- 00003810 - X"00000000", -- 00003814 - X"00000000", -- 00003818 - X"00000000", -- 0000381C - X"00000000", -- 00003820 - X"00000000", -- 00003824 - X"00000000", -- 00003828 - X"00000000", -- 0000382C - X"00000000", -- 00003830 - X"00000000", -- 00003834 - X"00000000", -- 00003838 - X"00000000", -- 0000383C - X"00000000", -- 00003840 - X"00000000", -- 00003844 - X"00000000", -- 00003848 - X"00000000", -- 0000384C - X"00000000", -- 00003850 - X"00000000", -- 00003854 - X"00000000", -- 00003858 - X"00000000", -- 0000385C - X"00000000", -- 00003860 - X"00000000", -- 00003864 - X"00000000", -- 00003868 - X"00000000", -- 0000386C - X"00000000", -- 00003870 - X"00000000", -- 00003874 - X"00000000", -- 00003878 - X"00000000", -- 0000387C - X"00000000", -- 00003880 - X"00000000", -- 00003884 - X"00000000", -- 00003888 - X"00000000", -- 0000388C - X"00000000", -- 00003890 - X"00000000", -- 00003894 - X"00000000", -- 00003898 - X"00000000", -- 0000389C - X"00000000", -- 000038A0 - X"00000000", -- 000038A4 - X"00000000", -- 000038A8 - X"00000000", -- 000038AC - X"00000000", -- 000038B0 - X"00000000", -- 000038B4 - X"00000000", -- 000038B8 - X"00000000", -- 000038BC - X"00000000", -- 000038C0 - X"00000000", -- 000038C4 - X"00000000", -- 000038C8 - X"00000000", -- 000038CC - X"00000000", -- 000038D0 - X"00000000", -- 000038D4 - X"00000000", -- 000038D8 - X"00000000", -- 000038DC - X"00000000", -- 000038E0 - X"00000000", -- 000038E4 - X"00000000", -- 000038E8 - X"00000000", -- 000038EC - X"00000000", -- 000038F0 - X"00000000", -- 000038F4 - X"00000000", -- 000038F8 - X"00000000", -- 000038FC - X"00000000", -- 00003900 - X"00000000", -- 00003904 - X"00000000", -- 00003908 - X"00000000", -- 0000390C - X"00000000", -- 00003910 - X"00000000", -- 00003914 - X"00000000", -- 00003918 - X"00000000", -- 0000391C - X"00000000", -- 00003920 - X"00000000", -- 00003924 - X"00000000", -- 00003928 - X"00000000", -- 0000392C - X"00000000", -- 00003930 - X"00000000", -- 00003934 - X"00000000", -- 00003938 - X"00000000", -- 0000393C - X"00000000", -- 00003940 - X"00000000", -- 00003944 - X"00000000", -- 00003948 - X"00000000", -- 0000394C - X"00000000", -- 00003950 - X"00000000", -- 00003954 - X"00000000", -- 00003958 - X"00000000", -- 0000395C - X"00000000", -- 00003960 - X"00000000", -- 00003964 - X"00000000", -- 00003968 - X"00000000", -- 0000396C - X"00000000", -- 00003970 - X"00000000", -- 00003974 - X"00000000", -- 00003978 - X"00000000", -- 0000397C - X"00000000", -- 00003980 - X"00000000", -- 00003984 - X"00000000", -- 00003988 - X"00000000", -- 0000398C - X"00000000", -- 00003990 - X"00000000", -- 00003994 - X"00000000", -- 00003998 - X"00000000", -- 0000399C - X"00000000", -- 000039A0 - X"00000000", -- 000039A4 - X"00000000", -- 000039A8 - X"00000000", -- 000039AC - X"00000000", -- 000039B0 - X"00000000", -- 000039B4 - X"00000000", -- 000039B8 - X"00000000", -- 000039BC - X"00000000", -- 000039C0 - X"00000000", -- 000039C4 - X"00000000", -- 000039C8 - X"00000000", -- 000039CC - X"00000000", -- 000039D0 - X"00000000", -- 000039D4 - X"00000000", -- 000039D8 - X"00000000", -- 000039DC - X"00000000", -- 000039E0 - X"00000000", -- 000039E4 - X"00000000", -- 000039E8 - X"00000000", -- 000039EC - X"00000000", -- 000039F0 - X"00000000", -- 000039F4 - X"00000000", -- 000039F8 - X"00000000", -- 000039FC - X"00000000", -- 00003A00 - X"00000000", -- 00003A04 - X"00000000", -- 00003A08 - X"00000000", -- 00003A0C - X"00000000", -- 00003A10 - X"00000000", -- 00003A14 - X"00000000", -- 00003A18 - X"00000000", -- 00003A1C - X"00000000", -- 00003A20 - X"00000000", -- 00003A24 - X"00000000", -- 00003A28 - X"00000000", -- 00003A2C - X"00000000", -- 00003A30 - X"00000000", -- 00003A34 - X"00000000", -- 00003A38 - X"00000000", -- 00003A3C - X"00000000", -- 00003A40 - X"00000000", -- 00003A44 - X"00000000", -- 00003A48 - X"00000000", -- 00003A4C - X"00000000", -- 00003A50 - X"00000000", -- 00003A54 - X"00000000", -- 00003A58 - X"00000000", -- 00003A5C - X"00000000", -- 00003A60 - X"00000000", -- 00003A64 - X"00000000", -- 00003A68 - X"00000000", -- 00003A6C - X"00000000", -- 00003A70 - X"00000000", -- 00003A74 - X"00000000", -- 00003A78 - X"00000000", -- 00003A7C - X"00000000", -- 00003A80 - X"00000000", -- 00003A84 - X"00000000", -- 00003A88 - X"00000000", -- 00003A8C - X"00000000", -- 00003A90 - X"00000000", -- 00003A94 - X"00000000", -- 00003A98 - X"00000000", -- 00003A9C - X"00000000", -- 00003AA0 - X"00000000", -- 00003AA4 - X"00000000", -- 00003AA8 - X"00000000", -- 00003AAC - X"00000000", -- 00003AB0 - X"00000000", -- 00003AB4 - X"00000000", -- 00003AB8 - X"00000000", -- 00003ABC - X"00000000", -- 00003AC0 - X"00000000", -- 00003AC4 - X"00000000", -- 00003AC8 - X"00000000", -- 00003ACC - X"00000000", -- 00003AD0 - X"00000000", -- 00003AD4 - X"00000000", -- 00003AD8 - X"00000000", -- 00003ADC - X"00000000", -- 00003AE0 - X"00000000", -- 00003AE4 - X"00000000", -- 00003AE8 - X"00000000", -- 00003AEC - X"00000000", -- 00003AF0 - X"00000000", -- 00003AF4 - X"00000000", -- 00003AF8 - X"00000000", -- 00003AFC - X"00000000", -- 00003B00 - X"00000000", -- 00003B04 - X"00000000", -- 00003B08 - X"00000000", -- 00003B0C - X"00000000", -- 00003B10 - X"00000000", -- 00003B14 - X"00000000", -- 00003B18 - X"00000000", -- 00003B1C - X"00000000", -- 00003B20 - X"00000000", -- 00003B24 - X"00000000", -- 00003B28 - X"00000000", -- 00003B2C - X"00000000", -- 00003B30 - X"00000000", -- 00003B34 - X"00000000", -- 00003B38 - X"00000000", -- 00003B3C - X"00000000", -- 00003B40 - X"00000000", -- 00003B44 - X"00000000", -- 00003B48 - X"00000000", -- 00003B4C - X"00000000", -- 00003B50 - X"00000000", -- 00003B54 - X"00000000", -- 00003B58 - X"00000000", -- 00003B5C - X"00000000", -- 00003B60 - X"00000000", -- 00003B64 - X"00000000", -- 00003B68 - X"00000000", -- 00003B6C - X"00000000", -- 00003B70 - X"00000000", -- 00003B74 - X"00000000", -- 00003B78 - X"00000000", -- 00003B7C - X"00000000", -- 00003B80 - X"00000000", -- 00003B84 - X"00000000", -- 00003B88 - X"00000000", -- 00003B8C - X"00000000", -- 00003B90 - X"00000000", -- 00003B94 - X"00000000", -- 00003B98 - X"00000000", -- 00003B9C - X"00000000", -- 00003BA0 - X"00000000", -- 00003BA4 - X"00000000", -- 00003BA8 - X"00000000", -- 00003BAC - X"00000000", -- 00003BB0 - X"00000000", -- 00003BB4 - X"00000000", -- 00003BB8 - X"00000000", -- 00003BBC - X"00000000", -- 00003BC0 - X"00000000", -- 00003BC4 - X"00000000", -- 00003BC8 - X"00000000", -- 00003BCC - X"00000000", -- 00003BD0 - X"00000000", -- 00003BD4 - X"00000000", -- 00003BD8 - X"00000000", -- 00003BDC - X"00000000", -- 00003BE0 - X"00000000", -- 00003BE4 - X"00000000", -- 00003BE8 - X"00000000", -- 00003BEC - X"00000000", -- 00003BF0 - X"00000000", -- 00003BF4 - X"00000000", -- 00003BF8 - X"00000000", -- 00003BFC - X"00000000", -- 00003C00 - X"00000000", -- 00003C04 - X"00000000", -- 00003C08 - X"00000000", -- 00003C0C - X"00000000", -- 00003C10 - X"00000000", -- 00003C14 - X"00000000", -- 00003C18 - X"00000000", -- 00003C1C - X"00000000", -- 00003C20 - X"00000000", -- 00003C24 - X"00000000", -- 00003C28 - X"00000000", -- 00003C2C - X"00000000", -- 00003C30 - X"00000000", -- 00003C34 - X"00000000", -- 00003C38 - X"00000000", -- 00003C3C - X"00000000", -- 00003C40 - X"00000000", -- 00003C44 - X"00000000", -- 00003C48 - X"00000000", -- 00003C4C - X"00000000", -- 00003C50 - X"00000000", -- 00003C54 - X"00000000", -- 00003C58 - X"00000000", -- 00003C5C - X"00000000", -- 00003C60 - X"00000000", -- 00003C64 - X"00000000", -- 00003C68 - X"00000000", -- 00003C6C - X"00000000", -- 00003C70 - X"00000000", -- 00003C74 - X"00000000", -- 00003C78 - X"00000000", -- 00003C7C - X"00000000", -- 00003C80 - X"00000000", -- 00003C84 - X"00000000", -- 00003C88 - X"00000000", -- 00003C8C - X"00000000", -- 00003C90 - X"00000000", -- 00003C94 - X"00000000", -- 00003C98 - X"00000000", -- 00003C9C - X"00000000", -- 00003CA0 - X"00000000", -- 00003CA4 - X"00000000", -- 00003CA8 - X"00000000", -- 00003CAC - X"00000000", -- 00003CB0 - X"00000000", -- 00003CB4 - X"00000000", -- 00003CB8 - X"00000000", -- 00003CBC - X"00000000", -- 00003CC0 - X"00000000", -- 00003CC4 - X"00000000", -- 00003CC8 - X"00000000", -- 00003CCC - X"00000000", -- 00003CD0 - X"00000000", -- 00003CD4 - X"00000000", -- 00003CD8 - X"00000000", -- 00003CDC - X"00000000", -- 00003CE0 - X"00000000", -- 00003CE4 - X"00000000", -- 00003CE8 - X"00000000", -- 00003CEC - X"00000000", -- 00003CF0 - X"00000000", -- 00003CF4 - X"00000000", -- 00003CF8 - X"00000000", -- 00003CFC - X"00000000", -- 00003D00 - X"00000000", -- 00003D04 - X"00000000", -- 00003D08 - X"00000000", -- 00003D0C - X"00000000", -- 00003D10 - X"00000000", -- 00003D14 - X"00000000", -- 00003D18 - X"00000000", -- 00003D1C - X"00000000", -- 00003D20 - X"00000000", -- 00003D24 - X"00000000", -- 00003D28 - X"00000000", -- 00003D2C - X"00000000", -- 00003D30 - X"00000000", -- 00003D34 - X"00000000", -- 00003D38 - X"00000000", -- 00003D3C - X"00000000", -- 00003D40 - X"00000000", -- 00003D44 - X"00000000", -- 00003D48 - X"00000000", -- 00003D4C - X"00000000", -- 00003D50 - X"00000000", -- 00003D54 - X"00000000", -- 00003D58 - X"00000000", -- 00003D5C - X"00000000", -- 00003D60 - X"00000000", -- 00003D64 - X"00000000", -- 00003D68 - X"00000000", -- 00003D6C - X"00000000", -- 00003D70 - X"00000000", -- 00003D74 - X"00000000", -- 00003D78 - X"00000000", -- 00003D7C - X"00000000", -- 00003D80 - X"00000000", -- 00003D84 - X"00000000", -- 00003D88 - X"00000000", -- 00003D8C - X"00000000", -- 00003D90 - X"00000000", -- 00003D94 - X"00000000", -- 00003D98 - X"00000000", -- 00003D9C - X"00000000", -- 00003DA0 - X"00000000", -- 00003DA4 - X"00000000", -- 00003DA8 - X"00000000", -- 00003DAC - X"00000000", -- 00003DB0 - X"00000000", -- 00003DB4 - X"00000000", -- 00003DB8 - X"00000000", -- 00003DBC - X"00000000", -- 00003DC0 - X"00000000", -- 00003DC4 - X"00000000", -- 00003DC8 - X"00000000", -- 00003DCC - X"00000000", -- 00003DD0 - X"00000000", -- 00003DD4 - X"00000000", -- 00003DD8 - X"00000000", -- 00003DDC - X"00000000", -- 00003DE0 - X"00000000", -- 00003DE4 - X"00000000", -- 00003DE8 - X"00000000", -- 00003DEC - X"00000000", -- 00003DF0 - X"00000000", -- 00003DF4 - X"00000000", -- 00003DF8 - X"00000000", -- 00003DFC - X"00000000", -- 00003E00 - X"00000000", -- 00003E04 - X"00000000", -- 00003E08 - X"00000000", -- 00003E0C - X"00000000", -- 00003E10 - X"00000000", -- 00003E14 - X"00000000", -- 00003E18 - X"00000000", -- 00003E1C - X"00000000", -- 00003E20 - X"00000000", -- 00003E24 - X"00000000", -- 00003E28 - X"00000000", -- 00003E2C - X"00000000", -- 00003E30 - X"00000000", -- 00003E34 - X"00000000", -- 00003E38 - X"00000000", -- 00003E3C - X"00000000", -- 00003E40 - X"00000000", -- 00003E44 - X"00000000", -- 00003E48 - X"00000000", -- 00003E4C - X"00000000", -- 00003E50 - X"00000000", -- 00003E54 - X"00000000", -- 00003E58 - X"00000000", -- 00003E5C - X"00000000", -- 00003E60 - X"00000000", -- 00003E64 - X"00000000", -- 00003E68 - X"00000000", -- 00003E6C - X"00000000", -- 00003E70 - X"00000000", -- 00003E74 - X"00000000", -- 00003E78 - X"00000000", -- 00003E7C - X"00000000", -- 00003E80 - X"00000000", -- 00003E84 - X"00000000", -- 00003E88 - X"00000000", -- 00003E8C - X"00000000", -- 00003E90 - X"00000000", -- 00003E94 - X"00000000", -- 00003E98 - X"00000000", -- 00003E9C - X"00000000", -- 00003EA0 - X"00000000", -- 00003EA4 - X"00000000", -- 00003EA8 - X"00000000", -- 00003EAC - X"00000000", -- 00003EB0 - X"00000000", -- 00003EB4 - X"00000000", -- 00003EB8 - X"00000000", -- 00003EBC - X"00000000", -- 00003EC0 - X"00000000", -- 00003EC4 - X"00000000", -- 00003EC8 - X"00000000", -- 00003ECC - X"00000000", -- 00003ED0 - X"00000000", -- 00003ED4 - X"00000000", -- 00003ED8 - X"00000000", -- 00003EDC - X"00000000", -- 00003EE0 - X"00000000", -- 00003EE4 - X"00000000", -- 00003EE8 - X"00000000", -- 00003EEC - X"00000000", -- 00003EF0 - X"00000000", -- 00003EF4 - X"00000000", -- 00003EF8 - X"00000000", -- 00003EFC - X"00000000", -- 00003F00 - X"00000000", -- 00003F04 - X"00000000", -- 00003F08 - X"00000000", -- 00003F0C - X"00000000", -- 00003F10 - X"00000000", -- 00003F14 - X"00000000", -- 00003F18 - X"00000000", -- 00003F1C - X"00000000", -- 00003F20 - X"00000000", -- 00003F24 - X"00000000", -- 00003F28 - X"00000000", -- 00003F2C - X"00000000", -- 00003F30 - X"00000000", -- 00003F34 - X"00000000", -- 00003F38 - X"00000000", -- 00003F3C - X"00000000", -- 00003F40 - X"00000000", -- 00003F44 - X"00000000", -- 00003F48 - X"00000000", -- 00003F4C - X"00000000", -- 00003F50 - X"00000000", -- 00003F54 - X"00000000", -- 00003F58 - X"00000000", -- 00003F5C - X"00000000", -- 00003F60 - X"00000000", -- 00003F64 - X"00000000", -- 00003F68 - X"00000000", -- 00003F6C - X"00000000", -- 00003F70 - X"00000000", -- 00003F74 - X"00000000", -- 00003F78 - X"00000000", -- 00003F7C - X"00000000", -- 00003F80 - X"00000000", -- 00003F84 - X"00000000", -- 00003F88 - X"00000000", -- 00003F8C - X"00000000", -- 00003F90 - X"00000000", -- 00003F94 - X"00000000", -- 00003F98 - X"00000000", -- 00003F9C - X"00000000", -- 00003FA0 - X"00000000", -- 00003FA4 - X"00000000", -- 00003FA8 - X"00000000", -- 00003FAC - X"00000000", -- 00003FB0 - X"00000000", -- 00003FB4 - X"00000000", -- 00003FB8 - X"00000000", -- 00003FBC - X"00000000", -- 00003FC0 - X"00000000", -- 00003FC4 - X"00000000", -- 00003FC8 - X"00000000", -- 00003FCC - X"00000000", -- 00003FD0 - X"00000000", -- 00003FD4 - X"00000000", -- 00003FD8 - X"00000000", -- 00003FDC - X"00000000", -- 00003FE0 - X"00000000", -- 00003FE4 - X"00000000", -- 00003FE8 - X"00000000", -- 00003FEC - X"00000000", -- 00003FF0 - X"00000000", -- 00003FF4 - X"00000000", -- 00003FF8 - X"00000000" -- 00003FFC - ); - -begin - -PROM_READ: - process(clk) - begin - if rising_edge(clk) and ce = '1' then - dout <= word_array(to_integer(addr(13 downto 2))); - end if; - end process; - - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length); - jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout; - - end if; - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - word_array(to_integer(jtag_ld_addr(11 downto 0))) <= jtag_ld_din; - else - jtag_ld_dout <= word_array(to_integer(jtag_ld_addr(11 downto 0))); - end if; - end if; - end process; - -end data; diff --git a/lib/CPUs/MIPS/tools/insrom.rb b/lib/CPUs/MIPS/tools/insrom.rb deleted file mode 100644 index fdbf1ed..0000000 --- a/lib/CPUs/MIPS/tools/insrom.rb +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env ruby - -# ---------------------------------------------------------------------- -# Project: JIPS, a portable 32-bit RISC CPU written in VHDL -# This file: Insertion of code fragments into templates -# -# Copyright (C) 2008 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -arg = $* -rom_filename = arg[0].to_s -tpl_filename = arg[1].to_s - -subst_pattern = "ROM_INSERT_HERE" - -# -------------------------------------------------------- -# Open file -# -------------------------------------------------------- -romfile = File.open(rom_filename, "r") -tplfile = File.open(tpl_filename, "r") -re = Regexp.new(subst_pattern) - -while (line = tplfile.gets) - puts line - line.scan(re).each do |word| - romfile.each do |raw_line| - puts raw_line - end - end -end diff --git a/lib/CPUs/MIPS/tools/irom.vhd.tpl b/lib/CPUs/MIPS/tools/irom.vhd.tpl deleted file mode 100644 index 5ffd6d7..0000000 --- a/lib/CPUs/MIPS/tools/irom.vhd.tpl +++ /dev/null @@ -1,29 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - --- ROM_INSERT_HERE - diff --git a/lib/CPUs/MIPS/tools/irom_ld.vhd.tpl b/lib/CPUs/MIPS/tools/irom_ld.vhd.tpl deleted file mode 100644 index 3bd3afb..0000000 --- a/lib/CPUs/MIPS/tools/irom_ld.vhd.tpl +++ /dev/null @@ -1,147 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : unsigned (15 downto 0); - signal jtag_ld_dout : unsigned (31 downto 0); - signal jtag_ld_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length); - jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk) - begin - if rising_edge(clk) then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/MIPS/tools/make b/lib/CPUs/MIPS/tools/make deleted file mode 100644 index cb50a10..0000000 --- a/lib/CPUs/MIPS/tools/make +++ /dev/null @@ -1,51 +0,0 @@ -#!/bin/sh - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: rom-file generation for cpu_core -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- -# $Header: /tmp/cvsroot/VHDL/lib/CPUs/MIPS/tools/make,v 1.3 2008-08-23 07:37:52 Jens Exp $ -# ---------------------------------------------------------------------- -TARGET=$2 -DSTDIR=$1 - -JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools - -$JASM_HOME/jasm.rb $TARGET.jsm - -irom_tcl_snippet="$TARGET.irom.tcl.snip" -irom_vhdl_snippet="$TARGET.irom.vhdl.snip" -irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip" -xrom_tcl_snippet="$TARGET.xrom.tcl.snip" -xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip" -xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip" - -$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl -$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl - -$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl -$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl - -cat $irom_tcl_snippet > $TARGET.tcl.snip.snip -cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip -$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl - -rm -f *.snip diff --git a/lib/CPUs/MIPS/tools/rom.tcl.tpl b/lib/CPUs/MIPS/tools/rom.tcl.tpl deleted file mode 100644 index 9f5c0dc..0000000 --- a/lib/CPUs/MIPS/tools/rom.tcl.tpl +++ /dev/null @@ -1,61 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/MIPS/tools/src/ramgen.c b/lib/CPUs/MIPS/tools/src/ramgen.c deleted file mode 100644 index a266e35..0000000 --- a/lib/CPUs/MIPS/tools/src/ramgen.c +++ /dev/null @@ -1,125 +0,0 @@ -#include -#include -#include -#include - -#define ARCH_NAME "data" -#define ENT_NAME "ram" -#define JTAG_ADDR_WIDTH 16 - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, word_addr, filesize, romsize; - char binstr_addr[33]; - char binstr_data[33]; - - char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fputs(tpl, pFileOut); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); - fprintf(pFileOut, "# ---------------------------------------------------------------\n"); - fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n"); - fprintf(pFileOut, "# User 2\n"); - fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n"); - - word_addr = 0; - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); - word_addr++; - } - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); - fprintf(pFileOut, "exit\n"); - - return 0; -} - -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_prj[1024]; - char name_rom_tcl[1024]; - - FILE *pFileIn; - int filesize, romsize, nbits_addr, nbits_data; - long start, end; - int word, i; - - if (argc < 2) - { - fprintf(stderr, "Usage: romgen \n"); - return 1; - } - - pFilenameIn = argv[1]; - if (argc == 3) - nbits_addr = atoi(argv[2]); - - - basename(pFilenameIn, name_prj); - sprintf(name_rom_tcl, "%s.tcl", name_prj); - - SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); - - - return 0; -} - diff --git a/lib/CPUs/MIPS/tools/src/romgen.c b/lib/CPUs/MIPS/tools/src/romgen.c deleted file mode 100644 index 6d1ec5f..0000000 --- a/lib/CPUs/MIPS/tools/src/romgen.c +++ /dev/null @@ -1,368 +0,0 @@ -#include -#include -#include -#include - -#define ARCH_NAME "data" -#define ENT_NAME "icache" -#define JTAG_ADDR_WIDTH 16 - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "begin\n", ARCH_NAME); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - - return 0; -} - -int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "library UNISIM;\n"); - fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); - fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); - fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); - fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "begin\n", ARCH_NAME); - - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "\n"); - fputs(tpl, pFileOut); - - fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); - fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\telse\n"); - fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - return 0; -} - -int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, word_addr, filesize, romsize; - char binstr_addr[33]; - char binstr_data[33]; - - char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fputs(tpl, pFileOut); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); - fprintf(pFileOut, "# ---------------------------------------------------------------\n"); - fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n"); - fprintf(pFileOut, "# User 1\n"); - fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n"); - - word_addr = 0; - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); - word_addr++; - } - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); - fprintf(pFileOut, "exit\n"); - - return 0; -} - -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_prj[1024]; - char name_rom[1024]; - char name_rom_v4ld[1024]; - char name_rom_tcl[1024]; - - FILE *pFileIn; - int filesize, romsize, nbits_addr, nbits_data; - long start, end; - int word, i; - - if (argc < 2) - { - fprintf(stderr, "Usage: romgen \n"); - return 1; - } - - pFilenameIn = argv[1]; - if (argc == 3) - nbits_addr = atoi(argv[2]); - - - basename(pFilenameIn, name_prj); - sprintf(name_rom, "%s.vhd", name_prj); - sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); - sprintf(name_rom_tcl, "%s.tcl", name_prj); - - SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); - - - return 0; -} - diff --git a/lib/FIFO/sim/tb_async_fifo_ctrl.fdo b/lib/FIFO/sim/tb_async_fifo_ctrl.fdo deleted file mode 100644 index cfa76ee..0000000 --- a/lib/FIFO/sim/tb_async_fifo_ctrl.fdo +++ /dev/null @@ -1,15 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../src/gray_counter.vhd" -vcom -explicit -93 "../src/dpram.vhd" -vcom -explicit -93 "../src/async_fifo_ctrl.vhd" -vcom -explicit -93 "../src/tb_async_fifo_ctrl.vhd" -vsim -t 1ps -lib work tb_async_fifo_ctrl -view wave -do {tb_async_fifo_ctrl.wdo} -view structure -view signals - -run 10us diff --git a/lib/FIFO/sim/tb_async_fifo_ctrl.wdo b/lib/FIFO/sim/tb_async_fifo_ctrl.wdo deleted file mode 100644 index 8f23edb..0000000 --- a/lib/FIFO/sim/tb_async_fifo_ctrl.wdo +++ /dev/null @@ -1,36 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_async_fifo_ctrl/rst -add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_w -add wave -noupdate -format Logic /tb_async_fifo_ctrl/we -add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_w -add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_r -add wave -noupdate -format Logic /tb_async_fifo_ctrl/re -add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_r -add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_empty -add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_empty -add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_full -add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_full -add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/din -add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/dout -add wave -noupdate -format Logic /tb_async_fifo_ctrl/uut/inst_gray_counter_w/ce -add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/uut/bnxt_w -add wave -noupdate -format Literal /tb_async_fifo_ctrl/uut/bcnt_r -add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffw -add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {250000 ps} 0} -configure wave -namecolwidth 190 -configure wave -valuecolwidth 80 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {115874 ps} {612358 ps} diff --git a/lib/FIFO/sim/tb_gray_counter.fdo b/lib/FIFO/sim/tb_gray_counter.fdo deleted file mode 100644 index b619f71..0000000 --- a/lib/FIFO/sim/tb_gray_counter.fdo +++ /dev/null @@ -1,13 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../src/gray_counter.vhd" -vcom -explicit -93 "../src/tb_gray_counter.vhd" -vsim -t 1ps -lib work tb_gray_counter -view wave -do {tb_gray_counter.wdo} -view structure -view signals - -run 1us diff --git a/lib/FIFO/sim/tb_gray_counter.wdo b/lib/FIFO/sim/tb_gray_counter.wdo deleted file mode 100644 index b33112f..0000000 --- a/lib/FIFO/sim/tb_gray_counter.wdo +++ /dev/null @@ -1,25 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_gray_counter/rst -add wave -noupdate -format Logic /tb_gray_counter/ce -add wave -noupdate -format Logic /tb_gray_counter/clk -add wave -noupdate -format Literal /tb_gray_counter/bcnt -add wave -noupdate -format Literal /tb_gray_counter/bnxt -add wave -noupdate -format Literal /tb_gray_counter/gcnt -add wave -noupdate -format Literal /tb_gray_counter/gnxt -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {20898 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {134759 ps} diff --git a/lib/FIFO/sim/tb_sync_fifo_ctrl.fdo b/lib/FIFO/sim/tb_sync_fifo_ctrl.fdo deleted file mode 100644 index fff4902..0000000 --- a/lib/FIFO/sim/tb_sync_fifo_ctrl.fdo +++ /dev/null @@ -1,15 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../src/gray_counter.vhd" -vcom -explicit -93 "../src/dpram.vhd" -vcom -explicit -93 "../src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../src/tb_sync_fifo_ctrl.vhd" -vsim -t 1ps -lib work tb_sync_fifo_ctrl -view wave -do {tb_sync_fifo_ctrl.wdo} -view structure -view signals - -run 10us diff --git a/lib/FIFO/sim/tb_sync_fifo_ctrl.wdo b/lib/FIFO/sim/tb_sync_fifo_ctrl.wdo deleted file mode 100644 index 8821953..0000000 --- a/lib/FIFO/sim/tb_sync_fifo_ctrl.wdo +++ /dev/null @@ -1,32 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_sync_fifo_ctrl/rst -add wave -noupdate -format Logic /tb_sync_fifo_ctrl/we -add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_w -add wave -noupdate -format Logic /tb_sync_fifo_ctrl/re -add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_r -add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_empty -add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_empty -add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_full -add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_full -add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/din -add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/dout -add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pw_next -add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pr_next -add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/diff -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {290000 ps} 0} -configure wave -namecolwidth 190 -configure wave -valuecolwidth 80 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {2166667 ps} diff --git a/lib/FIFO/src/async_fifo_ctrl.vhd b/lib/FIFO/src/async_fifo_ctrl.vhd deleted file mode 100644 index 90fe9be..0000000 --- a/lib/FIFO/src/async_fifo_ctrl.vhd +++ /dev/null @@ -1,244 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The call/return/data stack - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -LIBRARY WORK; -USE WORK.FIFO_CTRL_PKG.ALL; - -entity async_fifo_ctrl is - Generic ( - addr_width : integer := 3; - almost_full_thresh : integer := 6; - almost_empty_thresh : integer := 2 - ); - Port - ( - rst : in STD_LOGIC; - clk_w : in STD_LOGIC; - clk_r : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - ptr_w : out unsigned (addr_width-1 downto 0); - ptr_r : out unsigned (addr_width-1 downto 0); - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC - ); -end async_fifo_ctrl; - -architecture Behavioral of async_fifo_ctrl is - - signal gcnt_w : unsigned (addr_width downto 0); - signal gcnt2_w : unsigned (addr_width downto 0); - signal bcnt2_aw : unsigned (addr_width downto 0); - signal bcnt_w : unsigned (addr_width downto 0); - signal gnxt_w : unsigned (addr_width downto 0); - signal bnxt_w : unsigned (addr_width downto 0); - signal gcnt_r : unsigned (addr_width downto 0); - signal gcnt2_r : unsigned (addr_width downto 0); - signal bcnt2_ar : unsigned (addr_width downto 0); - signal bcnt_r : unsigned (addr_width downto 0); - signal gnxt_r : unsigned (addr_width downto 0); - signal bnxt_r : unsigned (addr_width downto 0); - - signal empty, full : std_logic; - signal write_inhibit, read_inhibit : std_logic; - signal winc, rinc : std_logic; - - -- synthesis translate_off - signal diffw : signed (addr_width downto 0); - signal diffr : signed (addr_width downto 0); - -- synthesis translate_on - -begin - - ptr_w <= bcnt_w(addr_width-1 downto 0); - ptr_r <= bcnt_r(addr_width-1 downto 0); - winc <= we and (not write_inhibit); - rinc <= re and (not read_inhibit); - fifo_full <= write_inhibit; - fifo_empty <= read_inhibit; - -proc_write_inhibit: - process(rst, clk_w) - begin - if rst = '1' then - write_inhibit <= '0'; - elsif rising_edge(clk_w) then - write_inhibit <= full; - end if; - end process; - -proc_read_inhibit: - process(rst, clk_r) - begin - if rst = '1' then - read_inhibit <= '1'; - elsif rising_edge(clk_r) then - read_inhibit <= empty; - end if; - end process; - -proc_sync_grptr: - process(clk_w) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_w) then - gcnt2_r <= p2; - p2 := p1; - p1 := gcnt_r; - end if; - end process; - -proc_ptr_gwptr: - process(clk_r) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_r) then - gcnt2_w <= p2; - p2 := p1; - p1 := gcnt_w; - end if; - end process; - -proc_status_full: - process(gnxt_w, gcnt2_r) - begin - if (gnxt_w = (not gcnt2_r(gcnt2_r'left downto gcnt2_r'left-1) & gcnt2_r(gcnt2_r'left-2 downto 0))) then - full <= '1'; - else - full <= '0'; - end if; - end process; - -proc_status_empty: - process(gnxt_r, gcnt2_w) - begin - if (gnxt_r = gcnt2_w) then - empty <= '1'; - else - empty <= '0'; - end if; - end process; - -proc_sync_arptr: - process(clk_w) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_w) then - bcnt2_ar <= p2; - p2 := p1; - p1 := bcnt_r; - end if; - end process; - -proc_ptr_awptr: - process(clk_r) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_r) then - bcnt2_aw <= p2; - p2 := p1; - p1 := bcnt_w; - end if; - end process; - -proc_status_almost_full: - process(rst, clk_w) - variable diff : unsigned (addr_width downto 0); - begin - -- synthesis translate_off - diffw <= signed(diff); - -- synthesis translate_on - if rst = '1' then - fifo_afull <= '0'; - diff := (others => '0'); - elsif rising_edge(clk_w) then - if diff >= almost_full_thresh-1 then - fifo_afull <= '1'; - else - fifo_afull <= '0'; - end if; - diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar))); - end if; - end process; - -proc_status_almost_empty: - process(rst, clk_r) - variable diff : unsigned (addr_width downto 0); - begin - -- synthesis translate_off - diffr <= signed(diff); - -- synthesis translate_on - if rst = '1' then - fifo_aempty <= '1'; - diff := (others => '0'); - elsif rising_edge(clk_r) then - if diff <= almost_empty_thresh+1 then - fifo_aempty <= '1'; - else - fifo_aempty <= '0'; - end if; - diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r))); - end if; - end process; - -inst_gray_counter_w : entity work.gray_counter - generic map ( - width => addr_width+1, - init_value => 0 - ) - port map ( - rst => rst, - clk => clk_w, - ce => winc, - bcnt => bcnt_w, - bnxt => bnxt_w, - gcnt => gcnt_w, - gnxt => gnxt_w - ); - -inst_gray_counter_r : entity work.gray_counter - generic map ( - width => addr_width+1, - init_value => 0 - ) - port map ( - rst => rst, - clk => clk_r, - ce => rinc, - bcnt => bcnt_r, - bnxt => bnxt_r, - gcnt => gcnt_r, - gnxt => gnxt_r - ); - -end Behavioral; - diff --git a/lib/FIFO/src/dpram.vhd b/lib/FIFO/src/dpram.vhd deleted file mode 100644 index b8f8565..0000000 --- a/lib/FIFO/src/dpram.vhd +++ /dev/null @@ -1,79 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/dpram.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -entity dpram is - Generic ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram; - -architecture Behavioral of dpram is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal RAM : RAMtype; - -begin - -process (clka) -begin -if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) <= din_a; - end if; - end if; -end if; -end process; - -process (clkb) -begin -if clkb'event and clkb = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); - end if; -end if; -end process; - - -end Behavioral; - diff --git a/lib/FIFO/src/fifo_ctrl_pkg.vhd b/lib/FIFO/src/fifo_ctrl_pkg.vhd deleted file mode 100644 index a8c9c61..0000000 --- a/lib/FIFO/src/fifo_ctrl_pkg.vhd +++ /dev/null @@ -1,46 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/fifo_ctrl_pkg.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package fifo_ctrl_pkg is - - -- Constants - -- Types - - -- Functions - function bin2gray(xb : unsigned) return unsigned; - function gray2bin(xg : unsigned) return unsigned; - -end fifo_ctrl_pkg; - -package body fifo_ctrl_pkg is - - function bin2gray(xb : unsigned) return unsigned is - variable xg : unsigned(xb'left downto xb'right); - begin - - xg(xg'left) := xb(xb'left); - for i in 1 to xb'left loop - xg(xg'left-i) := xb(xb'left-i+1) xor xb(xb'left-i); - end loop; - - return xg; - end bin2gray; - - function gray2bin(xg : unsigned) return unsigned is - variable xb : unsigned(xg'left downto xg'right); - begin - - xb(xb'left) := xg(xg'left); - for i in 1 to xg'left loop - xb(xb'left-i) := xb(xb'left-i+1) xor xg(xg'left-i); - end loop; - - return xb; - end gray2bin; - -end fifo_ctrl_pkg; - diff --git a/lib/FIFO/src/gray_counter.vhd b/lib/FIFO/src/gray_counter.vhd deleted file mode 100644 index eb17fd5..0000000 --- a/lib/FIFO/src/gray_counter.vhd +++ /dev/null @@ -1,88 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The call/return/data stack - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -LIBRARY WORK; -USE WORK.FIFO_CTRL_PKG.ALL; - -entity gray_counter is - Generic ( - width : natural := 3; - init_value : natural := 0 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - bcnt : out unsigned (width-1 downto 0); - bnxt : out unsigned (width-1 downto 0); - gcnt : out unsigned (width-1 downto 0); - gnxt : out unsigned (width-1 downto 0) - ); -end gray_counter; - -architecture Behavioral of gray_counter is - - signal cntb : unsigned (width-1 downto 0); - signal nxtb : unsigned (width-1 downto 0); - signal cntg : unsigned (width-1 downto 0); - signal nxtg : unsigned (width-1 downto 0); - -begin - - bnxt <= nxtb; - gnxt <= nxtg; - - process(rst, clk, ce, cntb, nxtb) - begin - if rst = '1' then - cntb <= to_unsigned(init_value, width); - nxtb <= to_unsigned(init_value, width); - cntg <= to_unsigned(init_value, width); - nxtg <= to_unsigned(init_value, width); - bcnt <= to_unsigned(init_value, width); - gcnt <= to_unsigned(init_value, width); - else - if rising_edge(clk) then - bcnt <= nxtb; - gcnt <= nxtg; - cntb <= nxtb; - cntg <= nxtg; - end if; - nxtg <= bin2gray(nxtb); - nxtb <= cntb; - if ce = '1' then - nxtb <= cntb + 1; - end if; - end if; - end process; - -end Behavioral; - diff --git a/lib/FIFO/src/sync_fifo_ctrl.vhd b/lib/FIFO/src/sync_fifo_ctrl.vhd deleted file mode 100644 index ef8661f..0000000 --- a/lib/FIFO/src/sync_fifo_ctrl.vhd +++ /dev/null @@ -1,199 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The call/return/data stack - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -entity sync_fifo_ctrl is - Generic ( - addr_width : integer := 3; - almost_full_thresh : integer := 6; - almost_empty_thresh : integer := 2 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - ptr_w : out unsigned (addr_width-1 downto 0); - ptr_r : out unsigned (addr_width-1 downto 0); - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC - ); -end sync_fifo_ctrl; - -architecture Behavioral of sync_fifo_ctrl is - - signal pW, pW_cnt, pW_next : unsigned (addr_width-1 downto 0); - signal pR, pR_cnt, pR_next : unsigned (addr_width-1 downto 0); - signal empty, full : std_logic; - signal pre_empty, pre_full : std_logic; - signal was_write : std_logic; - signal write, read : std_logic; - signal diff : unsigned (addr_width downto 0); - -begin - - read <= '1' when re = '1' and empty = '0' else '0'; - write <= '1' when we = '1' and full = '0' else '0'; - - fifo_full <= full; - fifo_empty <= empty; - - -proc_diff_gen: - process(rst, clk) - begin - if rst = '1' then - diff <= (others => '0'); - elsif rising_edge(clk) then - if write = '1' and read = '0' then - diff <= diff + 1; - elsif write = '0' and read = '1' then - diff <= diff - 1; - end if; - end if; - end process; - -proc_status_almost_full: - process(rst, clk) - begin - if rst = '1' then - fifo_afull <= '0'; - elsif rising_edge(clk) then - if diff >= almost_full_thresh-1 then - fifo_afull <= '1'; - else - fifo_afull <= '0'; - end if; - end if; - end process; - -proc_status_almost_empty: - process(rst, clk) - begin - if rst = '1' then - fifo_aempty <= '1'; - elsif rising_edge(clk) then - if diff <= almost_empty_thresh+1 then - fifo_aempty <= '1'; - else - fifo_aempty <= '0'; - end if; - end if; - end process; - -proc_full_reg: - process(rst, clk) - begin - if rst = '1' then - full <= '0'; - elsif rising_edge(clk) then - full <= pre_full; - end if; - end process; - -proc_empty_reg: - process(rst, clk) - begin - if rst = '1' then - empty <= '1'; - elsif rising_edge(clk) then - empty <= pre_empty; - end if; - end process; - -proc_status_w: - process(was_write, pW_next, pR_next, pW, pR, we, re) - begin - if (pW_next = pR) and (we = '1' or was_write = '1') then - pre_full <= '1'; - else - pre_full <= '0'; - end if; - if (pR_next = pW) and (re = '1' or was_write = '0') then - pre_empty <= '1'; - else - pre_empty <= '0'; - end if; - end process; - -proc_flag_write: - process(rst, clk) - begin - if rst = '1' then - was_write <= '0'; - elsif rising_edge(clk) then - if write = '1' then - was_write <= '1'; - elsif read = '1' then - was_write <= '0'; - end if; - end if; - end process; - -proc_ptr_w: - process(rst, clk, pW, we, full) - begin - if rst = '1' then - pW <= to_unsigned(0, addr_width); - pW_next <= to_unsigned(0, addr_width); - elsif rising_edge(clk) then - if we = '1' then - pW <= pW_next; - end if; - end if; - pW_next <= pW; - if we = '1' and full = '0' then - pW_next <= pW + 1; - end if; - ptr_w <= pW; - end process; - -proc_ptr_r: - process(rst, clk, pR_next, pR, re, empty) - begin - if rst = '1' then - pR <= to_unsigned(0, addr_width); - pR_next <= to_unsigned(0, addr_width); - elsif rising_edge(clk) then - if re = '1' then - pR <= pR_next; - end if; - end if; - pR_next <= pR; - if re = '1' and empty = '0' then - pR_next <= pR + 1; - end if; - ptr_r <= pR_next; - end process; - -end Behavioral; - diff --git a/lib/FIFO/src/tb_async_fifo_ctrl.vhd b/lib/FIFO/src/tb_async_fifo_ctrl.vhd deleted file mode 100644 index 2e95862..0000000 --- a/lib/FIFO/src/tb_async_fifo_ctrl.vhd +++ /dev/null @@ -1,176 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_nco --- Module Name: tb_nco.vhd --- Project Name: nco --- Target Device: --- Tool versions: --- Description: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE STD.TEXTIO.ALL; - --- LIBRARY WORK; --- USE.YOURLIB.WHATELSE - -ENTITY tb_async_fifo_ctrl IS -END tb_async_fifo_ctrl; - -ARCHITECTURE behavior OF tb_async_fifo_ctrl IS - - --Constants - constant PERIOD_W : time := 10 ns; - constant PERIOD_R : time := 20 ns; - constant ADDR_WIDTH : integer := 3; - - --Inputs - signal rst : STD_LOGIC := '1'; - signal clk_w : STD_LOGIC := '0'; - signal clk_r : STD_LOGIC := '0'; - signal we : STD_LOGIC := '0'; - signal re : STD_LOGIC := '0'; - signal din : unsigned (7 downto 0); - --Outputs - - signal ptr_w : unsigned (ADDR_WIDTH-1 downto 0); - signal ptr_r : unsigned (ADDR_WIDTH-1 downto 0); - signal dout : unsigned (7 downto 0); - signal fifo_full : STD_LOGIC; - signal fifo_empty : STD_LOGIC; - signal fifo_almost_full : STD_LOGIC; - signal fifo_almost_empty : STD_LOGIC; - signal mem_we : STD_LOGIC; - - signal write_en : STD_LOGIC := '0'; - signal read_en : STD_LOGIC := '0'; - - signal wdata : unsigned (7 downto 0) := (others => '0'); - signal rdata : unsigned (7 downto 0) := (others => '0'); - signal rdata2 : unsigned (7 downto 0) := (others => '0'); - -BEGIN - - din <= wdata; - - -- Instantiate the Unit Under Test (UUT) - uut: entity work.async_fifo_ctrl - GENERIC MAP - ( - addr_width => ADDR_WIDTH, - almost_full_thresh => 6, - almost_empty_thresh => 2 - ) - PORT MAP - ( - rst => rst, - clk_w => clk_w, - clk_r => clk_r, - we => we, - re => re, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => fifo_full, - fifo_empty => fifo_empty, - fifo_afull => fifo_almost_full, - fifo_aempty => fifo_almost_empty - - ); - - inst_dpram: entity work.dpram - GENERIC MAP ( - addr_width => ADDR_WIDTH, - data_width => 8 - ) - PORT MAP( - clka => clk_w, - clkb => clk_r, - en_a => '1', - en_b => '1', - we_a => mem_we, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => din, - dout_b => dout - ); - - tb_clk_w : PROCESS - BEGIN - clk_w <= not clk_w; - wait for PERIOD_W/2; - END PROCESS; - - tb_clk_r : PROCESS - BEGIN - clk_r <= not clk_r; - wait for PERIOD_R/2; - END PROCESS; - - tb_write : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 5*PERIOD_W; - rst <= '0'; - wait for 5*PERIOD_W; - write_en <= '1'; - wait for 15*PERIOD_W; - write_en <= '0'; - - wait; - - END PROCESS; - - tb_read : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 15*PERIOD_R; - read_en <= '1'; - - wait; - - END PROCESS; - - we <= write_en and not fifo_full; - mem_we <= we; - - tb_w : PROCESS(rst, clk_w) - BEGIN - - if rst = '1' then - wdata <= (others => '0'); - elsif rising_edge(clk_w) then - if we = '1' then - wdata <= wdata + 1; - end if; - end if; - - END PROCESS; - - re <= read_en and not fifo_empty; - - tb_r : PROCESS(rst, clk_r) - BEGIN - - if rst = '1' then - rdata <= (others => '0'); - elsif rising_edge(clk_r) then - rdata2 <= rdata; - if re = '1' then - assert rdata2 = dout report "FIFO read error!" severity failure; - rdata <= rdata + 1; - end if; - end if; - - END PROCESS; - -END behavior; \ No newline at end of file diff --git a/lib/FIFO/src/tb_gray_counter.vhd b/lib/FIFO/src/tb_gray_counter.vhd deleted file mode 100644 index 00380d7..0000000 --- a/lib/FIFO/src/tb_gray_counter.vhd +++ /dev/null @@ -1,83 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_gray_counter --- Module Name: tb_gray_counter.vhd --- Project Name: gray_counter package --- Target Device: --- Tool versions: --- Description: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE STD.TEXTIO.ALL; - -LIBRARY WORK; -USE WORK.FIFO_CTRL_PKG.ALL; - -ENTITY tb_gray_counter IS -END tb_gray_counter; - -ARCHITECTURE behavior OF tb_gray_counter IS - - constant PERIOD : time := 10 ns; - constant WIDTH : integer := 3; - - --Signals - signal gcnt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal bcnt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal gnxt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal bnxt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal rst : STD_LOGIC := '1'; - signal clk : STD_LOGIC := '0'; - signal ce : STD_LOGIC := '0'; - -BEGIN - -inst_gray_counter : entity work.gray_counter - generic map (width => WIDTH) - port map ( - rst => rst, - clk => clk, - ce => ce, - bcnt => bcnt, - bnxt => bnxt, - gcnt => gcnt, - gnxt => gnxt - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb_counter : PROCESS - - BEGIN - - wait for 4*PERIOD; - rst <= '0'; - wait for 1*PERIOD; - ce <= '1'; - wait for 3*PERIOD; - ce <= '0'; - wait for 4*PERIOD; - ce <= '1'; - wait for 1*PERIOD; - ce <= '0'; - wait for 1*PERIOD; - ce <= '1'; - - wait; - - END PROCESS; - -END behavior; \ No newline at end of file diff --git a/lib/FIFO/src/tb_sync_fifo_ctrl.vhd b/lib/FIFO/src/tb_sync_fifo_ctrl.vhd deleted file mode 100644 index 4eb81e3..0000000 --- a/lib/FIFO/src/tb_sync_fifo_ctrl.vhd +++ /dev/null @@ -1,221 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_nco --- Module Name: tb_nco.vhd --- Project Name: nco --- Target Device: --- Tool versions: --- Description: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_sync_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE STD.TEXTIO.ALL; - --- LIBRARY WORK; --- USE.YOURLIB.WHATELSE - -ENTITY tb_sync_fifo_ctrl IS -END tb_sync_fifo_ctrl; - -ARCHITECTURE behavior OF tb_sync_fifo_ctrl IS - - --Constants - constant PERIOD : time := 10 ns; - constant ADDR_WIDTH : integer := 3; - - --Inputs - signal rst : STD_LOGIC := '1'; - signal clk : STD_LOGIC := '0'; - signal we : STD_LOGIC := '0'; - signal re : STD_LOGIC := '0'; - signal din : unsigned (7 downto 0); - --Outputs - - signal ptr_w : unsigned (ADDR_WIDTH-1 downto 0); - signal ptr_r : unsigned (ADDR_WIDTH-1 downto 0); - signal dout : unsigned (7 downto 0); - signal fifo_full : STD_LOGIC; - signal fifo_empty : STD_LOGIC; - signal fifo_almost_full : STD_LOGIC; - signal fifo_almost_empty : STD_LOGIC; - signal mem_we : STD_LOGIC; - - signal write_en : STD_LOGIC := '0'; - signal read_en : STD_LOGIC := '0'; - - signal wdata : unsigned (7 downto 0) := (others => '0'); - signal rdata : unsigned (7 downto 0) := (others => '0'); - signal rdata2 : unsigned (7 downto 0) := (others => '0'); - -BEGIN - - din <= wdata; - - -- Instantiate the Unit Under Test (UUT) - uut: entity work.sync_fifo_ctrl - GENERIC MAP - ( - addr_width => ADDR_WIDTH, - almost_full_thresh => 6, - almost_empty_thresh => 2 - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => we, - re => re, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => fifo_full, - fifo_empty => fifo_empty, - fifo_afull => fifo_almost_full, - fifo_aempty => fifo_almost_empty - - ); - - inst_dpram: entity work.dpram - GENERIC MAP ( - addr_width => ADDR_WIDTH, - data_width => 8 - ) - PORT MAP( - clka => clk, - clkb => clk, - en_a => '1', - en_b => '1', - we_a => mem_we, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => din, - dout_b => dout - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb_write : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 5*PERIOD; - rst <= '0'; - wait for 7*PERIOD; - write_en <= '1'; - wait for 25*PERIOD; - write_en <= '0'; - wait for 7*PERIOD; - write_en <= '1'; - wait for 25*PERIOD; - write_en <= '0'; - wait for 7*PERIOD; - write_en <= '1'; - wait for 1*PERIOD; - write_en <= '0'; - wait for 1*PERIOD; - write_en <= '1'; - wait for 1*PERIOD; - write_en <= '0'; - wait for 3*PERIOD; - write_en <= '1'; - wait for 4*PERIOD; - write_en <= '0'; - wait for 17*PERIOD; - write_en <= '1'; - wait for 25*PERIOD; - write_en <= '0'; - - wait; - - END PROCESS; - - tb_read : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 25*PERIOD; - read_en <= '1'; - wait for 25*PERIOD; - read_en <= '0'; - wait for 25*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 7*PERIOD; - read_en <= '1'; - wait for 15*PERIOD; - read_en <= '0'; - - wait; - - END PROCESS; - - we <= write_en and not fifo_full; - mem_we <= we; - - tb_w : PROCESS(rst, clk) - BEGIN - - if rst = '1' then - wdata <= (others => '0'); - elsif rising_edge(clk) then - if we = '1' then - wdata <= wdata + 1; - end if; - end if; - - END PROCESS; - - re <= read_en and not fifo_empty; - - tb_r : PROCESS(rst, clk) - BEGIN - - if rst = '1' then - rdata <= (others => '0'); - elsif rising_edge(clk) then - rdata2 <= rdata; - if re = '1' then - assert rdata = dout report "FIFO read error!" severity failure; - rdata <= rdata + 1; - end if; - end if; - - END PROCESS; - -END behavior; \ No newline at end of file diff --git a/lib/PCK_FIO-1.16/PCK_FIO.html b/lib/PCK_FIO-1.16/PCK_FIO.html deleted file mode 100644 index 8b8c8c5..0000000 --- a/lib/PCK_FIO-1.16/PCK_FIO.html +++ /dev/null @@ -1,297 +0,0 @@ - - - - - - VHDL package for formatted file output - - - - -
-

-Name

-PCK_FIO - VHDL package for  formatted file output -

-

-

-Contents

-Usage -
The file output function 'fo' -
Format specifiers -
Special characters -
Things to watch out for -
Methodology notes -
Parametrization -
Test bench -
Known limitations and problems -
Author -

-

-

-Usage

-PCK_FIO is a VHDL package that defines  fprint, a function -for formatted file output. -

After installing the package you can call fprint as follows: -

  fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));
-where F is the filehandle and L is the line variable. -

The argument Format is the format string, which consists of ``normal'' -substrings which are copied verbatim, and format specifiers, starting with -'%'. -A typical format string looks as follows: -

   "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"
-The remaining arguments are the expressions whose results you want to write -to the file, embedded in fo function calls. There can be 0 to -32 of such arguments. The expressions can be of any type for which an fo -function exists. String expressions can also be called directly. -

-

-

-The file output function 'fo'

-The fo (file output) functions do the trick. They -return a tagged string representation that is meaningful to format specifiers. -Here are some examples: -
  fo (signed'("1100"))   returns "S:1100" 
-  fo (unsigned'("1100")) returns "U:1100" 
-  fo (TRUE)              returns "L:T"
-  fo (127)               returns "I:127"
-The internal behavior of fo is irrelevant to the typical user. -

The fo function is currently overloaded as follows: -

  function fo (Arg: unsigned)          return string;
-  function fo (Arg: signed)            return string;
-  function fo (Arg: std_logic_vector)  return string;
-  function fo (Arg: std_ulogic_vector) return string;
-  function fo (Arg: bit_vector)        return string;
-  function fo (Arg: integer)           return string;
-  function fo (Arg: std_ulogic)        return string;
-  function fo (Arg: bit)               return string;
-  function fo (Arg: boolean)           return string; 
-  function fo (Arg: character)         return string;
-  function fo (Arg: string)            return string;
-  function fo (Arg: time)              return string;
- -
-
- -

-Format specifiers

-The general format of a format specifier is: -
   %[-][n]c
-The optional - sign specifies left justified output; default is -right justified. -

The optional number n specifies a field-width. If it is not specified, -fprint -does something reasonable. -

c is the conversion specifier. Currently the following conversion -specifiers are supported: -

-
-r
- -
-reasonable output format (inspired by Synopsys VSS)
- -
Prints the ``most reasonable'' representation e.g. hex for -unsigned, signed and other bit-like vectors (not preferred for integers)
- -
-b
- -
-bit-oriented output
- -
-d
- -
-decimal output
- -
-s
- -
-string output (e.g. in combination with 'IMAGE for enum types)
- -
-q
- -
-``qualified'' string output (shows internal representation from fo)
- -
-{}
- -
-Iteration operator, used as follows:
- -
-%n{<format-string>}
- -
In this case, n is the iteration count and is mandatory. Iteration -can be nested.
- -
-

-Special characters

-To print a double-quote,  use '""' in the format string (VHDL -convention). To print the special characters, '\', and '%', -escape them with '\'. To prevent '{' and '}' -from being interpreted as opening and closing brackets in iteration strings, -escape them with '\'. -

A newline is specified in the format string by '\n'. -

-

-

-Things to notice

-The fprint function expands into VHDL write and writeline -commands. As in plain VHDL, nothing will be written to the output file -until a writeline is given. Therefore, don't forget to include -'\n' -commands in the format string, or it ``will not work''. -

The preferred format specifier for integers is, naturally, %d. -This calls the VHDL write for integers. If you specify a field -width that is too small, the field will automatically be expanded. If you -use %r for integers, the field is not expanded automatically, which -means that some digits are simply thrown away. This may sometimes be useful -but it is also dangerous. Look at the test bench output for differences -between %d and %r output. -

When using the %d format specifier, the VHDL constraints for -the allowed integer range apply. -

In VHDL, signed/unsigned types have been standardized only relatively -recently, in the package IEEE.numeric_std. The lack of a standard -has caused (and is causing) portability issues. The most popular non-standard -package that defines signed/unsigned is IEEE.std_logic_arith from -Synopsys. PCK_FIO has been developed with this latter package, and still -refers to this package by default. However, PCK_FIO  works with -IEEE.numeric_std -as well. To use IEEE.numeric_std, replace the reference to IEEE.std_logic_arith -in the source code.  This needs to be done consistently in a design -database (e.g. in the PCK_FIO test bench as well). -

-

-

-Methodology notes

-The obvious application for fprint is in test benches, to produce -output files that trace the simulation behavior. -

Another interesting application for fprint is to produce info, -warning and error messages in your models. As it can take arguments, fprint -is much better suited for this task than VHDL's assert or report -statements. Actually fprint produces its own (few) warning messages. -

An advanced usage is the generation of test vectors in a specific format. -Instead of using the fo functions, you can write your own set -of functions that return the symbols of a specific test format in a way -that is understandable to the fprint format specifiers. As an -example, when a high output value should be represented using the symbol -'H' it suffices to write a conversion function that returns "B:H" and call -it in combination with the %b format specifier. -

-

-

-Parametrization

-Prefix and postfix strings for bit-oriented and hex-oriented output are -parameterizable in the packages to accommodate different output styles. -The settings in the distribution are such that hex output is indicated -by the prefix '0x', while  bit output prefix and postfix are empty -strings. -

You can adapt the output style by modifying the following constants -in the package header: -

   -- prefix string for hex output -
  -- VHDL style:    "X""" -
  -- Verilog style: "h'" -
  -- C style:       "0x" -
  constant FIO_h_PRE:  string := "0x"; -

  -- postfix string for hex output -
  -- VHDL style:    """" -
  constant FIO_h_POST: string := ""; -

  -- prefix string for bit vector output -
  -- VHDL style:    "B""" -
  -- Verilog style: "b'" -
  constant FIO_bv_PRE:  string := ""; -

  -- postfix string for bit vector output -
  -- VHDL style:    """" -
  constant FIO_bv_POST: string := ""; -

  -- prefix string for bit output -
  -- VHDL style:    "'" -
  -- Verilog style: "b'" -
  constant FIO_b_PRE:  string := ""; -

  -- postfix string for bit output -
  -- VHDL style:    "'" -
  constant FIO_b_POST: string := ""; -

-

-

-Test bench

-Included in the distribution is a file TB_PCK_FIO.vhd with a test -bench for the PCK_FIO package. The file PCK_FIO.out.gold contains -the expected output. If you run the test bench it should produce the file -PCK_FIO.out -that should be identical to PCK_FIO.out.gold. The source files -should be analyzed in a VHDL library EASICS_PACKAGES. -

A good way to understand fprint is to inspect the test bench -and what it produces. -

-

-

-Known limitations and problems

-This VHDL package is an implementation of a flexible concept. It is likely -to be extended and modified in the future. Backward compatibility is not -guaranteed. Therefore, it is not recommended to give this package the status -of a company-wide standard package (or even worse, a VHDL standard package). -Rather, it should be linked with a particular project (and it can be regarded -as a standard package within that project). -

PCK_FIO is written in standard VHDL Std1076-1987. Nevertheless, some -simulators/versions have problems with the package. The following is an -overview of currently known issues: -
  -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
SimulatorPCK_FIO handling
Synopsys VSS 3.5 and earlierIncorrect (all zero) output in compiled mode
Synopsys VSS 97.01OK
Mentor quickhdlOK
Modeltech modelsimOK
Cadence LeapfrogShould work with 4.4.1 -
Mysterious problems have been reported - please run the test bench -and report problems
PCK_FIO and various simulators/versions
- -

Although the package name suggests file IO, it only does file output. -

-

-

-Author

-Jan Decaluwe -

-

- - diff --git a/lib/PCK_FIO-1.16/PCK_FIO.out.gold b/lib/PCK_FIO-1.16/PCK_FIO.out.gold deleted file mode 100644 index dcd183e..0000000 --- a/lib/PCK_FIO-1.16/PCK_FIO.out.gold +++ /dev/null @@ -1,206 +0,0 @@ -PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO ------------------------------------------ - -This is the result of running the PCK_FIO testbench. -This file should be compared with PCK_FIO.out.gold, which is -the reference output. Any difference indicates a portability -issue or a simulator non-compliance or bug. - - --------------------- --- Basic features -- --------------------- - --- First some auxiliary declarations -> file RESULT: text is out "PCK_FIO.out"; -> variable L: line; -> variable BoolTrue: boolean := TRUE; -> variable BoolFalse: boolean := FALSE; -> variable IntPos: integer := 5678; -> variable BigIntPos: integer := 12345678; -> variable IntNeg: integer := -8765; -> variable BigIntNeg: integer := -87654321; -> variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); -> variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); -> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); -> variable SigPos: signed(6 downto 0) := signed'("0010010"); -> variable SigNeg: signed(6 downto 0) := signed'("1010010"); -> variable BitX: std_logic := 'X'; -> variable Bit1: std_logic := '1'; -> variable Bit0: std_logic := '0'; - - --- fprint call with no arguments -> fprint(RESULT, L, "No arguments.\n);" -No arguments. - --- Special characters need to be escaped -> fprint(RESULT, L, "Special characters: \% \\ " \n"); -Special characters: % \ " - --- Various format specifiers interprete the same object differently -> fprint(RESULT, L, "Format specifiers: %r %d %b %q\n);" -> fo(Uns), fo(Uns), fo(Uns), fo(Uns) -> ); -Format specifiers: 0x52 82 1010010 U:1010010 - --- Format string can be shortened by using the iteration specifier -> fprint(RESULT, L, "Iteration specifier: %4{%r }\n);" -> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) -> ); -Iteration specifier: 0x52 0x12 0x52 0x12 - ------------------------------------- --- Support for bit-oriented types -- ------------------------------------- - --- Reasonable format -> fprint(RESULT, L, "Reasonable format: %9{%r }\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), -> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) -> ); -Reasonable format: 0x12 0x52 0x12 0x52 0x?? 1 X T F - --- Decimal format -> fprint(RESULT, L, "Decimal format: %7{%d }\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), -> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) -> ); -Decimal format: 18 82 18 -46 -1 1 -1 1 0 - --- Bit format -> fprint(RESULT, L, "Bit format: %7{%b }\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), -> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) -> ); -Bit format: 0010010 1010010 0010010 1010010 1X10Z10 1 X 1 0 - - --- Alignment --- Template of the call: ( stands for the format specifier) - -> fprint(RESULT, L, "Bitvectors with : %4{|}\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg) -> ); - --- Results of the call with various format specifiers - -Bitvectors with %1r: 0x52|0x12|0x12|0x52| -Bitvectors with %2r: 0x52|0x12|0x12|0x52| -Bitvectors with %3r: 0x52|0x12|0x12|0x52| -Bitvectors with %4r: 0x52|0x12|0x12|0x52| -Bitvectors with %5r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %6r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %7r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %8r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %9r: 0x52| 0x12| 0x12| 0x52| - -Bitvectors with %-1r: 0x52|0x12|0x12|0x52| -Bitvectors with %-2r: 0x52|0x12|0x12|0x52| -Bitvectors with %-3r: 0x52|0x12|0x12|0x52| -Bitvectors with %-4r: 0x52|0x12|0x12|0x52| -Bitvectors with %-5r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-6r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-7r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-8r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-9r: 0x52 |0x12 |0x12 |0x52 | - -Bitvectors with %1d: 82|18|18|-46| -Bitvectors with %2d: 82|18|18|-46| -Bitvectors with %3d: 82| 18| 18|-46| -Bitvectors with %4d: 82| 18| 18| -46| -Bitvectors with %5d: 82| 18| 18| -46| -Bitvectors with %6d: 82| 18| 18| -46| -Bitvectors with %7d: 82| 18| 18| -46| -Bitvectors with %8d: 82| 18| 18| -46| -Bitvectors with %9d: 82| 18| 18| -46| - -Bitvectors with %-1d: 82|18|18|-46| -Bitvectors with %-2d: 82|18|18|-46| -Bitvectors with %-3d: 82 |18 |18 |-46| -Bitvectors with %-4d: 82 |18 |18 |-46 | -Bitvectors with %-5d: 82 |18 |18 |-46 | -Bitvectors with %-6d: 82 |18 |18 |-46 | -Bitvectors with %-7d: 82 |18 |18 |-46 | -Bitvectors with %-8d: 82 |18 |18 |-46 | -Bitvectors with %-9d: 82 |18 |18 |-46 | - - -------------------------------- --- Support for integer types -- -------------------------------- - - --- Template of the call: ( stands for the format specifier) - -> fprint(RESULT, L, "Integers with : %4{|}\n", -> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) -> ); - --- Results of the call with various format specifiers - -Integers with %5d: 5678|-8765|12345678|-87654321| -Integers with %6d: 5678| -8765|12345678|-87654321| -Integers with %7d: 5678| -8765|12345678|-87654321| -Integers with %8d: 5678| -8765|12345678|-87654321| -Integers with %9d: 5678| -8765| 12345678|-87654321| -Integers with %10d: 5678| -8765| 12345678| -87654321| - -Integers with %-5d: 5678 |-8765|12345678|-87654321| -Integers with %-6d: 5678 |-8765 |12345678|-87654321| -Integers with %-7d: 5678 |-8765 |12345678|-87654321| -Integers with %-8d: 5678 |-8765 |12345678|-87654321| -Integers with %-9d: 5678 |-8765 |12345678 |-87654321| -Integers with %-10d: 5678 |-8765 |12345678 |-87654321 | - -Integers with %5r: 5678|-8765| 5678|-4321| -Integers with %6r: 5678|- 8765| 45678|-54321| -Integers with %7r: 5678|- 8765| 345678|-654321| -Integers with %8r: 5678|- 8765| 2345678|-7654321| -Integers with %9r: 5678|- 8765| 12345678|-87654321| -Integers with %10r: 5678|- 8765| 12345678|- 87654321| - -Integers with %-5r: 5678|-8765| 1234|-8765| -Integers with %-6r: 5678 |-8765 | 12345|-87654| -Integers with %-7r: 5678 |-8765 | 123456|-876543| -Integers with %-8r: 5678 |-8765 | 1234567|-8765432| -Integers with %-9r: 5678 |-8765 | 12345678|-87654321| -Integers with %-10r: 5678 |-8765 | 12345678 |-87654321 | - - ----------------------- --- Support for time -- ----------------------- --- For portability reasons, time is converted --- into an integer value (of nanoseconds) -> wait for 648 ns -> fprint (RESULT, L, "The time is now %d ns\n", fo(now)); -The time is now 648 ns - ----------------------------------------- --- Erroneous calls and error messages -- ----------------------------------------- - --- Less arguments than formats specifiers -> fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); -82 18 -** Warning: FIO_PrintLastValue: Format specifier beyond last argument -** in format string: "%d %d %d %d \n" -** ------^ - --- Unsupported format specifier -> fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); -0x52 -** Warning: FIO_PrintArg: Unexpected format specifier 'v' -** in format string: "%r %v %r %r\n" -** ----^ -** Assuming 'q' to proceed: V:0010010 0x52 0x12 - - ----------------------------------------- --- Things you wouldn't expect to work -- ----------------------------------------- - --- Nested iteration -> fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); -<<_END__END__END_>><<_END__END__END_>><<_END__END__END_>> diff --git a/lib/PCK_FIO-1.16/PCK_FIO.vhd b/lib/PCK_FIO-1.16/PCK_FIO.vhd deleted file mode 100644 index e5e6a8e..0000000 --- a/lib/PCK_FIO-1.16/PCK_FIO.vhd +++ /dev/null @@ -1,916 +0,0 @@ ----- File: PCK_FIO.vhd ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 1999 Easics NV ----- ----- This program is free software; you can redistribute it and/or modify ----- it under the terms of the GNU General Public License as published by ----- the Free Software Foundation; either version 1, or (at your option) ----- any later version. ----- ----- This program is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----- GNU General Public License for more details. ----- ----- You should have received a copy of the GNU General Public License ----- along with this program; if not, write to the Free Software ----- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- ----- ----- Revision history: ----- ----- $Source: /tmp/cvsroot/VHDL/lib/PCK_FIO-1.16/PCK_FIO.vhd,v $ ----- $Revision: 1.1 $ ----- $Log: not supported by cvs2svn $ ----- Revision 1.16 1999/04/21 08:28:46 jand ----- Tested with IEEE.numeric_std ----- Small patch for Leapfrog ----- ----- Revision 1.14 1997/07/14 10:16:04 jand ----- prefix/postfix for bits/bitvectors set to empty strings by default ----- ----- Revision 1.13 1997/07/11 17:42:57 jand ----- Corrected Easics address ----- ----- Revision 1.12 1997/07/11 17:38:49 jand ----- Improved prefix/postfix support ----- ----- Revision 1.11 1995/11/15 13:46:02 jand ----- Catched integer'low value in fo for integers ----- ----- Revision 1.10 1995/08/11 16:42:26 jand ----- Reimplemented FIO_FormatExpand as a procedure in an attempt to ----- avoid memory leakage problems in VSS ----- ----- Revision 1.9 1995/08/09 13:47:51 jand ----- Removed array of line trick in fprint for less memory, less ----- CPU time, and more conservatism in general ----- Rearranged FIO_PrintValue call so that fprint remains concise ----- ----- Revision 1.8 1995/08/09 10:32:27 jand ----- Removed fprint_flat to have a single call level ----- Added explicit deallocators of line variables (has strong influence ----- on memory usage in VSS - and possibly CPU time) ----- Redefined 'fo' for type time to make it more portable ----- ----- Revision 1.7 1995/08/07 08:56:04 jand ----- Improved conciseness of fprint argument handling through array of line type ----- ----- Revision 1.6 1995/08/04 18:19:13 jand ----- Increase # arguments from 16 to 32 ----- Corrected bug within fprint 's call to Arg16 ----- Added support for bit format specifier 'b' ----- ----- Revision 1.5 1995/08/02 10:22:37 jand ----- Release 1.1 under GNU ----- ----- Revision 1.4 1995/08/01 11:15:52 jand ----- Added escaping during iteration string read ----- ----- Revision 1.3 1995/08/01 08:23:47 jand ----- Many improvements in robustness, conciseness and coding style ----- ----- Revision 1.2 1995/07/30 16:15:43 jand ----- Improved robustness for release to the world ----- ----- Revision 1.1 1995/07/30 14:21:30 jand ----- Initial revision ----- - -use STD.TEXTIO.all; - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std -use IEEE.std_logic_arith.all; -- the Synopsys one --- use IEEE.numeric_std.all; - -package PCK_FIO is - - -- prefix string for hex output - -- VHDL style: "X""" - -- Verilog style: "h'" - -- C style: "0x" - constant FIO_h_PRE: string := "0x"; - - -- postfix string for hex output - -- VHDL style: """" - constant FIO_h_POST: string := ""; - - -- prefix string for bit vector output - -- VHDL style: "B""" - -- Verilog style: "b'" - constant FIO_bv_PRE: string := ""; - - -- postfix string for bit vector output - -- VHDL style: """" - constant FIO_bv_POST: string := ""; - - -- prefix string for bit output - -- VHDL style: "'" - -- Verilog style: "b'" - constant FIO_b_PRE: string := ""; - - -- postfix string for bit output - -- VHDL style: "'" - constant FIO_b_POST: string := ""; - - -- digit width for the string representation of integers - constant FIO_d_WIDTH: integer := 10; - - -- bit width for the string representation of integers - constant FIO_b_WIDTH: integer := 32; - - -- definition of the NIL string (default value for fprint arguments) - -- fprint stops consuming arguments at the first NIL argument - constant FIO_NIL: string := "\"; - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ); - - function fo (Arg: unsigned) return string; - function fo (Arg: signed) return string; - function fo (Arg: std_logic_vector) return string; - function fo (Arg: std_ulogic_vector) return string; - function fo (Arg: bit_vector) return string; - function fo (Arg: integer) return string; - function fo (Arg: std_ulogic) return string; - function fo (Arg: bit) return string; - function fo (Arg: boolean) return string; - function fo (Arg: character) return string; - function fo (Arg: string) return string; - function fo (Arg: time) return string; - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive); - -end PCK_FIO; - - -package body PCK_FIO is - - - -------------------------- - -- FIO Warnings support -- - -------------------------- - - procedure FIO_Warning_Fsbla (F: out text; - L: inout line; - Format: in string; - Pointer: in positive) is - begin - fprint (F, L, "\n** Warning: FIO_PrintLastValue: " & - "Format specifier beyond last argument\n"); - fprint (F, L, "** in format string: ""%s""\n", Format); - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n"); - end FIO_Warning_Fsbla; - - procedure FIO_Warning_Ufs (F: out text; - L: inout line; - Format: in string; - Pointer: in positive; - Char: in character) is - begin - fprint (F, L, "\n** Warning: FIO_PrintArg: " & - "Unexpected format specifier '%r'\n", - fo(Char)); - fprint (F, L, "** in format string: ""%s""\n", Format) ; - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n** Assuming 'q' to proceed: "); - end FIO_Warning_Ufs; - - - ---------------------------------- - -- bit conversion support -- - ---------------------------------- - - type T_bit_map is array(bit) of character; - - constant C_BIT_MAP: T_bit_map - := ('0', '1'); - - ---------------------------------- - -- std_logic conversion support -- - ---------------------------------- - - type T_std_logic_map is array(std_ulogic) of character; - - constant C_STD_LOGIC_MAP: T_std_logic_map - := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); - - ------------------------------ - -- Digit conversion support -- - ------------------------------ - - -- types & constants - - subtype S_digit_chars is character range '0' to '9'; - subtype S_digits is integer range 0 to 9 ; - - type T_digit_chars_map is array(S_digit_chars) of S_digits; - - constant C_DIGIT_CHARS_MAP: T_digit_chars_map - := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9); - - type T_digits_map is array(S_digits) of S_digit_chars; - - constant C_DIGITS_MAP: T_digits_map - := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9'); - - - -------------------------------- - -- Decimal conversion support -- - -------------------------------- - - function U_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - for i in Argument'range loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(-1); - end case; - end loop; - return (Result); - end U_To_d; - - function S_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - case Argument(Argument'left) is - when '1' => Result := - 2**(Argument'left-1); - when '0' => Result := 0; - when others => return (integer'low); - end case; - for i in Argument'left-1 downto 1 loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(integer'low); - end case; - end loop; - return (Result); - end S_To_d; - - function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is - constant Sign: character := Arg(1); - constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length); - variable Char: character; - variable Result: integer := 0; - begin - Result := 0; - for i in Value'range loop - Result := Result * 10; - Char := Value(i); - if (Char /= ' ') then - Result := Result + C_DIGIT_CHARS_MAP(Char); - end if; - end loop; - case Sign is when '-' => return(-Result); - when others => return(Result); - end case; - end I_To_d; - - function B_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "1" => return(1); - when "0" => return(0); - when others => return(-1); - end case; - end B_To_d; - - function L_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "T" => return(1); - when others => return(0); - end case; - end L_To_d; - - - - ---------------------------- - -- Hex conversion support -- - ---------------------------- - - -- Constants & types - - constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?"; - - -- Function to return Hex index of a nibble - - function U_To_h_Index(Arg: string(4 downto 1)) return integer is - variable Index: integer := 0; - begin - for i in Arg'range loop - case Arg(i) is when '1' => Index := 2**(i-1) + Index; - when '0' => null; - when others => return (17); - end case; - end loop; - return (Index+1); - end U_To_h_Index; - - -- Hex conversion - - function U_To_h (Arg: string) return string is - variable Result: string((Arg'length-1)/4 +1 downto 1); - variable ExtArg: string(Result'length*4 downto 1) := (others => '0'); - begin - ExtArg(Arg'length downto 1) := Arg; - for i in Result'range loop - Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) )); - end loop; - return (FIO_h_PRE & Result & FIO_h_POST); - end U_To_h; - - - - ---------------------------- - -- Bit conversion support -- - ---------------------------- - - function L_To_b (Arg: string(1 to 1)) return string is - variable Result: string(1 to 1); - begin - case Arg is when "T" => Result := "1"; - when others => Result := "0"; - end case; - return(FIO_b_PRE & Result & FIO_b_POST); - end L_To_b; - - - function I_To_b (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - - variable IntValue: integer := I_To_d(Arg); - variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' '); - variable Sign: character := ' '; - constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' '); - variable BitWidth: integer range 0 to FIO_b_WIDTH; - variable MsPos: integer range 1 to BitValue'length; - variable BitValueExtended: string(1 to 2*FIO_b_WIDTH); - - begin - - if (IntValue < 0) then - Sign := '-'; - IntValue := -IntValue; - end if; - - for i in BitValue'reverse_range loop - BitValue(i) := C_DIGITS_MAP(IntValue mod 2); - IntValue := IntValue / 2; - exit when (IntValue = 0); - end loop; - - BitValueExtended := BitValue & Blanks; - - if (Width = 0) or (Width > FIO_b_WIDTH+1) then - BitWidth := FIO_b_WIDTH; - else - BitWidth := Width-1; - end if; - - if (Justified = RIGHT) then - return (FIO_bv_PRE & - Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) & - FIO_bv_POST); - else - for i in BitValue'range loop - if BitValue(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (FIO_bv_PRE & - Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) & - FIO_bv_POST); - end if; - - end I_To_b; - - - ----------------------------------- - -- Reasonable conversion support -- - ----------------------------------- - - function I_To_r (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1); - constant Sign: character := Arg(1); - constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' '); - variable IntWidth: integer range 0 to FIO_d_WIDTH; - variable MsPos: integer range 1 to Value'length; - variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks; - begin - if (Width = 0) or (Width > FIO_d_WIDTH+1) then - IntWidth := FIO_d_WIDTH; - else - IntWidth := Width-1; - end if; - if (Justified = RIGHT) then - return (Sign & Value(Value'length-IntWidth+1 to Value'length)); - else - for i in Value'range loop - if Value(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1)); - end if; - end I_To_r; - - - ------------------------------------------- - -- Reasonable output conversion function -- - ------------------------------------------- - - function ReasonableOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return U_To_h(Value); - when "I:" => - return I_To_r(Value, Justified, Width); - when "B:" | "L:" | "C:" => - return Value; - when others => - return Argument; - end case; - - end ReasonableOutput; - - - ------------------------------------ - -- Bit output conversion function -- - ------------------------------------ - - function BitOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return (FIO_bv_PRE & Value & FIO_bv_POST); - when "B:" => - -- Value(1 to 1) instead of Value for LeapFrog - return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST); - when "I:" => - return I_To_b(Value, Justified, Width); - when "L:" => - -- Value(1 to 1) instead of Value for LeapFrog - return L_To_b(Value(1 to 1)); - when others => - return Argument; - end case; - - end BitOutput; - - - ------------------------------------------- - -- Decimal output conversion function -- - ------------------------------------------- - - function DecimalOutput (Arg: string) return integer is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:"| "V:" => - return U_To_d(Value); - when "S:" => - return S_To_d(Value); - when "I:" => - return I_To_d(Value); - when "B:" => - return B_To_d(Value); - when "L:" => - return L_To_d(Value); - when others => - return integer'low; - end case; - - end DecimalOutput; - - - ---------------------------- - -- Atomic print functions -- - ---------------------------- - - function FIO_EOS (Format: in string; - Pointer: in integer) - return boolean is - begin - return (Pointer > Format'length); - end FIO_EOS; - - - -- Atomic value print function - - procedure FIO_PrintValue (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Last: in boolean := FALSE) is - variable Char: character; - begin - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '\' => - Pointer := Pointer + 1; - exit when (FIO_EOS(Format, Pointer)); - Char := Format(Pointer); - case Char is when 'n' => writeline(F, L); - when others => write(L, Char); - end case; - when '%' => - if Last then - FIO_Warning_Fsbla(F, L, Format, Pointer); - end if; - Pointer := Pointer + 1; - exit; - when others => - write(L, char); - end case; - Pointer := Pointer + 1; - end loop; - end FIO_PrintValue; - - - ---- Atomic argument print function - - procedure FIO_PrintArg (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Arg: in string) is - variable Char: character; - variable Justified: side; - variable Width: integer; - begin - - FIO_PrintValue(F, L, Format, Pointer); - - Justified := RIGHT; - Width := 0; - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '-' => - Justified := LEFT; - Pointer := Pointer + 1; - when '0' to '9' => - Width := Width*10 + C_DIGIT_CHARS_MAP(Char); - Pointer := Pointer + 1; - when 'r' => - write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'b' => - write(L, BitOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'd' => - write(L, DecimalOutput(Arg), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'q' | 's' => - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - when others => - FIO_Warning_Ufs(F, L, Format, Pointer, Char); - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - end case; - end loop; - end FIO_PrintArg; - - - ----------------------------------------------------- - -- The format string iteration expansion procedure -- - ----------------------------------------------------- - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive) is - - variable Pointer: positive := StartPointer; - variable TokenStart: positive; - variable IterStringStart: positive; - variable IterStringEnd: positive; - variable IterCount: natural; - variable OpenBrackets: natural; - variable L: line; - - begin - - FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- look for format specifier - when '%' => - - -- initialize iteration token search - TokenStart := Pointer; - IterCount := 0; - Pointer := Pointer + 1; - - -- start iteration token search - TOKEN_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- read iteration counter - when '0' to '9' => - IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer)); - Pointer := Pointer + 1; - - -- expect open bracket - when '{' => - - -- initialize iteration string read - OpenBrackets := 1; - IterStringStart := Pointer + 1; - Pointer := Pointer + 1; - -- quit prematurely when iteration count is 0 - next FORMAT_SEARCH when (IterCount = 0); - - -- start iteration string read - ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - -- keep track of open brackets - when '{' => - OpenBrackets := OpenBrackets + 1; - Pointer := Pointer + 1; - -- when closing bracket is found, process iteration string - when '}' => - OpenBrackets := OpenBrackets - 1; - if (OpenBrackets = 0) then - IterStringEnd := Pointer-1; - if (TokenStart /= 1) then - write(L, Format(1 to TokenStart-1)); - end if; - for i in 1 to IterCount loop - write(L, Format(IterStringStart to IterStringEnd)); - end loop; - if (IterStringEnd /= Format'length) then - write(L, Format(IterStringEnd+2 to Format'length)); - end if; - -- call expansion procedure recursively on expanded format - FIO_FormatExpand(FMT, L.all, TokenStart); - deallocate(L); - return; - end if; - Pointer := Pointer + 1; - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - -- read iteration string - when others => - Pointer := Pointer + 1; - - end case; - - end loop ITER_STRING_READ; - - -- stop iteration token search when no opening bracket found - when others => - Pointer := Pointer + 1; - next FORMAT_SEARCH; - - end case; - - end loop TOKEN_READ; - - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - - -- read other characters - when others => - Pointer := Pointer + 1; - - end case; - - end loop FORMAT_SEARCH; - - write(FMT, Format); - deallocate(L); - - end FIO_FormatExpand; - - - - -------------------------- - -- The fprint procedure -- - -------------------------- - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ) is - - variable Pointer: integer; - variable FMT: line; - - begin - - Pointer := 1; - - FIO_FormatExpand (FMT, Format, Format'low); - - if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 ); - if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 ); - if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 ); - if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 ); - if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 ); - if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 ); - if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 ); - if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 ); - if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 ); - if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10); - if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11); - if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12); - if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13); - if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14); - if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15); - if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16); - if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17); - if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18); - if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19); - if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20); - if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21); - if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22); - if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23); - if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24); - if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25); - if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26); - if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27); - if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28); - if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29); - if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30); - if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31); - if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32); - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - - FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE); - - deallocate(FMT); - - end fprint; - - - ------------------------------------------- - -- Formatted output conversion functions -- - ------------------------------------------- - - function fo (Arg: unsigned) return string is - constant Argument: unsigned(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("U:" & Result); - end fo; - - function fo (Arg: signed) return string is - constant Argument: signed(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("S:" & Result); - end fo; - - function fo (Arg: std_logic_vector) return string is - constant Argument: std_logic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: std_ulogic_vector) return string is - constant Argument: std_ulogic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: bit_vector) return string is - constant Argument: bit_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_BIT_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: integer) return string is - variable Argument: integer := Arg; - variable Result: string(1 to FIO_d_WIDTH) := (others => ' '); - variable Sign: character := ' '; - begin - if (Argument < 0) and (Argument /= integer'low) then - Sign := '-'; - Argument := -Argument; - end if; - for i in Result'reverse_range loop - Result(i) := C_DIGITS_MAP(Argument mod 10); - Argument := Argument / 10; - exit when (Argument = 0); - end loop; - return ("I:" & Sign & Result); - end fo; - - function fo (Arg: std_ulogic) return string is - begin - return ("B:" & C_STD_LOGIC_MAP(Arg)); - end fo; - - function fo (Arg: bit) return string is - begin - return ("B:" & C_BIT_MAP(Arg)); - end fo; - - function fo (Arg: boolean) return string is - begin - if (ARG = TRUE) then - return ("L:T"); - else - return ("L:F"); - end if; - end fo; - - function fo (Arg: character) return string is - begin - return ("C:" & Arg); - end fo; - - function fo (Arg: string) return string is - begin - return Arg; - end fo; - - function fo (Arg: time) return string is - begin - return fo (integer (Arg / 1 ns)); - end fo; - -end PCK_FIO; diff --git a/lib/PCK_FIO-1.16/README b/lib/PCK_FIO-1.16/README deleted file mode 100644 index 4af4c99..0000000 --- a/lib/PCK_FIO-1.16/README +++ /dev/null @@ -1,72 +0,0 @@ -# $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $ -# $Log: not supported by cvs2svn $ -# Revision 1.3 1999/04/21 08:08:35 jand -# Tested with IEEE.numeric_std -# Small patch for Leapfrog -# -# - - PCK_FIO, Version 1.16 - Copyright (C) 1995, 1999 Easics NV - ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 1999 Easics NV ----- ----- This program is free software; you can redistribute it and/or modify ----- it under the terms of the GNU General Public License as published by ----- the Free Software Foundation; either version 1, or (at your option) ----- any later version. ----- ----- This program is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----- GNU General Public License for more details. ----- ----- You should have received a copy of the GNU General Public License ----- along with this program; if not, write to the Free Software ----- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - -Contents --------- - -This distribution contains the following files: - - PCK_FIO.vhd: VHDL source of the PCK_FIO package - TB_PCK_FIO.vhd: VHDL source of the testbench for package PCK_FIO - PCK_FIO.out.gold: Certified test bench output - PCK_FIO.html: Manual for PCK_FIO in html format - README: This file - - -Installation ------------- - -To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and -analyze the VHDL file PCK_FIO.vhd into this library. - -To install the test bench, analyze TB_PCK_FIO.vhd into the same library. - -If you want to use IEEE.numeric_std instead of IEEE.std_logic_arith, you need -to edit the source code of the package and the test bench and replace the -package use clause. PCK_FIO works with either of these packages. - -To install the documentation, point your web browser to the file PCK_FIO.html -and bookmark it. - - -Installation check ------------------- - -After installing the test bench, you should run it. The corresponding VHDL -design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB). - -Simulating the test bench should create a file called PCK_FIO.out. This file -should be identical to PCK_FIO.out.gold. Any difference indicates a portability -issue or a simulator non-compliance or bug. diff --git a/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd b/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd deleted file mode 100644 index c64d045..0000000 --- a/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd +++ /dev/null @@ -1,504 +0,0 @@ ----- File: TB_PCK_FIO.vhd ----- ----- TBC_PCK_FIO: a test bench for the PCK_FIO package. ----- Copyright (C) 1995, 1999 Easics NV ----- ----- This program is free software; you can redistribute it and/or modify ----- it under the terms of the GNU General Public License as published by ----- the Free Software Foundation; either version 1, or (at your option) ----- any later version. ----- ----- This program is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----- GNU General Public License for more details. ----- ----- You should have received a copy of the GNU General Public License ----- along with this program; if not, write to the Free Software ----- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 396 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- ----- ----- $Source: /tmp/cvsroot/VHDL/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd,v $ ----- $Revision: 1.1 $ ----- $Log: not supported by cvs2svn $ ----- Revision 1.7 1999/04/21 08:23:53 jand ----- Tested with IEEE.numeric_std ----- Small patch for Leapfrog ----- ----- Revision 1.3 1998/09/29 10:09:44 vhdl ----- to EASICS_PACKAGES ----- ----- Revision 1.2 1998/09/29 09:17:51 vhdl ----- library EASICS_PACKAGES; ----- ----- Revision 1.1 1998/09/29 09:15:44 vhdl ----- Initial revision ----- - - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std -use IEEE.std_logic_arith.all; -- the Synopsys one --- use IEEE.numeric_std.all; - -use STD.TEXTIO.all; - -library EASICS_PACKAGES; -use EASICS_PACKAGES.PCK_FIO.all; - -entity TBE_PCK_FIO is - -end TBE_PCK_FIO; - -architecture TB of TBE_PCK_FIO is - -begin - -USAGE: process - - file RESULT: text is out "PCK_FIO.out"; - variable L: line; - variable Pointer: integer; - variable BoolTrue: boolean := TRUE; - variable BoolFalse: boolean := FALSE; - variable IntPos: integer := 5678; - variable BigIntPos: integer := 12345678; - variable IntNeg: integer := -8765; - variable BigIntNeg: integer := -87654321; - variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); - variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); - variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); - variable SigPos: signed(6 downto 0) := signed'("0010010"); - variable SigNeg: signed(6 downto 0) := signed'("1010010"); - variable BitX: std_logic := 'X'; - variable Bit1: std_logic := '1'; - variable Bit0: std_logic := '0'; - - variable parameter_1: integer := 1234; - variable parameter_2: integer := 2345; - variable parameter_3: integer := 4567; - - -begin - -fprint(RESULT, L, - "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" & - "-----------------------------------------\n\n" & - "This is the result of running the PCK_FIO testbench.\n" & - "This file should be compared with PCK_FIO.out.gold, which is\n" & - "the reference output. Any difference indicates a portability\n" & - "issue or a simulator non-compliance or bug.\n\n" - ); - - -fprint(RESULT, L, - "\n--------------------\n" & - "-- Basic features --\n" & - "--------------------\n\n" - ); - -fprint(RESULT, L, - "-- First some auxiliary declarations\n" - ); - -fprint(RESULT, L, - "> file RESULT: text is out ""PCK_FIO.out"";\n" & - "> variable L: line;\n" & - "> variable BoolTrue: boolean := TRUE;\n" & - "> variable BoolFalse: boolean := FALSE;\n" & - "> variable IntPos: integer := 5678;\n" & - "> variable BigIntPos: integer := 12345678;\n" & - "> variable IntNeg: integer := -8765;\n" & - "> variable BigIntNeg: integer := -87654321;\n" & - "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" & - "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" & - "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" & - "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" & - "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" & - "> variable BitX: std_logic := 'X';\n" & - "> variable Bit1: std_logic := '1';\n" & - "> variable Bit0: std_logic := '0';\n" -); - - -fprint(RESULT, L, - "\n\n-- fprint call with no arguments\n" & - "> fprint(RESULT, L, ""No arguments.\\n);""\n" - ); -fprint(RESULT, L, "No arguments.\n"); - - -fprint(RESULT, L, - "\n-- Special characters need to be escaped\n" & - "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n" - ); - -fprint(RESULT, L, "Special characters: \% \\ "" \n"); - - -fprint(RESULT, L, - "\n-- Various format specifiers interprete the same object differently\n" & - "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n);""\n" & - "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Format specifiers: %r %d %b %q\n", - fo(Uns), fo(Uns), fo(Uns), fo(Uns) - ); - -fprint(RESULT, L, - "\n-- Format string can be shortened by using the iteration specifier\n" & - "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n);""\n" & - "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Iteration specifier: %4{%r }\n", - fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) - ); - - -fprint(RESULT, L, - "\n------------------------------------\n" & - "-- Support for bit-oriented types --\n" & - "------------------------------------\n" - ); - -fprint (RESULT, L, "\n-- Reasonable format\n" & - "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Reasonable format: %9{%r }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Decimal format\n" & - "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Decimal format: %9{%d }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Bit format\n" & - "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Bit format: %9{%b }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint(RESULT, L, - "\n\n" & - "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - -fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); - - - -fprint(RESULT, L, - "\n-------------------------------\n" & - "-- Support for integer types --\n" & - "-------------------------------\n" - ); - -fprint(RESULT, L, - "\n\n" & - "-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" & - "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - - -fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); - - -fprint(RESULT, L, - "\n----------------------\n" & - "-- Support for time --\n" & - "----------------------\n" - ); - -fprint (RESULT, L, "-- For portability reasons, time is converted \n" & - "-- into an integer value (of nanoseconds)\n" - ); -fprint (RESULT, L, "> wait for 648 ns\n"); -fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n"); - -wait for 648 ns; - -fprint (RESULT, L, "The time is now %d ns\n", fo(now)); - - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Erroneous calls and error messages --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" & - "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, "-- Unsupported format specifier\n" & - "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " & - "fo(Uns), fo(Std), fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Things you wouldn't expect to work --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Nested iteration\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n"); -fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); - -wait; - -end process USAGE; - -end TB; diff --git a/lib/PCK_FIO-2002.7/CHANGES b/lib/PCK_FIO-2002.7/CHANGES deleted file mode 100644 index b755a56..0000000 --- a/lib/PCK_FIO-2002.7/CHANGES +++ /dev/null @@ -1,86 +0,0 @@ ----- $Id: CHANGES,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -Changes from version 1.16 to version 2002.07 -============================================ - -PCK_FIO is now distributed under the GNU Lesser General Public Licencse -instead of the ordinary GPL, to better reflect intended usage. - -Cosmetic changes in source code to correct some typos in the testbench output. -A new testbench is also supplied. - -The package now uses IEEE.numeric_std as default. - -URL http://www.easics.com has been made part of address. - -Changed syntax in the PCK_FIO package and its testbench to support VHDL-1993. -Because of backwards-incompatibility, it has been necessary to supply -different sets of files for 1987 and 1993. - -Split the packages into a separate file for the header and a -separate file for the body (in compliance with Easics' guidelines). - -These changes resulted in the files: - -Files for VHDL-1993: --------------------- - PCK_FIO_1993.vhd : the source code of the header file for the package - PCK_FIO_1993_BODY.vhd: the source code of the body of the package - TB_PCK_FIO_1993.vhd: the testbench for the package - -Files for VHDL-1987: --------------------- - PCK_FIO_1987.vhd: the source code of the header file for the package - PCK_FIO_1987_BODY.vhd: the source code of the body of the package - TB_PCK_FIO_1987.vhd: the testbench for the package - -Updated README and PCK_FIO.html to support these changes. - -Adapted package files to support NUL termination of strings. -fo(Arg: string) now prints the string until the first NUL. -Several examples of its use are demonstrated in the supplied testbenches. - -Made cosmetic changes to code to improve readability. - -Acknowledgment --------------- -These changes have been implemented by Peter Geens. - - - - - - - - - - - - - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO.html b/lib/PCK_FIO-2002.7/PCK_FIO.html deleted file mode 100644 index 6b5fc72..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO.html +++ /dev/null @@ -1,339 +0,0 @@ - - - - - - VHDL package for formatted file output - - - - -
-

-Name

-PCK_FIO - VHDL package for  formatted file output -

-

-

-Contents

-Usage -
The file output function 'fo' -
Format specifiers -
Special characters -
Things to watch out for -
Methodology notes -
Parametrization -
Test bench -
Known limitations and problems -
Author -

-

-

-Usage

-PCK_FIO is a VHDL package that defines  fprint, a function -for formatted file output. -

After installing the package you can call fprint as follows: -

  fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));
-where F is the filehandle and L is the line variable. -

The argument Format is the format string, which consists of ``normal'' -substrings which are copied verbatim, and format specifiers, starting with -'%'. -A typical format string looks as follows: -

   "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"
-The remaining arguments are the expressions whose results you want to write -to the file, embedded in fo function calls. There can be 0 to -32 of such arguments. The expressions can be of any type for which an fo -function exists. String expressions can also be called directly. -

-

-

-The file output function 'fo'

-The fo (file output) functions do the trick. They -return a tagged string representation that is meaningful to format specifiers. -Here are some examples: -
  fo (signed'("1100"))   returns "S:1100" 
-  fo (unsigned'("1100")) returns "U:1100" 
-  fo (TRUE)              returns "L:T"
-  fo (127)               returns "I:127"
-The internal behavior of fo is irrelevant to the typical user. -
  -
The fo function is currently overloaded as follows:
- -
  function fo (Arg: unsigned)          return string;
-  function fo (Arg: signed)            return string;
-  function fo (Arg: std_logic_vector)  return string;
-  function fo (Arg: std_ulogic_vector) return string;
-  function fo (Arg: bit_vector)        return string;
-  function fo (Arg: integer)           return string;
-  function fo (Arg: std_ulogic)        return string;
-  function fo (Arg: bit)               return string;
-  function fo (Arg: boolean)           return string; 
-  function fo (Arg: character)         return string;
-  function fo (Arg: string)            return string;
-  function fo (Arg: time)              return string;
- -


To support null-terminated strings, the function fo(Arg: -string) processes Arg up to the first NUL character, -if any. If you want the whole string to be outputted you can just enter -the string as a direct argument in fprint.  See also the -examples in the testbench. -

-
- -

-Format specifiers

-The general format of a format specifier is: -
   %[-][n]c
-The optional - sign specifies left justified output; default is -right justified. -

The optional number n specifies a field-width. If it is not specified, -fprint -does something reasonable. -

c is the conversion specifier. Currently the following conversion -specifiers are supported: -

-
-r
- -
-reasonable output format (inspired by Synopsys VSS)
- -
Prints the ``most reasonable'' representation e.g. hex for -unsigned, signed and other bit-like vectors (not preferred for integers)
- -
-b
- -
-bit-oriented output
- -
-d
- -
-decimal output
- -
-s
- -
-string output (e.g. in combination with 'IMAGE for enum types)
- -
-q
- -
-``qualified'' string output (shows internal representation from fo)
- -
-{}
- -
-Iteration operator, used as follows:
- -
-%n{<format-string>}
- -
In this case, n is the iteration count and is mandatory. Iteration -can be nested.
- -
-

-Special characters

-To print a double quote,  use '""' in the format string (VHDL -convention). To print the special characters, '\', and '%', -escape them with '\'. To prevent '{' and '}' -from being interpreted as opening and closing brackets in iteration strings, -escape them with '\'. -

A newline is specified in the format string by '\n'. -

-

-

-Things to notice

-The fprint function expands into VHDL write and writeline -commands. As in plain VHDL, nothing will be written to the output file -until a writeline is given. Therefore, don't forget to include -'\n' -commands in the format string, or it ``will not work''. -

The preferred format specifier for integers is, naturally, %d. -This calls the VHDL write for integers. If you specify a field -width that is too small, the field will automatically be expanded. If you -use %r for integers, the field is not expanded automatically, which -means that some digits are simply thrown away. This may sometimes be useful -but it is also dangerous. Look at the test bench output for differences -between %d and %r output. -

When using the %d format specifier, the VHDL constraints for -the allowed integer range apply. -

In VHDL, signed/unsigned types have been standardized only relatively -recently, in the package IEEE.numeric_std. The lack of a standard -has caused (and is causing) portability issues. The most popular non-standard -package that defines signed/unsigned is IEEE.std_logic_arith from -Synopsys. PCK_FIO works with both packages,  but refers to the standard -package IEEE.numeric_std by default. To use IEEE.std_logic_arith -instead, replace the reference to IEEE.numeric_std in the source -code.  This needs to be done consistently in a design database (e.g. -in the PCK_FIO test bench as well). -

-

-

-Methodology notes

-The obvious application for fprint is in test benches, to produce -output files that trace the simulation behavior. -

Another interesting application for fprint is to produce info, -warning and error messages in your models. As it can take arguments, fprint -is much better suited for this task than VHDL's assert or report -statements. Actually fprint produces its own (few) warning messages. -

An advanced usage is the generation of test vectors in a specific format. -Instead of using the fo functions, you can write your own set -of functions that return the symbols of a specific test format in a way -that is understandable to the fprint format specifiers. As an -example, when a high output value should be represented using the symbol -'H' it suffices to write a conversion function that returns "B:H" and call -it in combination with the %b format specifier. -

-

-

-Parametrization

-Prefix and postfix strings for bit-oriented and hex-oriented output are -parameterizable in the packages to accommodate different output styles. -The settings in the distribution are such that hex output is indicated -by the prefix '0x', while  bit output prefix and postfix are empty -strings. -

You can adapt the output style by modifying the following constants -in the package header: -

   -- prefix string for hex output -
  -- VHDL style:    "X""" -
  -- Verilog style: "h'" -
  -- C style:       "0x" -
  constant FIO_h_PRE:  string := "0x"; -

  -- postfix string for hex output -
  -- VHDL style:    """" -
  constant FIO_h_POST: string := ""; -

  -- prefix string for bit vector output -
  -- VHDL style:    "B""" -
  -- Verilog style: "b'" -
  constant FIO_bv_PRE:  string := ""; -

  -- postfix string for bit vector output -
  -- VHDL style:    """" -
  constant FIO_bv_POST: string := ""; -

  -- prefix string for bit output -
  -- VHDL style:    "'" -
  -- Verilog style: "b'" -
  constant FIO_b_PRE:  string := ""; -

  -- postfix string for bit output -
  -- VHDL style:    "'" -
  constant FIO_b_POST: string := ""; -

-

-

-Test bench

-Included in the distribution are the files TB_PCK_FIO_1987.vhd and -TB_PCK_FIO_1993 with a test bench,depending on the standard you're -running, for the PCK_FIO package. The file PCK_FIO.out.gold contains -the expected output. If you run the test bench it should produce the file -PCK_FIO.out -that should be identical to PCK_FIO.out.gold. The source files -should be analyzed in a VHDL library EASICS_PACKAGES. -

A good way to understand fprint is to inspect the test bench -and what it produces. -

-

-

-Known limitations and problems

-This VHDL package is an implementation of a flexible concept. It is likely -to be extended and modified in the future. Backward compatibility is not -guaranteed. Therefore, it is not recommended to give this package the status -of a company wide standard package (or even worse, a VHDL standard package). -Rather, it should be linked with a particular project (and it can be regarded -as a standard package within that project). -

PCK_FIO is available in either standard VHDL Std1076-1987 or standard -VHDL Std1076-1993. Nevertheless, some simulators/versions have problems -with the package. The following is an overview of currently known issues: -
  -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PCK_FIO_1987 and various simulators/versions
SimulatorPCK_FIO_1987
Synopsys VSS 3.5 and earlierIncorrect (all zero) output in compiled mode
Synopsys VSS 97.01OK
Synopsys VSS/Scirocco 2000.02Incorrect output in compiled mode, interpreted mode works
Mentor quickhdlOK
Modeltech modelsimOK
Cadence LeapfrogShould work with 4.4.1 -
Mysterious problems have been reported - please run the test bench -and report problems
- -
  -
- - - - - - - - - - - - - - - - - - - - - - - - - -
PCK_FIO_1993 and various simulators/versions
SimulatorPCK_FIO_1993
Synopsys VSS/Scirocco 2000.02Compile errors due to improper handling of files by Synopsys
Synopsys VSS/Scirocco 2000.06works fine
Modeltech modelsim 5.4c and higherOK
- -

Although the package name suggests file IO, it only does file output. -

-

-

-Author

-Jan Decaluwe -

-

- - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO.out.gold b/lib/PCK_FIO-2002.7/PCK_FIO.out.gold deleted file mode 100644 index 3fcfe4c3ee52eaf461a691b4b3eca59aa1cc34dc..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8979 zcmd5?ZExa8628y;iV{*T$qGl1SBA@FmCPi%(M6ePLS{#&(MARu;vHkNw#kbo```De z>TcWMb^@n6-63KcQ%`lhc9*Mj{r;bK7au?E#Ph62{qvjt+4V?OH96NxmINI zwbTArg~?4e%9*6u=q`*W!SL=u4H0?E5-tA@$yltaWH-SicZ6FxefKp6xz*ob;I_?K zkbSj!Z;u$^0mzzM9T%vIOf(k5c*Md7Gza@0;{j zy1Ko@wfW)v0-3@oOye17GaC9~s27(gCO?_Xrz*-M{p9y8oqR32Y*F*7M6vTN;<#A2 zC46sYY8dz-4eyc5!%QV9MG6ZT0u1Y!N{9YTjX1rl{HxF&ecPaK->6A?Iu`{9@Vm_Y z1q(ntPiY({Qy=RKi!u&a1Wt`)mZ(h0>YMsldE&uuh_`%w%))24SQpFOdbE+y#)vis zwDCIxYXMh%jpHrk+ja}m)C_VM4C$Dp{dBNP-CZ)FMz=jP5?w7oyLyO44Cckgkz@*4 zO@n8er*^XmpuDWBg-P71eykEg+5I2T_m7nn)hVcz#u(XT#@T4Qtgdq+QMmoo*`;E{ zy1x3t?|tl{tf~q7sUHP1-o&tx)NDc}j==LC%=l3psgl(UyCSiu=gKFRkU4PFNuDX} zvfvg(Mj&@KAu0;a+lT;UDmY1G@@CIF+&FHfv1BKI;~X}kI=xq7C*1ymY-izuF~@v@ ztrmZwO4D*~LP{ zY}9Bz9pF2P%F;S(TxQ}{FR<(~cAY5+#UqA5%)`v4@Z)qoUE;>8Hdg8y9pCcIuG2I1 zetFww`xTpko3&Uep=*Y0h@1J0%U;RUL6CWI5@5IE&FOhoU$HJTWRuWm<)?8Z)h6;D zyNx?SD`Z$s-@UngIH|o~a+vxjt?e@b(hUUX{i5Z#dxA-PC?lzTIXNS~F%d%OZ zfBu;|^p)_Oq&MIX*l-c5Y~WgxEYiRpM?bKazPi2qukEoca;Gc%a+kdQL-IPXfn3_! z2r%}m1}J{l$`Ag(l`o5H>h8QGS^nP9#l8eZhu9vRE2klzG`OzhFTCnuZ$|kg+maNZ zJ=!`RrzhAi{b(fRo2*khii(gDiRZlW}gKIMe`h#KJ(ZZm@XNf(y{% zNaLA7)uSEmPIPx)I$eHam3LWWcNL;N>2rV;ff4`JFx%Jt5GE8#xzx}eXj&E!=3~C* zT0?(m=ncRi%tsC8$YLzWqU>i4uAAd>phZ|wiMLIcLEjbF0$iYrk;Yfu=B?y6Zzach z;yFBiBLehajntmF4unEwE}(UXrudGDHKDySy&E9T6M&)3KLq0jiT5%9Pb$*df@r!Lj>#y86hJ%)1`7$CnS{+!dB^tQ~ zw6vTU>>A+mdScNAPOB)~X_pqHoPp&~u+Vpm(Uz^|8EZ41*08o`%q=(rL?)TTg4g`y z8GCD_g|3J-1~=Foydv6I+@cG3fj9TuA?6vA=L||5N-Rn|WFc7!R9&c&oWK~1o3VRV zQ>a=1@gd6#$)U`Pci_g@LNx~&ls?OO@eXTnd7)YW4KnvEW_Qn76sje#L9Y@RopxU7 zmKhihMLc_Q$H-8PXTyYjWUb4y+i?Y8%_~mTRPdSztiSD7*BZ~-S4V{Vxk}YEj$K zX6g&Hpi2k4ID6(URoWtfqLGN>q6dW|f)V#F`BVf)I^65kr^i6sHQ* zqm*}`M_>0e=y1PF`gB$wA1#~@_0dbT6GibOACW{U9~+<@vV|MmGFBbbe zNzke1$80{mLd!WCk;1)%rs!__lhs>!Jg2lMF1an9AAh0y0ITTs1Ddb-F_OFe05$Ws z)iyu*;r0U5Mpc9|vhmYT^oyTx*Stsgr-Qp|K7+gT)9edd9`}}xnsBD`3?EPkl3YCI z!tHt69x;c0&0Gi!Acv5l&Rl+JJO3(bLrmQgRim7p)wV`ioP0gV`B&o9b@8~%XfKaq zZskuCnBq24Pned&(kf-8pv{L(t%*zH1!3wGM#^~JulmvJVqqv-$tahvMCo=NRT>t<8 diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd deleted file mode 100644 index d4cf8e6..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd +++ /dev/null @@ -1,105 +0,0 @@ ----- $Id: PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - -use STD.TEXTIO.all; - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one -use IEEE.numeric_std.all; - -package PCK_FIO is - - -- prefix string for hex output - -- VHDL style: "X""" - -- Verilog style: "h'" - -- C style: "0x" - constant FIO_h_PRE: string := "0x"; - - -- postfix string for hex output - -- VHDL style: """" - constant FIO_h_POST: string := ""; - - -- prefix string for bit vector output - -- VHDL style: "B""" - -- Verilog style: "b'" - constant FIO_bv_PRE: string := ""; - - -- postfix string for bit vector output - -- VHDL style: """" - constant FIO_bv_POST: string := ""; - - -- prefix string for bit output - -- VHDL style: "'" - -- Verilog style: "b'" - constant FIO_b_PRE: string := ""; - - -- postfix string for bit output - -- VHDL style: "'" - constant FIO_b_POST: string := ""; - - -- digit width for the string representation of integers - constant FIO_d_WIDTH: integer := 10; - - -- bit width for the string representation of integers - constant FIO_b_WIDTH: integer := 32; - - -- definition of the NIL string (default value for fprint arguments) - -- fprint stops consuming arguments at the first NIL argument - constant FIO_NIL: string := "\"; - - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ); - - function fo (Arg: unsigned) return string; - function fo (Arg: signed) return string; - function fo (Arg: std_logic_vector) return string; - function fo (Arg: std_ulogic_vector) return string; - function fo (Arg: bit_vector) return string; - function fo (Arg: integer) return string; - function fo (Arg: std_ulogic) return string; - function fo (Arg: bit) return string; - function fo (Arg: boolean) return string; - function fo (Arg: character) return string; - function fo (Arg: string) return string; - function fo (Arg: time) return string; - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive); - -end PCK_FIO; - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd deleted file mode 100644 index 44e42cf..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd +++ /dev/null @@ -1,821 +0,0 @@ ----- $Id: PCK_FIO_1987_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -package body PCK_FIO is - - -------------------------- - -- FIO Warnings support -- - -------------------------- - - procedure FIO_Warning_Fsbla (F: out text; - L: inout line; - Format: in string; - Pointer: in positive) is - begin - fprint (F, L, "\n** Warning: FIO_PrintLastValue: " & - "Format specifier beyond last argument\n"); - fprint (F, L, "** in format string: ""%s""\n", Format); - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n"); - end FIO_Warning_Fsbla; - - procedure FIO_Warning_Ufs (F: out text; - L: inout line; - Format: in string; - Pointer: in positive; - Char: in character) is - begin - fprint (F, L, "\n** Warning: FIO_PrintArg: " & - "Unexpected format specifier '%r'\n", - fo(Char)); - fprint (F, L, "** in format string: ""%s""\n", Format) ; - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n** Assuming 'q' to proceed: "); - end FIO_Warning_Ufs; - - - ---------------------------------- - -- bit conversion support -- - ---------------------------------- - - type T_bit_map is array(bit) of character; - - constant C_BIT_MAP: T_bit_map - := ('0', '1'); - - ---------------------------------- - -- std_logic conversion support -- - ---------------------------------- - - type T_std_logic_map is array(std_ulogic) of character; - - constant C_STD_LOGIC_MAP: T_std_logic_map - := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); - - ------------------------------ - -- Digit conversion support -- - ------------------------------ - - -- types & constants - - subtype S_digit_chars is character range '0' to '9'; - subtype S_digits is integer range 0 to 9 ; - - type T_digit_chars_map is array(S_digit_chars) of S_digits; - - constant C_DIGIT_CHARS_MAP: T_digit_chars_map - := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9); - - type T_digits_map is array(S_digits) of S_digit_chars; - - constant C_DIGITS_MAP: T_digits_map - := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9'); - - - -------------------------------- - -- Decimal conversion support -- - -------------------------------- - - -- unsigned to decimal - - function U_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - for i in Argument'range loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(-1); - end case; - end loop; - return (Result); - end U_To_d; - - -- signed to decimal - - function S_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - case Argument(Argument'left) is - when '1' => Result := - 2**(Argument'left-1); - when '0' => Result := 0; - when others => return (integer'low); - end case; - for i in Argument'left-1 downto 1 loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(integer'low); - end case; - end loop; - return (Result); - end S_To_d; - - -- string to decimal - - function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is - constant Sign: character := Arg(1); - constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length); - variable Char: character; - variable Result: integer := 0; - begin - Result := 0; - for i in Value'range loop - Result := Result * 10; - Char := Value(i); - if (Char /= ' ') then - Result := Result + C_DIGIT_CHARS_MAP(Char); - end if; - end loop; - case Sign is when '-' => return(-Result); - when others => return(Result); - end case; - end I_To_d; - - -- boolean (0,1) to decimal - - function B_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "1" => return(1); - when "0" => return(0); - when others => return(-1); - end case; - end B_To_d; - - -- boolean (T,F) to decimal - - function L_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "T" => return(1); - when others => return(0); - end case; - end L_To_d; - - - - ---------------------------- - -- Hex conversion support -- - ---------------------------- - - -- Constants & types - - constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?"; - - -- Function to return Hex index of a nibble - - function U_To_h_Index(Arg: string(4 downto 1)) return integer is - variable Index: integer := 0; - begin - for i in Arg'range loop - case Arg(i) is when '1' => Index := 2**(i-1) + Index; - when '0' => null; - when others => return (17); - end case; - end loop; - return (Index+1); - end U_To_h_Index; - - -- Hex conversion - - function U_To_h (Arg: string) return string is - variable Result: string((Arg'length-1)/4 +1 downto 1); - variable ExtArg: string(Result'length*4 downto 1) := (others => '0'); - begin - ExtArg(Arg'length downto 1) := Arg; - for i in Result'range loop - Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) )); - end loop; - return (FIO_h_PRE & Result & FIO_h_POST); - end U_To_h; - - - - ---------------------------- - -- Bit conversion support -- - ---------------------------- - - function L_To_b (Arg: string(1 to 1)) return string is - variable Result: string(1 to 1); - begin - case Arg is when "T" => Result := "1"; - when others => Result := "0"; - end case; - return(FIO_b_PRE & Result & FIO_b_POST); - end L_To_b; - - - function I_To_b (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - - variable IntValue: integer := I_To_d(Arg); - variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' '); - variable Sign: character := ' '; - constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' '); - variable BitWidth: integer range 0 to FIO_b_WIDTH; - variable MsPos: integer range 1 to BitValue'length; - variable BitValueExtended: string(1 to 2*FIO_b_WIDTH); - - begin - - if (IntValue < 0) then - Sign := '-'; - IntValue := -IntValue; - end if; - - for i in BitValue'reverse_range loop - BitValue(i) := C_DIGITS_MAP(IntValue mod 2); - IntValue := IntValue / 2; - exit when (IntValue = 0); - end loop; - - BitValueExtended := BitValue & Blanks; - - if (Width = 0) or (Width > FIO_b_WIDTH+1) then - BitWidth := FIO_b_WIDTH; - else - BitWidth := Width-1; - end if; - - if (Justified = RIGHT) then - return (FIO_bv_PRE & - Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) & - FIO_bv_POST); - else - for i in BitValue'range loop - if BitValue(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (FIO_bv_PRE & - Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) & - FIO_bv_POST); - end if; - - end I_To_b; - - - ----------------------------------- - -- Reasonable conversion support -- - ----------------------------------- - - function I_To_r (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1); - constant Sign: character := Arg(1); - constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' '); - variable IntWidth: integer range 0 to FIO_d_WIDTH; - variable MsPos: integer range 1 to Value'length; - variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks; - begin - if (Width = 0) or (Width > FIO_d_WIDTH+1) then - IntWidth := FIO_d_WIDTH; - else - IntWidth := Width-1; - end if; - if (Justified = RIGHT) then - return (Sign & Value(Value'length-IntWidth+1 to Value'length)); - else - for i in Value'range loop - if Value(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1)); - end if; - end I_To_r; - - - ------------------------------------------- - -- Reasonable output conversion function -- - ------------------------------------------- - - function ReasonableOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return U_To_h(Value); - when "I:" => - return I_To_r(Value, Justified, Width); - when "B:" | "L:" | "C:" => - return Value; - when others => - return Argument; - end case; - - end ReasonableOutput; - - - ------------------------------------ - -- Bit output conversion function -- - ------------------------------------ - - function BitOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return (FIO_bv_PRE & Value & FIO_bv_POST); - when "B:" => - -- Value(1 to 1) instead of Value for LeapFrog - return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST); - when "I:" => - return I_To_b(Value, Justified, Width); - when "L:" => - -- Value(1 to 1) instead of Value for LeapFrog - return L_To_b(Value(1 to 1)); - when others => - return Argument; - end case; - - end BitOutput; - - - ------------------------------------------- - -- Decimal output conversion function -- - ------------------------------------------- - - function DecimalOutput (Arg: string) return integer is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:"| "V:" => - return U_To_d(Value); - when "S:" => - return S_To_d(Value); - when "I:" => - return I_To_d(Value); - when "B:" => - return B_To_d(Value); - when "L:" => - return L_To_d(Value); - when others => - return integer'low; - end case; - - end DecimalOutput; - - - ---------------------------- - -- Atomic print functions -- - ---------------------------- - - -- test for end of format string - - function FIO_EOS (Format: in string; - Pointer: in integer) - return boolean is - begin - return (Pointer > Format'length); - end FIO_EOS; - - - -- Atomic value print function - - procedure FIO_PrintValue (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Last: in boolean := FALSE) is - variable Char: character; - begin - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '\' => - Pointer := Pointer + 1; - exit when (FIO_EOS(Format, Pointer)); - Char := Format(Pointer); - case Char is when 'n' => writeline(F, L); - when others => write(L, Char); - end case; - when '%' => - if Last then - FIO_Warning_Fsbla(F, L, Format, Pointer); - end if; - Pointer := Pointer + 1; - exit; - when others => - write(L, char); - end case; - Pointer := Pointer + 1; - end loop; - end FIO_PrintValue; - - - ---- Atomic argument print function - - procedure FIO_PrintArg (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Arg: in string) is - variable Char: character; - variable Justified: side; - variable Width: integer; - begin - - FIO_PrintValue(F, L, Format, Pointer); - - Justified := RIGHT; - Width := 0; - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '-' => - Justified := LEFT; - Pointer := Pointer + 1; - when '0' to '9' => - Width := Width*10 + C_DIGIT_CHARS_MAP(Char); - Pointer := Pointer + 1; - when 'r' => - write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'b' => - write(L, BitOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'd' => - write(L, DecimalOutput(Arg), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'q' | 's' => - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - when others => - FIO_Warning_Ufs(F, L, Format, Pointer, Char); - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - end case; - end loop; - end FIO_PrintArg; - - - ----------------------------------------------------- - -- The format string iteration expansion procedure -- - ----------------------------------------------------- - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive) is - - variable Pointer: positive := StartPointer; - variable TokenStart: positive; - variable IterStringStart: positive; - variable IterStringEnd: positive; - variable IterCount: natural; - variable OpenBrackets: natural; - variable L: line; - - begin - - FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- look for format specifier - when '%' => - - -- initialize iteration token search - TokenStart := Pointer; - IterCount := 0; - Pointer := Pointer + 1; - - -- start iteration token search - TOKEN_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- read iteration counter - when '0' to '9' => - IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer)); - Pointer := Pointer + 1; - - -- expect open bracket - when '{' => - - -- initialize iteration string read - OpenBrackets := 1; - IterStringStart := Pointer + 1; - Pointer := Pointer + 1; - -- quit prematurely when iteration count is 0 - next FORMAT_SEARCH when (IterCount = 0); - - -- start iteration string read - ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - -- keep track of open brackets - when '{' => - OpenBrackets := OpenBrackets + 1; - Pointer := Pointer + 1; - -- when closing bracket is found, process iteration string - when '}' => - OpenBrackets := OpenBrackets - 1; - if (OpenBrackets = 0) then - IterStringEnd := Pointer-1; - if (TokenStart /= 1) then - write(L, Format(1 to TokenStart-1)); - end if; - for i in 1 to IterCount loop - write(L, Format(IterStringStart to IterStringEnd)); - end loop; - if (IterStringEnd /= Format'length) then - write(L, Format(IterStringEnd+2 to Format'length)); - end if; - -- call expansion procedure recursively on expanded format - FIO_FormatExpand(FMT, L.all, TokenStart); - deallocate(L); - return; - end if; - Pointer := Pointer + 1; - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - -- read iteration string - when others => - Pointer := Pointer + 1; - - end case; - - end loop ITER_STRING_READ; - - -- stop iteration token search when no opening bracket found - when others => - Pointer := Pointer + 1; - next FORMAT_SEARCH; - - end case; - - end loop TOKEN_READ; - - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - - -- read other characters - when others => - Pointer := Pointer + 1; - - end case; - - end loop FORMAT_SEARCH; - - write(FMT, Format); - deallocate(L); - - end FIO_FormatExpand; - - - - -------------------------- - -- The fprint procedure -- - -------------------------- - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ) is - - variable Pointer: integer; - variable FMT: line; - - begin - - Pointer := 1; - - FIO_FormatExpand (FMT, Format, Format'low); - - if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 ); - if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 ); - if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 ); - if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 ); - if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 ); - if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 ); - if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 ); - if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 ); - if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 ); - if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10); - if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11); - if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12); - if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13); - if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14); - if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15); - if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16); - if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17); - if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18); - if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19); - if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20); - if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21); - if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22); - if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23); - if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24); - if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25); - if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26); - if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27); - if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28); - if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29); - if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30); - if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31); - if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32); - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - - FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE); - - deallocate(FMT); - - end fprint; - - - ------------------------------------------- - -- Formatted output conversion functions -- - ------------------------------------------- - - function fo (Arg: unsigned) return string is - constant Argument: unsigned(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("U:" & Result); - end fo; - - function fo (Arg: signed) return string is - constant Argument: signed(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("S:" & Result); - end fo; - - function fo (Arg: std_logic_vector) return string is - constant Argument: std_logic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: std_ulogic_vector) return string is - constant Argument: std_ulogic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: bit_vector) return string is - constant Argument: bit_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_BIT_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: integer) return string is - variable Argument: integer := Arg; - variable Result: string(1 to FIO_d_WIDTH) := (others => ' '); - variable Sign: character := ' '; - begin - if (Argument < 0) and (Argument /= integer'low) then - Sign := '-'; - Argument := -Argument; - end if; - for i in Result'reverse_range loop - Result(i) := C_DIGITS_MAP(Argument mod 10); - Argument := Argument / 10; - exit when (Argument = 0); - end loop; - return ("I:" & Sign & Result); - end fo; - - function fo (Arg: std_ulogic) return string is - begin - return ("B:" & C_STD_LOGIC_MAP(Arg)); - end fo; - - function fo (Arg: bit) return string is - begin - return ("B:" & C_BIT_MAP(Arg)); - end fo; - - function fo (Arg: boolean) return string is - begin - if (ARG = TRUE) then - return ("L:T"); - else - return ("L:F"); - end if; - end fo; - - function fo (Arg: character) return string is - begin - return ("C:" & Arg); - end fo; - - -- auxilary function fgets(Arg: string) - -- gives index until first NUL - -- reads string from 1 to Arg'length - function fgets (Arg: string) return integer is - variable index: integer := Arg'length; - begin - for i in 1 to Arg'length loop - if Arg(i) = NUL then - index := i - 1; - exit; - else - null; - end if; - end loop; - return index; - end fgets; - - function fo (Arg: string) return string is - begin - return Arg(1 to fgets(Arg)); - end fo; - - function fo (Arg: time) return string is - begin - return fo (integer (Arg / 1 ns)); - end fo; - -end PCK_FIO; - - - - - - - - - - - - - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd deleted file mode 100644 index 9df893e..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd +++ /dev/null @@ -1,108 +0,0 @@ ----- $Id: PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -use STD.TEXTIO.all; - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one -use IEEE.numeric_std.all; - -package PCK_FIO is - - - -- prefix string for hex output - -- VHDL style: "X""" - -- Verilog style: "h'" - -- C style: "0x" - constant FIO_h_PRE: string := "0x"; - - -- postfix string for hex output - -- VHDL style: """" - constant FIO_h_POST: string := ""; - - -- prefix string for bit vector output - -- VHDL style: "B""" - -- Verilog style: "b'" - constant FIO_bv_PRE: string := ""; - - -- postfix string for bit vector output - -- VHDL style: """" - constant FIO_bv_POST: string := ""; - - -- prefix string for bit output - -- VHDL style: "'" - -- Verilog style: "b'" - constant FIO_b_PRE: string := ""; - - -- postfix string for bit output - -- VHDL style: "'" - constant FIO_b_POST: string := ""; - - -- digit width for the string representation of integers - constant FIO_d_WIDTH: integer := 10; - - -- bit width for the string representation of integers - constant FIO_b_WIDTH: integer := 32; - - -- definition of the NIL string (default value for fprint arguments) - -- fprint stops consuming arguments at the first NIL argument - constant FIO_NIL: string := "\"; - - procedure fprint - (file F: text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ); - - function fo (Arg: unsigned) return string; - function fo (Arg: signed) return string; - function fo (Arg: std_logic_vector) return string; - function fo (Arg: std_ulogic_vector) return string; - function fo (Arg: bit_vector) return string; - function fo (Arg: integer) return string; - function fo (Arg: std_ulogic) return string; - function fo (Arg: bit) return string; - function fo (Arg: boolean) return string; - function fo (Arg: character) return string; - function fo (Arg: string) return string; - function fo (Arg: time) return string; - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive); - -end PCK_FIO; - - - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd deleted file mode 100644 index 3d123f0..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd +++ /dev/null @@ -1,814 +0,0 @@ ----- $Id: PCK_FIO_1993_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - - package body PCK_FIO is - - -------------------------- - -- FIO Warnings support -- - -------------------------- - - procedure FIO_Warning_Fsbla (file F: text; - L: inout line; - Format: in string; - Pointer: in positive) is - begin - fprint (F, L, "\n** Warning: FIO_PrintLastValue: " & - "Format specifier beyond last argument\n"); - fprint (F, L, "** in format string: ""%s""\n", Format); - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n"); - end FIO_Warning_Fsbla; - - procedure FIO_Warning_Ufs (file F: text; - L: inout line; - Format: in string; - Pointer: in positive; - Char: in character) is - begin - fprint (F, L, "\n** Warning: FIO_PrintArg: " & - "Unexpected format specifier '%r'\n", - fo(Char)); - fprint (F, L, "** in format string: ""%s""\n", Format) ; - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n** Assuming 'q' to proceed: "); - end FIO_Warning_Ufs; - - - ---------------------------------- - -- bit conversion support -- - ---------------------------------- - - type T_bit_map is array(bit) of character; - - constant C_BIT_MAP: T_bit_map - := ('0', '1'); - - ---------------------------------- - -- std_logic conversion support -- - ---------------------------------- - - type T_std_logic_map is array(std_ulogic) of character; - - constant C_STD_LOGIC_MAP: T_std_logic_map - := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); - - ------------------------------ - -- Digit conversion support -- - ------------------------------ - - -- types & constants - - subtype S_digit_chars is character range '0' to '9'; - subtype S_digits is integer range 0 to 9 ; - - type T_digit_chars_map is array(S_digit_chars) of S_digits; - - constant C_DIGIT_CHARS_MAP: T_digit_chars_map - := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9); - - type T_digits_map is array(S_digits) of S_digit_chars; - - constant C_DIGITS_MAP: T_digits_map - := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9'); - - - -------------------------------- - -- Decimal conversion support -- - -------------------------------- - - -- unsigned to decimal - - function U_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - for i in Argument'range loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(-1); - end case; - end loop; - return (Result); - end U_To_d; - - -- signed to decimal - - function S_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - case Argument(Argument'left) is - when '1' => Result := - 2**(Argument'left-1); - when '0' => Result := 0; - when others => return (integer'low); - end case; - for i in Argument'left-1 downto 1 loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(integer'low); - end case; - end loop; - return (Result); - end S_To_d; - - -- string to decimal - - function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is - constant Sign: character := Arg(1); - constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length); - variable Char: character; - variable Result: integer := 0; - begin - Result := 0; - for i in Value'range loop - Result := Result * 10; - Char := Value(i); - if (Char /= ' ') then - Result := Result + C_DIGIT_CHARS_MAP(Char); - end if; - end loop; - case Sign is when '-' => return(-Result); - when others => return(Result); - end case; - end I_To_d; - - -- boolean (0,1) to decimal - - function B_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "1" => return(1); - when "0" => return(0); - when others => return(-1); - end case; - end B_To_d; - - -- boolean (T,F) to decimal - - function L_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "T" => return(1); - when others => return(0); - end case; - end L_To_d; - - - - ---------------------------- - -- Hex conversion support -- - ---------------------------- - - -- Constants & types - - constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?"; - - -- Function to return Hex index of a nibble - - function U_To_h_Index(Arg: string(4 downto 1)) return integer is - variable Index: integer := 0; - begin - for i in Arg'range loop - case Arg(i) is when '1' => Index := 2**(i-1) + Index; - when '0' => null; - when others => return (17); - end case; - end loop; - return (Index+1); - end U_To_h_Index; - - -- Hex conversion - - function U_To_h (Arg: string) return string is - variable Result: string((Arg'length-1)/4 +1 downto 1); - variable ExtArg: string(Result'length*4 downto 1) := (others => '0'); - begin - ExtArg(Arg'length downto 1) := Arg; - for i in Result'range loop - Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) )); - end loop; - return (FIO_h_PRE & Result & FIO_h_POST); - end U_To_h; - - - - ---------------------------- - -- Bit conversion support -- - ---------------------------- - - function L_To_b (Arg: string(1 to 1)) return string is - variable Result: string(1 to 1); - begin - case Arg is when "T" => Result := "1"; - when others => Result := "0"; - end case; - return(FIO_b_PRE & Result & FIO_b_POST); - end L_To_b; - - - function I_To_b (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - - variable IntValue: integer := I_To_d(Arg); - variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' '); - variable Sign: character := ' '; - constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' '); - variable BitWidth: integer range 0 to FIO_b_WIDTH; - variable MsPos: integer range 1 to BitValue'length; - variable BitValueExtended: string(1 to 2*FIO_b_WIDTH); - - begin - - if (IntValue < 0) then - Sign := '-'; - IntValue := -IntValue; - end if; - - for i in BitValue'reverse_range loop - BitValue(i) := C_DIGITS_MAP(IntValue mod 2); - IntValue := IntValue / 2; - exit when (IntValue = 0); - end loop; - - BitValueExtended := BitValue & Blanks; - - if (Width = 0) or (Width > FIO_b_WIDTH+1) then - BitWidth := FIO_b_WIDTH; - else - BitWidth := Width-1; - end if; - - if (Justified = RIGHT) then - return (FIO_bv_PRE & - Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) & - FIO_bv_POST); - else - for i in BitValue'range loop - if BitValue(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (FIO_bv_PRE & - Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) & - FIO_bv_POST); - end if; - - end I_To_b; - - - ----------------------------------- - -- Reasonable conversion support -- - ----------------------------------- - - function I_To_r (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1); - constant Sign: character := Arg(1); - constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' '); - variable IntWidth: integer range 0 to FIO_d_WIDTH; - variable MsPos: integer range 1 to Value'length; - variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks; - begin - if (Width = 0) or (Width > FIO_d_WIDTH+1) then - IntWidth := FIO_d_WIDTH; - else - IntWidth := Width-1; - end if; - if (Justified = RIGHT) then - return (Sign & Value(Value'length-IntWidth+1 to Value'length)); - else - for i in Value'range loop - if Value(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1)); - end if; - end I_To_r; - - - ------------------------------------------- - -- Reasonable output conversion function -- - ------------------------------------------- - - function ReasonableOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return U_To_h(Value); - when "I:" => - return I_To_r(Value, Justified, Width); - when "B:" | "L:" | "C:" => - return Value; - when others => - return Argument; - end case; - - end ReasonableOutput; - - - ------------------------------------ - -- Bit output conversion function -- - ------------------------------------ - - function BitOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return (FIO_bv_PRE & Value & FIO_bv_POST); - when "B:" => - -- Value(1 to 1) instead of Value for LeapFrog - return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST); - when "I:" => - return I_To_b(Value, Justified, Width); - when "L:" => - -- Value(1 to 1) instead of Value for LeapFrog - return L_To_b(Value(1 to 1)); - when others => - return Argument; - end case; - - end BitOutput; - - - ------------------------------------------- - -- Decimal output conversion function -- - ------------------------------------------- - - function DecimalOutput (Arg: string) return integer is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:"| "V:" => - return U_To_d(Value); - when "S:" => - return S_To_d(Value); - when "I:" => - return I_To_d(Value); - when "B:" => - return B_To_d(Value); - when "L:" => - return L_To_d(Value); - when others => - return integer'low; - end case; - - end DecimalOutput; - - - ---------------------------- - -- Atomic print functions -- - ---------------------------- - - -- test for end of format string - - function FIO_EOS (Format: in string; - Pointer: in integer) - return boolean is - begin - return (Pointer > Format'length); - end FIO_EOS; - - - -- Atomic value print function - - procedure FIO_PrintValue (file F: text; - L: inout line; - Format: in string; - Pointer: inout integer; - Last: in boolean := FALSE) is - variable Char: character; - begin - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '\' => - Pointer := Pointer + 1; - exit when (FIO_EOS(Format, Pointer)); - Char := Format(Pointer); - case Char is when 'n' => writeline(F, L); - when others => write(L, Char); - end case; - when '%' => - if Last then - FIO_Warning_Fsbla(F, L, Format, Pointer); - end if; - Pointer := Pointer + 1; - exit; - when others => - write(L, char); - end case; - Pointer := Pointer + 1; - end loop; - end FIO_PrintValue; - - - ---- Atomic argument print function - - procedure FIO_PrintArg (file F: text; - L: inout line; - Format: in string; - Pointer: inout integer; - Arg: in string) is - variable Char: character; - variable Justified: side; - variable Width: integer; - - begin - - FIO_PrintValue(F, L, Format, Pointer); - - Justified := RIGHT; - Width := 0; - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '-' => - Justified := LEFT; - Pointer := Pointer + 1; - when '0' to '9' => - Width := Width*10 + C_DIGIT_CHARS_MAP(Char); - Pointer := Pointer + 1; - when 'r' => - write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'b' => - write(L, BitOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'd' => - write(L, DecimalOutput(Arg), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'q' | 's' => - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - when others => - FIO_Warning_Ufs(F, L, Format, Pointer, Char); - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - end case; - end loop; - end FIO_PrintArg; - - - ----------------------------------------------------- - -- The format string iteration expansion procedure -- - ----------------------------------------------------- - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive) is - - variable Pointer: positive := StartPointer; - variable TokenStart: positive; - variable IterStringStart: positive; - variable IterStringEnd: positive; - variable IterCount: natural; - variable OpenBrackets: natural; - variable L: line; - - begin - - FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- look for format specifier - when '%' => - - -- initialize iteration token search - TokenStart := Pointer; - IterCount := 0; - Pointer := Pointer + 1; - - -- start iteration token search - TOKEN_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- read iteration counter - when '0' to '9' => - IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer)); - Pointer := Pointer + 1; - - -- expect open bracket - when '{' => - - -- initialize iteration string read - OpenBrackets := 1; - IterStringStart := Pointer + 1; - Pointer := Pointer + 1; - -- quit prematurely when iteration count is 0 - next FORMAT_SEARCH when (IterCount = 0); - - -- start iteration string read - ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - -- keep track of open brackets - when '{' => - OpenBrackets := OpenBrackets + 1; - Pointer := Pointer + 1; - -- when closing bracket is found, process iteration string - when '}' => - OpenBrackets := OpenBrackets - 1; - if (OpenBrackets = 0) then - IterStringEnd := Pointer-1; - if (TokenStart /= 1) then - write(L, Format(1 to TokenStart-1)); - end if; - for i in 1 to IterCount loop - write(L, Format(IterStringStart to IterStringEnd)); - end loop; - if (IterStringEnd /= Format'length) then - write(L, Format(IterStringEnd+2 to Format'length)); - end if; - -- call expansion procedure recursively on expanded format - FIO_FormatExpand(FMT, L.all, TokenStart); - deallocate(L); - return; - end if; - Pointer := Pointer + 1; - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - -- read iteration string - when others => - Pointer := Pointer + 1; - - end case; - - end loop ITER_STRING_READ; - - -- stop iteration token search when no opening bracket found - when others => - Pointer := Pointer + 1; - next FORMAT_SEARCH; - - end case; - - end loop TOKEN_READ; - - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - - -- read other characters - when others => - Pointer := Pointer + 1; - - end case; - - end loop FORMAT_SEARCH; - - write(FMT, Format); - deallocate(L); - - end FIO_FormatExpand; - - - - -------------------------- - -- The fprint procedure -- - -------------------------- - - procedure fprint - (file F: text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ) is - - variable Pointer: integer; - variable FMT: line; - - begin - - Pointer := 1; - - FIO_FormatExpand (FMT, Format, Format'low); - - if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 ); - if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 ); - if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 ); - if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 ); - if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 ); - if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 ); - if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 ); - if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 ); - if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 ); - if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10); - if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11); - if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12); - if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13); - if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14); - if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15); - if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16); - if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17); - if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18); - if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19); - if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20); - if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21); - if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22); - if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23); - if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24); - if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25); - if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26); - if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27); - if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28); - if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29); - if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30); - if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31); - if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32); - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - - FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE); - - deallocate(FMT); - - end fprint; - - - ------------------------------------------- - -- Formatted output conversion functions -- - ------------------------------------------- - - function fo (Arg: unsigned) return string is - constant Argument: unsigned(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("U:" & Result); - end fo; - - function fo (Arg: signed) return string is - constant Argument: signed(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("S:" & Result); - end fo; - - function fo (Arg: std_logic_vector) return string is - constant Argument: std_logic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: std_ulogic_vector) return string is - constant Argument: std_ulogic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: bit_vector) return string is - constant Argument: bit_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_BIT_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: integer) return string is - variable Argument: integer := Arg; - variable Result: string(1 to FIO_d_WIDTH) := (others => ' '); - variable Sign: character := ' '; - begin - if (Argument < 0) and (Argument /= integer'low) then - Sign := '-'; - Argument := -Argument; - end if; - for i in Result'reverse_range loop - Result(i) := C_DIGITS_MAP(Argument mod 10); - Argument := Argument / 10; - exit when (Argument = 0); - end loop; - return ("I:" & Sign & Result); - end fo; - - function fo (Arg: std_ulogic) return string is - begin - return ("B:" & C_STD_LOGIC_MAP(Arg)); - end fo; - - function fo (Arg: bit) return string is - begin - return ("B:" & C_BIT_MAP(Arg)); - end fo; - - function fo (Arg: boolean) return string is - begin - if (ARG = TRUE) then - return ("L:T"); - else - return ("L:F"); - end if; - end fo; - - function fo (Arg: character) return string is - begin - return ("C:" & Arg); - end fo; - - -- auxilary function fgets(Arg :string) - -- returns index of first NUL in Arg or if no NUL is present just Arg'length - -- goes through Arg from 1 to Arg'length - function fgets (Arg: string) return integer is - variable index: integer := Arg'length; - begin - for i in 1 to Arg'length loop - if Arg(i) = NUL then - index := i - 1; - exit; - else - null; - end if; - end loop; - return index; - end fgets; - - -- returns the Arg string until the first NUL was encountered - -- if fo is used on a string with NUL in it it will stop reading the rest - -- of the string, even if a larger field width has been supplied. fo will - -- then just pad the remaining characters with blanco's - function fo (Arg: string) return string is - begin - return Arg(1 to fgets(Arg)); - end fo; - - function fo (Arg: time) return string is - begin - return fo (integer (Arg / 1 ns)); - end fo; - -end PCK_FIO; - diff --git a/lib/PCK_FIO-2002.7/README b/lib/PCK_FIO-2002.7/README deleted file mode 100644 index b16c6c5..0000000 --- a/lib/PCK_FIO-2002.7/README +++ /dev/null @@ -1,88 +0,0 @@ ----- $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - -Version 2002.07 -=============== - -Contents -======== - -This distribution contains the following files: - - PCK_FIO_1987.vhd: VHDL-87 source of the header of the PCK_FIO package - PCK_FIO_1987_BODY.vhd: VHDL-87 source of the body of the PCK_FIO package - PCK_FIO_1993.vhd: VHDL-93 source of the header of the PCK_FIO package - PCK_FIO_1993_BODY.vhd: VHDL-93 source of the body of the PCK_FIO package - TB_PCK_FIO_1987.vhd: VHDL-87 source of the testbench for package PCK_FIO - TB_PCK_FIO_1993.vhd: VHDL-93 source of the testbench for package PCK_FIO - PCK_FIO.out.gold: Certified test bench output - PCK_FIO.html: Manual for PCK_FIO in html format - README: This file - - -Installation -============ - -VHDL-1987 ---------- -To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and -analyze the VHDL file PCK_FIO_1987.vhd and PCK_FIO_1987_BODY.vhd into this library. - -To install the test bench, analyze TB_PCK_FIO_1987.vhd into the same library. - -VHDL-1993 ---------- -To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and -analyze the VHDL file PCK_FIO_1993.vhd and PCK_FIO_1993_BODY.vhd into this library. - -To install the test bench, analyze TB_PCK_FIO_1993.vhd into the same library. - -Numeric packages ----------------- -If you want to use IEEE.std_logic_arith instead of IEEE.numeric_std, you need -to edit the source code of the package, both header and body, and the test bench -and replace the package use clause. PCK_FIO works with either of these packages. - -Documentation -------------- -To install the documentation, put the file point PCK_FIO.html in a path of -your choosing, point your web browser to it, and bookmark it. - - -Installation check -================== - -After installing the test bench, you should run it. The corresponding VHDL -design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB). - -Simulating the test bench should create a file called PCK_FIO.out. This file -should be identical to PCK_FIO.out.gold. Any difference indicates a portability -issue or a simulator non-compliance or bug. - - - - diff --git a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd deleted file mode 100644 index 2e18ff4..0000000 --- a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd +++ /dev/null @@ -1,531 +0,0 @@ ----- $Id: TB_PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one - use IEEE.numeric_std.all; - -use STD.TEXTIO.all; - -library EASICS_PACKAGES; -use EASICS_PACKAGES.PCK_FIO.all; - -entity TBE_PCK_FIO is - -end TBE_PCK_FIO; - -architecture TB of TBE_PCK_FIO is - -begin - -USAGE: process - - file RESULT: text is out "PCK_FIO.out"; - variable L: line; - variable Pointer: integer; - variable BoolTrue: boolean := TRUE; - variable BoolFalse: boolean := FALSE; - variable IntPos: integer := 5678; - variable BigIntPos: integer := 12345678; - variable IntNeg: integer := -8765; - variable BigIntNeg: integer := -87654321; - variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); - variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); - variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); - variable SigPos: signed(6 downto 0) := signed'("0010010"); - variable SigNeg: signed(6 downto 0) := signed'("1010010"); - variable BitX: std_logic := 'X'; - variable Bit1: std_logic := '1'; - variable Bit0: std_logic := '0'; - - variable parameter_1: integer := 1234; - variable parameter_2: integer := 2345; - variable parameter_3: integer := 4567; - - constant TempString: string :="ABC" & NUL & "DEF"; -begin - -fprint(RESULT, L, - "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" & - "-----------------------------------------\n\n" & - "This is the result of running the PCK_FIO testbench.\n" & - "This file should be compared with PCK_FIO.out.gold, which is\n" & - "the reference output. Any difference indicates a portability\n" & - "issue or a simulator non-compliance or bug.\n\n" - ); - - -fprint(RESULT, L, - "\n--------------------\n" & - "-- Basic features --\n" & - "--------------------\n\n" - ); - -fprint(RESULT, L, - "-- First some auxiliary declarations\n" - ); - -fprint(RESULT, L, - "> file RESULT: text is out ""PCK_FIO.out"";\n" & - "> variable L: line;\n" & - "> variable BoolTrue: boolean := TRUE;\n" & - "> variable BoolFalse: boolean := FALSE;\n" & - "> variable IntPos: integer := 5678;\n" & - "> variable BigIntPos: integer := 12345678;\n" & - "> variable IntNeg: integer := -8765;\n" & - "> variable BigIntNeg: integer := -87654321;\n" & - "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" & - "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" & - "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" & - "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" & - "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" & - "> variable BitX: std_logic := 'X';\n" & - "> variable Bit1: std_logic := '1';\n" & - "> variable Bit0: std_logic := '0';\n" & - "> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n" -); - - -fprint(RESULT, L, - "\n\n-- fprint call with no arguments\n" & - "> fprint(RESULT, L, ""No arguments.\\n"");\n" - ); -fprint(RESULT, L, "No arguments.\n"); - - -fprint(RESULT, L, - "\n-- Special characters need to be escaped\n" & - "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n" - ); - -fprint(RESULT, L, "Special characters: \% \\ "" \n"); - - -fprint(RESULT, L, - "\n-- Various format specifiers interprete the same object differently\n" & - "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" & - "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Format specifiers: %r %d %b %q\n", - fo(Uns), fo(Uns), fo(Uns), fo(Uns) - ); - -fprint(RESULT, L, - "\n-- Format string can be shortened by using the iteration specifier\n" & - "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" & - "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Iteration specifier: %4{%r }\n", - fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) - ); -fprint(RESULT, L, - "\n-------------------------------\n"& - "--Testing string manipulation--\n"& - "-------------------------------\n"); -fprint(RESULT, L, "--testing done using the string TempString : " & """ABC""" - & " & NUL & ""DEF""\n"); --- temp_string: string:="ABC"&NUL&"DEF" --- test for detecting NUL in string -fprint(RESULT, L, "\n--test for NUL ending in strings\n"); -fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n"); -fprint(RESULT, L, fo(TempString)); - --- direct inclusion of string in fprint should give whole string -fprint(RESULT, L, "\n--same without fo,so without NUL testing\n"); -fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n"); -fprint(RESULT, L, TempString & "\n"); - --- influence of given width - -fprint(RESULT, L, "\n--if there are less characters in the given string then" - & " in the width fo will\n"& - "-- pad the remaining with blanco's according to the given justification\n"); -fprint(RESULT, L, "\n--with specified width, justified right,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n"); -fprint(RESULT, L, "%5s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width, justified left, using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n"); -fprint(RESULT, L, "%-5s",fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n"); -fprint(RESULT, L, "%9s", TempString); -fprint(RESULT, L, "\n\n-- if the width is smaller then the number" & - " of characters in the string fprint\n" & - "-- will output the string with the minimum of characters needed\n"); -fprint(RESULT, L, "\n--with specified width,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n"); -fprint(RESULT, L, "%2s",fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n"); -fprint(RESULT, L, "%4s", TempString); - - -fprint(RESULT, L, - "\n\n------------------------------------\n" & - "-- Support for bit-oriented types --\n" & - "------------------------------------\n" - ); - -fprint (RESULT, L, "\n-- Reasonable format\n" & - "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Reasonable format: %9{%r }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Decimal format\n" & - "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Decimal format: %9{%d }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Bit format\n" & - "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Bit format: %9{%b }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint(RESULT, L, - "\n\n" & - "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - -fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); - - - -fprint(RESULT, L, - "\n-------------------------------\n" & - "-- Support for integer types --\n" & - "-------------------------------\n" - ); - -fprint(RESULT, L, - "\n\n" & - "-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" & - "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - - -fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); - - -fprint(RESULT, L, - "\n----------------------\n" & - "-- Support for time --\n" & - "----------------------\n" - ); - -fprint (RESULT, L, "-- For portability reasons, time is converted \n" & - "-- into an integer value (of nanoseconds)\n" - ); -fprint (RESULT, L, "> wait for 648 ns\n"); -fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n"); - -wait for 648 ns; - -fprint (RESULT, L, "The time is now %d ns\n", fo(now)); - - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Erroneous calls and error messages --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" & - "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, "-- Unsupported format specifier\n" & - "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " & - "fo(Uns), fo(Std), fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Things you wouldn't expect to work --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Nested iteration\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n"); -fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); - -wait; - -end process USAGE; - -end TB; - - diff --git a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd deleted file mode 100644 index 0386a11..0000000 --- a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd +++ /dev/null @@ -1,536 +0,0 @@ ----- $Id: TB_PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one -use IEEE.numeric_std.all; - -use STD.TEXTIO.all; - -library EASICS_PACKAGES; -use EASICS_PACKAGES.PCK_FIO.all; - -entity TBE_PCK_FIO is - -end TBE_PCK_FIO; - -architecture TB of TBE_PCK_FIO is - -begin - -USAGE: process - - file RESULT: text open write_mode is "PCK_FIO.out"; - variable L: line; - variable Pointer: integer; - variable BoolTrue: boolean := TRUE; - variable BoolFalse: boolean := FALSE; - variable IntPos: integer := 5678; - variable BigIntPos: integer := 12345678; - variable IntNeg: integer := -8765; - variable BigIntNeg: integer := -87654321; - variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); - variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); - variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); - variable SigPos: signed(6 downto 0) := signed'("0010010"); - variable SigNeg: signed(6 downto 0) := signed'("1010010"); - variable BitX: std_logic := 'X'; - variable Bit1: std_logic := '1'; - variable Bit0: std_logic := '0'; - - variable parameter_1: integer := 1234; - variable parameter_2: integer := 2345; - variable parameter_3: integer := 4567; - - constant TempString: string :="ABC" & NUL & "DEF"; -begin - -fprint(RESULT, L, - "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" & - "-----------------------------------------\n\n" & - "This is the result of running the PCK_FIO testbench.\n" & - "This file should be compared with PCK_FIO.out.gold, which is\n" & - "the reference output. Any difference indicates a portability\n" & - "issue or a simulator non-compliance or bug.\n\n" - ); - - -fprint(RESULT, L, - "\n--------------------\n" & - "-- Basic features --\n" & - "--------------------\n\n" - ); - -fprint(RESULT, L, - "-- First some auxiliary declarations\n" - ); - -fprint(RESULT, L, - "> file RESULT: text is out ""PCK_FIO.out"";\n" & - "> variable L: line;\n" & - "> variable BoolTrue: boolean := TRUE;\n" & - "> variable BoolFalse: boolean := FALSE;\n" & - "> variable IntPos: integer := 5678;\n" & - "> variable BigIntPos: integer := 12345678;\n" & - "> variable IntNeg: integer := -8765;\n" & - "> variable BigIntNeg: integer := -87654321;\n" & - "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" & - "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" & - "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" & - "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" & - "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" & - "> variable BitX: std_logic := 'X';\n" & - "> variable Bit1: std_logic := '1';\n" & - "> variable Bit0: std_logic := '0';\n" & - "> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n" -); - - -fprint(RESULT, L, - "\n\n-- fprint call with no arguments\n" & - "> fprint(RESULT, L, ""No arguments.\\n"");\n" - ); -fprint(RESULT, L, "No arguments.\n"); - - -fprint(RESULT, L, - "\n-- Special characters need to be escaped\n" & - "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n" - ); - -fprint(RESULT, L, "Special characters: \% \\ "" \n"); - - -fprint(RESULT, L, - "\n-- Various format specifiers interprete the same object differently\n" & - "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" & - "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Format specifiers: %r %d %b %q\n", - fo(Uns), fo(Uns), fo(Uns), fo(Uns) - ); - -fprint(RESULT, L, - "\n-- Format string can be shortened by using the iteration specifier\n" & - "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" & - "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Iteration specifier: %4{%r }\n", - fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) - ); -fprint(RESULT, L, - "\n-------------------------------\n"& - "--Testing string manipulation--\n"& - "-------------------------------\n"); -fprint(RESULT, L, "--testing done using the string TempString : " & """ABC""" - & " & NUL & ""DEF""\n"); --- TempString: string:="ABC" & NUL & "DEF" --- test for detecting NUL in string -fprint(RESULT, L ,"\n--test for NUL ending in strings\n"); -fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n"); -fprint(RESULT, L, fo(TempString)); - --- direct inclusion of string in fprint should give whole string -fprint(RESULT, L, "\n--same without fo,so without NUL testing\n"); -fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n"); -fprint(RESULT, L, TempString & "\n"); - --- influence of given width - -fprint(RESULT, L, "\n--if there are less characters in the given string then in the width fo will\n"& - "-- pad the remaining with blanco's according to the given justification\n"); -fprint(RESULT, L, "\n--with specified width, justified right,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n"); -fprint(RESULT, L, "%5s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width, justified left, using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n"); -fprint(RESULT, L, "%-5s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n"); -fprint(RESULT, L, "%9s", TempString); -fprint(RESULT, L, "\n\n-- if the width is smaller then the number of characters in the string fprint\n"& - "-- will output the string with the minimum of characters needed\n"); -fprint(RESULT, L, "\n--with specified width,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n"); -fprint(RESULT, L, "%2s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n"); -fprint(RESULT, L, "%4s", TempString); - -fprint(RESULT, L, - "\n\n------------------------------------\n" & - "-- Support for bit-oriented types --\n" & - "------------------------------------\n" - ); - -fprint (RESULT, L, "\n-- Reasonable format\n" & - "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Reasonable format: %9{%r }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Decimal format\n" & - "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Decimal format: %9{%d }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Bit format\n" & - "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Bit format: %9{%b }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint(RESULT, L, - "\n\n" & - "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" & - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - -fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); - - - -fprint(RESULT, L, - "\n-------------------------------\n" & - "-- Support for integer types --\n" & - "-------------------------------\n" - ); - -fprint(RESULT, L, - "\n\n" & - "-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" & - "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - - -fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); - - -fprint(RESULT, L, - "\n----------------------\n" & - "-- Support for time --\n" & - "----------------------\n" - ); - -fprint (RESULT, L, "-- For portability reasons, time is converted \n" & - "-- into an integer value (of nanoseconds)\n" - ); -fprint (RESULT, L, "> wait for 648 ns\n"); -fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n"); - -wait for 648 ns; - -fprint (RESULT, L, "The time is now %d ns\n", fo(now)); - - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Erroneous calls and error messages --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" & - "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, "-- Unsupported format specifier\n" & - "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " & - "fo(Uns), fo(Std), fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Things you wouldn't expect to work --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Nested iteration\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n"); -fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); - -wait; - -end process USAGE; - -end TB; - - - - - - - - - - - diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 deleted file mode 100644 index c5a4a92..0000000 --- a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 +++ /dev/null @@ -1,34 +0,0 @@ -### msMakefile generated by vma on Thu Oct 4 17:33:56 CEST 2001 - -ANALYZER = vcom -quiet -nologo -ANALYZER_C = vcom -quiet -nologo -all : \ - bin/tbe_pck_fio/tb.dat \ - bin/tbe_pck_fio/_primary.dat - -# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB) -# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO - -bin/tbe_pck_fio/tb.dat \ -bin/tbe_pck_fio/_primary.dat : \ - bin/pck_fio/body.dat \ - bin/pck_fio/_primary.dat \ - TB_PCK_FIO_1987.vhd - ${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1987.vhd - - -# Prerequisites for package body EASICS_PACKAGES.PCK_FIO() - -bin/pck_fio/body.dat : \ - bin/pck_fio/_primary.dat \ - PCK_FIO_1987_BODY.vhd - ${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1987_BODY.vhd - - -# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO - -bin/pck_fio/_primary.dat : \ - PCK_FIO_1987.vhd - ${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1987.vhd - - diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 deleted file mode 100644 index 0f9a351..0000000 --- a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 +++ /dev/null @@ -1,34 +0,0 @@ -### msMakefile generated by vma on Thu Oct 4 17:32:23 CEST 2001 - -ANALYZER = vcom -quiet -nologo -93 -ANALYZER_C = vcom -quiet -nologo -93 -all : \ - bin/tbe_pck_fio/tb.dat \ - bin/tbe_pck_fio/_primary.dat - -# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB) -# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO - -bin/tbe_pck_fio/tb.dat \ -bin/tbe_pck_fio/_primary.dat : \ - bin/pck_fio/body.dat \ - bin/pck_fio/_primary.dat \ - TB_PCK_FIO_1993.vhd - ${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1993.vhd - - -# Prerequisites for package body EASICS_PACKAGES.PCK_FIO() - -bin/pck_fio/body.dat : \ - bin/pck_fio/_primary.dat \ - PCK_FIO_1993_BODY.vhd - ${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1993_BODY.vhd - - -# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO - -bin/pck_fio/_primary.dat : \ - PCK_FIO_1993.vhd - ${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1993.vhd - - diff --git a/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj b/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj deleted file mode 100644 index ba54b14..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj +++ /dev/null @@ -1,13 +0,0 @@ -vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_config.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\dpram.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd" diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/compile_simprim.do b/lib/SDRAM/ddr_sdr_v1_4/sim/compile_simprim.do deleted file mode 100644 index 16b23bb..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/compile_simprim.do +++ /dev/null @@ -1,6 +0,0 @@ -vlib simprim - -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/compile_unisim.do b/lib/SDRAM/ddr_sdr_v1_4/sim/compile_unisim.do deleted file mode 100644 index d35d8c9..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/compile_unisim.do +++ /dev/null @@ -1,6 +0,0 @@ -vlib unisim - -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo deleted file mode 100644 index 7af84ba..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w2r.vhd" -vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl -do {tb_sdr_ctrl.wdo} -view wave -view structure -view signals -run 800us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo deleted file mode 100644 index 4a9d3f1..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo +++ /dev/null @@ -1,93 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {Main controller} -add wave -noupdate -divider {Main controller} -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/st_sdr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_in -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_in -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_in -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_out -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_empty -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_full -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_re -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_we -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Logic /tb_sdr_ctrl/clk -add wave -noupdate -format Logic /tb_sdr_ctrl/rst -add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb -add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency -add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270 -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy -add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0 -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {14963876 ps} 0} -configure wave -namecolwidth 184 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {14733925 ps} {15711632 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo deleted file mode 100644 index 4f1cf1c..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w2r.vhd" -vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl_fifo.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl_fifo -do {tb_sdr_ctrl_fifo.wdo} -view wave -view structure -view signals -run 20us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo deleted file mode 100644 index 4088038..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo +++ /dev/null @@ -1,68 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/rst_out -add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/st_sdr -add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_we_n -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_addr -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_busy -add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_cmd_we -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_r -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_data_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_w -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_rd -add wave -noupdate -divider {Read FIFO} -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_empty -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_we -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_re -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/read_fifo_dout -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/was_write -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pr -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pr_next -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pw -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pw_next -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/fifo_full -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/fifo_empty -add wave -noupdate -divider {Write FIFO} -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_w -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/we -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/re -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_empty -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_full -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pr -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pr_next -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pw -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pw_next -add wave -noupdate -divider {Command FIFO} -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_w -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/we -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/re -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_sync_fifo_ctrl/fifo_empty -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_sync_fifo_ctrl/fifo_full -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {13893123 ps} 0} -configure wave -namecolwidth 172 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {13879998 ps} {13928553 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo deleted file mode 100644 index eee9b52..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w2r.vhd" -vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl_lin_r_rand_w.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl -do {tb_sdr_ctrl_lin_r_rand_w.wdo} -view wave -view structure -view signals -run 1200us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo deleted file mode 100644 index 542c24b..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo +++ /dev/null @@ -1,87 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {Main controller} -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/clk -add wave -noupdate -format Logic /tb_sdr_ctrl/rst -add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb -add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency -add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270 -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy -add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0 -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {21813900 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {21725359 ps} {22204052 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo deleted file mode 100644 index 4716a01..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w2r.vhd" -vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl_lin_w_rand_r.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl -do {tb_sdr_ctrl_lin_w_rand_r.wdo} -view wave -view structure -view signals -run 1200us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo deleted file mode 100644 index 542c24b..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo +++ /dev/null @@ -1,87 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {Main controller} -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/clk -add wave -noupdate -format Logic /tb_sdr_ctrl/rst -add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb -add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency -add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270 -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy -add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0 -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {21813900 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {21725359 ps} {22204052 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo deleted file mode 100644 index 9be2261..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w2r.vhd" -vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl_rand_addr.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl -do {tb_sdr_ctrl_rand_rw.wdo} -view wave -view structure -view signals -run 1000us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo deleted file mode 100644 index eb20b08..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo +++ /dev/null @@ -1,82 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/clk -add wave -noupdate -format Logic /tb_sdr_ctrl/rst -add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb -add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency -add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270 -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy -add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0 -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {60573747 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {60552548 ps} {60600861 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo deleted file mode 100644 index c868866..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w2r.vhd" -vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl_rand_rw.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl -do {tb_sdr_ctrl_rand_rw.wdo} -view wave -view structure -view signals -run 10000us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo deleted file mode 100644 index e3087e6..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo +++ /dev/null @@ -1,84 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/clk -add wave -noupdate -format Logic /tb_sdr_ctrl/rst -add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb -add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency -add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270 -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy -add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0 -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {16004147 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {15914249 ps} {16324366 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo deleted file mode 100644 index dbf023a..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo +++ /dev/null @@ -1,28 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w2r.vhd" -vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/sdram_ctrl_frontend.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdram_ctrl_frontend.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdram_ctrl_frontend -do {tb_sdram_ctrl_frontend.wdo} -view wave -view structure -view signals -run 40us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo deleted file mode 100644 index 565f89c..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo +++ /dev/null @@ -1,45 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/addr -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/busy -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/en -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/r_wn -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/din -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/be -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/dout_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout_reg -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/clk_out -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cs_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_we_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_ras_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cas_n -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_ba -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_data -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_busy -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd_we -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_cmd/st_sdr -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/sdr_cmd_busy -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/cat_fifo_full -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/write_fifo_full -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/read_fifo_full -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {27951315 ps} 0} -configure wave -namecolwidth 172 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {42 us} diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd deleted file mode 100644 index c924c8c..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd +++ /dev/null @@ -1,240 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Clock generator (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library ieee, work; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity clockgen is - generic - ( - read_phaseshift : integer := 0; - frequency_hz : integer := 100E6 - ); - port - ( - -- Clocks and Reset - rst : in std_logic; -- external async reset, low active - clk_in : in std_logic; -- system clock (e.g. 100MHz), from board - clk_fb_in : in std_logic; -- feedback clock - read_clk0_out : out std_logic; -- Clock for DDR-SDRAM data capture, dcm#1 output 0° - read_clk270_out : out std_logic; -- Clock for DDR-SDRAM data capture, dcm#1 output 270° - sys_clk0_out : out std_logic; -- System clock, dcm#0 output 0° - sys_clk270_out : out std_logic; -- System clock, dcm#0 output 270° - locked_out : out std_logic; -- DCM locked status - error_out : out std_logic -- indicates DCM Errors - ); - -end; - -architecture tech of clockgen is - - constant CLKIN_PER : real := real(1000E6/frequency_hz); - - signal locked : unsigned(1 downto 0); - signal dcm_rst : unsigned(1 downto 0); - signal read_clk0 : std_logic; - signal read_clk270 : std_logic; - signal read_clk0_bufg : std_logic; - signal read_clk270_bufg : std_logic; - signal sys_clk0 : std_logic; - signal sys_clk270 : std_logic; - signal sys_clk0_bufg : std_logic; - signal sys_clk270_bufg : std_logic; - signal dcm1_locked, dcm2_locked : unsigned(2 downto 0); - signal cnt_q : unsigned(4 downto 0); - - type STATE_TYPE is (s0, s1, s2, s3, s4); - signal state_q : STATE_TYPE; - -begin - - read_clk0_out <= read_clk0_bufg; - read_clk270_out <= read_clk270_bufg; - sys_clk0_out <= sys_clk0_bufg; - sys_clk270_out <= sys_clk270_bufg; - -bufg11: bufg - port map - ( - o => sys_clk0_bufg, - i => sys_clk0 - ); - -bufg12: bufg - port map ( - o => sys_clk270_bufg, - i => sys_clk270 - ); - -bufg13: bufg - port map - ( - o => read_clk0_bufg, - i => read_clk0 - ); - -bufg14: bufg - port map ( - o => read_clk270_bufg, - i => read_clk270 - ); - - ------------------------------------------------------------------------------------------------------- - -- Clock generation - ------------------------------------------------------------------------------------------------------- - -inst_DCM_BASE_0 : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => sys_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => sys_clk270, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked(0), -- DCM LOCK status output - CLKFB => clk_fb_in, -- DCM clock feedback - CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM) - RST => dcm_rst(0) -- DCM asynchronous reset input - ); - - inst_DCM_BASE_1 : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => read_phaseshift, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => read_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => read_clk270, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked(1), -- DCM LOCK status output - CLKFB => read_clk0_bufg, -- DCM clock feedback - CLKIN => clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) - RST => dcm_rst(1) -- DCM asynchronous reset input - ); - - dcm_rst(1) <= not locked(0); - -dcm_fsm: - process(rst, clk_in) - begin - if rst = '1' then - state_q <= s0; - dcm_rst(0) <= '0'; - cnt_q <= "11111"; - error_out <= '0'; - locked_out <= '0'; - dcm1_locked <= (others => '0'); - dcm2_locked <= (others => '0'); - elsif rising_edge(clk_in) then - case state_q is - when s0 => - state_q <= s1; - - when s1 => - cnt_q <= cnt_q - 1; - if cnt_q = 0 then - dcm_rst(0) <= '1'; - state_q <= s2; - end if; - - when s2 => - cnt_q <= cnt_q - 1; - if cnt_q = 0 then - dcm_rst(0) <= '0'; - state_q <= s3; - end if; - - when s3 => - if dcm1_locked(2)='1' and dcm2_locked(2)='1' then - state_q <= s4; - error_out <= '0'; - end if; - - when s4 => - if dcm1_locked(2)='1' and dcm2_locked(2)='1' then - locked_out <= '1'; - else - error_out <= '1'; - end if; - end case; - - -- synchronize 'dcm1_locked' - dcm1_locked <= dcm1_locked(1 downto 0) & locked(0); - dcm2_locked <= dcm2_locked(1 downto 0) & locked(1); - - end if; - end process; - -end architecture tech; - - diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd deleted file mode 100644 index 1494c9b..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd +++ /dev/null @@ -1,370 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: DDR physical layer (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity ddr_phy is - Port ( - sys_rst : in STD_LOGIC; - sys_clk0 : in STD_LOGIC; - sys_clk270 : in STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_rd : out user_tag_t; - u_tag_wr : out user_tag_t; - read_clk : in STD_LOGIC; - phy_ctrl : in phy_ctrl_t; - part_ctrl : in part_ctrl_t; - sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0); - sdr_dm : in unsigned(SDR_DM_WIDTH-1 downto 0); - sdr_data_r : out unsigned(SDR_DATA_WIDTH-1 downto 0); - sdr_data_vld : out STD_LOGIC; - sdr_data_req_w : out STD_LOGIC; - sdr_data_req_r : out STD_LOGIC; - part_clk_p : out STD_LOGIC; - part_clk_n : out STD_LOGIC; - part_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - part_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - part_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0); - part_ba : out unsigned(DDR_BANK_WIDTH-1 downto 0); - part_addr : out unsigned(DDR_ADDR_WIDTH-1 downto 0); - part_cs_n : out STD_LOGIC; - part_we_n : out STD_LOGIC; - part_cas_n : out STD_LOGIC; - part_ras_n : out STD_LOGIC; - part_cke : out STD_LOGIC - ); -end ddr_phy; - -architecture tech of ddr_phy is - - signal dqs_drive : std_logic; - signal drive : std_logic; - signal dqs : unsigned(DDR_DQS_WIDTH-1 downto 0); - signal dqs_zen : unsigned(DDR_DQS_WIDTH-1 downto 0); - signal dqs_rst : std_logic; - signal ddr_data_w : unsigned(DDR_DATA_WIDTH-1 downto 0); - signal data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal data_reg_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal drive270 : unsigned(DDR_DATA_WIDTH-1 downto 0); - signal part_ctrl_reg : part_ctrl_t; - signal we_reg : std_logic; - signal read_en : std_logic; - - type u_tag_array_t is array (natural range 0 to 4) of user_tag_t; - signal u_tag_pipe : u_tag_array_t; - -begin - ------------------------------------------------------------------------------------------------------------------------------------------------- -utag_pipe: - process(sys_rst, sys_clk0) - begin - if rising_edge(sys_clk0) then - for i in u_tag_pipe'length-1 downto 1 loop - u_tag_pipe(i) <= u_tag_pipe(i-1); - end loop; - if phy_ctrl.utag_we = '1' then - u_tag_pipe(0) <= u_tag_in; - end if; - end if; - end process; - -WE_REGISTER: - process(sys_rst, sys_clk0) - begin - if sys_rst = '1' then - we_reg <= '0'; - elsif rising_edge(sys_clk0) then - we_reg <= phy_ctrl.we; - end if; - end process; - -DATA_DRIVE_GEN: - process(sys_clk0) - begin - if falling_edge(sys_clk0) then - dqs_rst <= not we_reg; - drive <= we_reg; - end if; - end process; - -DQS_DRIVE_GEN: - process(sys_clk0) - variable p : unsigned(1 downto 0); - begin - if rising_edge(sys_clk0) then - if phy_ctrl.drive_en = '1' then - p := (others => '1'); - else - p := p(p'left-1 downto 0) & '0'; - end if; - end if; - dqs_drive <= p(p'left); - end process; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- SDRAM Clock -ODDR_clk_p : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_clk_p, -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => '1', -- 1-bit data input (positive edge) - D2 => '0', -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - -ODDR_clk_n : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_clk_n, -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => '0', -- 1-bit data input (positive edge) - D2 => '1', -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - ------------------------------------------------------------------------------------------------------------------------------------------------- --- Data OUT DDR-FFs -gen_ddr_data_out: - for n in 0 to DDR_DATA_WIDTH-1 generate - begin - ODDR_data : ODDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => ddr_data_w(n), -- 1-bit DDR output - C => sys_clk270, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => sdr_data_w(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_data_w(n), -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_ddr_data_out; - --- Sample tristate on clock90 - process (sys_clk270) - begin - if rising_edge(sys_clk270) then - for n in 0 to DDR_DATA_WIDTH-1 loop - drive270(n) <= drive; - end loop; - end if; - end process; - --- Output mux -out_mux_data: - for n in 0 to DDR_DATA_WIDTH-1 generate - part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z'; - end generate; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- Data-mask OUT DDR-FFs -gen_ddr_dm_out: - for n in 0 to DDR_DM_WIDTH-1 generate - begin - ODDR_dm : ODDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_dm(n), -- 1-bit DDR output - C => sys_clk270, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => sdr_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_dm(n), -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_ddr_dm_out; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- DQS OUT DDR-FFs -gen_dqs_out: - for n in 0 to DDR_DQS_WIDTH-1 generate - begin - ODDR_dqs : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => dqs(n), -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D2 => '0', -- 1-bit data input (positive edge) - D1 => '1', -- 1-bit data input (negative edge) - R => dqs_rst, -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_dqs_out; - --- Tristate-Control fuer dqs - process (sys_clk0) is - variable zctrl : boolean; - begin - if rising_edge(sys_clk0) then - if dqs_drive = '1' then - zctrl := false; - else - zctrl := true; - end if; - if zctrl then - dqs_zen <= (others => '1'); - else - dqs_zen <= (others => '0'); - end if; - end if; - end process; - --- Tristate-Buffer fuer dqs -gen_out_mux_dqs: - for n in 0 to DDR_DQS_WIDTH-1 generate - part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n); - end generate gen_out_mux_dqs; - ------------------------------------------------------------------------------------------------------------------------------------------------- - process (sys_rst, sys_clk0) is - begin - if sys_rst = '1' then - part_ctrl_reg.cmd <= COMMAND(SD_DESELECT); - part_ctrl_reg.ba <= (others=>'0'); - part_ctrl_reg.addr <= (others=>'0'); - part_ctrl_reg.cke <= '0'; - elsif rising_edge(sys_clk0) then - part_ctrl_reg <= part_ctrl; - end if; - end process; - - process (sys_clk0) is - begin - if falling_edge(sys_clk0) then - part_ras_n <= part_ctrl_reg.cmd.ras_n; - part_cas_n <= part_ctrl_reg.cmd.cas_n; - part_we_n <= part_ctrl_reg.cmd.we_n; - part_cs_n <= part_ctrl_reg.cmd.cs_n; - part_ba <= part_ctrl_reg.ba; - part_addr <= part_ctrl_reg.addr; - part_cke <= part_ctrl_reg.cke; - end if; - end process; - ------------------------------------------------------------------ --- READ DATA Processing ------------------------------------------------------------------ -gen_ddr_data_in: - for n in 0 to DDR_DATA_WIDTH-1 generate - begin - IDDR_data : IDDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" - INIT_Q1 => '0', -- Initial value of Q1: '0' or '1' - INIT_Q2 => '0', -- Initial value of Q2: '0' or '1' - SRTYPE => "SYNC" -- Set/Reset type: "SYNC" or "ASYNC" - ) - port map - ( - Q1 => data_r(n), -- 1-bit output for positive edge of clock - Q2 => data_r(n + DDR_DATA_WIDTH), -- 1-bit output for negative edge of clock - C => read_clk, -- 1-bit clock input - CE => read_en, -- 1-bit clock enable input - D => part_data(n), -- 1-bit DDR data input - R => '0', -- 1-bit reset - S => '0' -- 1-bit set - ); - end generate; - - -data_sample_stage: - process (sys_clk0) - begin - if falling_edge(sys_clk0) then - data_reg_r <= data_r; - end if; - end process; - -misc_flags_and_data_out: - process (sys_rst, sys_clk0) - variable p : unsigned(3 downto 0); - begin - if sys_rst = '1' then - p := (others => '0'); - read_en <= '0'; - sdr_data_vld <= '0'; - sdr_data_req_w <= '0'; - sdr_data_req_r <= '0'; - elsif rising_edge(sys_clk0) then - sdr_data_r <= data_reg_r; - if p(3) = '1' then - u_tag_rd <= u_tag_pipe(4); - end if; - if phy_ctrl.we = '1' then - u_tag_wr <= u_tag_pipe(0); - end if; - sdr_data_req_w <= phy_ctrl.we; - sdr_data_req_r <= phy_ctrl.re; - sdr_data_vld <= p(3); - read_en <= p(1); - if phy_ctrl.re = '1' then - p := p(p'left-1 downto 0) & '1'; - else - p := p(p'left-1 downto 0) & '0'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end tech; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd deleted file mode 100644 index 79ce51f..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd +++ /dev/null @@ -1,111 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.fifo_ctrl_pkg.all; - -entity fifo_sync is - Generic ( - addr_width : natural := 4; - data_width : natural := 8; - almost_full_thresh : integer := 12; - almost_empty_thresh : integer := 4 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC; - data_w : in unsigned (data_width-1 downto 0); - data_r : out unsigned (data_width-1 downto 0) - ); -end fifo_sync; - -architecture Behavioral of fifo_sync is - - signal mem_we : STD_LOGIC; - signal ptr_w : unsigned (addr_width-1 downto 0); - signal ptr_r : unsigned (addr_width-1 downto 0); - signal full : STD_LOGIC; - signal empty : STD_LOGIC; - signal almost_full : STD_LOGIC; - signal almost_empty : STD_LOGIC; - -begin - - mem_we <= we; - fifo_full <= full; - fifo_empty <= empty; - fifo_afull <= almost_full; - fifo_aempty <= almost_empty; - - inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl - GENERIC MAP - ( - addr_width => addr_width, - almost_full_thresh => almost_full_thresh, - almost_empty_thresh => almost_empty_thresh - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => we, - re => re, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => full, - fifo_empty => empty, - fifo_afull => almost_full, - fifo_aempty => almost_empty - - ); - - inst_dpram_1w1r: entity work.dpram_1w1r_dist - GENERIC MAP ( - addr_width => addr_width, - data_width => data_width - ) - PORT MAP( - clka => clk, - clkb => clk, - en_a => '1', - en_b => '1', - we_a => mem_we, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => data_w, - dout_b => data_r - ); - -end Behavioral; - diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd deleted file mode 100644 index 356bb28..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd +++ /dev/null @@ -1,1320 +0,0 @@ ------------------------------------------------------------------------------------------ --- --- File Name: MT46V16M16.VHD --- Version: 2.1 --- Date: January 14th, 2002 --- Model: Behavioral --- Simulator: NCDesktop - http://www.cadence.com --- ModelSim PE - http://www.model.com --- --- Dependencies: None --- --- Author: Son P. Huynh --- Email: sphuynh@micron.com --- Phone: (208) 368-3825 --- Company: Micron Technology, Inc. --- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks) --- --- Description: Micron 256 Mb SDRAM DDR (Double Data Rate) --- --- Limitation: Doesn't model internal refresh counter --- --- Note: --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright (c) 1998 Micron Semiconductor Products, Inc. --- All rights researved --- --- Rev Author Date Changes --- --- ---------------------------- ---------- ------------------------------------- --- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter --- Micron Technology, Inc. --- --- 2.0 Son P. Huynh 11/08/2001 - Second release --- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE --- ------------------------------------------------------------------------------------------ - -LIBRARY IEEE; - USE IEEE.STD_LOGIC_1164.ALL; - USE IEEE.STD_LOGIC_UNSIGNED.ALL; - USE IEEE.STD_LOGIC_ARITH.ALL; - -ENTITY MT46V16M16 IS - GENERIC ( -- Timing for -75Z CL2 - tCK : TIME := 7.500 ns; - tCH : TIME := 3.375 ns; -- 0.45*tCK - tCL : TIME := 3.375 ns; -- 0.45*tCK - tDH : TIME := 0.500 ns; - tDS : TIME := 0.500 ns; - tIH : TIME := 0.900 ns; - tIS : TIME := 0.900 ns; - tMRD : TIME := 15.000 ns; - tRAS : TIME := 40.000 ns; - tRAP : TIME := 20.000 ns; - tRC : TIME := 65.000 ns; - tRFC : TIME := 75.000 ns; - tRCD : TIME := 20.000 ns; - tRP : TIME := 20.000 ns; - tRRD : TIME := 15.000 ns; - tWR : TIME := 15.000 ns; - addr_bits : INTEGER := 13; - data_bits : INTEGER := 16; - cols_bits : INTEGER := 9 - ); - PORT ( - Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - Clk : IN STD_LOGIC; - Clk_n : IN STD_LOGIC; - Cke : IN STD_LOGIC; - Cs_n : IN STD_LOGIC; - Ras_n : IN STD_LOGIC; - Cas_n : IN STD_LOGIC; - We_n : IN STD_LOGIC; - Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); -END MT46V16M16; - -ARCHITECTURE behave OF MT46V16M16 IS - -- Array for Read pipeline - TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Write pipeline - TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Auto Precharge - TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER; - - -- Array for Manual Precharge - TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Burst Terminate - TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Memory Access - TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - TYPE Array_ram_pntr IS ACCESS Array_ram_type; - TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr; - - -- Data pair - SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0); - SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0); - - -- Mode Register - SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); - - -- Command Decode Variables - SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0'; - SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0'; - - -- Burst Length Decode Variables - SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0'; - - -- Cas Latency Decode Variables - SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0'; - - -- Internal Control Signals - SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0'; - - -- System Clock - SIGNAL Sys_clk : STD_LOGIC := '0'; - - -- Dqs buffer - SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - -BEGIN - -- Strip the strength - Cs_in <= To_X01 (Cs_n); - Ras_in <= To_X01 (Ras_n); - Cas_in <= To_X01 (Cas_n); - We_in <= To_X01 (We_n); - - -- Commands Decode - Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in; - Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in; - Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in); - Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1)); - Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1)); - Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in); - Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in; - Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in); - - -- Burst Length Decode - Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); - Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); - Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - - -- CAS Latency Decode - Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4)); - Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); - Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4)); - - -- Dqs buffer - Dqs <= Dqs_out; - - -- - -- System Clock - -- - int_clk : PROCESS (Clk, Clk_n) - VARIABLE ClkZ, CkeZ : STD_LOGIC := '0'; - begin - IF Clk = '1' AND Clk_n = '0' THEN - ClkZ := '1'; - CkeZ := Cke; - ELSIF Clk = '0' AND Clk_n = '1' THEN - ClkZ := '0'; - END IF; - Sys_clk <= CkeZ AND ClkZ; - END PROCESS; - - -- - -- Main Process - -- - state_register : PROCESS - -- Precharge Variables - VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0'; - - -- Activate Variables - VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1'; - - -- Data IO variables - VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0'; - - -- Internal address mux variables - VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0); - VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - - -- DLL Reset variables - VARIABLE DLL_enable : STD_LOGIC := '0'; - VARIABLE DLL_reset : STD_LOGIC := '0'; - VARIABLE DLL_done : STD_LOGIC := '0'; - VARIABLE DLL_count : INTEGER := 0; - - -- Timing Check - VARIABLE MRD_chk : TIME := 0 ns; - VARIABLE RFC_chk : TIME := 0 ns; - VARIABLE RRD_chk : TIME := 0 ns; - VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; - VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns; - VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns; - VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; - VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; - VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns; - - -- Read pipeline variables - VARIABLE Read_cmnd : Array_Read_cmnd; - VARIABLE Read_bank : Array_Read_bank; - VARIABLE Read_cols : Array_Read_cols; - - -- Write pipeline variables - VARIABLE Write_cmnd : Array_Write_cmnd; - VARIABLE Write_bank : Array_Write_bank; - VARIABLE Write_cols : Array_Write_cols; - - -- Auto Precharge variables - VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 ); - - -- Manual Precharge variables - VARIABLE A10_precharge : Array_A10_precharge; - VARIABLE Bank_precharge : Array_Bank_precharge; - VARIABLE Cmnd_precharge : Array_Cmnd_precharge; - - -- Burst Terminate variable - VARIABLE Cmnd_bst : Array_Cmnd_bst; - - -- Memory Banks - VARIABLE Bank0 : Array_ram_stor; - VARIABLE Bank1 : Array_ram_stor; - VARIABLE Bank2 : Array_ram_stor; - VARIABLE Bank3 : Array_ram_stor; - - -- Burst Counter - VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Internal Dqs initialize - VARIABLE Dqs_int : STD_LOGIC := '0'; - - -- Data buffer for DM Mask - VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - - -- - -- Initialize empty rows - -- - PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS - VARIABLE i, j : INTEGER := 0; - BEGIN - IF Bank = "00" THEN - IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty - Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank0 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "01" THEN - IF Bank1 (Row_index) = NULL THEN - Bank1 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank1 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "10" THEN - IF Bank2 (Row_index) = NULL THEN - Bank2 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank2 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "11" THEN - IF Bank3 (Row_index) = NULL THEN - Bank3 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank3 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - END IF; - END; - - -- - -- Burst Counter - -- - PROCEDURE Burst_decode IS - VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0'); - BEGIN - -- Advance burst counter - Burst_counter := Burst_counter + 1; - - -- Burst Type - IF Mode_reg (3) = '0' THEN - Cols_temp := Cols_addr + 1; - ELSIF Mode_reg (3) = '1' THEN - Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2); - Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1); - Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0); - END IF; - - -- Burst Length - IF Burst_length_2 = '1' THEN - Cols_addr (0) := Cols_temp (0); - ELSIF Burst_length_4 = '1' THEN - Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0); - ELSIF Burst_length_8 = '1' THEN - Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0); - ELSE - Cols_addr := Cols_temp; - END IF; - - -- Data counter - IF Burst_length_2 = '1' THEN - IF Burst_counter >= 2 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_4 = '1' THEN - IF Burst_counter >= 4 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_8 = '1' THEN - IF Burst_counter >= 8 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - END IF; - END; - - BEGIN - WAIT ON Sys_clk; - - -- - -- Manual Precharge Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- A10 Precharge Pipeline - A10_precharge(0) := A10_precharge(1); - A10_precharge(1) := A10_precharge(2); - A10_precharge(2) := A10_precharge(3); - A10_precharge(3) := A10_precharge(4); - A10_precharge(4) := A10_precharge(5); - A10_precharge(5) := A10_precharge(6); - A10_precharge(6) := A10_precharge(7); - A10_precharge(7) := A10_precharge(8); - A10_precharge(8) := '0'; - - -- Bank Precharge Pipeline - Bank_precharge(0) := Bank_precharge(1); - Bank_precharge(1) := Bank_precharge(2); - Bank_precharge(2) := Bank_precharge(3); - Bank_precharge(3) := Bank_precharge(4); - Bank_precharge(4) := Bank_precharge(5); - Bank_precharge(5) := Bank_precharge(6); - Bank_precharge(6) := Bank_precharge(7); - Bank_precharge(7) := Bank_precharge(8); - Bank_precharge(8) := "00"; - - -- Command Precharge Pipeline - Cmnd_precharge(0) := Cmnd_precharge(1); - Cmnd_precharge(1) := Cmnd_precharge(2); - Cmnd_precharge(2) := Cmnd_precharge(3); - Cmnd_precharge(3) := Cmnd_precharge(4); - Cmnd_precharge(4) := Cmnd_precharge(5); - Cmnd_precharge(5) := Cmnd_precharge(6); - Cmnd_precharge(6) := Cmnd_precharge(7); - Cmnd_precharge(7) := Cmnd_precharge(8); - Cmnd_precharge(8) := '0'; - - -- Terminate Read if same bank or all banks - IF ((Cmnd_precharge (0) = '1') AND - (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND - (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Burst Terminate Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Burst Terminate pipeline - Cmnd_bst (0) := Cmnd_bst (1); - Cmnd_bst (1) := Cmnd_bst (2); - Cmnd_bst (2) := Cmnd_bst (3); - Cmnd_bst (3) := Cmnd_bst (4); - Cmnd_bst (4) := Cmnd_bst (5); - Cmnd_bst (5) := Cmnd_bst (6); - Cmnd_bst (6) := Cmnd_bst (7); - Cmnd_bst (7) := Cmnd_bst (8); - Cmnd_bst (8) := '0'; - - -- Terminate current Read - IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Dq and Dqs Drivers - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Read Command Pipeline - Read_cmnd (0) := Read_cmnd (1); - Read_cmnd (1) := Read_cmnd (2); - Read_cmnd (2) := Read_cmnd (3); - Read_cmnd (3) := Read_cmnd (4); - Read_cmnd (4) := Read_cmnd (5); - Read_cmnd (5) := Read_cmnd (6); - Read_cmnd (6) := Read_cmnd (7); - Read_cmnd (7) := Read_cmnd (8); - Read_cmnd (8) := '0'; - - -- Read Bank Pipeline - Read_bank (0) := Read_bank (1); - Read_bank (1) := Read_bank (2); - Read_bank (2) := Read_bank (3); - Read_bank (3) := Read_bank (4); - Read_bank (4) := Read_bank (5); - Read_bank (5) := Read_bank (6); - Read_bank (6) := Read_bank (7); - Read_bank (7) := Read_bank (8); - Read_bank (8) := "00"; - - -- Read Column Pipeline - Read_cols (0) := Read_cols (1); - Read_cols (1) := Read_cols (2); - Read_cols (2) := Read_cols (3); - Read_cols (3) := Read_cols (4); - Read_cols (4) := Read_cols (5); - Read_cols (5) := Read_cols (6); - Read_cols (6) := Read_cols (7); - Read_cols (7) := Read_cols (8); - Read_cols (8) := (OTHERS => '0'); - - -- Initialize Read command - IF Read_cmnd (0) = '1' THEN - Data_out_enable := '1'; - Bank_addr := Read_bank (0); - Cols_addr := Read_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Toggle Dqs during Read command - IF Data_out_enable = '1' THEN - Dqs_int := '0'; - IF Dqs_out = "00" THEN - Dqs_out <= "11"; - ELSIF Dqs_out = "11" THEN - Dqs_out <= "00"; - ELSE - Dqs_out <= "00"; - END IF; - ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN - Dqs_out <= "ZZ"; - END IF; - - -- Initialize Dqs for Read command - IF Read_cmnd (2) = '1' THEN - IF Data_out_enable = '0' THEN - Dqs_int := '1'; - Dqs_out <= "00"; - END IF; - END IF; - - -- Read Latch - IF Data_out_enable = '1' THEN - -- Initialize Memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Output Data - CASE Bank_addr IS - WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Increase Burst Counter - Burst_decode; - ELSE - Dq <= (OTHERS => 'Z'); - END IF; - END IF; - - -- - -- Write FIFO and DM Mask Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Write command pipeline - Write_cmnd (0) := Write_cmnd (1); - Write_cmnd (1) := Write_cmnd (2); - Write_cmnd (2) := '0'; - - -- Write command pipeline - Write_bank (0) := Write_bank (1); - Write_bank (1) := Write_bank (2); - Write_bank (2) := "00"; - - -- Write column pipeline - Write_cols (0) := Write_cols (1); - Write_cols (1) := Write_cols (2); - Write_cols (2) := (OTHERS => '0'); - - -- Initialize Write command - IF Write_cmnd (0) = '1' THEN - Data_in_enable := '1'; - Bank_addr := Write_bank (0); - Cols_addr := Write_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Write data - IF Data_in_enable = '1' THEN - -- Initialize memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Write first data - IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (0) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0); - END IF; - IF Dm_pair (1) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- Write second data - IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (2) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16); - END IF; - IF Dm_pair (3) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- tWR start and tWTR check - IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN - CASE Bank_addr IS - WHEN "00" => WR_chk0 := NOW; - WHEN "01" => WR_chk1 := NOW; - WHEN "10" => WR_chk2 := NOW; - WHEN OTHERS => WR_chk3 := NOW; - END CASE; - - -- tWTR check - ASSERT (Read_enable = '0') - REPORT "tWTR violation during Read" - SEVERITY WARNING; - END IF; - END IF; - END IF; - - -- - -- Auto Precharge Calculation - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Precharge counter - IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN - Count_precharge (0) := Count_precharge (0) + 1; - END IF; - IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN - Count_precharge (1) := Count_precharge (1) + 1; - END IF; - IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN - Count_precharge (2) := Count_precharge (2) + 1; - END IF; - IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN - Count_precharge (3) := Count_precharge (3) + 1; - END IF; - - -- Read with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. BL/2 cycles after command - IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW; - Read_precharge(0) := '0'; - END IF; - END IF; - IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW; - Read_precharge(1) := '0'; - END IF; - END IF; - IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW; - Read_precharge(2) := '0'; - END IF; - END IF; - IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW; - Read_precharge(3) := '0'; - END IF; - END IF; - - -- Write with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. Two clock after last burst - -- Since tWR is time base, the model will compensate tRP - IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW - ((2 * tCK) - tWR); - Write_precharge(0) := '0'; - END IF; - END IF; - IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW - ((2 * tCK) - tWR); - Write_precharge(1) := '0'; - END IF; - END IF; - IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW - ((2 * tCK) - tWR); - Write_precharge(2) := '0'; - END IF; - END IF; - IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW - ((2 * tCK) - tWR); - Write_precharge(3) := '0'; - END IF; - END IF; - END IF; - - -- - -- DLL Counter - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - IF (DLL_Reset = '1' AND DLL_done = '0') THEN - DLL_count := DLL_count + 1; - IF (DLL_count >= 200) THEN - DLL_done := '1'; - END IF; - END IF; - END IF; - - -- - -- Control Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Auto Refresh - IF Aref_enable = '1' THEN - -- Auto Refresh to Auto Refresh - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All banks must be Precharge before Auto Refresh" - SEVERITY WARNING; - - -- Record current tRFC time - RFC_chk := NOW; - END IF; - - -- Extended Load Mode Register - IF Ext_mode_enable = '1' THEN - IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN - IF (Addr (0) = '0') THEN - DLL_enable := '1'; - ELSE - DLL_enable := '0'; - END IF; - END IF; - - -- Precharge to EMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Extended Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Extended Load Register" - SEVERITY WARNING; - - -- LMR/EMR to EMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Extended Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Load Mode Register - IF Mode_reg_enable = '1' THEN - -- Register mode - Mode_reg <= Addr; - - -- DLL Reset - IF (DLL_enable = '1' AND Addr (8) = '1') THEN - DLL_reset := '1'; - DLL_done := '0'; - DLL_count := 0; - ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN - ASSERT (FALSE) - REPORT "DLL is ENABLE: DLL RESET is require" - SEVERITY WARNING; - ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN - ASSERT (FALSE) - REPORT "DLL is DISABLE: DLL RESET will be ignored" - SEVERITY WARNING; - END IF; - - -- Precharge to LMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Load Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Load Mode Register" - SEVERITY WARNING; - - -- LMR/ELMR to LMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid Burst Length - ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2 - (Addr (2 DOWNTO 0) = "010") OR -- BL = 4 - (Addr (2 DOWNTO 0) = "011")) -- BL = 8 - REPORT "Invalid Burst Length during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid CAS Latency - ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0 - (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5 - REPORT "Invalid CAS Latency during Load Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Active Block (latch Bank and Row Address) - IF Active_enable = '1' THEN - -- Activate an OPEN bank can corrupt data - ASSERT ((Ba = "00" AND Act_b0 = '0') OR - (Ba = "01" AND Act_b1 = '0') OR - (Ba = "10" AND Act_b2 = '0') OR - (Ba = "11" AND Act_b3 = '0')) - REPORT "Bank is already activated - data can be corrupted" - SEVERITY WARNING; - - -- Activate Bank 0 - IF Ba = "00" AND Pc_b0 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk0 >= tRC) - REPORT "tRC violation during Activate Bank 0" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk0 >= tRP) - REPORT "tRP violation during Activate Bank 0" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b0 := '1'; - Pc_b0 := '0'; - B0_row_addr := Addr; - RC_chk0 := NOW; - RCD_chk0 := NOW; - RAS_chk0 := NOW; - RAP_chk0 := NOW; - END IF; - - -- Activate Bank 1 - IF Ba = "01" AND Pc_b1 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk1 >= tRC) - REPORT "tRC violation during Activate Bank 1" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk1 >= tRP) - REPORT "tRP violation during Activate Bank 1" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b1 := '1'; - Pc_b1 := '0'; - B1_row_addr := Addr; - RC_chk1 := NOW; - RCD_chk1 := NOW; - RAS_chk1 := NOW; - RAP_chk1 := NOW; - END IF; - - -- Activate Bank 2 - IF Ba = "10" AND Pc_b2 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk2 >= tRC) - REPORT "tRC violation during Activate Bank 2" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk2 >= tRP) - REPORT "tRP violation during Activate Bank 2" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b2 := '1'; - Pc_b2 := '0'; - B2_row_addr := Addr; - RC_chk2 := NOW; - RCD_chk2 := NOW; - RAS_chk2 := NOW; - RAP_chk2 := NOW; - END IF; - - -- Activate Bank 3 - IF Ba = "11" AND Pc_b3 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk3 >= tRC) - REPORT "tRC violation during Activate Bank 3" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk3 >= tRP) - REPORT "tRP violation during Activate Bank 3" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b3 := '1'; - Pc_b3 := '0'; - B3_row_addr := Addr; - RC_chk3 := NOW; - RCD_chk3 := NOW; - RAS_chk3 := NOW; - RAP_chk3 := NOW; - END IF; - - -- Activate Bank A to Activate Bank B - IF (Prev_bank /= Ba) THEN - ASSERT (NOW - RRD_chk >= tRRD) - REPORT "tRRD violation during Activate" - SEVERITY WARNING; - END IF; - - -- AutoRefresh to Activate - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Activate" - SEVERITY WARNING; - - -- Record Variables for Checking Violation - RRD_chk := NOW; - Prev_bank := Ba; - END IF; - - -- Precharge Block - Consider NOP if bank already precharged or in process of precharging - IF Prech_enable = '1' THEN - -- EMR or LMR to Precharge - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Precharge" - SEVERITY WARNING; - - -- Precharge Bank 0 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN - Act_b0 := '0'; - Pc_b0 := '1'; - RP_chk0 := NOW; - - -- Activate to Precharge bank 0 - ASSERT (NOW - RAS_chk0 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk0 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 1 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN - Act_b1 := '0'; - Pc_b1 := '1'; - RP_chk1 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk1 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk1 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 2 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN - Act_b2 := '0'; - Pc_b2 := '1'; - RP_chk2 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk2 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk2 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 3 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN - Act_b3 := '0'; - Pc_b3 := '1'; - RP_chk3 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk3 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk3 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Pipeline for READ - IF CAS_latency_15 = '1' THEN - A10_precharge (3) := Addr(10); - Bank_precharge (3) := Ba; - Cmnd_precharge (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - A10_precharge (4) := Addr(10); - Bank_precharge (4) := Ba; - Cmnd_precharge (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - A10_precharge (5) := Addr(10); - Bank_precharge (5) := Ba; - Cmnd_precharge (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - A10_precharge (6) := Addr(10); - Bank_precharge (6) := Ba; - Cmnd_precharge (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - A10_precharge (8) := Addr(10); - Bank_precharge (8) := Ba; - Cmnd_precharge (8) := '1'; - END IF; - END IF; - - -- Burst Terminate - IF Burst_term = '1' THEN - -- Pipeline for Read - IF CAS_latency_15 = '1' THEN - Cmnd_bst (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - Cmnd_bst (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - Cmnd_bst (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - Cmnd_bst (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - Cmnd_bst (8) := '1'; - END IF; - - -- Terminate Write - ASSERT (Data_in_enable = '0') - REPORT "It's illegal to Burst Terminate a Write" - SEVERITY WARNING; - - -- Terminate Read with Auto Precharge - ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND - Read_precharge (2) = '0' AND Read_precharge (3) = '0') - REPORT "It's illegal to Burst Terminate a Read with Auto Precharge" - SEVERITY WARNING; - END IF; - - -- Read Command - IF Read_enable = '1' THEN - -- CAS Latency Pipeline - IF Cas_latency_15 = '1' THEN - Read_cmnd (3) := '1'; - Read_bank (3) := Ba; - Read_cols (3) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_2 = '1' THEN - Read_cmnd (4) := '1'; - Read_bank (4) := Ba; - Read_cols (4) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_25 = '1' THEN - Read_cmnd (5) := '1'; - Read_bank (5) := Ba; - Read_cols (5) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_3 = '1' THEN - Read_cmnd (6) := '1'; - Read_bank (6) := Ba; - Read_cols (6) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_4 = '1' THEN - Read_cmnd (8) := '1'; - Read_bank (8) := Ba; - Read_cols (8) := Addr (8 DOWNTO 0); - END IF; - - -- Write to Read: Terminate Write Immediately - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - END IF; - - -- Interrupting a Read with Auto Precharge (same bank only) - ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Read with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Read - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Read" - SEVERITY WARNING; - - -- Activate to Read without Auto Precharge - IF Addr (10) = '0' THEN - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Read" - SEVERITY WARNING; - END IF; - - -- Activate to Read with Auto Precharge - IF Addr (10) = '1' THEN - ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR - (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR - (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR - (Ba = "11" AND NOW - RAP_chk3 >= tRAP)) - REPORT "tRAP violation during Read" - SEVERITY WARNING; - END IF; - - -- Auto precharge - IF Addr (10) = '1' THEN - Read_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - - -- DLL Check - IF (DLL_reset = '1') THEN - ASSERT (DLL_done = '1') - REPORT "DLL RESET not complete" - SEVERITY WARNING; - END IF; - END IF; - - -- Write Command - IF Write_enable = '1' THEN - -- Pipeline for Write - Write_cmnd (2) := '1'; - Write_bank (2) := Ba; - Write_cols (2) := Addr (8 DOWNTO 0); - - -- Interrupting a Write with Auto Precharge (same bank only) - ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Write with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Write" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Write" - SEVERITY WARNING; - - -- Auto precharge - IF Addr (10) = '1' THEN - Write_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - END IF; - END IF; - END PROCESS; - - -- - -- Dqs Receiver - -- - dqs_rcvrs : PROCESS - VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0); - VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - BEGIN - WAIT ON Dqs; - -- Latch data at posedge Dqs - IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN - Dq_temp := Dq; - Dm_temp := Dm; - END IF; - -- Latch data at negedge Dqs - IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN - Dq_pair <= (Dq & Dq_temp); - Dm_pair <= (Dm & Dm_temp); - END IF; - END PROCESS; - - -- - -- Setup timing checks - -- - Setup_check : PROCESS - BEGIN - WAIT ON Sys_clk; - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIS) - REPORT "CKE Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIS) - REPORT "CS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIS) - REPORT "CAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIS) - REPORT "RAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIS) - REPORT "WE# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIS) - REPORT "ADDR Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIS) - REPORT "BA Setup time violation -- tIS" - SEVERITY WARNING; - END IF; - END PROCESS; - - -- - -- Hold timing checks - -- - Hold_check : PROCESS - BEGIN - WAIT ON Sys_clk'DELAYED (tIH); - IF Sys_clk'DELAYED (tIH) = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIH) - REPORT "CKE Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIH) - REPORT "CS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIH) - REPORT "CAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIH) - REPORT "RAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIH) - REPORT "WE# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIH) - REPORT "ADDR Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIH) - REPORT "BA Hold time violation -- tIH" - SEVERITY WARNING; - END IF; - END PROCESS; - -END behave; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd deleted file mode 100644 index 4f799c5..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd +++ /dev/null @@ -1,111 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Reset generator (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity reset is - port - ( - clk : in std_logic; - rst_in : in std_logic; - rst_out : out std_logic - ); -end; - -architecture tech of reset is - - signal rst : std_logic; - signal shift_pipe : std_logic_vector(3 downto 0); - attribute KEEP : string; - attribute KEEP of shift_pipe : signal is "TRUE"; - -begin - - rst <= shift_pipe(0); - -bufg_reset: bufg - port map - ( - o => rst_out, - i => rst - ); - -fdp0: fdp - generic map - ( - init => '1' - ) - port map - ( - d => rst_in, - c => clk, - pre => '0', - q => shift_pipe(3) - ); - -fdp1: fdp - generic map - ( - init => '1' - ) - port map - ( - - d => shift_pipe(3), - c => clk, - pre => '0', - q => shift_pipe(2) - ); - -fdp2: fdp - generic map - ( - init => '1' - ) - port map - ( - d => shift_pipe(2), - c => clk, - pre => '0', - q => shift_pipe(1) - ); - -fdp3: fdp - generic map - ( - init => '1' - ) - port map - ( - - d => shift_pipe(1), - c => clk, - pre => '0', - q => shift_pipe(0) - ); - -end tech; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd deleted file mode 100644 index a50b6e8..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd +++ /dev/null @@ -1,269 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: SDRAM command controller --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_cmd is - Generic (BL : natural := 2); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - enable : in STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_out : out user_tag_t; - phy_ctrl : out phy_ctrl_t; - cmd : in sdr_cmd_t; - cmd_we : in STD_LOGIC; - cmd_ack : out STD_LOGIC; - col_addr : in col_addr_t; - mode_word : in mode_word_t; - sdr_cmd_ctrl : out sdr_cmd_lines_t; - sdr_addr : out sdr_addr_t; - sdr_ba : out sdr_ba_t - ); -end sdram_cmd; - -architecture behaviour of sdram_cmd is - - signal st_sdr, st_sdr_next : sdr_state_t; - - signal cc_preset : natural range 0 to 10; - signal cc_load_en : std_logic; - signal cycle_finished : std_logic; - - signal burst_preset : natural range 0 to 3; - signal burst_load_en : std_logic; - signal burst_finished : std_logic; - -begin - - u_tag_out <= u_tag_in; - ------------------------------------------------------------------------------------------- - -fsm_sdr_state: - process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr) - begin - st_sdr_next <= st_sdr; - sdr_cmd_ctrl <= COMMAND(SD_NOP); - - cc_load_en <= '0'; - cc_preset <= TIMING(cmd); - burst_load_en <= '0'; - cmd_ack <= '0'; - burst_preset <= BL/2-1; - phy_ctrl.re <= '0'; - phy_ctrl.drive_en <= '0'; - phy_ctrl.we <= '0'; - phy_ctrl.utag_we <= '0'; - sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right); - sdr_ba <= mode_word(mode_word_t'left downto mode_word_t'left-1); - - case st_sdr is - when PWR_DOWN => - sdr_cmd_ctrl <= COMMAND(SD_DESELECT); - if enable = '1' then - st_sdr_next <= IDLE; - end if; - - when PRECHARGE => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when MODE => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when IDLE => - if cmd_we = '1' then - cmd_ack <= '1'; - cc_load_en <= '1'; - cc_preset <= TIMING(cmd); - sdr_cmd_ctrl <= COMMAND(cmd); - case cmd is - when SD_PRE => - st_sdr_next <= PRECHARGE; - sdr_addr(BIT_PRE_ALL) <= mode_word(BIT_PRE_ALL); - when SD_LMR => - st_sdr_next <= MODE; - when SD_ACT => - st_sdr_next <= ROW_ACT; - when SD_AR => - st_sdr_next <= AUTO_REF; - when others => null; - end case; - end if; - - when ROW_ACT => - if cycle_finished = '1' then - if cmd_we = '1' then - cmd_ack <= '1'; - burst_load_en <= '1'; - cc_load_en <= '1'; - cc_preset <= TIMING(cmd); - sdr_cmd_ctrl <= COMMAND(cmd); - case cmd is - when SD_PRE => - st_sdr_next <= PRECHARGE; - when SD_READ => - phy_ctrl.utag_we <= '1'; - st_sdr_next <= READ; - sdr_addr(col_addr_t'range) <= col_addr; - when SD_WRITE => - phy_ctrl.utag_we <= '1'; - phy_ctrl.drive_en <= '1'; - st_sdr_next <= WRITE; - sdr_addr(col_addr_t'range) <= col_addr; - when others => null; - end case; - end if; - end if; - - when WRITE => - phy_ctrl.drive_en <= '1'; - phy_ctrl.we <= '1'; - if burst_finished = '1' then - if cmd_we = '1' and cmd = SD_WRITE then - sdr_addr(col_addr_t'range) <= col_addr; - cmd_ack <= '1'; - burst_load_en <= '1'; - sdr_cmd_ctrl <= COMMAND(cmd); - phy_ctrl.utag_we <= '1'; - else - phy_ctrl.drive_en <= '0'; - cc_load_en <= '1'; - cc_preset <= TIMING(SD_WRITE)+1; - st_sdr_next <= ROW_ACT; - end if; - end if; - - when READ => - phy_ctrl.re <= '1'; - if burst_finished = '1' then - if cmd_we = '1' and cmd = SD_READ then - sdr_addr(col_addr_t'range) <= col_addr; - cmd_ack <= '1'; - burst_load_en <= '1'; - sdr_cmd_ctrl <= COMMAND(cmd); - phy_ctrl.utag_we <= '1'; - else - cc_load_en <= '1'; - cc_preset <= TIMING(SD_READ); - st_sdr_next <= ROW_ACT; - end if; - end if; - - when WRITE_A => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when READ_A => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when BURST_STOP => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when SELF_REF => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when PRE_PWR_DOWN => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when ACT_PWR_DOWN => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when AUTO_REF => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when others => - st_sdr_next <= IDLE; - end case; - - end process; - -fsm_sdr_state_next: - process (rst, clk) - begin - if rst = '1' then - st_sdr <= PWR_DOWN; - elsif rising_edge(clk) then - st_sdr <= st_sdr_next; - end if; - end process; - ------------------------------------------------------------------------------------------- -cycle_counter: - process (rst, clk) - variable cycle_cnt : natural range 0 to 10; - begin - if rst = '1' then - cycle_cnt := 0; - cycle_finished <= '0'; - elsif rising_edge(clk) then - cycle_finished <= '0'; - if cc_load_en = '1' then - cycle_cnt := cc_preset; - elsif cycle_cnt /= 0 then - cycle_cnt := cycle_cnt - 1; - else - cycle_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -burst_counter: - process (rst, clk) - variable burst_cnt : natural range 0 to 3; - begin - if rst = '1' then - burst_cnt := 0; - elsif rising_edge(clk) then - burst_finished <= '0'; - if burst_load_en = '1' then - burst_cnt := burst_preset; - elsif burst_cnt /= 0 then - burst_cnt := burst_cnt - 1; - end if; - if burst_cnt = 0 then - burst_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end behaviour; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd deleted file mode 100644 index b62e085..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd +++ /dev/null @@ -1,74 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: User SDRAM component adjustments --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package sdram_config is - - constant DDR_DATA_WIDTH : positive := 16; -- External DDR-SDRAM Module data bus width - constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module - constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM - constant DDR_ROW_ADDR_WIDTH : positive := 13; -- - constant DDR_COL_ADDR_WIDTH : positive := 9; -- - - constant LMR_REG_BASE : natural := 0; - constant LMR_REG_EXTENDED : natural := 1; - constant LMR_OP_NORMAL : natural := 0; - constant LMR_OP_RES_DLL : natural := 2; - constant LMR_BT_SEQ : natural := 0; - constant LMR_BT_ILVD : natural := 1; - constant LMR_BL2 : natural := 1; - constant LMR_BL4 : natural := 2; - constant LMR_BL8 : natural := 3; - constant LMR_CL2 : natural := 2; - constant LMR_CL3 : natural := 3; - constant LMR_CL2_5 : natural := 6; - - -- DDR SDRAM Hardware defined constants - constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) - constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) - constant ENABLE_PRE_ALL : std_logic := '1'; - constant ENABLE_AUTO_PRE : std_logic := '0'; - - -- DDR-SDR TIMING constants ------------------------------------------------------------------ - -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh - constant REFRESH_INTERVAL : real := 7.8125; -- us - - -- These values are for your SDRAM part (see datasheet) - constant TCAS : positive := 2; -- CAS latency [clocks] - constant TRP : positive := 2; -- precharge command period - constant TRAS : positive := 4; -- active to precharge delay - constant TRFC : positive := 8; -- auto refresh command period - constant TMRD : positive := 2; -- load mode register command cylce time - constant TRCD : positive := 2; -- active to read or write delay ! - constant TWR : positive := 2; -- write recovery time - - constant PWR_UP_WAIT : natural := 1; -- µs - - subtype user_tag_t is unsigned(3 downto 0); - - ---------------------------------------------------------------------------------------------- - -end sdram_config; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd deleted file mode 100644 index dbb5b80..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd +++ /dev/null @@ -1,487 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: SDRAM main controller and user I/F --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity sdram_ctrl is - Generic - ( - f_sysclk : natural := 100E6; - BL : natural := 2 - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - u_busy : out STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_out : out user_tag_t; - u_addr : in user_addr_t; - u_cmd : in user_cmd_t; - u_cmd_we : in STD_LOGIC; - col_addr : out col_addr_t; - sdr_cmd_busy : in STD_LOGIC; - sdr_cmd : out sdr_cmd_t; - sdr_cmd_we : out STD_LOGIC; - sdr_mode : out mode_word_t; - sdr_cke : out STD_LOGIC - ); -end sdram_ctrl; - -architecture behaviour of sdram_ctrl is - - constant LMR_BURST_LEN : natural := NextExpBaseTwo(BL); - - type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH); - signal st_ctrl, st_ctrl_next : ctrl_state_t; - - constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6); - signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1; - signal pwr_up_cnt_rst : std_logic; - signal pwr_up_finished : std_logic; - - signal cycle_cnt : natural range 0 to 255; - signal cc_preset : natural range 0 to 255; - signal cc_load_en : std_logic; - signal cycle_finished : std_logic; - - signal seq_cnt : natural range 0 to 31; - signal seq_rst_en : std_logic; - signal seq_cnt_en : std_logic; - - constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6); - signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1; - signal refresh_request : std_logic; - signal refresh_cnt_rst : std_logic; - - signal addr_reg_load_en : std_logic; - - signal u_tag_reg : user_tag_t; - signal bank_addr_reg : bank_addr_t; - signal row_addr_reg : row_addr_t; - signal col_addr_reg : col_addr_t; - - signal u_bank_addr : bank_addr_t; - signal u_row_addr : row_addr_t; - signal u_col_addr : col_addr_t; - - signal act_request : std_logic; - signal act_request_set : std_logic; - signal act_request_clr : std_logic; - - type init_seq_rom_t is array (0 to 14) of init_seq_t; - - constant init_seq_rom : init_seq_rom_t := - ( - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_PRE, - mode_word => "000010000000000", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_EXTENDED, 2) & "0000000000010", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3), - wait_cycle => 200 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_PRE, - mode_word => "000010000000000", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_AR, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_AR, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3), - wait_cycle => 200 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ) - - ); - -begin - - u_row_addr <= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1); - u_bank_addr <= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1); - u_col_addr <= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0); - ------------------------------------------------------------------------------------------- -fsm_ctrl_state: - process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, refresh_request, act_request) - begin - - u_busy <= '1'; - pwr_up_cnt_rst <= '0'; - cc_preset <= init_seq_rom(seq_cnt).wait_cycle; - cc_load_en <= '0'; - sdr_cmd <= init_seq_rom(seq_cnt).cmd; - sdr_cmd_we <= '0'; - sdr_mode <= bank_addr_reg & row_addr_reg; - col_addr <= col_addr_reg; - sdr_cke <= '1'; - seq_cnt_en <= '0'; - seq_rst_en <= '0'; - addr_reg_load_en <= '0'; - refresh_cnt_rst <= '0'; - act_request_set <= '0'; - act_request_clr <= '0'; - u_tag_out <= u_tag_reg; - - st_ctrl_next <= st_ctrl; - case st_ctrl is - when RESET => - sdr_cke <= '0'; - pwr_up_cnt_rst <= '1'; - st_ctrl_next <= POWER_WAIT; - - when POWER_WAIT => - sdr_cke <= '0'; - if pwr_up_finished = '1' then - seq_rst_en <= '1'; - st_ctrl_next <= INIT; - end if; - - when INIT => - sdr_mode <= init_seq_rom(seq_cnt).mode_word; - sdr_cmd <= init_seq_rom(seq_cnt).cmd; - cc_preset <= init_seq_rom(seq_cnt).wait_cycle; - if seq_cnt = init_seq_rom_t'high then - act_request_set <= '1'; - refresh_cnt_rst <= '1'; - st_ctrl_next <= USER_READY; - elsif sdr_cmd_busy = '0' then - cc_load_en <= '1'; - sdr_cmd_we <= '1'; - st_ctrl_next <= INIT_WAIT; - end if; - - when INIT_WAIT => - if sdr_cmd_busy = '0' and cycle_finished = '1' then - seq_cnt_en <= '1'; - st_ctrl_next <= INIT; - end if; - - when USER_READY => - if sdr_cmd_busy = '0' then - if refresh_request = '1' then - sdr_mode(BIT_PRE_ALL) <= '1'; - sdr_cmd_we <= '1'; - sdr_cmd <= SD_PRE; - st_ctrl_next <= REFRESH; - else - u_busy <= '0'; - if u_cmd_we = '1' then - case u_cmd is - when UCMD_NOP => - sdr_cmd <= SD_NOP; - when UCMD_LMR => - sdr_cmd <= SD_NOP; - when UCMD_WRITE => - col_addr <= u_col_addr; - u_tag_out <= u_tag_in; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - addr_reg_load_en <= '1'; - act_request_clr <= '1'; - sdr_cmd <= SD_WRITE; - if (u_row_addr /= row_addr_reg) or act_request = '1' then - st_ctrl_next <= USER_WRITE_PRE; - elsif (u_bank_addr /= bank_addr_reg) then - if ENABLE_PRE_ALL = '1' then - st_ctrl_next <= USER_WRITE_ACT; - else - st_ctrl_next <= USER_WRITE_PRE; - end if; - elsif sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - else - st_ctrl_next <= USER_WRITE; - end if; - when UCMD_READ => - col_addr <= u_col_addr; - u_tag_out <= u_tag_in; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - addr_reg_load_en <= '1'; - act_request_clr <= '1'; - sdr_cmd <= SD_READ; - if (u_row_addr /= row_addr_reg) or act_request = '1' then - st_ctrl_next <= USER_READ_PRE; - elsif (u_bank_addr /= bank_addr_reg) then - if ENABLE_PRE_ALL = '1' then - st_ctrl_next <= USER_READ_ACT; - else - st_ctrl_next <= USER_READ_PRE; - end if; - elsif sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - else - st_ctrl_next <= USER_READ; - end if; - when others => null; - end case; - end if; - end if; - end if; - - when USER_WRITE_PRE => - sdr_cmd <= SD_PRE; - sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_WRITE_ACT; - end if; - - when USER_WRITE_ACT => - sdr_cmd <= SD_ACT; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_WRITE; - end if; - - when USER_WRITE => - sdr_cmd <= SD_WRITE; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - end if; - - when USER_READ_PRE => - sdr_cmd <= SD_PRE; - sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READ_ACT; - end if; - - when USER_READ_ACT => - sdr_cmd <= SD_ACT; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READ; - end if; - - when USER_READ => - sdr_cmd <= SD_READ; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - end if; - - when REFRESH => - sdr_cmd <= SD_AR; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - refresh_cnt_rst <= '1'; - act_request_set <= '1'; - end if; - - when others => - st_ctrl_next <= RESET; - end case; - - end process; - -fsm_ctrl_state_next: - process (rst, clk) - begin - if rst = '1' then - st_ctrl <= RESET; - elsif rising_edge(clk) then - st_ctrl <= st_ctrl_next; - end if; - end process; - ------------------------------------------------------------------------------------------- -act_request_register: - process (rst, clk) - begin - if rst = '1' then - act_request <= '1'; - elsif rising_edge(clk) then - if act_request_set = '1' then - act_request <= '1'; - elsif act_request_clr = '1' then - act_request <= '0'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -user_addr_register: - process (rst, clk) - begin - if rst = '1' then - bank_addr_reg <= (others => '0'); - row_addr_reg <= (others => '0'); - col_addr_reg <= (others => '0'); - u_tag_reg <= (others => '0'); - elsif rising_edge(clk) then - if addr_reg_load_en = '1' then - bank_addr_reg <= u_bank_addr; - row_addr_reg <= u_row_addr; - col_addr_reg <= u_col_addr; - u_tag_reg <= u_tag_in; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -power_up_counter: - process (rst, clk) - begin - if rst = '1' then - pwr_up_cnt <= 0; - pwr_up_finished <= '0'; - elsif rising_edge(clk) then - pwr_up_finished <= '0'; - if pwr_up_cnt_rst = '1' then - pwr_up_cnt <= PWR_UP_CLOCK_INTERVAL-1; - else - if pwr_up_cnt /= 0 then - pwr_up_cnt <= pwr_up_cnt - 1; - else - pwr_up_finished <= '1'; - end if; - end if; - end if; - end process; - - ------------------------------------------------------------------------------------------- -refresh_counter: - process (rst, clk) - begin - if rst = '1' then - refresh_cnt <= 0; - refresh_request <= '0'; - elsif rising_edge(clk) then - refresh_request <= '0'; - if refresh_cnt_rst = '1' then - refresh_cnt <= REFRESH_CLOCK_INTERVAL-1; - else - if refresh_cnt /= 0 then - refresh_cnt <= refresh_cnt - 1; - else - refresh_request <= '1'; - end if; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -cycle_counter: - process (rst, clk) - begin - if rst = '1' then - cycle_cnt <= 0; - cycle_finished <= '0'; - elsif rising_edge(clk) then - cycle_finished <= '0'; - if cc_load_en = '1' then - cycle_cnt <= cc_preset; - elsif cycle_cnt /= 0 then - cycle_cnt <= cycle_cnt - 1; - else - cycle_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -seq_counter: - process (rst, clk) - begin - if rst = '1' then - seq_cnt <= 0; - elsif rising_edge(clk) then - if seq_rst_en = '1' then - seq_cnt <= 0; - elsif seq_cnt_en = '1' then - if seq_cnt /= init_seq_rom_t'high then - seq_cnt <= seq_cnt + 1; - end if; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end behaviour; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd deleted file mode 100644 index 98dea2a..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd +++ /dev/null @@ -1,277 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_ctrl_frontend is - Generic - ( - BL : natural := 2; - f_sysclk : natural := 100E6; - read_phaseshift : integer := 0; - fifo_depth : integer := 4 - ); - Port - ( - sys_rst_in : in STD_LOGIC; - sys_clk_in : in STD_LOGIC; - sys_rst_out : out STD_LOGIC; - sys_clk_out : out STD_LOGIC; - sys_clk_fb : in STD_LOGIC; - - -- User interface - busy : out STD_LOGIC; - en : in STD_LOGIC; - r_wn : in STD_LOGIC; - be : in unsigned(SDR_DM_WIDTH-1 downto 0); - addr : in user_addr_t; - din : in unsigned(SDR_DATA_WIDTH-1 downto 0); - dout : out unsigned(SDR_DATA_WIDTH-1 downto 0); - dout_re : in STD_LOGIC; - dout_vld : out STD_LOGIC; - - -- SDRAM signals - sd_clk_p : out STD_LOGIC; - sd_clk_n : out STD_LOGIC; - sd_cke : out STD_LOGIC; - sd_cs_n : out STD_LOGIC; - sd_cas_n : out STD_LOGIC; - sd_ras_n : out STD_LOGIC; - sd_we_n : out STD_LOGIC; - sd_addr : out sdr_addr_t; - sd_ba : out sdr_ba_t; - sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) - - ); -end sdram_ctrl_frontend; - -architecture struct of sdram_ctrl_frontend is - - -- Number of user data words for simulation - signal rst_out : std_logic; - signal clk_out : std_logic; - - signal u_addr : user_addr_t; - signal u_tag_in : user_tag_t; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t; - signal u_cmd_we : std_logic; - signal u_busy : std_logic; - signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_dm : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - - constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH; - signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_re : std_logic; - signal cat_fifo_we : std_logic; - signal cat_fifo_full : std_logic; - signal cat_fifo_empty : std_logic; --- signal cat_fifo_almost_full : std_logic; --- signal cat_fifo_almost_empty : std_logic; - - signal write_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal write_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal write_fifo_re : std_logic; - signal write_fifo_we : std_logic; - signal write_fifo_full : std_logic; - signal write_fifo_empty : std_logic; --- signal write_fifo_almost_full : std_logic; --- signal write_fifo_almost_empty : std_logic; - - signal read_fifo_din : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal read_fifo_dout : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal read_fifo_re : std_logic; - signal read_fifo_we : std_logic; - signal read_fifo_full : std_logic; - signal read_fifo_empty : std_logic; --- signal read_fifo_almost_full : std_logic; --- signal read_fifo_almost_empty : std_logic; - - alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0); - alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0); - alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-SDR_DM_WIDTH); - alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-SDR_DM_WIDTH-1 downto 0); - alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-SDR_DM_WIDTH); - alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-SDR_DM_WIDTH-1 downto 0); - -begin - - -- Instantiate synchronous FIFO - inst_cat_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => CAT_FIFO_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => cat_fifo_we, - re => cat_fifo_re, - fifo_full => cat_fifo_full, - fifo_empty => cat_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => cat_fifo_din, - data_r => cat_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_write_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => 2*DDR_DATA_WIDTH + SDR_DM_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_fifo_full, - fifo_empty => write_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => write_fifo_din, - data_r => write_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_read_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => 2*DDR_DATA_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => read_fifo_we, - re => read_fifo_re, - fifo_full => read_fifo_full, - fifo_empty => read_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => read_fifo_din, - data_r => read_fifo_dout - ); - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BL, - read_phaseshift => read_phaseshift, - f_sysclk => f_sysclk - ) - Port map - ( - - sys_rst_in => sys_rst_in, - sys_clk_in => sys_clk_in, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => sys_clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => open, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm, - - -- SDRAM signals - sd_clk_p => sd_clk_p, - sd_clk_n => sd_clk_n, - sd_cke => sd_cke, - sd_cs_n => sd_cs_n, - sd_cas_n => sd_cas_n, - sd_ras_n => sd_ras_n, - sd_we_n => sd_we_n, - sd_addr => sd_addr, - sd_ba => sd_ba, - sd_dm => sd_dm, - sd_dqs => sd_dqs, - sd_data => sd_data - - ); - ------------------------------------------------------------------------------------------- - sys_rst_out <= rst_out; - sys_clk_out <= clk_out; - - busy <= cat_fifo_full or write_fifo_full or read_fifo_full; - write_fifo_we <= en and not r_wn and not write_fifo_full and not cat_fifo_full and not read_fifo_full; - write_fifo_data_in <= din; - write_fifo_dm_in <= not be; - cat_fifo_we <= en and not cat_fifo_full and not write_fifo_full and not read_fifo_full; - cmd_fifo_in <= UCMD_WRITE when r_wn = '0' else UCMD_READ; - addr_fifo_in <= addr; - tag_fifo_in <= (others=>'0'); - dout <= read_fifo_dout; - dout_vld <= not read_fifo_empty; - - u_cmd_we <= (not cat_fifo_empty) and (not u_busy); - u_cmd <= cmd_fifo_out; - u_addr <= addr_fifo_out; - u_dm <= write_fifo_dm_out; - u_tag_in <= tag_fifo_out; - - write_fifo_re <= u_req_wr and (not write_fifo_empty); - cat_fifo_re <= u_cmd_we; - u_data_w <= write_fifo_data_out; - read_fifo_re <= (not read_fifo_empty) and dout_re; - read_fifo_we <= u_data_vld; - read_fifo_din <= u_data_r; - - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd deleted file mode 100644 index ba9ee71..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd +++ /dev/null @@ -1,285 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Top-level put all together --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_ctrl_top is - Generic - ( - BL : natural := 2; - f_sysclk : natural := 100E6; - read_phaseshift : integer := 0 - ); - Port - ( - sys_rst_in : in STD_LOGIC; - sys_clk_in : in STD_LOGIC; - sys_rst_out : out STD_LOGIC; - sys_clk_out : out STD_LOGIC; - sys_clk_fb : in STD_LOGIC; - - -- User interface - u_data_vld : out STD_LOGIC; - u_data_req_w : out STD_LOGIC; - u_data_req_r : out STD_LOGIC; - u_busy : out STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_rd : out user_tag_t; - u_tag_wr : out user_tag_t; - u_addr : in user_addr_t; - u_cmd : in user_cmd_t; - u_cmd_we : in STD_LOGIC; - u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0); - u_dm : in unsigned(SDR_DM_WIDTH-1 downto 0); - u_data_rd : out unsigned(SDR_DATA_WIDTH-1 downto 0); - - -- SDRAM signals - sd_clk_p : out STD_LOGIC; - sd_clk_n : out STD_LOGIC; - sd_cke : out STD_LOGIC; - sd_cs_n : out STD_LOGIC; - sd_cas_n : out STD_LOGIC; - sd_ras_n : out STD_LOGIC; - sd_we_n : out STD_LOGIC; - sd_addr : out sdr_addr_t; - sd_ba : out sdr_ba_t; - sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) - - ); -end sdram_ctrl_top; - -architecture rtl of sdram_ctrl_top is - - signal clk0 : std_logic; - signal clk270 : std_logic; - signal read_clk270 : std_logic; - - signal phy_ctrl : phy_ctrl_t; - - signal u_tag : user_tag_t; - signal sd_cmd_in : sdr_cmd_t; - signal sd_cmd : sdr_cmd_t; - signal sd_cmd_we : std_logic; - signal cmd_ctrl : sdr_cmd_lines_t; - signal cke : std_logic; - signal ba : unsigned(DDR_BANK_WIDTH-1 downto 0); - signal addr : unsigned(DDR_ADDR_WIDTH-1 downto 0); - - -- Clock generator - - signal cg_rst : std_logic; - signal cg_read_clk0 : std_logic; - signal cg_read_clk270 : std_logic; - signal cg_sys_clk0 : std_logic; - signal cg_sys_clk270 : std_logic; - signal cg_locked : std_logic; - signal cg_error : std_logic; - signal ctrl_rst : std_logic; - signal part_ctrl : part_ctrl_t; - - -- SD command FIFO - - constant CMD_FIFO_ADDR_WIDTH : positive := 2; - constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length; - signal cmd_fifo_din : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); - signal cmd_fifo_dout : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); - signal cmd_fifo_re : std_logic; - signal cmd_fifo_we : std_logic; - signal cmd_fifo_full : std_logic; - signal cmd_fifo_empty : std_logic; - - alias tag_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length); - alias cmd_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4); - alias mode_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length); - alias col_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0); - - alias tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length); - alias cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4); - alias mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length); - alias col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0); - -begin - - --------------------------------- - clk0 <= cg_sys_clk0; - clk270 <= cg_sys_clk270; - read_clk270 <= cg_read_clk270; - cg_rst <= not cg_locked; - - --------------------------------- - sys_clk_out <= cg_sys_clk0; - sys_rst_out <= ctrl_rst; - - --------------------------------- - part_ctrl.cmd <= cmd_ctrl; - part_ctrl.ba <= ba; - part_ctrl.addr <= addr; - part_ctrl.cke <= cke; - - --------------------------------- - sd_cmd_we <= not cmd_fifo_empty; - cmd_fifo_in <= to_unsigned(sd_cmd_in, 4); - sd_cmd <= sdr_cmd_t(to_integer(cmd_fifo_out)); - - --------------------------------- - inst_reset: entity work.reset - port map - ( - clk => clk0, - rst_in => cg_rst, - rst_out => ctrl_rst - ); - - inst_clockgen : entity work.clockgen - generic map - ( - read_phaseshift => read_phaseshift, - frequency_hz => f_sysclk - ) - port map - ( - rst => sys_rst_in, - clk_in => sys_clk_in, - clk_fb_in => sys_clk_fb, - read_clk0_out => cg_read_clk0, - read_clk270_out => cg_read_clk270, - sys_clk0_out => cg_sys_clk0, - sys_clk270_out => cg_sys_clk270, - locked_out => cg_locked, - error_out => cg_error - ); - - -- Main controller - inst_sdram_ctrl : entity work.sdram_ctrl - Generic map - ( - f_sysclk => 100E6, - BL => BL - ) - Port map - ( - rst => ctrl_rst, - clk => clk0, - u_busy => u_busy, - u_tag_in => u_tag_in, - u_tag_out => tag_fifo_in, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_addr => u_addr, - sdr_cmd_busy => cmd_fifo_full, - sdr_cmd => sd_cmd_in, - sdr_cmd_we => cmd_fifo_we, - col_addr => col_fifo_in, - sdr_mode => mode_fifo_in, - sdr_cke => cke - ); - - -- Instantiate synchronous FIFO - inst_sd_cmd_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => CMD_FIFO_ADDR_WIDTH, - data_width => CMD_FIFO_DATA_WIDTH, - almost_full_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1), - almost_empty_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1) - ) - PORT MAP - ( - rst => ctrl_rst, - clk => clk0, - we => cmd_fifo_we, - re => cmd_fifo_re, - fifo_full => cmd_fifo_full, - fifo_empty => cmd_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => cmd_fifo_din, - data_r => cmd_fifo_dout - ); - - -- DDR SDRAM command fsm - inst_sdram_cmd : entity work.sdram_cmd - Generic map - ( - BL => BL - ) - Port map - ( - rst => ctrl_rst, - clk => clk0, - u_tag_in => tag_fifo_out, - u_tag_out => u_tag, - phy_ctrl => phy_ctrl, - enable => cke, - cmd => sd_cmd, - cmd_we => sd_cmd_we, - cmd_ack => cmd_fifo_re, - sdr_cmd_ctrl => cmd_ctrl, - col_addr => col_fifo_out, - mode_word => mode_fifo_out, - sdr_ba => ba, - sdr_addr => addr - ); - - -- DDR phy - inst_ddr_phy : entity work.ddr_phy - Port map - ( - sys_rst => ctrl_rst, - sys_clk0 => clk0, - sys_clk270 => clk270, - u_tag_in => u_tag, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - read_clk => read_clk270, - phy_ctrl => phy_ctrl, - part_ctrl => part_ctrl, - sdr_data_req_w => u_data_req_w, - sdr_data_req_r => u_data_req_r, - sdr_data_w => u_data_wr, - sdr_dm => u_dm, - sdr_data_r => u_data_rd, - sdr_data_vld => u_data_vld, - part_clk_p => sd_clk_p, - part_clk_n => sd_clk_n, - part_addr => sd_addr, - part_ba => sd_ba, - part_dm => sd_dm, - part_dqs => sd_dqs, - part_data => sd_data, - part_cs_n => sd_cs_n, - part_we_n => sd_we_n, - part_cas_n => sd_cas_n, - part_ras_n => sd_ras_n, - part_cke => sd_cke - ); - -end architecture rtl; - diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd deleted file mode 100644 index d235d75..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd +++ /dev/null @@ -1,133 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Type definitions --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.sdram_config.all; - -package sdram_types is - - ----------------------------------------------------------------------------------------- - -- Table of Timing Parameters as a function of operation - - -- Derived constants from sdram_config - - constant DDR_DQS_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines - constant DDR_DM_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines - constant SDR_DATA_WIDTH : positive := 2*DDR_DATA_WIDTH; -- - constant SDR_DM_WIDTH : positive := 2*DDR_DM_WIDTH; -- - - subtype user_cmd_t is unsigned(1 downto 0); - constant UCMD_NOP : user_cmd_t := "00"; - constant UCMD_READ : user_cmd_t := "01"; - constant UCMD_WRITE : user_cmd_t := "10"; - constant UCMD_LMR : user_cmd_t := "11"; - - subtype sdr_cmd_t is natural range 0 to 9; - constant SD_DESELECT : sdr_cmd_t := 0; - constant SD_NOP : sdr_cmd_t := 1; - constant SD_LMR : sdr_cmd_t := 2; - constant SD_ACT : sdr_cmd_t := 3; - constant SD_READ : sdr_cmd_t := 4; - constant SD_WRITE : sdr_cmd_t := 5; - constant SD_PRE : sdr_cmd_t := 6; - constant SD_BST : sdr_cmd_t := 7; - constant SD_AR : sdr_cmd_t := 8; - constant SD_SR : sdr_cmd_t := 9; - - type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN); - subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0); - subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0); - subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0); - subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0); - - subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0); - subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0); - subtype col_addr_t is unsigned(8 downto 0); - - subtype cycle_cnt_t is natural range 0 to 10; - - type phy_ctrl_t is - record - drive_en : std_logic; - re : std_logic; - we : std_logic; - utag_we : std_logic; - end record phy_ctrl_t; - - type sdr_cmd_lines_t is - record - cs_n : std_logic; - ras_n : std_logic; - cas_n : std_logic; - we_n : std_logic; - end record sdr_cmd_lines_t; - - type part_ctrl_t is - record - cmd : sdr_cmd_lines_t; - ba : unsigned(DDR_BANK_WIDTH-1 downto 0); - addr : unsigned(DDR_ADDR_WIDTH-1 downto 0); - cke : std_logic; - end record part_ctrl_t; - - type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t; - constant COMMAND : part_cmd_array_t := - -- command cs_n ras_qn cas_qn we_qn - ( SD_DESELECT => ( '1', '1', '1', '1'), - SD_NOP => ( '0', '1', '1', '1'), - SD_LMR => ( '0', '0', '0', '0'), - SD_ACT => ( '0', '0', '1', '1'), - SD_READ => ( '0', '1', '0', '1'), - SD_WRITE => ( '0', '1', '0', '0'), - SD_PRE => ( '0', '0', '1', '0'), - SD_BST => ( '0', '1', '1', '0'), - SD_AR => ( '0', '0', '0', '1'), - SD_SR => ( '0', '0', '0', '1') - ); - - type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t; - constant TIMING : part_timing_array_t := - -- command cycle_cnt - ( SD_DESELECT => ( 0 ), - SD_NOP => ( 0 ), - SD_LMR => ( TMRD-1 ), - SD_ACT => ( TRCD-1 ), - SD_READ => ( TCAS-1 ), - SD_WRITE => ( TWR-1 ), - SD_PRE => ( TRP-1 ), - SD_BST => ( 0 ), - SD_AR => ( TRFC-1 ), - SD_SR => ( TRFC-1 ) - ); - - type init_seq_t is - record - cmd : sdr_cmd_t; - mode_word : mode_word_t; - wait_cycle : natural; - end record init_seq_t; - -end sdram_types; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd deleted file mode 100644 index cc18253..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd +++ /dev/null @@ -1,332 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - end if; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_read_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - u_addr <= u_addr_preset; - elsif u_addr_cnt_en = '1' then - if u_addr_mode = MONOTONIC then - u_addr <= u_addr + BURST_LEN; - else - if u_addr(u_addr'left) = '1' then - if BURST_LEN = 2 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100"; - elsif BURST_LEN = 4 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110"; - elsif BURST_LEN = 8 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100"; - end if; - else - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left); - end if; - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000"; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0'; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - u_addr_preset <= X"000000"; - u_addr_end <= X"008000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 1 - u_addr_preset <= X"400000"; - u_addr_end <= X"408000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - u_addr_preset <= X"000000"; - u_addr_end <= X"008000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 1 - u_addr_preset <= X"400000"; - u_addr_end <= X"408000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd deleted file mode 100644 index 6a2a9da..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd +++ /dev/null @@ -1,416 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity tb_sdr_ctrl_fifo is -end; - -architecture struct of tb_sdr_ctrl_fifo is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - - signal cmd_fifo_din : unsigned(25 downto 0) := (others => '0'); - signal cmd_fifo_dout : unsigned(25 downto 0) := (others => '0'); - signal cmd_fifo_re : std_logic := '0'; - signal cmd_fifo_we : std_logic := '0'; - signal cmd_fifo_full : std_logic := '0'; - signal cmd_fifo_empty : std_logic := '0'; - signal cmd_fifo_almost_full : std_logic := '0'; - signal cmd_fifo_almost_empty : std_logic := '0'; - - signal write_fifo_din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal write_fifo_dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal write_fifo_re : std_logic := '0'; - signal write_fifo_we : std_logic := '0'; - signal write_fifo_full : std_logic := '0'; - signal write_fifo_empty : std_logic := '0'; - signal write_fifo_almost_full : std_logic := '0'; - signal write_fifo_almost_empty : std_logic := '0'; - - signal read_fifo_din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal read_fifo_dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal read_fifo_re : std_logic := '0'; - signal read_fifo_we : std_logic := '0'; - signal read_fifo_full : std_logic := '0'; - signal read_fifo_empty : std_logic := '0'; - signal read_fifo_almost_full : std_logic := '0'; - signal read_fifo_almost_empty : std_logic := '0'; - - signal write_start : std_logic := '1'; - signal read_start : std_logic := '1'; - - alias cmd_fifo_in is cmd_fifo_din(25 downto 24); - alias addr_fifo_in is cmd_fifo_din(23 downto 0); - alias cmd_fifo_out is cmd_fifo_dout(25 downto 24); - alias addr_fifo_out is cmd_fifo_dout(23 downto 0); - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- Instantiate synchronous FIFO - inst_command_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 8, - data_width => 2+24 - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => cmd_fifo_we, - re => cmd_fifo_re, - fifo_full => cmd_fifo_full, - fifo_empty => cmd_fifo_empty, - fifo_afull => cmd_fifo_almost_full, - fifo_aempty => cmd_fifo_almost_empty, - data_w => cmd_fifo_din, - data_r => cmd_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_write_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 8, - data_width => 2*DDR_DATA_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_fifo_full, - fifo_empty => write_fifo_empty, - fifo_afull => write_fifo_almost_full, - fifo_aempty => write_fifo_almost_empty, - data_w => write_fifo_din, - data_r => write_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_read_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 8, - data_width => 2*DDR_DATA_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => read_fifo_we, - re => read_fifo_re, - fifo_full => read_fifo_full, - fifo_empty => read_fifo_empty, - fifo_afull => read_fifo_almost_full, - fifo_aempty => read_fifo_almost_empty, - data_w => read_fifo_din, - data_r => read_fifo_dout - ); - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - u_cmd_we <= (not cmd_fifo_empty) and write_start and (not u_busy); - u_cmd <= cmd_fifo_out; - u_addr <= addr_fifo_out; - - write_fifo_re <= u_req_wr and (not write_fifo_empty); - cmd_fifo_re <= u_cmd_we; - u_data_w <= write_fifo_dout; - read_fifo_re <= (not read_fifo_empty) and read_start; - read_fifo_we <= u_data_vld; - read_fifo_din <= u_data_r; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait for 4*CLK_PERIOD; - wait until rising_edge(clk_out) and rst_out='0'; - - write_fifo_we <= '1'; - cmd_fifo_we <= '1'; - write_fifo_din <= X"01020304"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000000"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"05060708"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000002"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"00001111"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000004"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"22223333"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000006"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"44445555"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000008"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"66667777"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00000a"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"88889999"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00000c"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"AAAABBBB"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00000e"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"CCCCDDDD"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000010"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"EEEEFFFF"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000012"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_we <= '0'; - --- wait until rising_edge(clk_out) and u_busy='0'; --- write_start <= '1'; --- wait until rising_edge(clk_out) and write_fifo_empty='1'; - - write_fifo_we <= '1'; - cmd_fifo_we <= '1'; - write_fifo_din <= X"01234567"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000014"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000014"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"89ABCDEF"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000016"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"11223344"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000018"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000010"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"55667788"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00001a"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"99990000"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00001c"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"AAAA5555"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000020"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000000"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000018"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"00001A"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"00001C"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000020"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_we <= '0'; - - wait for 40*CLK_PERIOD; - read_start <= '1'; - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd deleted file mode 100644 index 3ab72bd..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd +++ /dev/null @@ -1,318 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal lin_addr : user_addr_t := (others => '0'); - signal rand_gen : unsigned(7 downto 0) := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal rw_null_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' and u_tag_rd = "0000" then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - end if; - elsif u_read_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' and u_tag_wr = "0000" then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - lin_addr <= u_addr_preset; - rand_gen <= X"80"; - elsif u_addr_cnt_en = '1' then - lin_addr <= lin_addr + BURST_LEN; - if rand_gen(rand_gen'left) = '1' then - rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010"; - else - rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left); - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= "000" & rw_null_en; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0'; - u_addr <= (rand_gen(7) and (not rw_null_en)) & lin_addr(lin_addr'left-1 downto 0); - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_write_en <= '1'; - rw_null_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_READ; - rw_null_en <= '1'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_WRITE; - end if; - rw_null_en <= '0'; - end if; - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - wait for 200*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_read_en <= '1'; - rw_null_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_WRITE; - rw_null_en <= '1'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_READ; - end if; - rw_null_en <= '0'; - end if; - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd deleted file mode 100644 index 312d2a8..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd +++ /dev/null @@ -1,316 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal lin_addr : user_addr_t := (others => '0'); - signal rand_gen : unsigned(7 downto 0) := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal rw_null_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' and u_tag_rd = "0000" then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - end if; - elsif u_read_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' and u_tag_wr = "0000" then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - lin_addr <= u_addr_preset; - rand_gen <= X"80"; - elsif u_addr_cnt_en = '1' then - lin_addr <= lin_addr + BURST_LEN; - if rand_gen(rand_gen'left) = '1' then - rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010"; - else - rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left); - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= "000" & rw_null_en; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0'; - u_addr <= (rand_gen(7) and (rw_null_en)) & lin_addr(lin_addr'left-1 downto 0); - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_WRITE; - rw_null_en <= '0'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_READ; - end if; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - wait for 200*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_READ; - rw_null_en <= '0'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_WRITE; - end if; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd deleted file mode 100644 index e20e4af..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd +++ /dev/null @@ -1,315 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - end if; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_read_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - u_addr <= u_addr_preset; - elsif u_addr_cnt_en = '1' then - if u_addr_mode = MONOTONIC then - u_addr <= u_addr + BURST_LEN; - else - if u_addr(u_addr'left) = '1' then - if BURST_LEN = 2 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100"; - elsif BURST_LEN = 4 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110"; - elsif BURST_LEN = 8 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100"; - end if; - else - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left); - end if; - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000"; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0'; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"5E2330"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"5E2330"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd deleted file mode 100644 index 26c8b9b..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd +++ /dev/null @@ -1,329 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal rw_null_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - end if; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_read_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - u_addr <= u_addr_preset; - elsif u_addr_cnt_en = '1' then - if u_addr_mode = MONOTONIC then - u_addr <= u_addr + BURST_LEN; - else - if u_addr(u_addr'left) = '1' then - if BURST_LEN = 2 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100"; - elsif BURST_LEN = 4 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110"; - elsif BURST_LEN = 8 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100"; - end if; - else - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left); - end if; - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000"; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0'; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"646808"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - while u_addr /= u_addr_end loop - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - rw_null_en <= '0'; - if u_addr(20) = '0' then - u_cmd <= UCMD_READ; - u_write_en <= '0'; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - rw_null_en <= '0'; - wait for 200*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"646808"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - while u_addr /= u_addr_end loop - u_cmd <= UCMD_READ; - u_read_en <= '1'; - rw_null_en <= '0'; - if u_addr(20) = '0' then - u_cmd <= UCMD_WRITE; - u_read_en <= '0'; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd deleted file mode 100644 index 95ffa58..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd +++ /dev/null @@ -1,385 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity tb_sdram_ctrl_frontend is -end; - -architecture struct of tb_sdram_ctrl_frontend is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal addr : user_addr_t := (others => '0'); - signal r_wn : std_logic := '0'; - signal en : std_logic := '0'; - signal busy : std_logic; - signal din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal be : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "1111"; - signal dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal dout_vld : std_logic; - signal dout_re : std_logic; - signal dout_reg : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl_frontend : entity work.sdram_ctrl_frontend - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6, - fifo_depth => 4 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - busy => busy, - en => en, - r_wn => r_wn, - be => be, - addr => addr, - din => din, - dout => dout, - dout_re => dout_re, - dout_vld => dout_vld, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -read_register: - process(clk_out) - begin - if rising_edge(clk_out) then - if dout_vld = '1' then - dout_reg <= dout; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- - dout_re <= dout_vld; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait for 4*CLK_PERIOD; - wait until rising_edge(clk_out) and rst_out='0'; - - for i in 0 to 999 loop - en <= '1'; - r_wn <= '0'; - din <= to_unsigned(i, 32); - addr <= to_unsigned(2*i, 24); - wait until rising_edge(clk_out) and busy = '0'; - end loop; - - for i in 0 to 999 loop - en <= '1'; - r_wn <= '1'; - din <= to_unsigned(i, 32); - addr <= to_unsigned(2*i, 24); - wait until rising_edge(clk_out) and busy = '0'; - end loop; - - en <= '1'; - r_wn <= '0'; - din <= X"01020304"; - addr <= X"000000"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"05060708"; - addr <= X"000002"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"00001111"; - addr <= X"000004"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"22223333"; - addr <= X"000006"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"44445555"; - addr <= X"000008"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"66667777"; - addr <= X"00000a"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"88889999"; - addr <= X"00000c"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"AAAABBBB"; - addr <= X"00000e"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CCCCDDDD"; - addr <= X"000010"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"EEEEFFFF"; - addr <= X"000012"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"FFFFFFFF"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"87CCCCCC"; - be <= "1000"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CC65CCCC"; - be <= "0100"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CCCC43CC"; - be <= "0010"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"89ABCDEF"; - addr <= X"000016"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CCCCCC21"; - be <= "0001"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"55555555"; - be <= "1010"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"AAAAAAAA"; - be <= "0101"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - be <= "1111"; - en <= '1'; - r_wn <= '0'; - din <= X"11223344"; - addr <= X"000018"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000010"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"55667788"; - addr <= X"00001a"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"99990000"; - addr <= X"00001c"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"AAAA5555"; - addr <= X"000020"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000000"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000018"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"00001A"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"00001C"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000020"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/VGA_ctrl/src/char_gen.vhd b/lib/VGA_ctrl/src/char_gen.vhd deleted file mode 100644 index 5d82fc9..0000000 --- a/lib/VGA_ctrl/src/char_gen.vhd +++ /dev/null @@ -1,546 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: char_gen - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity char_gen is - Generic - ( - tsvga : vga_timespec_t := ts_vga_800_600_72; - - -- User supplied parameters - CHARACTER_SCALE : natural := 1; - CHAR_ROM_SIZE_X : natural := 8; -- Pixels - CHAR_ROM_SIZE_Y : natural := 16; -- Pixels - CHAR_ROM_DEPTH : natural := 256; -- Chars - MAX_CHAR_PER_LINE : natural := 32; -- Chars - MAX_LINE_PER_FRAME : natural := 16; -- Chars - CHAR_SPACING_X : natural := 0; -- Pixels - CHAR_SPACING_Y : natural := 0; -- Pixels - SCREEN_OFFSET_X : natural := 16; -- Pixels - SCREEN_OFFSET_Y : natural := 16 -- Pixels - ); - Port - ( - -- System signals - rst : in std_logic; - vga_clk : in std_logic; - sys_clk : in std_logic; - ce : in std_logic; - frame_pulse : in std_logic; - - - -- Host Signals - clr_screen : in std_logic; - clr_line : in std_logic; - ascii_data : in unsigned(7 downto 0); - ascii_data_we : in std_logic; - ascii_posy_we : in std_logic; - ascii_posx_we : in std_logic; - ready : out std_logic; - - -- Control signals - pos_x : in natural range 0 to tsvga.ts_h.ncyc_scan-1; - pos_y : in natural range 0 to tsvga.ts_v.ncyc_scan-1; - - -- Output - char_draw_en : out std_logic - - ); -end char_gen; - -architecture Behavioral of char_gen is - - constant A_RAM_ADDR_WIDTH : integer := 12; - constant A_RAM_DATA_WIDTH : integer := 8; - - type offset_rom_t is array (0 to MAX_LINE_PER_FRAME-1) of unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - - - - function gen_offset_rom(num_char_per_line, num_lines : natural) return offset_rom_t is - variable result : offset_rom_t; - - variable offset : unsigned(A_RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); - begin - for i in 0 to num_lines-1 loop - result(i) := offset; - offset := offset + to_unsigned(num_char_per_line, A_RAM_ADDR_WIDTH-1); - end loop; - return result; - end gen_offset_rom; - - constant offset_rom : offset_rom_t := gen_offset_rom(MAX_CHAR_PER_LINE, MAX_LINE_PER_FRAME); - - -- Calculated parameters - type cg_state_t is (cg_init, cg_ready, cg_clr_line, cg_clr_screen); - signal s, sn : cg_state_t; - - constant CELL_SIZE_X : natural := (CHAR_ROM_SIZE_X+CHAR_SPACING_X)*CHARACTER_SCALE; - constant CELL_SIZE_Y : natural := (CHAR_ROM_SIZE_Y+CHAR_SPACING_Y)*CHARACTER_SCALE; - constant CHAR_SIZE_X : natural := CHAR_ROM_SIZE_X*CHARACTER_SCALE; - constant CHAR_SIZE_Y : natural := CHAR_ROM_SIZE_Y*CHARACTER_SCALE; - - signal line_offset : natural range 0 to MAX_LINE_PER_FRAME-1; - signal cell_x_cnt : natural range 0 to MAX_CHAR_PER_LINE-1; - signal cell_y_cnt : natural range 0 to MAX_LINE_PER_FRAME-1; - signal char_x_cnt : natural range 0 to CELL_SIZE_X-1; - signal char_y_cnt : natural range 0 to CELL_SIZE_Y-1; - signal char_rom_row : unsigned(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto 0); - signal char_rom_addr : unsigned(NextExpBaseTwo(CHAR_ROM_DEPTH*CHAR_ROM_SIZE_Y)-1 downto 0); - signal char_rom_data : unsigned(CHAR_ROM_SIZE_X-1 downto 0); - signal char_reg : unsigned((CHARACTER_SCALE*CHAR_ROM_SIZE_X)-1 downto 0); - - signal a_addr_rd : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - signal a_addr_wr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - signal a_data_rd : unsigned(A_RAM_DATA_WIDTH-1 downto 0); - signal a_data_wr : unsigned(A_RAM_DATA_WIDTH-1 downto 0); - signal a_ram_we : std_logic; - signal a_cnt : natural range 0 to 2**A_RAM_ADDR_WIDTH-1; - signal a_cnt_rst : std_logic; - signal a_cnt_en : std_logic; - signal csr_posx_reg : natural range 0 to MAX_CHAR_PER_LINE-1; - signal csr_posy_reg : natural range 0 to MAX_LINE_PER_FRAME-1; - signal a_data_reg : unsigned(A_RAM_DATA_WIDTH-1 downto 0); - signal a_data_we : std_logic; - signal csr_posx_overflow : std_logic; - signal csr_posx_cnt_din : natural range 0 to MAX_CHAR_PER_LINE-1; - signal csr_posx_cnt_set : std_logic; - signal csr_posx_cnt_en : std_logic; - signal csr_posy_overflow : std_logic; - signal csr_posy_cnt_din : natural range 0 to MAX_LINE_PER_FRAME-1; - signal csr_posy_cnt_set : std_logic; - signal csr_posy_cnt_en : std_logic; - - signal line_addr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - signal char_addr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - - -- Visible Cursor - constant CURSOR_BLINK_INTERVAL : natural := tsvga.nfps/2; - - type cursor_rom_t is array (0 to 2*CHAR_ROM_SIZE_Y-1) of unsigned (CHAR_ROM_SIZE_X-1 downto 0); - constant cursor_rom : cursor_rom_t := - ( - -- Cursor off - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "11111111", - "11111111", - "11111111", - - -- Cursor on - "00000000", - "00000000", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "00000000", - "00000000", - "00000000" - - ); - signal cursor_rom_addr : unsigned(NextExpBaseTwo(2*CHAR_ROM_SIZE_Y)-1 downto 0); - signal cursor_rom_data : unsigned(CHAR_ROM_SIZE_X-1 downto 0); - signal cursor_visible : std_logic; - signal cursor_cnt : natural range 0 to CURSOR_BLINK_INTERVAL-1; - signal csr_posx_synced : natural range 0 to MAX_CHAR_PER_LINE-1; - signal csr_posy_synced : natural range 0 to MAX_LINE_PER_FRAME-1; - - -- Scrolling - signal scroll_offset : natural range 0 to MAX_CHAR_PER_LINE-1; - signal scroll_active : std_logic; - - -begin - - a_addr_rd <= to_unsigned(cell_x_cnt, a_addr_rd'length) + offset_rom(line_offset); - line_addr <= offset_rom(csr_posy_reg); - char_addr <= to_unsigned(csr_posx_reg, char_addr'length); - char_rom_addr <= a_data_rd & char_rom_row(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto (CHARACTER_SCALE-1)); - cursor_rom_addr <= cursor_visible & char_rom_row(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto (CHARACTER_SCALE-1)); - - inst_char_rom : entity work.char_rom - PORT MAP - ( - CLK => vga_clk, - ADDR => char_rom_addr, - DATA => char_rom_data - ); - - inst_ascii_ram: entity work.dpram - GENERIC MAP ( - addr_width => A_RAM_ADDR_WIDTH, - data_width => A_RAM_DATA_WIDTH - ) - PORT MAP( - clka => sys_clk, - clkb => vga_clk, - en_a => '1', - en_b => '1', - we_a => a_ram_we, - addr_a => a_addr_wr, - addr_b => a_addr_rd, - din_a => a_data_wr, - dout_b => a_data_rd - ); - - --------------------------------------------------------------------------------------------- - --- ASCII RAM control - --------------------------------------------------------------------------------------------- - asci_ram_fsm: - process (s, a_cnt, clr_line, clr_screen, a_data_we, a_data_reg, char_addr, line_addr) - begin - sn <= s; - a_cnt_rst <= '0'; - a_cnt_en <= '0'; - a_ram_we <= '0'; - a_data_wr <= a_data_reg; - a_addr_wr <= char_addr + line_addr; - ready <= '0'; - - case s is - - when cg_init => - sn <= cg_clr_screen; - a_cnt_rst <= '1'; - when cg_ready => - ready <= '1'; - a_ram_we <= a_data_we; - if clr_screen = '1' then - a_cnt_rst <= '1'; - sn <= cg_clr_screen; - elsif clr_line = '1' then - a_cnt_rst <= '1'; - sn <= cg_clr_line; - end if; - when cg_clr_line => - a_ram_we <= '1'; - a_cnt_en <= '1'; - a_data_wr <= to_unsigned(0, A_RAM_DATA_WIDTH); - a_addr_wr <= to_unsigned(a_cnt + to_integer(line_addr), A_RAM_ADDR_WIDTH); - if a_cnt = MAX_CHAR_PER_LINE-1 then - sn <= cg_ready; - end if; - when cg_clr_screen => - a_ram_we <= '1'; - a_cnt_en <= '1'; - a_data_wr <= to_unsigned(0, A_RAM_DATA_WIDTH); - a_addr_wr <= to_unsigned(a_cnt, A_RAM_ADDR_WIDTH); - if a_cnt = (2**A_RAM_ADDR_WIDTH-1) then - sn <= cg_ready; - end if; - - when others => - sn <= cg_ready; - - end case; - end process; - - asci_ram_fsm_next: process (rst, sys_clk) - begin - if rst = '1' then - s <= cg_init; - elsif rising_edge(sys_clk) then - s <= sn; - end if; - end process; - - --------------------------------------------------------------------------------------------- - asci_ram_cnt: process (rst, sys_clk) - begin - if rst = '1' then - a_cnt <= 0; - elsif rising_edge(sys_clk) then - if a_cnt_rst = '1' then - a_cnt <= 0; - elsif a_cnt_en = '1' then - if a_cnt < (2**A_RAM_ADDR_WIDTH-1) then - a_cnt <= a_cnt + 1; - end if; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - asci_addr_reg: process (rst, sys_clk) - begin - if rst = '1' then - csr_posx_cnt_en <= '0'; - csr_posx_cnt_set <= '0'; - csr_posy_cnt_en <= '0'; - csr_posy_cnt_set <= '0'; - a_data_reg <= (others => '0'); - a_data_we <= '0'; - elsif rising_edge(sys_clk) then - a_data_we <= '0'; - csr_posx_cnt_en <= '0'; - csr_posx_cnt_set <= '0'; - csr_posy_cnt_en <= '0'; - csr_posy_cnt_set <= '0'; - if ascii_posy_we = '1' then - csr_posy_cnt_din <= to_integer(ascii_data); - csr_posy_cnt_set <= '1'; - elsif ascii_posx_we = '1' then - csr_posx_cnt_din <= to_integer(ascii_data); - csr_posx_cnt_set <= '1'; - elsif ascii_data_we = '1' then - if ascii_data < X"20" then - if ascii_data = X"0D" then - csr_posx_cnt_din <= 0; - csr_posx_cnt_set <= '1'; - elsif ascii_data = X"0A" then - csr_posy_cnt_en <= '1'; - end if; - else - a_data_reg <= ascii_data - X"20"; - a_data_we <= '1'; - csr_posx_cnt_en <= '1'; - end if; - end if; - end if; - end process; - - asci_csr_posx_counter: - process (rst, sys_clk) - begin - if rst = '1' then - csr_posx_reg <= 0; - csr_posx_overflow <= '0'; - elsif rising_edge(sys_clk) then - csr_posx_overflow <= '0'; - if csr_posx_cnt_set = '1' then - csr_posx_reg <= csr_posx_cnt_din; - elsif csr_posx_cnt_en = '1' then - if csr_posx_reg < MAX_CHAR_PER_LINE-1 then - csr_posx_reg <= csr_posx_reg + 1; - else - csr_posx_reg <= 0; - csr_posx_overflow <= '1'; - end if; - end if; - end if; - end process; - - asci_csr_posy_counter: - process (rst, sys_clk) - begin - if rst = '1' then - csr_posy_reg <= 0; - csr_posy_overflow <= '0'; - elsif rising_edge(sys_clk) then - csr_posy_overflow <= '0'; - if csr_posy_cnt_set = '1' then - csr_posy_reg <= csr_posy_cnt_din; - elsif csr_posy_cnt_en = '1' or csr_posx_overflow = '1' then - if csr_posy_reg < MAX_LINE_PER_FRAME-1 then - csr_posy_reg <= csr_posy_reg + 1; - else - csr_posy_reg <= 0; - csr_posy_overflow <= '1'; - end if; - end if; - end if; - end process; - - scroll_gen: process (rst, sys_clk) - begin - if rst = '1' then - scroll_offset <= 0; - scroll_active <= '0'; - elsif rising_edge(sys_clk) then - if clr_screen = '1' then - scroll_offset <= 0; - scroll_active <= '0'; - elsif csr_posy_overflow = '1' then - scroll_active <= '1'; - scroll_offset <= 1; - end if; - if (csr_posy_cnt_en = '1' or csr_posx_overflow = '1') and scroll_active = '1' then - scroll_offset <= scroll_offset + 1; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - --- Cursor generator - --------------------------------------------------------------------------------------------- - proc_sync_csr_posx: - process(vga_clk) - variable p1, p2 : natural range 0 to MAX_CHAR_PER_LINE-1; - begin - if rising_edge(vga_clk) then - csr_posx_synced <= p2; - p2 := p1; - p1 := csr_posx_reg; - end if; - end process; - - proc_sync_csr_posy: - process(vga_clk) - variable p1, p2 : natural range 0 to MAX_LINE_PER_FRAME-1; - begin - if rising_edge(vga_clk) then - csr_posy_synced <= p2; - p2 := p1; - p1 := csr_posy_reg; - end if; - end process; - - csr_blink_cnt: process (rst, vga_clk) - begin - if rst = '1' then - cursor_cnt <= 0; - cursor_visible <= '0'; - elsif rising_edge(vga_clk) then - if frame_pulse = '1' then - if cursor_cnt < CURSOR_BLINK_INTERVAL-1 then - cursor_cnt <= cursor_cnt + 1; - else - cursor_cnt <= 0; - cursor_visible <= not cursor_visible; - end if; - end if; - end if; - end process; - - cursor_rom_read: process (vga_clk) - begin - if rising_edge(vga_clk) then - cursor_rom_data <= (others => '0'); - if (cell_x_cnt = csr_posx_synced) and (line_offset = csr_posy_synced) then - cursor_rom_data <= cursor_rom(to_integer(cursor_rom_addr)); - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - --- Character generator - --------------------------------------------------------------------------------------------- - char_rom_ctrl: process (vga_clk) - begin - if rising_edge(vga_clk) then - char_rom_row <= to_unsigned(char_y_cnt, char_rom_row'length); - end if; - end process; - - --------------------------------------------------------------------------------------------- - char_reg_ctrl: process (vga_clk) - begin - if rising_edge(vga_clk) and ce = '1' then - if char_x_cnt = 2 then -- +2 delay for ASCII-RAM access and CHAR-ROM access - for i in 0 to CHAR_ROM_SIZE_X-1 loop - for j in 0 to CHARACTER_SCALE-1 loop - char_reg(i*CHARACTER_SCALE + j) <= char_rom_data(i) xor cursor_rom_data(i); - end loop; - end loop; - else - char_reg <= char_reg(char_reg'left-1 downto 0) & '0'; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - cg_ctrl: process (rst, vga_clk) - variable enable_x : std_logic; - variable enable_y : std_logic; - variable char_en : std_logic; - variable char_en2 : std_logic; - begin - - if (rst = '1') then - enable_x := '0'; - enable_y := '0'; - line_offset <= 0; - cell_x_cnt <= 0; - cell_y_cnt <= 0; - char_x_cnt <= 0; - char_y_cnt <= 0; - char_en := '0'; - elsif rising_edge(vga_clk) and ce = '1' then - char_draw_en <= char_en2 and char_reg(char_reg'left); - char_en2 := char_en; - char_en := '0'; - if pos_y = SCREEN_OFFSET_Y then - enable_y := '1'; - cell_y_cnt <= 0; - char_x_cnt <= 0; - line_offset <= scroll_offset; - end if; - if pos_x = SCREEN_OFFSET_X and enable_y = '1' then - enable_x := '1'; - cell_x_cnt <= 0; - char_x_cnt <= 0; - elsif enable_x = '1' and enable_y = '1' then - if char_x_cnt < CELL_SIZE_X-1 then - char_x_cnt <= char_x_cnt + 1; - else - char_x_cnt <= 0; - if cell_x_cnt < MAX_CHAR_PER_LINE-1 then - cell_x_cnt <= cell_x_cnt + 1; - else - enable_x := '0'; - if char_y_cnt < CELL_SIZE_Y-1 then - char_y_cnt <= char_y_cnt + 1; - else - char_y_cnt <= 0; - if cell_y_cnt < MAX_LINE_PER_FRAME-1 then - cell_y_cnt <= cell_y_cnt + 1; - else - enable_y := '0'; - end if; - if line_offset < MAX_LINE_PER_FRAME-1 then - line_offset <= line_offset + 1; - else - line_offset <= 0; - end if; - end if; - end if; - end if; - if (char_x_cnt < CHAR_SIZE_X) and (char_y_cnt < CHAR_SIZE_Y) then - char_en := '1'; - end if; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/VGA_ctrl/src/clkgen_virtex4.vhd b/lib/VGA_ctrl/src/clkgen_virtex4.vhd deleted file mode 100644 index 0b58baf..0000000 --- a/lib/VGA_ctrl/src/clkgen_virtex4.vhd +++ /dev/null @@ -1,105 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_ctrl_core - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -Library UNISIM; -use UNISIM.vcomponents.all; - -entity clkgen is - Generic - ( - sys_freq : integer := 100E6; - tsvga : vga_timespec_t := ts_vga_800_600_72 - ); - Port - ( - rst : in std_logic; - clk : in std_logic; - vga_clk : out std_logic; - dcm_locked : out std_logic - ); -end clkgen; - -architecture tech of clkgen is - - signal vga_clk0 : std_logic; - signal dcm_clk0 : std_logic; - signal dcm_clk_fb : std_logic; - - begin - - -- Compnent instantiation - DCM_VGA_CLK_inst : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => DCM_FREQ_D(sys_freq, tsvga.f_pxl_clk), -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => DCM_FREQ_M(sys_freq, tsvga.f_pxl_clk), -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => DCM_PERIOD(sys_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => dcm_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => vga_clk0, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => dcm_locked, -- DCM LOCK status output - CLKFB => dcm_clk_fb, -- DCM clock feedback - CLKIN => clk, -- Clock input (from IBUFG, BUFG or DCM) - RST => rst -- DCM asynchronous reset input - ); - - BUFG_dcm_clk_fb : BUFG - port map - ( - O => dcm_clk_fb, -- Clock buffer output - I => dcm_clk0 -- Clock buffer input - ); - - BUFG_vga_clk : BUFG - port map - ( - O => vga_clk, -- Clock buffer output - I => vga_clk0 -- Clock buffer input - ); - - -end tech; diff --git a/lib/VGA_ctrl/src/dpram.vhd b/lib/VGA_ctrl/src/dpram.vhd deleted file mode 100644 index b6c5419..0000000 --- a/lib/VGA_ctrl/src/dpram.vhd +++ /dev/null @@ -1,79 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -entity dpram is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram; - -architecture Behavioral of dpram is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal RAM : RAMtype; - -begin - -process (clka) - begin - if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) <= din_a; - end if; - end if; - end if; -end process; - -process (clkb) - begin - if clkb'event and clkb = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); - end if; - end if; -end process; - - -end Behavioral; - diff --git a/lib/VGA_ctrl/src/fonts/Fixedsys_8x15.bff b/lib/VGA_ctrl/src/fonts/Fixedsys_8x15.bff deleted file mode 100644 index a1d2353cf29b6d12c0b71d0401cf7a42f8db4341..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 33044 zcmeHJS(f8S4$J=Qzqvvmb#69y>I2jp0whRAD74tQIIB{6DRBcp24%bIfB(My_4fAP zx3{;y?fwt!KY#!5%a(9o#~b+d>$v`>SN;6I{`fWMoNsUR>=715QG3~}B6cUk203v> z4C)x#!ui3=VkMAA#8Mb0cKU?`tLcj;PRfnv2j1@Z6Bt%Xv+bB;pG-W$@pF0D(i9eN0nx6NG_Zfo%>G{qLB8i+=?t4WUMJ&)*=#avW~BlWS!{Vh)EpI&u3A1DJEqu?kb(LS*uWhhV-cSKffp+Ler0Xju38+@@7_ zRKf$8aSo?`vRUu})L=?yml{(It5b3Xf>lzs*StP%&F3n##SWlBluk$?j%+zW%7U{v zkL1)>P@g75b8f|ZHrd%>M5-=3RxMfp<76TWTyCM=c_OKE$4jj+pH06ZY@YzZt-FE(--_>W#>ilS?9_e!e zPrI8>LRUI-F9&Lx)ft7z8WYOmE$e=ypE^QkzLmi1R1GJC?~i6H1BfoC*;D*(0b0e% z%L3EogTu7fSY;D_3@sU$UCRPw!&%^6WU3E@qK_UTzkHHm9=s)Wb?d#Amz4ld)EMGW zCXay@2>9ogHL%qWj^c3wX%2QcKZzWPaz$sCUhui&>67s3gZK2y6&?ICW4o!B{Aez9c0O%GDFcSHY zbae3WyFS~*A24E53%6xHK>rgYK6JpX*f#SCXZSXf@ioYK#uyQIKY@2zcy7%kB*`d{lrEj^f)z`v%z;B|8}k?TeTZZxAhhVWrzfoXZY||(2JOjX@icd| zUCipdj&rOSdHzUb_2T*Kyqv75z-_l)J`u_rhjBbJ><)A{=Z}3z$3=R-*jE%f&QoG| z=Rjv$t6n@mrn5@|Aqz9zetvJ4HAm^`Le!(AJeLn?CMWGs9eXA)v^uACq^vz?l}C&W zl4rN31g@)0Jc%VN9SAU3JD$~o5uML8%OURf+)y>;E&h=6TT@6=Ry}5mvifeVsuJ>; zx;#_rtB)rH_bgmrv(W(SO(sgIFFxs zYSxLnlb%o!c5wIC=)>$pS2){4jfaX-o=7|C2^C=ncYlpO%5K<^7|oHwBQ<<{S0A69 z^saOl>HaQZT{vj_4%Kz9J9}^7kJ$jeIQWLV+S)?ni^_3cKF?S0Bae@ha~YW6_3!1Y z_P~?+x9W$V-@gW5wfFDRXZ}I`E^~d=9QXOh4Sdz!ze}I-^gri!U;BU6`RBfOd~e|1 zz^8A(zxMuLolkG}dpEFEed7aQxOWYRPr~8(PRfVenk`h$nweT5`&`I+WvnZYW3Uot zZ!E%^u=t606*O~Hn5?6)$)TF~UKLa}VWl^FPRDa~OF*??7pW$hg%J-pB|MpMg|b=~w=46rgF%3;e8R<=twYITmn4)1J?9Ch zqGDMr0{-^$tZ>38=DA3U%6Li>#i?9d+-(m+{IMyft}25J0>5?saR9FhBMHXTu}9E# ze5MN+>Byo9T_-^&5=HLs)Lw!;`3 zlqG^7p5qa<%;sFZKH^vzn=)#sohlJrd zuorNmvD|o@J&lSL&0YzPb8K-@4}uvcI0FNZb>89=fi#>5s#>W5Cx9m#3vLT{aVnhI zuD8(L&;xIVf21hz!I&yutSzQSWLK5zG|G-;!aE)?L7U757qz{-sHjVCAuE_{>rQ3l zgBI~D!Uhc{rHw6Oc^lA&Cwi~$=dq4DIw4PpO&~SsRP{*7Y7&!o0{@_LpSAlr(1U%T zG3t!bzFgog?`vP_fyyx46!dT1bxF-%V(wKwemY`L%Fi8k_(-#KR+paXldyxg+BlDR zvO7Gaqf`iSXq9%0XWZy0KkYz0=0{)G)fBU)^eoSQ!pS!LFpqd;&-$odjE6kyZtM61 zFCFWu#e3ohg9HQ$S2oaioy5eM<;W%LLLZl}c`z7h8rLWB zAw7qT;_{Rktwl`e0ek6YlZ)6%Gv-svYyCpQz#CpaFN=?zKl*!vOJ^U?!-1~za{kRZ zE@~w2=-dPWz|-y9>S><;#XgSTt%2BrlyM)I_|fVrw&U2D&3QV_v9>4YPc1)(e;J^C zc1srmXIRutFwCqi{sZ>(t!ldc_b$XZ`vd3C^IYSs`^~$!6mRx;bV~Kzv;F*d={>&Y zU*o7h*5)6FOJ`lpv*Ew<{HgcQ`PuaP8S4BXUgs^|fp0MPSfOLb*v`cB?b#~lP>1-` z;VE#AWBtNQ)`=E*B6J=%@1#H8@Vha7_5$K#_uXE~JW{-ub^5-n0T za0~~&0FAY*k2w4&WtRc(LDob|yT?m_j?@x#dp{&h$hz2_fAI32=`45>F!2lTS+A_> z$hCeudO3_{aawzx_bG%oj8;m!#nWyaMT>Bp@1-@AyX2EoiojL`Pd6O=5rAjlWCNG= zR0FPIDK4u?wZebIlFdo-C7s_;|OOx&(43w->>K1p4y*u zxqf``Aa}tMWI2l906;Jpp^z*q7iU#U&k{EPWKd35{qNtmzuw;d z`}X$scf0=s`_JD${Ax?Muj38;`gL6Y)2llFuRnebKIhvTz4izTq0M{0uT>vbQsU>1T1}sq$AHYTL7R_ zEyH}M-0@L}{uM@KsI`3e5;SC^-uqYB!WX_hgOU1nXj$*gF{aMv^Xt7Jse_9^0kMttDM`pHpMNB zjLcLv%b*q~T*uxcm|5U*Gf@#pMuE1+%C@H$AZxO1kg=w8S&PWH$qL_3l6@vz4(Blm z1n5{l%a}^g`eX`;#Td#B_Y1nZ=2t*Jh4O>=d0iv^%Tluk$?j%;^=lm)Rk zkLBFgP)!q}Ik)3Io9yf`B3-u~t1Vg%a9`E; zGtP2r-W#|#@G%?s;lB&huQz|q`E#zlFvg+-XSi{;y&nI-8Az&fQ1rHG+rzf=8*%El zi9-j#dLyW@{1_w+#M@P3;Np^NB4J~XRw72g@jRkAXT*ljRu-wY^7s6zK4VtrM>F?G zpA#r8H=l&Abmm?HdYaW4jmR1k&f+cmex{#0LTA36!0U7kCxfp?u{{HbFVWi5{AvMO z#m?ITQ{{uhv}&xf3BQId8JJzm0%XHk;3YEE2STTh9wJ?uWS9qU$z5gD+j(0H@I-}S z4rTHfXn}wqS=PXIKRAxZ39LET;rt|WB+7LIdUN8Weeu>)Rsx|q<7+7t^S-$4%qaAteQSDrJTYho!{geHOxB%aey&5{%rJGdUPC(=nEUM(DT$_&IZ4E_`kz?vQ@hwHw6A)$9A|5 z>)sZ1B6FE;;$U0g&vgC>b1g1A(PIrA`MJ!+HUzq=v!4<$zT;X3icv^j#&Eh`_0gcl z@`ZQz$@1loI2}hLtozg+Y{+p(Z0{q4InKA(t6$7KXyti18H5)7_VkQ(->s!wo56ch zY@X+iwu@QCt2klJ$n!@ct0&Lj&&$b*3fyx0qw;bi+x3* z;*>H&odcb1TlM7mFhesf?>JWMcI^9vv+E?OyMo)=``U>T?{ zaf+`zJ?q5XNl&N^KmkOE*6(;K_Y;ve3zE%yjO<32PJ<;)8-4<{y*qziTnS~J# zI46`$xI^14(81};{<0WZ)M}l6d(1X@vlH^EQDWulGs)f-nzt+Svx7l^?fHb8HCsW+ zVwWUz4SM1k=b~dKMtU( zF_vIVo%RU2kI!@mMmn-+LRTc{M55EH0MFl00c^5CG%qZ10WQ6Zes43prPUk*V4TbF z7zC|6?reuKHmH^ef_cItDw)l>YJJ49GB#yYP&-v3xX1-yO0f$T)Eu6`JjWB>r!fx} zSC1i}T+K%&w!vP&nZ|PAZT2)O_GtFH;5f$?7xf@C!vtqwpxEc_d?JvB6G5-`)POTU z$-;tL!d;vTk8IUj=x*qNZ-yUI9B446Ixp51QzL3uFZa_pJC+Hrc)$!TG8!_m$c|vRgsX?b#kCa-?V)h=u zKd4-1t$q&lWFKgZI%Bji7r4{=+E;p_G7L8b^{?){N0>wFv}qD(5js+=+JSn^&q2i5=tn)P z?C0@qOYdQx>vL?Gr!uYkwLi2|>MsQOSZ6K17yM$7fWYC(1{$xE_}TV!TY&|zjb2#t za$&$NzNbeya>+W;NAi6h3`UyA)g&5HIbF+253LJtqXxiSk#+fm|5HWC+x$w>go31yAk8;Pne_APl0nB>vz0mMQo80q4T_XC;j<`-;MFJ7Z6{& z@AgvedF~B7vw`w8&L2|n72sdWxLTq_&IXR*z&D_vH}0;z90&C9DC7HI3gr@l_8w=oKWQIrbdS zT50t@&+;$g8x73)6#MahrR!Xo#kzQDSNIn>(M{d0akLN5xo55MthL^=ycyq?hZREZ zlm&>ufRm>MP-cz+Q_rsz0LhJ1TVXm^5GweOEQ86E+u zK&M^6($irM*zxCkScDdel_6C7u3w0$EN)Q~gXkls?^nIlL2A((qLmOaK z%mPv(x^Tp9nS@rvuQ=^kMKxEyYVU~qR78%UmP?T(A}5=Th!t9DEV%5#vPUhz7*=jO z3%I2SH6sHXnL^~a2)IHc%j3-PAQUMr%KJe~XDz!^5JF00wcDW=iDn5H?5NOkM-@f! z0@#d8L?g6q3?gWXT>TuCW}H&)-2?S7Q|uR7@>{q;d66_f37)4k4zS5(mk|Zj5|LdI zy153`1%~#RRnP(%^8@DqWhb6e6PO6Lm5)-0&_6j<4Ewna%-{QhgN&4`nnD6<;|7rH zW&%pZ5n!gRN4cYTlm1S4Z@G!@XY1G4683Yrlg@IT_rdr{+W6opU-qvPc%8uO1a6+d z_;px2e#OUkeSX;^8Ikbq90h_^s^akP7DikFas%)|PI>>`8(sLyc1|Nsazc;>kfA8l zVO4HQmWWVo7Sl=%Hk%I6QP6hHd1A5O_&8_Jqe13ZPRgQzNCx5!5nuQz6iJ2mVDw!% z=sN4sFxKkJA8|Zp+^U0WYIRPNUjKk2B7v2OO0H!rK|16eIc`Q~$l|t|FoLvLWtbr) z4CJ5R(Uyn#IRn)Y(N@Jj?Axf`pe`5Lm5bf;U+g2Mvq}c2a|-9#I5A5(JIW$!!c?5! zDDJ^eY@@+7!k+0ns8kEiRX*tIAzPA#cfwY{X@$dNDl-_T*!z_Vjil70EYK2OQi^&0 zR4QF^RPlWH=E4#glXJR&mz%gx5#Q$AiQpZqePnc5IosyKk6nYYNQ0EjZ5v)0>9$Cf zF}ou=;o7>%Zs3b2+iQe}Wzsf2cKDe+y3 z*&~L1u#=Po1i+ys*|hK)sS;2sxcG_4UdoIrXou?Tn;h<2Elp6bp1AiJbL~= z{s105xR>sA0*{}-@?*zu^v5l~lCplysO#lKlz9-8VW9`Dj%98g_6=~jTB+}mrKu?} zZDBD-=~xwr+VAKTNjht!cmTL*7z?;bmdZPKY0lW~QhVkUowj4GsYc^AIFat&nw9^# z6(h?w!L$u)#SRPc>G&GXX59daDFPqoc#3O@ggigWf;^}iIsMA9t2|*fwOq5DpYz+=%1es$|+cQ**N9ISpu_snh4F#OX!UaOT zxj8e~H$Y11yOLW?6ctA)i+sfVd_UNnw@S=)GdV)8&i6l8*FxpMQ$4b%P%F4WW^tF6 zbCw9N43Ew#6}3cWaTufc!IF-dB<6Y`c~AJ*`Z#k~Z;%X|L&=iZ$#$_t_*mfB`Z#k~ zX^;$?L&=ih+ggb^k}v6l_GRlYuw6Y+_&8IX6%B5~X63#juM>Ekzz;ovcYim~U|r+4 zF239HH!!}-d13W-b{qW}bBlL`8 zYvg$3Y@37jArJq$Zu3$<&mZQffWuPZCjnRIx6yJ+oslUqx5j6nQehuk=$~Y4wGj<+ z0L|7x{@2woEcoN%PKZn}5?_6O^dBSUm>O1~&0jG;3`=~e`J-Pno)?xM8`$r*?+;u z&^}p=TA4(<`Q?Q=;(P*V{izK+KkPA(UQy1$l@Ag7H~}5Qm^6w;N_xL5^_ieG(B}83 zy2uBrCz>PiaGcdV{QuyDm;3nyW>;wI+$#hX~FimLy9ZI?dKy5-atYptZp{vhDG)l17fQATy7+XdWL9 zK(k39pwwpqRkt?Tb*|aP@U-=g3}B?F`R?5K6@D@_&wt(?&&pU0o@<^vTk~J(6GQv* zP3FIE4i0_asa-kQpUTNE4xZ~%okD90P>-{mOQisO323+MqepNM zk2iPe2&4YvHK3FW!Ml(3QuD2E=d*Z*eK$sM$d(p$BDiufO1n%YUQ6L6lJ8Qw%d0Jw zKLOE@$>*Zk3ht?w3#$zQ21BxBV01oyj_KM_A3KEyK;JfiCbaMYYEl54Sf7-^P5-xSEITTU?W^D(V)|O8zC=; z99P*;B(gFVNfCi-Gon(yjnKUyee#Zq-Xpvc#OMd}2N!1umlUi0JLk7CP+Y@l*kj<5 zQFbws)k4}ju0kI4({}$(D7Ys+lNZFBG zlU$5AO|A}iS3Q#@dy*12o?aHZKEL`mnTY=wX(;Nv$=W%D<#}6R6_pa@I zxK}#x-`U3C_2oD1kpS|TeVd^x936z8ZU~N5@gjJdABh_{mUmTSHSIl64ghi&;4zr% z2?sTe!S@T~ttvUK#M<(iyf?BcqtW_NoBBcNt?c^*b$adiBWAb!7qi-7;5?3jKhQkQ zW6&~j`f0-qa|obx)^D9Z%+$)A;Ia8NBPO|0^v2kEe76n=hMdfO{x zERQ<*06_FwUMKK6f!7KA>=WSE$n zJG0Yz+_Co-)F>BJWd+!w7ieawM+~hkjH^y3y{Vcke9wF8P62 zkDb7Hdby!t$`gES6FAOvQ9KrZB8NVmJ(bXtl->zJx(fEsA9dt!dm2WH8$~xj;v3+y z;aXHL=bE|}!J&&xLl49SV9UVK<^eh*~!x5<%e04@&F35XJ|stzDJbCxRVr94Yj z&%udaqx?W(31wD8IZpsnPth;8%`y5g9iNSJm3QXx$8#8>&C=jmcYMpvIM1Hr+n+yl N-fcymz4uS(@BhLsE@A)x diff --git a/lib/VGA_ctrl/src/fonts/System_16x16.bff b/lib/VGA_ctrl/src/fonts/System_16x16.bff deleted file mode 100644 index 4ca2523ea9769b9bf3e5a1084b2b998d5935b133..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 65812 zcmeHN3v%qZ4ct`O`^J8oRF07QUm|zP0k%Q_BGKKXMaeVc&zP$BEHuz)e5e_DKmYyT zAOHB{5BvM?a&xrQ<@NRH*UROv*8&V({#BfX z{d{@8Tz*|HCGF|y*VA8?{A}pejHl;klia;tyyDa4`StnN<>}S3i|VhZlKkuU@84TD z|9r8_gkIw+4cYaw#s4ZjSPQNHGE`h;3F}%LSR1Gt`1|i_`Q0G93hEq?^7j^GP7*pl zI~ZA7?@6)uSQ9-78)R2O@h}OTGrq(Hg3!Co>m)T>@uaPjbUC|;_zlARbPNP_0L6opYg~7h ze@AQF5uQem?-kV4Dkn6TIFw$oV zBhye1V}4>d*5|66@iAwFeU9x1a>Kqb48Z#KrwMyyEa4&iZkI_7J6#ht#i+xKG~ z?_5}XOj8Eoz8-~(qGIusFfz>E!yFBS{E}R*@gO7b5iWCj)O(;32R(o;vk@BsaUaL% zV1CK>f_pz$F4o8U>li3^q(9`Fje>q$TuKOzoLKEI?D9+T4}$-q-A@s-INPf!qB4-4xA3fn_|-o=`4_zP&Vjs zAc5(OiuqoVQMmv1f^3v#fFAhF6xdF9y*+g5iSrt`_aY6CNG7ilj+Ck5s zYy~GP?crpl75ws(T+$u~oqX;5rC=)^>uAf=W*W{Gt-nMyKLs&n-r%PXTUTzl8?&kViN)y0bbN2PPLP7Co zQwVNmo*HT>dlnSb*-5GiF7&eArfgu1gW(q`yhaiqIla5d$2&AyZHlpyG zzc$uj&-eO|h0Xh17s4h(A0`E;T1X5;(OMhh|ycm!2kzuxdqO(&K zj3`vVblz1VQE-4kXJ}fra4_J1BZ{I&kcUPlebysQ;N2tZhBeJkV zVeh9D+w#*JR^q-W$2vZ3w`2!SZ%JSUfxAK4bl=+E;9E@Oy?8cP^^@gRLLUgrLZ;XYpi?EzRE+(8v)_mRku6k3c|j5or9)%eSbC321wC=IG*~`R31_ zZwHp%%|Zu6O*TVO1hdC+@OJVdXkvbac3(})Yd1CTQSRM*;t=>KW4AfF`NScxi3b+tXF-p z{fao(yjp*RGkcVe-Hqa0W2DatSS=dF_$VJUj>Kntt*3m(a5yD^xyGygRDZ=)Lvi)j zyT(Vja_xR3KI5B4z0fvakJ-a0`>B4rSG(#Vu665u#(z(|YLDuV^pr1{+9yzmRj>Lh zt{RG~zun~vQ=k>7(vhMBi8HyR2w(eA{s^NFZEMJI{fpRazoftF{>Z!byjS}ScTeZ5 z#PDp6^z>-+cb}jAB|O~t`{Sj4@D{ezzlG$!h7=U2 z3$XvV2ESd#?*{t?&P7@MT<*KrQc$4I-<9b3-Gazb0PWBA2@Xc3ngxLnW;&|H_ljz2 zVlM}OAz!>q-XEtM)cGKrL7m@s+W!jkDU;KNL{CQXHaPcIP1SCXfB9-SfGg*N3k>RmgiWwxYuc*IeS`(o`-s!3Sja2`=0sQDHg`6%h0U{+k>0#Em@`JX-is2^T8 zGZ>v7pQRUC8(16oQ5%r&kM0X(#rbhq`&j$H4Xoz@x6%LZxc0O5gBw`S18!q|UOxMI z;L})WZD4I+ZQuuQK)#R#KKx>2UV)D{{@DSQ|7du2!jCqu&a>v<-+=Dx(eVECkN?jr zYySNWJlgZF^XyN*o`2ofcgM5yUh%bowSl#P2iZXU?^ODw{UF2LVvOl(2LE>(Hd zpffvxgvCZ!0&zmXNb_Bm>P>K{;I1x8k)Q^W?0UjL%M*(KOZwrFPDoRwj zv;5#|7E~#rohT5)oa#wNr(G6MMsAlu#4XSa4l^pGS-uz8uh2>zF|O6?1~^hQIaj8q z&^NW#{NME8R@-X>M>a5f9URg4M9!>z{r*xseHq*P=fr$Uo@Q?eEpLXUVgLQ;?f&$a z4aK6?3)%Q5=I_Xp{_NKYE81#wI6^HBRBv{spUN>C2!%s_S{ym0AB4j0p^}gF2U%|J zU@6&m2f2mIX#ShD@iFH^=I4UcfIqMpr|x7K4uwpRq({lFjww1n#zq1fm-8uMVW?+@ zHD8+WeouU0CB2)!IH+L)ntTB3cqPRoQC2A&N9M5JlrYSyPA=x&s|0y_MX#u_U{uT_ zGXhdL&bhT~yw4fPRy(SZ_c}q6dUJgHr~J60TGrees__k0_Ra4D{p{uXYDJ6X9KmNS zqRAP>Guk&~QhV_}gFTU7x9zcOce)hr(IgtfI4_0|M9`?m97 ztwZO3?Y#5+!TdS%*?w=$x7R_QM(OM3INlhw?|QEru=SzuJg!P{M=kRl!N@WD-WWT^ zT1Wf6bw2j+^X9+y`8%8Mr`(PZcmE0JALX-&yWo^B6B+;qn7)$_#!)Vd-UY{ZTK$$C zJufw8tMLn-j~Q;%ckPd}KLq8rKcw8(EAq1!P@dy}t4(c?$F&@cZt$zJFtZs^<6o0eNVOzHZMKoQb`@<|p@^77H@+?!@)Z zGA)he7|rVmzp0K5+a_j&%^pPYhC(gQpT{xRY;T}F;aXpDpB);TzqVTM`tWq^IkB-l z>^-$Q7K3=V|FiKX3>|}hnCUo)Yht}q>sHYMEx2Ly#AzlYtlQyj>UMKwcmi)-kDsou zIe+XtR&wq9dcfO$Y2Q)9UA`VZe^W?CShvNg=9LRfPgw8ArkL5=WZ)ULP#Gv)ZRolsPIe?4lpf|T<~06NzBaD&(Oqxo3NMvhw9k@C;tIPWrJtuRX&M@e)oCEYUBObp_J6P%mg@G;EA}(U8~pSbGOvG4W#w$IJAA1;JC$* ze;#jp-EO9Kou20N$gJ&?sf!z0Xl-C^U~S;1Y(Tz!{rj9|Kl^ogl7C(O>#}`L?N_k8 zUL59c2i^O$dp*)FM?mWF>#KXc8XGgvHg&<$efM8C`;<MNApYjgCM%*|9)UNG&)gEhx2BTU^Zd~5-U}dUofR(BX_Ysw%U>5s3SXlI{w>Z zUaJ(e;@H4R9H}5Mkks%by=(oo*p1_Acew}xQzx{cy0oDfA2G$1F2G$1F z2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2L2D3 CZx);Y diff --git a/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd b/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd deleted file mode 100644 index 5a544d0..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd +++ /dev/null @@ -1,540 +0,0 @@ --- generated with romgen v3.0 by MikeJ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0000 - x"18",x"3C",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0008 - x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0010 - x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0018 - x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0020 - x"7E",x"60",x"60",x"78",x"60",x"60",x"7E",x"00", -- 0x0028 - x"7E",x"60",x"60",x"78",x"60",x"60",x"60",x"00", -- 0x0030 - x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0038 - x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0040 - x"3C",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0048 - x"1E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0050 - x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0058 - x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0060 - x"63",x"77",x"7F",x"6B",x"63",x"63",x"63",x"00", -- 0x0068 - x"66",x"76",x"7E",x"7E",x"6E",x"66",x"66",x"00", -- 0x0070 - x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0078 - x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0080 - x"3C",x"66",x"66",x"66",x"66",x"3C",x"0E",x"00", -- 0x0088 - x"7C",x"66",x"66",x"7C",x"78",x"6C",x"66",x"00", -- 0x0090 - x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0098 - x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x00A0 - x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x00A8 - x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x00B0 - x"63",x"63",x"63",x"6B",x"7F",x"77",x"63",x"00", -- 0x00B8 - x"66",x"66",x"3C",x"18",x"3C",x"66",x"66",x"00", -- 0x00C0 - x"66",x"66",x"66",x"3C",x"18",x"18",x"18",x"00", -- 0x00C8 - x"7E",x"06",x"0C",x"18",x"30",x"60",x"7E",x"00", -- 0x00D0 - x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x00D8 - x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x00E0 - x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x00E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x00F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"18",x"18",x"18",x"18",x"00",x"00",x"18",x"00", -- 0x0108 - x"66",x"66",x"66",x"00",x"00",x"00",x"00",x"00", -- 0x0110 - x"66",x"66",x"FF",x"66",x"FF",x"66",x"66",x"00", -- 0x0118 - x"18",x"3E",x"60",x"3C",x"06",x"7C",x"18",x"00", -- 0x0120 - x"62",x"66",x"0C",x"18",x"30",x"66",x"46",x"00", -- 0x0128 - x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0130 - x"06",x"0C",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0138 - x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0140 - x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0148 - x"00",x"66",x"3C",x"FF",x"3C",x"66",x"00",x"00", -- 0x0150 - x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0178 - x"3C",x"66",x"6E",x"76",x"66",x"66",x"3C",x"00", -- 0x0180 - x"18",x"18",x"38",x"18",x"18",x"18",x"7E",x"00", -- 0x0188 - x"3C",x"66",x"06",x"0C",x"30",x"60",x"7E",x"00", -- 0x0190 - x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0198 - x"06",x"0E",x"1E",x"66",x"7F",x"06",x"06",x"00", -- 0x01A0 - x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x01A8 - x"3C",x"66",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x01B0 - x"7E",x"66",x"0C",x"18",x"18",x"18",x"18",x"00", -- 0x01B8 - x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x01C0 - x"3C",x"66",x"66",x"3E",x"06",x"66",x"3C",x"00", -- 0x01C8 - x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x01D0 - x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x01D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0 - x"3C",x"66",x"06",x"0C",x"18",x"00",x"18",x"00", -- 0x01F8 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0200 - x"08",x"1C",x"3E",x"7F",x"7F",x"1C",x"3E",x"00", -- 0x0208 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0210 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0218 - x"00",x"00",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0220 - x"00",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0228 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"00",x"00", -- 0x0230 - x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0238 - x"0C",x"0C",x"0C",x"0C",x"0C",x"0C",x"0C",x"0C", -- 0x0240 - x"00",x"00",x"00",x"E0",x"F0",x"38",x"18",x"18", -- 0x0248 - x"18",x"18",x"1C",x"0F",x"07",x"00",x"00",x"00", -- 0x0250 - x"18",x"18",x"38",x"F0",x"E0",x"00",x"00",x"00", -- 0x0258 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FF",x"FF", -- 0x0260 - x"C0",x"E0",x"70",x"38",x"1C",x"0E",x"07",x"03", -- 0x0268 - x"03",x"07",x"0E",x"1C",x"38",x"70",x"E0",x"C0", -- 0x0270 - x"FF",x"FF",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0278 - x"FF",x"FF",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0280 - x"00",x"3C",x"7E",x"7E",x"7E",x"7E",x"3C",x"00", -- 0x0288 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"00", -- 0x0290 - x"36",x"7F",x"7F",x"7F",x"3E",x"1C",x"08",x"00", -- 0x0298 - x"60",x"60",x"60",x"60",x"60",x"60",x"60",x"60", -- 0x02A0 - x"00",x"00",x"00",x"07",x"0F",x"1C",x"18",x"18", -- 0x02A8 - x"C3",x"E7",x"7E",x"3C",x"3C",x"7E",x"E7",x"C3", -- 0x02B0 - x"00",x"3C",x"7E",x"66",x"66",x"7E",x"3C",x"00", -- 0x02B8 - x"18",x"18",x"66",x"66",x"18",x"18",x"3C",x"00", -- 0x02C0 - x"06",x"06",x"06",x"06",x"06",x"06",x"06",x"06", -- 0x02C8 - x"08",x"1C",x"3E",x"7F",x"3E",x"1C",x"08",x"00", -- 0x02D0 - x"18",x"18",x"18",x"FF",x"FF",x"18",x"18",x"18", -- 0x02D8 - x"C0",x"C0",x"30",x"30",x"C0",x"C0",x"30",x"30", -- 0x02E0 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x02E8 - x"00",x"00",x"03",x"3E",x"76",x"36",x"36",x"00", -- 0x02F0 - x"FF",x"7F",x"3F",x"1F",x"0F",x"07",x"03",x"01", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0308 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0310 - x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0320 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0328 - x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0330 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0338 - x"00",x"00",x"00",x"00",x"CC",x"CC",x"33",x"33", -- 0x0340 - x"FF",x"FE",x"FC",x"F8",x"F0",x"E0",x"C0",x"80", -- 0x0348 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0350 - x"18",x"18",x"18",x"1F",x"1F",x"18",x"18",x"18", -- 0x0358 - x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0360 - x"18",x"18",x"18",x"1F",x"1F",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"F8",x"F8",x"18",x"18",x"18", -- 0x0370 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0378 - x"00",x"00",x"00",x"1F",x"1F",x"18",x"18",x"18", -- 0x0380 - x"18",x"18",x"18",x"FF",x"FF",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"FF",x"FF",x"18",x"18",x"18", -- 0x0390 - x"18",x"18",x"18",x"F8",x"F8",x"18",x"18",x"18", -- 0x0398 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x03A0 - x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x03A8 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x03B0 - x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x03C8 - x"03",x"03",x"03",x"03",x"03",x"03",x"FF",x"FF", -- 0x03D0 - x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x03D8 - x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x03E0 - x"18",x"18",x"18",x"F8",x"F8",x"00",x"00",x"00", -- 0x03E8 - x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x03F0 - x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x03F8 - x"C3",x"99",x"91",x"91",x"9F",x"99",x"C3",x"FF", -- 0x0400 - x"E7",x"C3",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0408 - x"83",x"99",x"99",x"83",x"99",x"99",x"83",x"FF", -- 0x0410 - x"C3",x"99",x"9F",x"9F",x"9F",x"99",x"C3",x"FF", -- 0x0418 - x"87",x"93",x"99",x"99",x"99",x"93",x"87",x"FF", -- 0x0420 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0428 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0430 - x"C3",x"99",x"9F",x"91",x"99",x"99",x"C3",x"FF", -- 0x0438 - x"99",x"99",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0440 - x"C3",x"E7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0448 - x"E1",x"F3",x"F3",x"F3",x"F3",x"93",x"C7",x"FF", -- 0x0450 - x"99",x"93",x"87",x"8F",x"87",x"93",x"99",x"FF", -- 0x0458 - x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0460 - x"9C",x"88",x"80",x"94",x"9C",x"9C",x"9C",x"FF", -- 0x0468 - x"99",x"89",x"81",x"81",x"91",x"99",x"99",x"FF", -- 0x0470 - x"C3",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0478 - x"83",x"99",x"99",x"83",x"9F",x"9F",x"9F",x"FF", -- 0x0480 - x"C3",x"99",x"99",x"99",x"99",x"C3",x"F1",x"FF", -- 0x0488 - x"83",x"99",x"99",x"83",x"87",x"93",x"99",x"FF", -- 0x0490 - x"C3",x"99",x"9F",x"C3",x"F9",x"99",x"C3",x"FF", -- 0x0498 - x"81",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x04A0 - x"99",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x04A8 - x"99",x"99",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x04B0 - x"9C",x"9C",x"9C",x"94",x"80",x"88",x"9C",x"FF", -- 0x04B8 - x"99",x"99",x"C3",x"E7",x"C3",x"99",x"99",x"FF", -- 0x04C0 - x"99",x"99",x"99",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x04C8 - x"81",x"F9",x"F3",x"E7",x"CF",x"9F",x"81",x"FF", -- 0x04D0 - x"C3",x"CF",x"CF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x04D8 - x"F3",x"ED",x"CF",x"83",x"CF",x"9D",x"03",x"FF", -- 0x04E0 - x"C3",x"F3",x"F3",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x04E8 - x"FF",x"E7",x"C3",x"81",x"E7",x"E7",x"E7",x"E7", -- 0x04F0 - x"FF",x"EF",x"CF",x"80",x"80",x"CF",x"EF",x"FF", -- 0x04F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0500 - x"E7",x"E7",x"E7",x"E7",x"FF",x"FF",x"E7",x"FF", -- 0x0508 - x"99",x"99",x"99",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0510 - x"99",x"99",x"00",x"99",x"00",x"99",x"99",x"FF", -- 0x0518 - x"E7",x"C1",x"9F",x"C3",x"F9",x"83",x"E7",x"FF", -- 0x0520 - x"9D",x"99",x"F3",x"E7",x"CF",x"99",x"B9",x"FF", -- 0x0528 - x"C3",x"99",x"C3",x"C7",x"98",x"99",x"C0",x"FF", -- 0x0530 - x"F9",x"F3",x"E7",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0538 - x"F3",x"E7",x"CF",x"CF",x"CF",x"E7",x"F3",x"FF", -- 0x0540 - x"CF",x"E7",x"F3",x"F3",x"F3",x"E7",x"CF",x"FF", -- 0x0548 - x"FF",x"99",x"C3",x"00",x"C3",x"99",x"FF",x"FF", -- 0x0550 - x"FF",x"E7",x"E7",x"81",x"E7",x"E7",x"FF",x"FF", -- 0x0558 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0560 - x"FF",x"FF",x"FF",x"81",x"FF",x"FF",x"FF",x"FF", -- 0x0568 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0570 - x"FF",x"FC",x"F9",x"F3",x"E7",x"CF",x"9F",x"FF", -- 0x0578 - x"C3",x"99",x"91",x"89",x"99",x"99",x"C3",x"FF", -- 0x0580 - x"E7",x"E7",x"C7",x"E7",x"E7",x"E7",x"81",x"FF", -- 0x0588 - x"C3",x"99",x"F9",x"F3",x"CF",x"9F",x"81",x"FF", -- 0x0590 - x"C3",x"99",x"F9",x"E3",x"F9",x"99",x"C3",x"FF", -- 0x0598 - x"F9",x"F1",x"E1",x"99",x"80",x"F9",x"F9",x"FF", -- 0x05A0 - x"81",x"9F",x"83",x"F9",x"F9",x"99",x"C3",x"FF", -- 0x05A8 - x"C3",x"99",x"9F",x"83",x"99",x"99",x"C3",x"FF", -- 0x05B0 - x"81",x"99",x"F3",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x05B8 - x"C3",x"99",x"99",x"C3",x"99",x"99",x"C3",x"FF", -- 0x05C0 - x"C3",x"99",x"99",x"C1",x"F9",x"99",x"C3",x"FF", -- 0x05C8 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"FF",x"FF", -- 0x05D0 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x05D8 - x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x05E0 - x"FF",x"FF",x"81",x"FF",x"81",x"FF",x"FF",x"FF", -- 0x05E8 - x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x05F0 - x"C3",x"99",x"F9",x"F3",x"E7",x"FF",x"E7",x"FF", -- 0x05F8 - x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0600 - x"F7",x"E3",x"C1",x"80",x"80",x"E3",x"C1",x"FF", -- 0x0608 - x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x0610 - x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0618 - x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0620 - x"FF",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0628 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF", -- 0x0630 - x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF", -- 0x0638 - x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0640 - x"FF",x"FF",x"FF",x"1F",x"0F",x"C7",x"E7",x"E7", -- 0x0648 - x"E7",x"E7",x"E3",x"F0",x"F8",x"FF",x"FF",x"FF", -- 0x0650 - x"E7",x"E7",x"C7",x"0F",x"1F",x"FF",x"FF",x"FF", -- 0x0658 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"00",x"00", -- 0x0660 - x"3F",x"1F",x"8F",x"C7",x"E3",x"F1",x"F8",x"FC", -- 0x0668 - x"FC",x"F8",x"F1",x"E3",x"C7",x"8F",x"1F",x"3F", -- 0x0670 - x"00",x"00",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0678 - x"00",x"00",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0680 - x"FF",x"C3",x"81",x"81",x"81",x"81",x"C3",x"FF", -- 0x0688 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"FF", -- 0x0690 - x"C9",x"80",x"80",x"80",x"C1",x"E3",x"F7",x"FF", -- 0x0698 - x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"9F", -- 0x06A0 - x"FF",x"FF",x"FF",x"F8",x"F0",x"E3",x"E7",x"E7", -- 0x06A8 - x"3C",x"18",x"81",x"C3",x"C3",x"81",x"18",x"3C", -- 0x06B0 - x"FF",x"C3",x"81",x"99",x"99",x"81",x"C3",x"FF", -- 0x06B8 - x"E7",x"E7",x"99",x"99",x"E7",x"E7",x"C3",x"FF", -- 0x06C0 - x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9", -- 0x06C8 - x"F7",x"E3",x"C1",x"80",x"C1",x"E3",x"F7",x"FF", -- 0x06D0 - x"E7",x"E7",x"E7",x"00",x"00",x"E7",x"E7",x"E7", -- 0x06D8 - x"3F",x"3F",x"CF",x"CF",x"3F",x"3F",x"CF",x"CF", -- 0x06E0 - x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x06E8 - x"FF",x"FF",x"FC",x"C1",x"89",x"C9",x"C9",x"FF", -- 0x06F0 - x"00",x"80",x"C0",x"E0",x"F0",x"F8",x"FC",x"FE", -- 0x06F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0700 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0708 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0718 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0720 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0728 - x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0730 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0738 - x"FF",x"FF",x"FF",x"FF",x"33",x"33",x"CC",x"CC", -- 0x0740 - x"00",x"01",x"03",x"07",x"0F",x"1F",x"3F",x"7F", -- 0x0748 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0750 - x"E7",x"E7",x"E7",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0758 - x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0760 - x"E7",x"E7",x"E7",x"E0",x"E0",x"FF",x"FF",x"FF", -- 0x0768 - x"FF",x"FF",x"FF",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0770 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0778 - x"FF",x"FF",x"FF",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0780 - x"E7",x"E7",x"E7",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0788 - x"FF",x"FF",x"FF",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0790 - x"E7",x"E7",x"E7",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0798 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x07A0 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x07A8 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x07B0 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B8 - x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x07C8 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"00",x"00", -- 0x07D0 - x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x07D8 - x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x07E0 - x"E7",x"E7",x"E7",x"07",x"07",x"FF",x"FF",x"FF", -- 0x07E8 - x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x07F0 - x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"F0", -- 0x07F8 - x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0800 - x"00",x"00",x"3C",x"06",x"3E",x"66",x"3E",x"00", -- 0x0808 - x"00",x"60",x"60",x"7C",x"66",x"66",x"7C",x"00", -- 0x0810 - x"00",x"00",x"3C",x"60",x"60",x"60",x"3C",x"00", -- 0x0818 - x"00",x"06",x"06",x"3E",x"66",x"66",x"3E",x"00", -- 0x0820 - x"00",x"00",x"3C",x"66",x"7E",x"60",x"3C",x"00", -- 0x0828 - x"00",x"0E",x"18",x"3E",x"18",x"18",x"18",x"00", -- 0x0830 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"7C", -- 0x0838 - x"00",x"60",x"60",x"7C",x"66",x"66",x"66",x"00", -- 0x0840 - x"00",x"18",x"00",x"38",x"18",x"18",x"3C",x"00", -- 0x0848 - x"00",x"06",x"00",x"06",x"06",x"06",x"06",x"3C", -- 0x0850 - x"00",x"60",x"60",x"6C",x"78",x"6C",x"66",x"00", -- 0x0858 - x"00",x"38",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0860 - x"00",x"00",x"66",x"7F",x"7F",x"6B",x"63",x"00", -- 0x0868 - x"00",x"00",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0870 - x"00",x"00",x"3C",x"66",x"66",x"66",x"3C",x"00", -- 0x0878 - x"00",x"00",x"7C",x"66",x"66",x"7C",x"60",x"60", -- 0x0880 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"06", -- 0x0888 - x"00",x"00",x"7C",x"66",x"60",x"60",x"60",x"00", -- 0x0890 - x"00",x"00",x"3E",x"60",x"3C",x"06",x"7C",x"00", -- 0x0898 - x"00",x"18",x"7E",x"18",x"18",x"18",x"0E",x"00", -- 0x08A0 - x"00",x"00",x"66",x"66",x"66",x"66",x"3E",x"00", -- 0x08A8 - x"00",x"00",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x08B0 - x"00",x"00",x"63",x"6B",x"7F",x"3E",x"36",x"00", -- 0x08B8 - x"00",x"00",x"66",x"3C",x"18",x"3C",x"66",x"00", -- 0x08C0 - x"00",x"00",x"66",x"66",x"66",x"3E",x"0C",x"78", -- 0x08C8 - x"00",x"00",x"7E",x"0C",x"18",x"30",x"7E",x"00", -- 0x08D0 - x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x08D8 - x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x08E0 - x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x08E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x08F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"18",x"18",x"18",x"18",x"00",x"00",x"18",x"00", -- 0x0908 - x"66",x"66",x"66",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"66",x"66",x"FF",x"66",x"FF",x"66",x"66",x"00", -- 0x0918 - x"18",x"3E",x"60",x"3C",x"06",x"7C",x"18",x"00", -- 0x0920 - x"62",x"66",x"0C",x"18",x"30",x"66",x"46",x"00", -- 0x0928 - x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0930 - x"06",x"0C",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0940 - x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0948 - x"00",x"66",x"3C",x"FF",x"3C",x"66",x"00",x"00", -- 0x0950 - x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0960 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0970 - x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0978 - x"3C",x"66",x"6E",x"76",x"66",x"66",x"3C",x"00", -- 0x0980 - x"18",x"18",x"38",x"18",x"18",x"18",x"7E",x"00", -- 0x0988 - x"3C",x"66",x"06",x"0C",x"30",x"60",x"7E",x"00", -- 0x0990 - x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0998 - x"06",x"0E",x"1E",x"66",x"7F",x"06",x"06",x"00", -- 0x09A0 - x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x09A8 - x"3C",x"66",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x09B0 - x"7E",x"66",x"0C",x"18",x"18",x"18",x"18",x"00", -- 0x09B8 - x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x09C0 - x"3C",x"66",x"66",x"3E",x"06",x"66",x"3C",x"00", -- 0x09C8 - x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x09D0 - x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x09D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x09E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x09E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x09F0 - x"3C",x"66",x"06",x"0C",x"18",x"00",x"18",x"00", -- 0x09F8 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0A00 - x"18",x"3C",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0A08 - x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0A10 - x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0A18 - x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0A20 - x"7E",x"60",x"60",x"78",x"60",x"60",x"7E",x"00", -- 0x0A28 - x"7E",x"60",x"60",x"78",x"60",x"60",x"60",x"00", -- 0x0A30 - x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0A38 - x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0A40 - x"3C",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0A48 - x"1E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0A50 - x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0A58 - x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0A60 - x"63",x"77",x"7F",x"6B",x"63",x"63",x"63",x"00", -- 0x0A68 - x"66",x"76",x"7E",x"7E",x"6E",x"66",x"66",x"00", -- 0x0A70 - x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0A78 - x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0A80 - x"3C",x"66",x"66",x"66",x"66",x"3C",x"0E",x"00", -- 0x0A88 - x"7C",x"66",x"66",x"7C",x"78",x"6C",x"66",x"00", -- 0x0A90 - x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0A98 - x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x0AA0 - x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0AA8 - x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x0AB0 - x"63",x"63",x"63",x"6B",x"7F",x"77",x"63",x"00", -- 0x0AB8 - x"66",x"66",x"3C",x"18",x"3C",x"66",x"66",x"00", -- 0x0AC0 - x"66",x"66",x"66",x"3C",x"18",x"18",x"18",x"00", -- 0x0AC8 - x"7E",x"06",x"0C",x"18",x"30",x"60",x"7E",x"00", -- 0x0AD0 - x"18",x"18",x"18",x"FF",x"FF",x"18",x"18",x"18", -- 0x0AD8 - x"C0",x"C0",x"30",x"30",x"C0",x"C0",x"30",x"30", -- 0x0AE0 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0AE8 - x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0AF0 - x"33",x"99",x"CC",x"66",x"33",x"99",x"CC",x"66", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0B08 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0B10 - x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0B20 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0B28 - x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0B30 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0B38 - x"00",x"00",x"00",x"00",x"CC",x"CC",x"33",x"33", -- 0x0B40 - x"CC",x"99",x"33",x"66",x"CC",x"99",x"33",x"66", -- 0x0B48 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0B50 - x"18",x"18",x"18",x"1F",x"1F",x"18",x"18",x"18", -- 0x0B58 - x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0B60 - x"18",x"18",x"18",x"1F",x"1F",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"F8",x"F8",x"18",x"18",x"18", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0B78 - x"00",x"00",x"00",x"1F",x"1F",x"18",x"18",x"18", -- 0x0B80 - x"18",x"18",x"18",x"FF",x"FF",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"FF",x"FF",x"18",x"18",x"18", -- 0x0B90 - x"18",x"18",x"18",x"F8",x"F8",x"18",x"18",x"18", -- 0x0B98 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0BA0 - x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0BA8 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0BB0 - x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0BC8 - x"01",x"03",x"06",x"6C",x"78",x"70",x"60",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x0BD8 - x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"18",x"18",x"18",x"F8",x"F8",x"00",x"00",x"00", -- 0x0BE8 - x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x0BF8 - x"C3",x"99",x"91",x"91",x"9F",x"99",x"C3",x"FF", -- 0x0C00 - x"FF",x"FF",x"C3",x"F9",x"C1",x"99",x"C1",x"FF", -- 0x0C08 - x"FF",x"9F",x"9F",x"83",x"99",x"99",x"83",x"FF", -- 0x0C10 - x"FF",x"FF",x"C3",x"9F",x"9F",x"9F",x"C3",x"FF", -- 0x0C18 - x"FF",x"F9",x"F9",x"C1",x"99",x"99",x"C1",x"FF", -- 0x0C20 - x"FF",x"FF",x"C3",x"99",x"81",x"9F",x"C3",x"FF", -- 0x0C28 - x"FF",x"F1",x"E7",x"C1",x"E7",x"E7",x"E7",x"FF", -- 0x0C30 - x"FF",x"FF",x"C1",x"99",x"99",x"C1",x"F9",x"83", -- 0x0C38 - x"FF",x"9F",x"9F",x"83",x"99",x"99",x"99",x"FF", -- 0x0C40 - x"FF",x"E7",x"FF",x"C7",x"E7",x"E7",x"C3",x"FF", -- 0x0C48 - x"FF",x"F9",x"FF",x"F9",x"F9",x"F9",x"F9",x"C3", -- 0x0C50 - x"FF",x"9F",x"9F",x"93",x"87",x"93",x"99",x"FF", -- 0x0C58 - x"FF",x"C7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0C60 - x"FF",x"FF",x"99",x"80",x"80",x"94",x"9C",x"FF", -- 0x0C68 - x"FF",x"FF",x"83",x"99",x"99",x"99",x"99",x"FF", -- 0x0C70 - x"FF",x"FF",x"C3",x"99",x"99",x"99",x"C3",x"FF", -- 0x0C78 - x"FF",x"FF",x"83",x"99",x"99",x"83",x"9F",x"9F", -- 0x0C80 - x"FF",x"FF",x"C1",x"99",x"99",x"C1",x"F9",x"F9", -- 0x0C88 - x"FF",x"FF",x"83",x"99",x"9F",x"9F",x"9F",x"FF", -- 0x0C90 - x"FF",x"FF",x"C1",x"9F",x"C3",x"F9",x"83",x"FF", -- 0x0C98 - x"FF",x"E7",x"81",x"E7",x"E7",x"E7",x"F1",x"FF", -- 0x0CA0 - x"FF",x"FF",x"99",x"99",x"99",x"99",x"C1",x"FF", -- 0x0CA8 - x"FF",x"FF",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x0CB0 - x"FF",x"FF",x"9C",x"94",x"80",x"C1",x"C9",x"FF", -- 0x0CB8 - x"FF",x"FF",x"99",x"C3",x"E7",x"C3",x"99",x"FF", -- 0x0CC0 - x"FF",x"FF",x"99",x"99",x"99",x"C1",x"F3",x"87", -- 0x0CC8 - x"FF",x"FF",x"81",x"F3",x"E7",x"CF",x"81",x"FF", -- 0x0CD0 - x"C3",x"CF",x"CF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x0CD8 - x"F3",x"ED",x"CF",x"83",x"CF",x"9D",x"03",x"FF", -- 0x0CE0 - x"C3",x"F3",x"F3",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x0CE8 - x"FF",x"E7",x"C3",x"81",x"E7",x"E7",x"E7",x"E7", -- 0x0CF0 - x"FF",x"EF",x"CF",x"80",x"80",x"CF",x"EF",x"FF", -- 0x0CF8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D00 - x"E7",x"E7",x"E7",x"E7",x"FF",x"FF",x"E7",x"FF", -- 0x0D08 - x"99",x"99",x"99",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D10 - x"99",x"99",x"00",x"99",x"00",x"99",x"99",x"FF", -- 0x0D18 - x"E7",x"C1",x"9F",x"C3",x"F9",x"83",x"E7",x"FF", -- 0x0D20 - x"9D",x"99",x"F3",x"E7",x"CF",x"99",x"B9",x"FF", -- 0x0D28 - x"C3",x"99",x"C3",x"C7",x"98",x"99",x"C0",x"FF", -- 0x0D30 - x"F9",x"F3",x"E7",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D38 - x"F3",x"E7",x"CF",x"CF",x"CF",x"E7",x"F3",x"FF", -- 0x0D40 - x"CF",x"E7",x"F3",x"F3",x"F3",x"E7",x"CF",x"FF", -- 0x0D48 - x"FF",x"99",x"C3",x"00",x"C3",x"99",x"FF",x"FF", -- 0x0D50 - x"FF",x"E7",x"E7",x"81",x"E7",x"E7",x"FF",x"FF", -- 0x0D58 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0D60 - x"FF",x"FF",x"FF",x"81",x"FF",x"FF",x"FF",x"FF", -- 0x0D68 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0D70 - x"FF",x"FC",x"F9",x"F3",x"E7",x"CF",x"9F",x"FF", -- 0x0D78 - x"C3",x"99",x"91",x"89",x"99",x"99",x"C3",x"FF", -- 0x0D80 - x"E7",x"E7",x"C7",x"E7",x"E7",x"E7",x"81",x"FF", -- 0x0D88 - x"C3",x"99",x"F9",x"F3",x"CF",x"9F",x"81",x"FF", -- 0x0D90 - x"C3",x"99",x"F9",x"E3",x"F9",x"99",x"C3",x"FF", -- 0x0D98 - x"F9",x"F1",x"E1",x"99",x"80",x"F9",x"F9",x"FF", -- 0x0DA0 - x"81",x"9F",x"83",x"F9",x"F9",x"99",x"C3",x"FF", -- 0x0DA8 - x"C3",x"99",x"9F",x"83",x"99",x"99",x"C3",x"FF", -- 0x0DB0 - x"81",x"99",x"F3",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0DB8 - x"C3",x"99",x"99",x"C3",x"99",x"99",x"C3",x"FF", -- 0x0DC0 - x"C3",x"99",x"99",x"C1",x"F9",x"99",x"C3",x"FF", -- 0x0DC8 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"FF",x"FF", -- 0x0DD0 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0DD8 - x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x0DE0 - x"FF",x"FF",x"81",x"FF",x"81",x"FF",x"FF",x"FF", -- 0x0DE8 - x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x0DF0 - x"C3",x"99",x"F9",x"F3",x"E7",x"FF",x"E7",x"FF", -- 0x0DF8 - x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0E00 - x"E7",x"C3",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0E08 - x"83",x"99",x"99",x"83",x"99",x"99",x"83",x"FF", -- 0x0E10 - x"C3",x"99",x"9F",x"9F",x"9F",x"99",x"C3",x"FF", -- 0x0E18 - x"87",x"93",x"99",x"99",x"99",x"93",x"87",x"FF", -- 0x0E20 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0E28 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0E30 - x"C3",x"99",x"9F",x"91",x"99",x"99",x"C3",x"FF", -- 0x0E38 - x"99",x"99",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0E40 - x"C3",x"E7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0E48 - x"E1",x"F3",x"F3",x"F3",x"F3",x"93",x"C7",x"FF", -- 0x0E50 - x"99",x"93",x"87",x"8F",x"87",x"93",x"99",x"FF", -- 0x0E58 - x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0E60 - x"9C",x"88",x"80",x"94",x"9C",x"9C",x"9C",x"FF", -- 0x0E68 - x"99",x"89",x"81",x"81",x"91",x"99",x"99",x"FF", -- 0x0E70 - x"C3",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0E78 - x"83",x"99",x"99",x"83",x"9F",x"9F",x"9F",x"FF", -- 0x0E80 - x"C3",x"99",x"99",x"99",x"99",x"C3",x"F1",x"FF", -- 0x0E88 - x"83",x"99",x"99",x"83",x"87",x"93",x"99",x"FF", -- 0x0E90 - x"C3",x"99",x"9F",x"C3",x"F9",x"99",x"C3",x"FF", -- 0x0E98 - x"81",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0EA0 - x"99",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0EA8 - x"99",x"99",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x0EB0 - x"9C",x"9C",x"9C",x"94",x"80",x"88",x"9C",x"FF", -- 0x0EB8 - x"99",x"99",x"C3",x"E7",x"C3",x"99",x"99",x"FF", -- 0x0EC0 - x"99",x"99",x"99",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x0EC8 - x"81",x"F9",x"F3",x"E7",x"CF",x"9F",x"81",x"FF", -- 0x0ED0 - x"E7",x"E7",x"E7",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0ED8 - x"3F",x"3F",x"CF",x"CF",x"3F",x"3F",x"CF",x"CF", -- 0x0EE0 - x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x0EE8 - x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0EF0 - x"CC",x"66",x"33",x"99",x"CC",x"66",x"33",x"99", -- 0x0EF8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F00 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0F08 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F18 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0F20 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0F28 - x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0F30 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0F38 - x"FF",x"FF",x"FF",x"FF",x"33",x"33",x"CC",x"CC", -- 0x0F40 - x"33",x"66",x"CC",x"99",x"33",x"66",x"CC",x"99", -- 0x0F48 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0F50 - x"E7",x"E7",x"E7",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0F58 - x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0F60 - x"E7",x"E7",x"E7",x"E0",x"E0",x"FF",x"FF",x"FF", -- 0x0F68 - x"FF",x"FF",x"FF",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0F70 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0F78 - x"FF",x"FF",x"FF",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0F80 - x"E7",x"E7",x"E7",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0F88 - x"FF",x"FF",x"FF",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0F90 - x"E7",x"E7",x"E7",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0F98 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0FA0 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x0FA8 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0FB0 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FB8 - x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FC0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x0FC8 - x"FE",x"FC",x"F9",x"93",x"87",x"8F",x"9F",x"FF", -- 0x0FD0 - x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x0FD8 - x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x0FE0 - x"E7",x"E7",x"E7",x"07",x"07",x"FF",x"FF",x"FF", -- 0x0FE8 - x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x0FF0 - x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"F0" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_data.vhd b/lib/VGA_ctrl/src/fonts/char_rom_data.vhd deleted file mode 100644 index c52e7f7..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_data.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"7C",x"40",x"7C",x"44",x"7C",x"0C",x"0C",x"7C", -- 0x0000 - x"3C",x"24",x"7E",x"62",x"62",x"62",x"62",x"00", -- 0x0008 - x"7C",x"24",x"3E",x"32",x"32",x"32",x"7E",x"00", -- 0x0010 - x"7E",x"42",x"40",x"60",x"60",x"62",x"7E",x"00", -- 0x0018 - x"7E",x"22",x"22",x"32",x"32",x"32",x"7E",x"00", -- 0x0020 - x"7E",x"40",x"40",x"78",x"60",x"60",x"7E",x"00", -- 0x0028 - x"7E",x"40",x"40",x"78",x"60",x"60",x"60",x"00", -- 0x0030 - x"7E",x"42",x"40",x"6E",x"62",x"62",x"7E",x"00", -- 0x0038 - x"42",x"42",x"42",x"7E",x"62",x"62",x"62",x"00", -- 0x0040 - x"10",x"10",x"10",x"18",x"18",x"18",x"18",x"00", -- 0x0048 - x"02",x"02",x"02",x"06",x"06",x"46",x"3C",x"00", -- 0x0050 - x"42",x"44",x"48",x"7E",x"62",x"62",x"62",x"00", -- 0x0058 - x"40",x"40",x"40",x"60",x"60",x"60",x"7E",x"00", -- 0x0060 - x"66",x"5A",x"42",x"62",x"62",x"62",x"62",x"00", -- 0x0068 - x"72",x"4A",x"4A",x"6A",x"6A",x"6A",x"66",x"00", -- 0x0070 - x"7E",x"42",x"42",x"62",x"62",x"62",x"7E",x"00", -- 0x0078 - x"7E",x"42",x"42",x"7E",x"60",x"60",x"60",x"00", -- 0x0080 - x"7E",x"42",x"42",x"62",x"6A",x"64",x"7A",x"00", -- 0x0088 - x"7E",x"42",x"42",x"7E",x"64",x"62",x"62",x"00", -- 0x0090 - x"7E",x"42",x"40",x"7E",x"06",x"46",x"7E",x"00", -- 0x0098 - x"7C",x"10",x"10",x"18",x"18",x"18",x"18",x"00", -- 0x00A0 - x"42",x"42",x"42",x"62",x"62",x"62",x"7E",x"00", -- 0x00A8 - x"42",x"42",x"42",x"24",x"24",x"18",x"18",x"00", -- 0x00B0 - x"62",x"62",x"62",x"62",x"42",x"5A",x"66",x"00", -- 0x00B8 - x"42",x"24",x"18",x"7C",x"62",x"62",x"62",x"00", -- 0x00C0 - x"42",x"42",x"42",x"3C",x"18",x"18",x"18",x"00", -- 0x00C8 - x"7E",x"02",x"1C",x"60",x"60",x"60",x"7E",x"00", -- 0x00D0 - x"3C",x"20",x"20",x"30",x"30",x"30",x"3C",x"00", -- 0x00D8 - x"18",x"20",x"20",x"78",x"60",x"60",x"7C",x"00", -- 0x00E0 - x"3C",x"04",x"04",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x00E8 - x"08",x"1C",x"2A",x"08",x"08",x"08",x"08",x"00", -- 0x00F0 - x"00",x"20",x"40",x"FE",x"40",x"20",x"00",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"18",x"18",x"1C",x"1C",x"1C",x"00",x"1C",x"00", -- 0x0108 - x"36",x"36",x"12",x"12",x"00",x"00",x"00",x"00", -- 0x0110 - x"24",x"24",x"7E",x"34",x"7E",x"34",x"34",x"00", -- 0x0118 - x"08",x"3E",x"28",x"3E",x"1A",x"3E",x"18",x"00", -- 0x0120 - x"70",x"52",x"74",x"08",x"1E",x"2A",x"4E",x"00", -- 0x0128 - x"78",x"48",x"30",x"70",x"6A",x"64",x"7A",x"00", -- 0x0130 - x"38",x"38",x"08",x"08",x"00",x"00",x"00",x"00", -- 0x0138 - x"0C",x"10",x"20",x"30",x"30",x"10",x"0C",x"00", -- 0x0140 - x"30",x"08",x"04",x"0C",x"0C",x"08",x"30",x"00", -- 0x0148 - x"08",x"2A",x"1C",x"3E",x"1C",x"2A",x"08",x"00", -- 0x0150 - x"00",x"08",x"08",x"3E",x"3E",x"0C",x"0C",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"1C",x"1C",x"04",x"04", -- 0x0160 - x"00",x"00",x"00",x"7E",x"7E",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"02",x"04",x"08",x"10",x"20",x"40",x"00", -- 0x0178 - x"7E",x"42",x"46",x"6A",x"72",x"62",x"7E",x"00", -- 0x0180 - x"38",x"08",x"08",x"18",x"18",x"18",x"3C",x"00", -- 0x0188 - x"7E",x"42",x"02",x"7E",x"60",x"60",x"7E",x"00", -- 0x0190 - x"3E",x"02",x"02",x"1E",x"06",x"06",x"7E",x"00", -- 0x0198 - x"40",x"40",x"44",x"44",x"7E",x"0C",x"0C",x"00", -- 0x01A0 - x"3E",x"20",x"20",x"3E",x"06",x"46",x"7E",x"00", -- 0x01A8 - x"7E",x"40",x"40",x"7E",x"62",x"62",x"7E",x"00", -- 0x01B0 - x"7E",x"42",x"04",x"08",x"18",x"18",x"18",x"00", -- 0x01B8 - x"3C",x"24",x"24",x"7E",x"62",x"62",x"7E",x"00", -- 0x01C0 - x"7E",x"42",x"42",x"7E",x"06",x"06",x"7E",x"00", -- 0x01C8 - x"00",x"00",x"18",x"00",x"18",x"18",x"00",x"00", -- 0x01D0 - x"00",x"00",x"1C",x"00",x"1C",x"1C",x"04",x"04", -- 0x01D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"7E",x"00",x"00", -- 0x01E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0 - x"7E",x"42",x"02",x"3E",x"30",x"00",x"30",x"00", -- 0x01F8 - x"00",x"00",x"00",x"00",x"FF",x"00",x"00",x"00", -- 0x0200 - x"18",x"3C",x"7E",x"7E",x"18",x"18",x"7E",x"00", -- 0x0208 - x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"10", -- 0x0210 - x"00",x"00",x"00",x"FF",x"00",x"00",x"00",x"00", -- 0x0218 - x"00",x"00",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0220 - x"00",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0228 - x"00",x"00",x"00",x"00",x"00",x"FF",x"00",x"00", -- 0x0230 - x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x0238 - x"04",x"04",x"04",x"04",x"04",x"04",x"04",x"04", -- 0x0240 - x"00",x"00",x"00",x"C0",x"30",x"10",x"08",x"08", -- 0x0248 - x"10",x"10",x"08",x"0C",x"03",x"00",x"00",x"00", -- 0x0250 - x"08",x"08",x"10",x"30",x"C0",x"00",x"00",x"00", -- 0x0258 - x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"FF", -- 0x0260 - x"80",x"40",x"20",x"10",x"08",x"04",x"02",x"01", -- 0x0268 - x"01",x"02",x"04",x"08",x"10",x"20",x"40",x"80", -- 0x0270 - x"FF",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- 0x0278 - x"FF",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0280 - x"3C",x"7E",x"7E",x"7E",x"7E",x"7E",x"3C",x"00", -- 0x0288 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"00", -- 0x0290 - x"24",x"7E",x"7E",x"7E",x"3C",x"18",x"18",x"00", -- 0x0298 - x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x02A0 - x"00",x"00",x"00",x"03",x"0C",x"08",x"10",x"10", -- 0x02A8 - x"81",x"42",x"24",x"18",x"18",x"24",x"42",x"81", -- 0x02B0 - x"3C",x"7E",x"66",x"42",x"66",x"7E",x"3C",x"00", -- 0x02B8 - x"18",x"18",x"7E",x"7E",x"18",x"18",x"7E",x"00", -- 0x02C0 - x"02",x"02",x"02",x"02",x"02",x"02",x"02",x"02", -- 0x02C8 - x"00",x"18",x"3C",x"7E",x"7E",x"3C",x"18",x"00", -- 0x02D0 - x"08",x"08",x"08",x"FF",x"08",x"08",x"08",x"08", -- 0x02D8 - x"C0",x"30",x"C0",x"30",x"C0",x"30",x"C0",x"30", -- 0x02E0 - x"08",x"08",x"08",x"08",x"08",x"08",x"08",x"08", -- 0x02E8 - x"00",x"00",x"7C",x"24",x"64",x"64",x"66",x"00", -- 0x02F0 - x"FF",x"7F",x"3F",x"1F",x"0F",x"07",x"03",x"01", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0308 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0310 - x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0320 - x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- 0x0328 - x"CC",x"33",x"CC",x"33",x"CC",x"33",x"CC",x"33", -- 0x0330 - x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0338 - x"00",x"00",x"00",x"00",x"CC",x"33",x"CC",x"33", -- 0x0340 - x"FF",x"FE",x"FC",x"F8",x"F0",x"E0",x"C0",x"80", -- 0x0348 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0350 - x"08",x"08",x"08",x"0F",x"08",x"08",x"08",x"08", -- 0x0358 - x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0360 - x"08",x"08",x"08",x"0F",x"00",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"F8",x"08",x"08",x"08",x"08", -- 0x0370 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0378 - x"00",x"00",x"00",x"0F",x"08",x"08",x"08",x"08", -- 0x0380 - x"08",x"08",x"08",x"FF",x"00",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"FF",x"08",x"08",x"08",x"08", -- 0x0390 - x"08",x"08",x"08",x"F8",x"08",x"08",x"08",x"08", -- 0x0398 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x03A0 - x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x03A8 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x03B0 - x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x03C8 - x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"FF", -- 0x03D0 - x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x03D8 - x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x03E0 - x"08",x"08",x"08",x"F8",x"00",x"00",x"00",x"00", -- 0x03E8 - x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x03F0 - x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x03F8 - x"83",x"BF",x"83",x"BB",x"83",x"F3",x"F3",x"83", -- 0x0400 - x"C3",x"DB",x"81",x"9D",x"9D",x"9D",x"9D",x"FF", -- 0x0408 - x"83",x"DB",x"C1",x"CD",x"CD",x"CD",x"81",x"FF", -- 0x0410 - x"81",x"BD",x"BF",x"9F",x"9F",x"9D",x"81",x"FF", -- 0x0418 - x"81",x"DD",x"DD",x"CD",x"CD",x"CD",x"81",x"FF", -- 0x0420 - x"81",x"BF",x"BF",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0428 - x"81",x"BF",x"BF",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0430 - x"81",x"BD",x"BF",x"91",x"9D",x"9D",x"81",x"FF", -- 0x0438 - x"BD",x"BD",x"BD",x"81",x"9D",x"9D",x"9D",x"FF", -- 0x0440 - x"EF",x"EF",x"EF",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0448 - x"FD",x"FD",x"FD",x"F9",x"F9",x"B9",x"C3",x"FF", -- 0x0450 - x"BD",x"BB",x"B7",x"81",x"9D",x"9D",x"9D",x"FF", -- 0x0458 - x"BF",x"BF",x"BF",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0460 - x"99",x"A5",x"BD",x"9D",x"9D",x"9D",x"9D",x"FF", -- 0x0468 - x"8D",x"B5",x"B5",x"95",x"95",x"95",x"99",x"FF", -- 0x0470 - x"81",x"BD",x"BD",x"9D",x"9D",x"9D",x"81",x"FF", -- 0x0478 - x"81",x"BD",x"BD",x"81",x"9F",x"9F",x"9F",x"FF", -- 0x0480 - x"81",x"BD",x"BD",x"9D",x"95",x"9B",x"85",x"FF", -- 0x0488 - x"81",x"BD",x"BD",x"81",x"9B",x"9D",x"9D",x"FF", -- 0x0490 - x"81",x"BD",x"BF",x"81",x"F9",x"B9",x"81",x"FF", -- 0x0498 - x"83",x"EF",x"EF",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x04A0 - x"BD",x"BD",x"BD",x"9D",x"9D",x"9D",x"81",x"FF", -- 0x04A8 - x"BD",x"BD",x"BD",x"DB",x"DB",x"E7",x"E7",x"FF", -- 0x04B0 - x"9D",x"9D",x"9D",x"9D",x"BD",x"A5",x"99",x"FF", -- 0x04B8 - x"BD",x"DB",x"E7",x"83",x"9D",x"9D",x"9D",x"FF", -- 0x04C0 - x"BD",x"BD",x"BD",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x04C8 - x"81",x"FD",x"E3",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x04D0 - x"C3",x"DF",x"DF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x04D8 - x"E7",x"DF",x"DF",x"87",x"9F",x"9F",x"83",x"FF", -- 0x04E0 - x"C3",x"FB",x"FB",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x04E8 - x"F7",x"E3",x"D5",x"F7",x"F7",x"F7",x"F7",x"FF", -- 0x04F0 - x"FF",x"DF",x"BF",x"01",x"BF",x"DF",x"FF",x"FF", -- 0x04F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0500 - x"E7",x"E7",x"E3",x"E3",x"E3",x"FF",x"E3",x"FF", -- 0x0508 - x"C9",x"C9",x"ED",x"ED",x"FF",x"FF",x"FF",x"FF", -- 0x0510 - x"DB",x"DB",x"81",x"CB",x"81",x"CB",x"CB",x"FF", -- 0x0518 - x"F7",x"C1",x"D7",x"C1",x"E5",x"C1",x"E7",x"FF", -- 0x0520 - x"8F",x"AD",x"8B",x"F7",x"E1",x"D5",x"B1",x"FF", -- 0x0528 - x"87",x"B7",x"CF",x"8F",x"95",x"9B",x"85",x"FF", -- 0x0530 - x"C7",x"C7",x"F7",x"F7",x"FF",x"FF",x"FF",x"FF", -- 0x0538 - x"F3",x"EF",x"DF",x"CF",x"CF",x"EF",x"F3",x"FF", -- 0x0540 - x"CF",x"F7",x"FB",x"F3",x"F3",x"F7",x"CF",x"FF", -- 0x0548 - x"F7",x"D5",x"E3",x"C1",x"E3",x"D5",x"F7",x"FF", -- 0x0550 - x"FF",x"F7",x"F7",x"C1",x"C1",x"F3",x"F3",x"FF", -- 0x0558 - x"FF",x"FF",x"FF",x"FF",x"E3",x"E3",x"FB",x"FB", -- 0x0560 - x"FF",x"FF",x"FF",x"81",x"81",x"FF",x"FF",x"FF", -- 0x0568 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0570 - x"FF",x"FD",x"FB",x"F7",x"EF",x"DF",x"BF",x"FF", -- 0x0578 - x"81",x"BD",x"B9",x"95",x"8D",x"9D",x"81",x"FF", -- 0x0580 - x"C7",x"F7",x"F7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0588 - x"81",x"BD",x"FD",x"81",x"9F",x"9F",x"81",x"FF", -- 0x0590 - x"C1",x"FD",x"FD",x"E1",x"F9",x"F9",x"81",x"FF", -- 0x0598 - x"BF",x"BF",x"BB",x"BB",x"81",x"F3",x"F3",x"FF", -- 0x05A0 - x"C1",x"DF",x"DF",x"C1",x"F9",x"B9",x"81",x"FF", -- 0x05A8 - x"81",x"BF",x"BF",x"81",x"9D",x"9D",x"81",x"FF", -- 0x05B0 - x"81",x"BD",x"FB",x"F7",x"E7",x"E7",x"E7",x"FF", -- 0x05B8 - x"C3",x"DB",x"DB",x"81",x"9D",x"9D",x"81",x"FF", -- 0x05C0 - x"81",x"BD",x"BD",x"81",x"F9",x"F9",x"81",x"FF", -- 0x05C8 - x"FF",x"FF",x"E7",x"FF",x"E7",x"E7",x"FF",x"FF", -- 0x05D0 - x"FF",x"FF",x"E3",x"FF",x"E3",x"E3",x"FB",x"FB", -- 0x05D8 - x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x05E0 - x"FF",x"FF",x"81",x"FF",x"81",x"81",x"FF",x"FF", -- 0x05E8 - x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x05F0 - x"81",x"BD",x"FD",x"C1",x"CF",x"FF",x"CF",x"FF", -- 0x05F8 - x"FF",x"FF",x"FF",x"FF",x"00",x"FF",x"FF",x"FF", -- 0x0600 - x"E7",x"C3",x"81",x"81",x"E7",x"E7",x"81",x"FF", -- 0x0608 - x"EF",x"EF",x"EF",x"EF",x"EF",x"EF",x"EF",x"EF", -- 0x0610 - x"FF",x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0618 - x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0620 - x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0628 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"FF",x"FF", -- 0x0630 - x"DF",x"DF",x"DF",x"DF",x"DF",x"DF",x"DF",x"DF", -- 0x0638 - x"FB",x"FB",x"FB",x"FB",x"FB",x"FB",x"FB",x"FB", -- 0x0640 - x"FF",x"FF",x"FF",x"3F",x"CF",x"EF",x"F7",x"F7", -- 0x0648 - x"EF",x"EF",x"F7",x"F3",x"FC",x"FF",x"FF",x"FF", -- 0x0650 - x"F7",x"F7",x"EF",x"CF",x"3F",x"FF",x"FF",x"FF", -- 0x0658 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"00", -- 0x0660 - x"7F",x"BF",x"DF",x"EF",x"F7",x"FB",x"FD",x"FE", -- 0x0668 - x"FE",x"FD",x"FB",x"F7",x"EF",x"DF",x"BF",x"7F", -- 0x0670 - x"00",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0678 - x"00",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0680 - x"C3",x"81",x"81",x"81",x"81",x"81",x"C3",x"FF", -- 0x0688 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"FF", -- 0x0690 - x"DB",x"81",x"81",x"81",x"C3",x"E7",x"E7",x"FF", -- 0x0698 - x"BF",x"BF",x"BF",x"BF",x"BF",x"BF",x"BF",x"BF", -- 0x06A0 - x"FF",x"FF",x"FF",x"FC",x"F3",x"F7",x"EF",x"EF", -- 0x06A8 - x"7E",x"BD",x"DB",x"E7",x"E7",x"DB",x"BD",x"7E", -- 0x06B0 - x"C3",x"81",x"99",x"BD",x"99",x"81",x"C3",x"FF", -- 0x06B8 - x"E7",x"E7",x"81",x"81",x"E7",x"E7",x"81",x"FF", -- 0x06C0 - x"FD",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD", -- 0x06C8 - x"FF",x"E7",x"C3",x"81",x"81",x"C3",x"E7",x"FF", -- 0x06D0 - x"F7",x"F7",x"F7",x"00",x"F7",x"F7",x"F7",x"F7", -- 0x06D8 - x"3F",x"CF",x"3F",x"CF",x"3F",x"CF",x"3F",x"CF", -- 0x06E0 - x"F7",x"F7",x"F7",x"F7",x"F7",x"F7",x"F7",x"F7", -- 0x06E8 - x"FF",x"FF",x"83",x"DB",x"9B",x"9B",x"99",x"FF", -- 0x06F0 - x"00",x"80",x"C0",x"E0",x"F0",x"F8",x"FC",x"FE", -- 0x06F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0700 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0708 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0718 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0720 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0728 - x"33",x"CC",x"33",x"CC",x"33",x"CC",x"33",x"CC", -- 0x0730 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0738 - x"FF",x"FF",x"FF",x"FF",x"33",x"CC",x"33",x"CC", -- 0x0740 - x"00",x"01",x"03",x"07",x"0F",x"1F",x"3F",x"7F", -- 0x0748 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0750 - x"F7",x"F7",x"F7",x"F0",x"F7",x"F7",x"F7",x"F7", -- 0x0758 - x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0760 - x"F7",x"F7",x"F7",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x0768 - x"FF",x"FF",x"FF",x"07",x"F7",x"F7",x"F7",x"F7", -- 0x0770 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0778 - x"FF",x"FF",x"FF",x"F0",x"F7",x"F7",x"F7",x"F7", -- 0x0780 - x"F7",x"F7",x"F7",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0788 - x"FF",x"FF",x"FF",x"00",x"F7",x"F7",x"F7",x"F7", -- 0x0790 - x"F7",x"F7",x"F7",x"07",x"F7",x"F7",x"F7",x"F7", -- 0x0798 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x07A0 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x07A8 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x07B0 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B8 - x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x07C8 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"00", -- 0x07D0 - x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x07D8 - x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x07E0 - x"F7",x"F7",x"F7",x"07",x"FF",x"FF",x"FF",x"FF", -- 0x07E8 - x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x07F0 - x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd b/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd deleted file mode 100644 index 95a9bd1..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0000 - x"08",x"14",x"14",x"22",x"3E",x"41",x"41",x"80", -- 0x0008 - x"FC",x"42",x"42",x"7C",x"42",x"42",x"42",x"FC", -- 0x0010 - x"3C",x"46",x"40",x"40",x"40",x"40",x"46",x"3C", -- 0x0018 - x"FC",x"42",x"42",x"42",x"42",x"42",x"42",x"FC", -- 0x0020 - x"FC",x"46",x"50",x"70",x"50",x"40",x"46",x"FC", -- 0x0028 - x"FC",x"46",x"50",x"70",x"50",x"40",x"40",x"E0", -- 0x0030 - x"3C",x"46",x"40",x"4E",x"44",x"44",x"44",x"3C", -- 0x0038 - x"EE",x"44",x"44",x"7C",x"44",x"44",x"44",x"EE", -- 0x0040 - x"1C",x"08",x"08",x"08",x"08",x"08",x"08",x"1C", -- 0x0048 - x"1C",x"08",x"08",x"08",x"08",x"08",x"C8",x"70", -- 0x0050 - x"E6",x"48",x"50",x"60",x"50",x"48",x"44",x"EE", -- 0x0058 - x"E0",x"40",x"40",x"40",x"40",x"40",x"46",x"FC", -- 0x0060 - x"C6",x"6C",x"6C",x"54",x"54",x"44",x"44",x"EE", -- 0x0068 - x"CE",x"64",x"64",x"54",x"54",x"4C",x"4C",x"E6", -- 0x0070 - x"3C",x"42",x"42",x"42",x"42",x"42",x"42",x"3C", -- 0x0078 - x"FC",x"42",x"42",x"7C",x"40",x"40",x"40",x"E0", -- 0x0080 - x"3C",x"42",x"42",x"42",x"42",x"4A",x"46",x"3D", -- 0x0088 - x"FC",x"42",x"42",x"7C",x"50",x"48",x"44",x"EE", -- 0x0090 - x"3C",x"42",x"40",x"20",x"1C",x"02",x"C2",x"7C", -- 0x0098 - x"FE",x"92",x"10",x"10",x"10",x"10",x"10",x"38", -- 0x00A0 - x"E7",x"42",x"42",x"42",x"42",x"42",x"42",x"3C", -- 0x00A8 - x"E7",x"42",x"42",x"42",x"42",x"42",x"24",x"18", -- 0x00B0 - x"C3",x"41",x"5D",x"49",x"49",x"55",x"63",x"41", -- 0x00B8 - x"EE",x"44",x"28",x"10",x"10",x"28",x"44",x"EE", -- 0x00C0 - x"EE",x"44",x"44",x"28",x"10",x"10",x"10",x"38", -- 0x00C8 - x"FE",x"84",x"08",x"7C",x"24",x"40",x"82",x"FE", -- 0x00D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"10",x"10",x"10",x"10",x"10",x"00",x"10",x"10", -- 0x0108 - x"CC",x"44",x"44",x"22",x"00",x"00",x"00",x"00", -- 0x0110 - x"77",x"22",x"FF",x"22",x"22",x"FF",x"22",x"77", -- 0x0118 - x"10",x"3E",x"50",x"3C",x"12",x"12",x"7C",x"10", -- 0x0120 - x"87",x"42",x"04",x"08",x"10",x"20",x"44",x"E2", -- 0x0128 - x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0130 - x"1E",x"08",x"3C",x"00",x"00",x"00",x"00",x"00", -- 0x0138 - x"0E",x"12",x"60",x"40",x"40",x"60",x"12",x"0E", -- 0x0140 - x"70",x"48",x"06",x"02",x"02",x"06",x"48",x"70", -- 0x0148 - x"42",x"24",x"99",x"7E",x"99",x"24",x"42",x"00", -- 0x0150 - x"08",x"08",x"08",x"7F",x"08",x"08",x"08",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0178 - x"7C",x"82",x"82",x"82",x"82",x"82",x"82",x"7C", -- 0x0180 - x"10",x"30",x"50",x"10",x"10",x"10",x"10",x"7C", -- 0x0188 - x"7C",x"C2",x"02",x"1C",x"60",x"80",x"86",x"FC", -- 0x0190 - x"7C",x"C2",x"02",x"1C",x"02",x"02",x"C2",x"7C", -- 0x0198 - x"08",x"18",x"28",x"48",x"FE",x"08",x"08",x"3E", -- 0x01A0 - x"FE",x"80",x"80",x"FC",x"02",x"02",x"C2",x"7C", -- 0x01A8 - x"7C",x"86",x"80",x"FC",x"82",x"82",x"82",x"7C", -- 0x01B0 - x"7E",x"C2",x"04",x"08",x"10",x"10",x"10",x"7C", -- 0x01B8 - x"7C",x"82",x"82",x"7C",x"82",x"82",x"82",x"7C", -- 0x01C0 - x"7C",x"82",x"82",x"7E",x"02",x"02",x"C2",x"7C", -- 0x01C8 - x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x01D0 - x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x01D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0 - x"3C",x"62",x"02",x"04",x"08",x"08",x"00",x"08", -- 0x01F8 - x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0200 - x"FE",x"FE",x"C6",x"FE",x"C6",x"C6",x"C6",x"C6", -- 0x0208 - x"FE",x"FE",x"C6",x"FC",x"C6",x"C6",x"FE",x"FE", -- 0x0210 - x"FE",x"FE",x"C0",x"C0",x"C0",x"C0",x"FE",x"FE", -- 0x0218 - x"FE",x"FE",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x0220 - x"FE",x"FE",x"C0",x"FE",x"C0",x"C0",x"FE",x"FE", -- 0x0228 - x"FE",x"FE",x"C0",x"FE",x"C0",x"C0",x"C0",x"C0", -- 0x0230 - x"FE",x"FE",x"C0",x"DE",x"C6",x"C6",x"FE",x"FE", -- 0x0238 - x"C6",x"C6",x"C6",x"FE",x"C6",x"C6",x"C6",x"C6", -- 0x0240 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0248 - x"18",x"18",x"18",x"18",x"18",x"18",x"78",x"78", -- 0x0250 - x"C6",x"C6",x"DC",x"F0",x"D8",x"CC",x"C6",x"C6", -- 0x0258 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FE",x"FE", -- 0x0260 - x"FE",x"FE",x"D6",x"D6",x"D6",x"D6",x"D6",x"D6", -- 0x0268 - x"E6",x"E6",x"F6",x"D6",x"D6",x"DE",x"CE",x"CE", -- 0x0270 - x"FE",x"FE",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x0278 - x"FE",x"FE",x"C6",x"FE",x"C0",x"C0",x"C0",x"C0", -- 0x0280 - x"FE",x"FE",x"C6",x"C6",x"C6",x"CE",x"FE",x"FF", -- 0x0288 - x"FE",x"FE",x"C6",x"FE",x"D8",x"D8",x"C6",x"C6", -- 0x0290 - x"FE",x"FE",x"C0",x"FE",x"06",x"06",x"FE",x"FE", -- 0x0298 - x"FE",x"FE",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x02A0 - x"C6",x"C6",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x02A8 - x"C6",x"C6",x"C6",x"C6",x"C6",x"C6",x"FE",x"7C", -- 0x02B0 - x"D6",x"D6",x"D6",x"D6",x"D6",x"D6",x"FE",x"FE", -- 0x02B8 - x"C6",x"C6",x"6C",x"38",x"38",x"6C",x"C6",x"C6", -- 0x02C0 - x"C6",x"C6",x"C6",x"FE",x"06",x"06",x"FE",x"FE", -- 0x02C8 - x"FE",x"FE",x"0E",x"18",x"30",x"E0",x"FE",x"FE", -- 0x02D0 - x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x02D8 - x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x02E0 - x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x02E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x02F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"07",x"1F",x"3F",x"3F",x"7F", -- 0x0370 - x"00",x"00",x"00",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0378 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400 - x"03",x"1F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0408 - x"FC",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"0F", -- 0x0410 - x"00",x"80",x"E0",x"F8",x"F8",x"FE",x"FE",x"FE", -- 0x0418 - x"00",x"00",x"00",x"00",x"00",x"00",x"07",x"07", -- 0x0420 - x"00",x"00",x"00",x"00",x"00",x"00",x"F8",x"FE", -- 0x0428 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0430 - x"00",x"00",x"00",x"00",x"00",x"00",x"F0",x"F0", -- 0x0438 - x"00",x"00",x"00",x"00",x"00",x"00",x"7F",x"7F", -- 0x0440 - x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x0448 - x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"3F", -- 0x0450 - x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"C0", -- 0x0458 - x"00",x"00",x"00",x"00",x"00",x"00",x"1F",x"7F", -- 0x0460 - x"00",x"00",x"00",x"00",x"00",x"00",x"E0",x"F8", -- 0x0468 - x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7F",x"7F", -- 0x0470 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"FF",x"FF", -- 0x0478 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FC",x"FC", -- 0x0480 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0488 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F1", -- 0x0490 - x"00",x"00",x"00",x"00",x"00",x"00",x"7F",x"FF", -- 0x0498 - x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x04A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"3F", -- 0x04A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"F0",x"F0", -- 0x04B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0508 - x"03",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0510 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0518 - x"07",x"07",x"07",x"00",x"00",x"07",x"0F",x"3F", -- 0x0520 - x"FE",x"FF",x"FF",x"7F",x"3F",x"FF",x"FF",x"FF", -- 0x0528 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0530 - x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00",x"03", -- 0x0538 - x"7F",x"7F",x"7F",x"07",x"03",x"7F",x"FF",x"FF", -- 0x0540 - x"E0",x"F0",x"F1",x"F1",x"F3",x"F3",x"F3",x"F1", -- 0x0548 - x"7F",x"FF",x"FF",x"FC",x"F0",x"F0",x"F0",x"F8", -- 0x0550 - x"C0",x"C1",x"C1",x"03",x"03",x"03",x"03",x"03", -- 0x0558 - x"FF",x"FF",x"FF",x"FF",x"F8",x"F0",x"F0",x"F0", -- 0x0560 - x"FC",x"FE",x"FE",x"FF",x"7F",x"3F",x"3F",x"3F", -- 0x0568 - x"7F",x"7F",x"7F",x"7E",x"7E",x"7E",x"7E",x"7E", -- 0x0570 - x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0578 - x"FC",x"FC",x"FC",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0580 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0588 - x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0590 - x"FF",x"FF",x"FF",x"F3",x"F1",x"F1",x"F1",x"F1", -- 0x0598 - x"F0",x"F0",x"F8",x"F9",x"F9",x"F9",x"F9",x"F9", -- 0x05A0 - x"7F",x"FF",x"FF",x"FC",x"F8",x"F8",x"F8",x"F8", -- 0x05A8 - x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 - x"3C",x"42",x"B9",x"A5",x"B9",x"A9",x"A5",x"42", -- 0x05B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0608 - x"01",x"01",x"03",x"0F",x"7F",x"7F",x"7F",x"7F", -- 0x0610 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FC",x"FC", -- 0x0618 - x"3F",x"7F",x"7E",x"7C",x"7E",x"7F",x"3F",x"3F", -- 0x0620 - x"FF",x"FF",x"3F",x"3F",x"3F",x"BF",x"BF",x"BF", -- 0x0628 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"1F", -- 0x0630 - x"03",x"07",x"07",x"07",x"07",x"F7",x"F3",x"F3", -- 0x0638 - x"FF",x"FF",x"E3",x"C3",x"E3",x"FB",x"FB",x"FB", -- 0x0640 - x"F1",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0648 - x"FC",x"FE",x"7F",x"3F",x"1F",x"0F",x"07",x"03", -- 0x0650 - x"03",x"03",x"83",x"C3",x"E3",x"F1",x"F1",x"F0", -- 0x0658 - x"F0",x"F0",x"F0",x"F0",x"F8",x"FF",x"FF",x"FF", -- 0x0660 - x"3F",x"3F",x"3F",x"3F",x"7F",x"FE",x"FE",x"FC", -- 0x0668 - x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7E", -- 0x0670 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"07", -- 0x0678 - x"C0",x"C0",x"C0",x"C0",x"C0",x"FC",x"FC",x"FC", -- 0x0680 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0688 - x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0690 - x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0698 - x"F9",x"F9",x"F9",x"F9",x"F9",x"F8",x"F8",x"F8", -- 0x06A0 - x"F8",x"F8",x"F8",x"F8",x"FC",x"FF",x"FF",x"7F", -- 0x06A8 - x"00",x"00",x"00",x"00",x"00",x"FC",x"FC",x"FC", -- 0x06B0 - x"3C",x"00",x"00",x"00",x"78",x"FC",x"FC",x"FC", -- 0x06B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 - x"7F",x"7F",x"7F",x"00",x"00",x"00",x"00",x"00", -- 0x0708 - x"7F",x"7F",x"7F",x"00",x"00",x"00",x"00",x"00", -- 0x0710 - x"F0",x"E0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718 - x"0F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720 - x"BF",x"BF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 - x"1F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730 - x"F0",x"F0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 - x"FB",x"7B",x"03",x"01",x"00",x"00",x"00",x"00", -- 0x0740 - x"F0",x"F8",x"FE",x"FF",x"FF",x"FF",x"3F",x"07", -- 0x0748 - x"03",x"07",x"1F",x"FF",x"FF",x"FF",x"FE",x"F0", -- 0x0750 - x"F0",x"F0",x"E0",x"E0",x"C0",x"80",x"00",x"00", -- 0x0758 - x"7F",x"1F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760 - x"F8",x"E0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768 - x"7E",x"7E",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 - x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 - x"FC",x"FC",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780 - x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788 - x"F3",x"F3",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790 - x"F1",x"F1",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798 - x"F8",x"F8",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0 - x"3F",x"0F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8 - x"FC",x"FC",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0 - x"FC",x"78",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd b/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd deleted file mode 100644 index ce977b6..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"3C",x"66",x"6E",x"6A",x"6E",x"60",x"3C",x"00", -- 0x0000 - x"00",x"00",x"3C",x"06",x"3E",x"66",x"3E",x"00", -- 0x0008 - x"60",x"60",x"7C",x"66",x"66",x"66",x"7C",x"00", -- 0x0010 - x"00",x"00",x"3C",x"66",x"60",x"66",x"3C",x"00", -- 0x0018 - x"06",x"06",x"3E",x"66",x"66",x"66",x"3E",x"00", -- 0x0020 - x"00",x"00",x"3C",x"66",x"7E",x"60",x"3C",x"00", -- 0x0028 - x"1C",x"30",x"30",x"7C",x"30",x"30",x"30",x"00", -- 0x0030 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"3C", -- 0x0038 - x"60",x"60",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0040 - x"18",x"00",x"38",x"18",x"18",x"18",x"3C",x"00", -- 0x0048 - x"18",x"00",x"38",x"18",x"18",x"18",x"18",x"70", -- 0x0050 - x"60",x"60",x"66",x"6C",x"78",x"6C",x"66",x"00", -- 0x0058 - x"38",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0060 - x"00",x"00",x"36",x"7F",x"6B",x"6B",x"63",x"00", -- 0x0068 - x"00",x"00",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0070 - x"00",x"00",x"3C",x"66",x"66",x"66",x"3C",x"00", -- 0x0078 - x"00",x"00",x"7C",x"66",x"66",x"7C",x"60",x"60", -- 0x0080 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"07", -- 0x0088 - x"00",x"00",x"6C",x"76",x"60",x"60",x"60",x"00", -- 0x0090 - x"00",x"00",x"3E",x"60",x"3C",x"06",x"7C",x"00", -- 0x0098 - x"30",x"30",x"7C",x"30",x"30",x"30",x"1C",x"00", -- 0x00A0 - x"00",x"00",x"66",x"66",x"66",x"66",x"3E",x"00", -- 0x00A8 - x"00",x"00",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x00B0 - x"00",x"00",x"63",x"6B",x"6B",x"7F",x"36",x"00", -- 0x00B8 - x"00",x"00",x"66",x"3C",x"18",x"3C",x"66",x"00", -- 0x00C0 - x"00",x"00",x"66",x"66",x"66",x"3E",x"06",x"3C", -- 0x00C8 - x"00",x"00",x"7E",x"0C",x"18",x"30",x"7E",x"00", -- 0x00D0 - x"7C",x"60",x"60",x"60",x"60",x"60",x"7C",x"00", -- 0x00D8 - x"1C",x"36",x"30",x"7C",x"30",x"30",x"7E",x"00", -- 0x00E0 - x"3E",x"06",x"06",x"06",x"06",x"06",x"3E",x"00", -- 0x00E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x00F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"18",x"18",x"18",x"18",x"18",x"00",x"18",x"00", -- 0x0108 - x"6C",x"6C",x"6C",x"00",x"00",x"00",x"00",x"00", -- 0x0110 - x"36",x"36",x"7F",x"36",x"7F",x"36",x"36",x"00", -- 0x0118 - x"0C",x"3F",x"68",x"3E",x"0B",x"7E",x"18",x"00", -- 0x0120 - x"60",x"66",x"0C",x"18",x"30",x"66",x"06",x"00", -- 0x0128 - x"38",x"6C",x"6C",x"38",x"6D",x"66",x"3B",x"00", -- 0x0130 - x"0C",x"18",x"30",x"00",x"00",x"00",x"00",x"00", -- 0x0138 - x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0140 - x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0148 - x"00",x"18",x"7E",x"3C",x"7E",x"18",x"00",x"00", -- 0x0150 - x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"06",x"0C",x"18",x"30",x"60",x"00",x"00", -- 0x0178 - x"3C",x"66",x"6E",x"7E",x"76",x"66",x"3C",x"00", -- 0x0180 - x"18",x"38",x"18",x"18",x"18",x"18",x"7E",x"00", -- 0x0188 - x"3C",x"66",x"06",x"0C",x"18",x"30",x"7E",x"00", -- 0x0190 - x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0198 - x"0C",x"1C",x"3C",x"6C",x"7E",x"0C",x"0C",x"00", -- 0x01A0 - x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x01A8 - x"1C",x"30",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x01B0 - x"7E",x"06",x"0C",x"18",x"30",x"30",x"30",x"00", -- 0x01B8 - x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x01C0 - x"3C",x"66",x"66",x"3E",x"06",x"0C",x"38",x"00", -- 0x01C8 - x"00",x"00",x"18",x"18",x"00",x"18",x"18",x"00", -- 0x01D0 - x"00",x"00",x"18",x"18",x"00",x"18",x"18",x"30", -- 0x01D8 - x"0C",x"18",x"30",x"60",x"30",x"18",x"0C",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8 - x"30",x"18",x"0C",x"06",x"0C",x"18",x"30",x"00", -- 0x01F0 - x"3C",x"66",x"0C",x"18",x"18",x"00",x"18",x"00", -- 0x01F8 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0200 - x"3C",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0208 - x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0210 - x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0218 - x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0220 - x"7E",x"60",x"60",x"7C",x"60",x"60",x"7E",x"00", -- 0x0228 - x"7E",x"60",x"60",x"7C",x"60",x"60",x"60",x"00", -- 0x0230 - x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0238 - x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0240 - x"7E",x"18",x"18",x"18",x"18",x"18",x"7E",x"00", -- 0x0248 - x"3E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0250 - x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0258 - x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0260 - x"63",x"77",x"7F",x"6B",x"6B",x"63",x"63",x"00", -- 0x0268 - x"66",x"66",x"76",x"7E",x"6E",x"66",x"66",x"00", -- 0x0270 - x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0278 - x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0280 - x"3C",x"66",x"66",x"66",x"6A",x"6C",x"36",x"00", -- 0x0288 - x"7C",x"66",x"66",x"7C",x"6C",x"66",x"66",x"00", -- 0x0290 - x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0298 - x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x02A0 - x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x02A8 - x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x02B0 - x"63",x"63",x"6B",x"00",x"00",x"00",x"00",x"00", -- 0x02B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0370 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0410 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0420 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0450 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0460 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0480 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0618 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0650 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0658 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0668 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0698 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd deleted file mode 100644 index 3b60051..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd +++ /dev/null @@ -1,4383 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 033 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "00111100", -- | #### | 05 - "00111100", -- | #### | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 034 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 035 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110110", -- | ## ## | 03 - "00110110", -- | ## ## | 04 - "01111111", -- | #######| 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "00110110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 036 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00011000", -- | ## | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00001100", -- | ## | 08 - "00000110", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 037 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01110000", -- | ### | 02 - "11011000", -- |## ## | 03 - "11011010", -- |## ## # | 04 - "01110110", -- | ### ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00110000", -- | ## | 08 - "01101110", -- | ## ### | 09 - "01011011", -- | # ## ##| 10 - "00011011", -- | ## ##| 11 - "00001110", -- | ### | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 038 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "11111111", -- |########| 13 - "00000000", -- | | 14 - -- ASCII 039 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 040 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 041 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00110000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 042 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00110110", -- | ## ## | 05 - "00011100", -- | ### | 06 - "01111111", -- | #######| 07 - "00011100", -- | ### | 08 - "00110110", -- | ## ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 043 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 044 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 045 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 046 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 047 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "01100000", -- | ## | 11 - "01100000", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 048 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011110", -- | #### | 03 - "00110011", -- | ## ##| 04 - "00110111", -- | ## ###| 05 - "00110111", -- | ## ###| 06 - "00110011", -- | ## ##| 07 - "00111011", -- | ### ##| 08 - "00111011", -- | ### ##| 09 - "00110011", -- | ## ##| 10 - "00011110", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 049 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011100", -- | ### | 04 - "01111100", -- | ##### | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 050 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00001100", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 051 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00011100", -- | ### | 07 - "00000110", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 052 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00110000", -- | ## | 04 - "00110110", -- | ## ## | 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00000110", -- | ## | 10 - "00000110", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 053 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "00000110", -- | ## | 08 - "00000110", -- | ## | 09 - "00001100", -- | ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 054 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011100", -- | ### | 03 - "00011000", -- | ## | 04 - "00110000", -- | ## | 05 - "01111100", -- | ##### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 055 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "00000110", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00110000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 056 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01110110", -- | ### ## | 06 - "00111100", -- | #### | 07 - "01101110", -- | ## ### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 057 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "00111110", -- | ##### | 08 - "00001100", -- | ## | 09 - "00011000", -- | ## | 10 - "00111000", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 058 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 059 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 060 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00001100", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "01100000", -- | ## | 07 - "00110000", -- | ## | 08 - "00011000", -- | ## | 09 - "00001100", -- | ## | 10 - "00000110", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 061 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "01111110", -- | ###### | 06 - "00000000", -- | | 07 - "01111110", -- | ###### | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 062 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "00110000", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00000110", -- | ## | 07 - "00001100", -- | ## | 08 - "00011000", -- | ## | 09 - "00110000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 063 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 064 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "11000011", -- |## ##| 04 - "11000011", -- |## ##| 05 - "11001111", -- |## ####| 06 - "11011011", -- |## ## ##| 07 - "11011011", -- |## ## ##| 08 - "11001111", -- |## ####| 09 - "11000000", -- |## | 10 - "01111111", -- | #######| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 065 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 066 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111100", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111100", -- | ##### | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 067 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 068 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111000", -- | #### | 03 - "01101100", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01101100", -- | ## ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 069 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 070 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 071 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01101110", -- | ## ### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 072 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111110", -- | ###### | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 073 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 074 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00000110", -- | ## | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00000110", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 075 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01101100", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "01111000", -- | #### | 07 - "01101100", -- | ## ## | 08 - "01101100", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 076 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 077 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01110111", -- | ### ###| 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "01100011", -- | ## ##| 09 - "01100011", -- | ## ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 078 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01110011", -- | ### ##| 05 - "01111011", -- | #### ##| 06 - "01101111", -- | ## ####| 07 - "01100111", -- | ## ###| 08 - "01100011", -- | ## ##| 09 - "01100011", -- | ## ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 079 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 080 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111100", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 081 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00000110", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 082 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111100", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111100", -- | ##### | 07 - "01101100", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 083 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00001100", -- | ## | 08 - "00000110", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 084 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 085 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 086 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 087 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01100011", -- | ## ##| 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "00110110", -- | ## ## | 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 088 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "00110100", -- | ## # | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00101100", -- | # ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 089 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 090 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "00000110", -- | ## | 04 - "00000110", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00110000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 091 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00110000", -- | ## | 04 - "00110000", -- | ## | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00110000", -- | ## | 11 - "00110000", -- | ## | 12 - "00110000", -- | ## | 13 - "00111100", -- | #### | 14 - -- ASCII 092 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "00110000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00000110", -- | ## | 11 - "00000110", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 093 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00001100", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00001100", -- | ## | 12 - "00001100", -- | ## | 13 - "00111100", -- | #### | 14 - -- ASCII 094 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 095 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "11111111", -- |########| 14 - -- ASCII 096 --------------- - "00000000", -- | | 00 - "00111000", -- | ### | 01 - "00011000", -- | ## | 02 - "00001100", -- | ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 097 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 098 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 099 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 100 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 101 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 102 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011110", -- | #### | 03 - "00110000", -- | ## | 04 - "00110000", -- | ## | 05 - "00110000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00110000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 103 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000110", -- | ## | 12 - "00000110", -- | ## | 13 - "01111100", -- | ##### | 14 - -- ASCII 104 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 105 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00011000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 106 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00001100", -- | ## | 02 - "00001100", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00001100", -- | ## | 12 - "00001100", -- | ## | 13 - "01111000", -- | #### | 14 - -- ASCII 107 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01101100", -- | ## ## | 07 - "01111000", -- | #### | 08 - "01101100", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 108 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111000", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 109 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111110", -- | ###### | 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "01101011", -- | ## # ##| 09 - "01101011", -- | ## # ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 110 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 111 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 112 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "01100000", -- | ## | 14 - -- ASCII 113 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000110", -- | ## | 12 - "00000110", -- | ## | 13 - "00000110", -- | ## | 14 - -- ASCII 114 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01101110", -- | ## ### | 06 - "01110000", -- | ### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 115 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "00111100", -- | #### | 08 - "00000110", -- | ## | 09 - "00000110", -- | ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 116 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00110000", -- | ## | 04 - "01111110", -- | ###### | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00011110", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 117 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 118 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 119 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100011", -- | ## ##| 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "01101011", -- | ## # ##| 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 120 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00011000", -- | ## | 08 - "00111100", -- | #### | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 121 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - -- ASCII 122 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111110", -- | ###### | 05 - "00000110", -- | ## | 06 - "00001100", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 123 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00110000", -- | ## | 07 - "01100000", -- | ## | 08 - "00110000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 124 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00011000", -- | ## | 14 - -- ASCII 125 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00001100", -- | ## | 07 - "00000110", -- | ## | 08 - "00001100", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00110000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 126 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01110001", -- | ### #| 03 - "11011011", -- |## ## ##| 04 - "10001110", -- |# ### | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 127 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 128 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 129 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 130 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 131 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 132 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 133 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 134 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 135 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 136 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 137 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 138 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 139 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 140 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 141 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 142 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 143 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 144 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 145 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 146 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011100", -- | ### | 03 - "00011100", -- | ### | 04 - "00001100", -- | ## | 05 - "00011000", -- | ## | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 147 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 148 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 149 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 150 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 151 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 152 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 153 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 154 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 155 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 156 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 157 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 158 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 159 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 160 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 161 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00111100", -- | #### | 12 - "00111100", -- | #### | 13 - "00011000", -- | ## | 14 - -- ASCII 162 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 163 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "11111100", -- |###### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "11000000", -- |## | 10 - "11111110", -- |####### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 164 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "01100110", -- | ## ## | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "00111100", -- | #### | 08 - "01100110", -- | ## ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 165 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00111100", -- | #### | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "01111110", -- | ###### | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 166 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00011000", -- | ## | 14 - -- ASCII 167 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00111000", -- | ### | 06 - "00111100", -- | #### | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011100", -- | ### | 11 - "00000110", -- | ## | 12 - "01100110", -- | ## ## | 13 - "00111100", -- | #### | 14 - -- ASCII 168 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 169 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "11000011", -- |## ##| 04 - "10011001", -- |# ## #| 05 - "10100101", -- |# # # #| 06 - "10100001", -- |# # #| 07 - "10100101", -- |# # # #| 08 - "10011001", -- |# ## #| 09 - "11000011", -- |## ##| 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 170 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00000110", -- | ## | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "00111110", -- | ##### | 07 - "00000000", -- | | 08 - "01111110", -- | ###### | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 171 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00110011", -- | ## ##| 07 - "01100110", -- | ## ## | 08 - "11001100", -- |## ## | 09 - "01100110", -- | ## ## | 10 - "00110011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 172 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000110", -- | ## | 08 - "00000110", -- | ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 173 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 174 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "11000011", -- |## ##| 04 - "10111001", -- |# ### #| 05 - "10100101", -- |# # # #| 06 - "10100101", -- |# # # #| 07 - "10111001", -- |# ### #| 08 - "10100101", -- |# # # #| 09 - "11000011", -- |## ##| 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 175 --------------- - "11111111", -- |########| 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 176 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "00111100", -- | #### | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 177 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00000000", -- | | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 178 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111000", -- | ### | 03 - "00001100", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "00111100", -- | #### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 179 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111000", -- | ### | 03 - "00001100", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00111000", -- | ### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 180 --------------- - "00000000", -- | | 00 - "00011100", -- | ### | 01 - "00011000", -- | ## | 02 - "00110000", -- | ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 181 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111011", -- | #### ##| 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "11000000", -- |## | 14 - -- ASCII 182 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011111", -- | #####| 03 - "00111110", -- | ##### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "00111110", -- | ##### | 08 - "00011110", -- | #### | 09 - "00000110", -- | ## | 10 - "00000110", -- | ## | 11 - "00000110", -- | ## | 12 - "00000110", -- | ## | 13 - "00000110", -- | ## | 14 - -- ASCII 183 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00011100", -- | ### | 06 - "00011100", -- | ### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 184 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00111000", -- | ### | 14 - -- ASCII 185 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111000", -- | ### | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 186 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00000000", -- | | 08 - "01111110", -- | ###### | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 187 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "11001100", -- |## ## | 07 - "01100110", -- | ## ## | 08 - "00110011", -- | ## ##| 09 - "01100110", -- | ## ## | 10 - "11001100", -- |## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 188 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100000", -- | ## | 02 - "11100000", -- |### | 03 - "01100011", -- | ## ##| 04 - "01100110", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "00011000", -- | ## | 07 - "00110111", -- | ## ###| 08 - "01101111", -- | ## ####| 09 - "11011011", -- |## ## ##| 10 - "00011111", -- | #####| 11 - "00000011", -- | ##| 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 189 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100000", -- | ## | 02 - "11100000", -- |### | 03 - "01100011", -- | ## ##| 04 - "01100110", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "00011000", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100011", -- | ## ##| 09 - "11000110", -- |## ## | 10 - "00001100", -- | ## | 11 - "00001111", -- | ####| 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 190 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "11100000", -- |### | 02 - "00110000", -- | ## | 03 - "01100011", -- | ## ##| 04 - "00110110", -- | ## ## | 05 - "11101100", -- |### ## | 06 - "00011000", -- | ## | 07 - "00110111", -- | ## ###| 08 - "01101111", -- | ## ####| 09 - "11011011", -- |## ## ##| 10 - "00011111", -- | #####| 11 - "00000011", -- | ##| 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 191 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00110000", -- | ## | 11 - "01100110", -- | ## ## | 12 - "01100110", -- | ## ## | 13 - "00111100", -- | #### | 14 - -- ASCII 192 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 193 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 194 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 195 --------------- - "00111011", -- | ### ##| 00 - "01101110", -- | ## ### | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 196 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 197 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00111100", -- | #### | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 198 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001111", -- | ####| 03 - "00011100", -- | ### | 04 - "00111100", -- | #### | 05 - "01101100", -- | ## ## | 06 - "01101111", -- | ## ####| 07 - "01111100", -- | ##### | 08 - "01101100", -- | ## ## | 09 - "01101100", -- | ## ## | 10 - "01101111", -- | ## ####| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 199 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00111000", -- | ### | 14 - -- ASCII 200 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 201 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 202 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 203 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 204 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 205 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 206 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 207 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 208 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111000", -- | #### | 03 - "01101100", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "11110110", -- |#### ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01101100", -- | ## ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 209 --------------- - "00111011", -- | ### ##| 00 - "01101110", -- | ## ### | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01110011", -- | ### ##| 05 - "01111011", -- | #### ##| 06 - "01101111", -- | ## ####| 07 - "01100111", -- | ## ###| 08 - "01100011", -- | ## ##| 09 - "01100011", -- | ## ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 210 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 211 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 212 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 213 --------------- - "00111011", -- | ### ##| 00 - "01101110", -- | ## ### | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 214 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 215 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "01000010", -- | # # | 04 - "01100110", -- | ## ## | 05 - "00111100", -- | #### | 06 - "00011000", -- | ## | 07 - "00111100", -- | #### | 08 - "01100110", -- | ## ## | 09 - "01000010", -- | # # | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 216 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111110", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01101110", -- | ## ### | 05 - "01101110", -- | ## ### | 06 - "01111110", -- | ###### | 07 - "01110110", -- | ### ## | 08 - "01110110", -- | ### ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 217 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 218 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 219 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 220 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 221 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 222 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01111100", -- | ##### | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 223 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111000", -- | ### | 03 - "01101100", -- | ## ## | 04 - "01101100", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01101100", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 224 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 225 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 226 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 227 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 228 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 229 --------------- - "00000000", -- | | 00 - "00111100", -- | #### | 01 - "01100110", -- | ## ## | 02 - "00111100", -- | #### | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 230 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01101110", -- | ## ### | 05 - "00011011", -- | ## ##| 06 - "00011011", -- | ## ##| 07 - "01111111", -- | #######| 08 - "11011000", -- |## ## | 09 - "11011000", -- |## ## | 10 - "01110111", -- | ### ###| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 231 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00111000", -- | ### | 14 - -- ASCII 232 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 233 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 234 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 235 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 236 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 237 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 238 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 239 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 240 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110110", -- | ## ## | 03 - "00011000", -- | ## | 04 - "01101100", -- | ## ## | 05 - "00011110", -- | #### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 241 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 242 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 243 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 244 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 245 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 246 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 247 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 248 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01101110", -- | ## ### | 07 - "01111110", -- | ###### | 08 - "01110110", -- | ### ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 249 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 250 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 251 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 252 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 253 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - -- ASCII 254 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01111100", -- | ##### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "01100000", -- | ## | 14 - -- ASCII 255 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - -- ASCII 256 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 257 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 258 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 259 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 260 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 261 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 262 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 263 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 264 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 265 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 266 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 267 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 268 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 269 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 270 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 271 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 272 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 273 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 274 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 275 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 276 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 277 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 278 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 279 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 280 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 281 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 282 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 283 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 284 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 285 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 286 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 287 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- Padding --------------- - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000" -- Padded - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd deleted file mode 100644 index e46151c..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd +++ /dev/null @@ -1,4382 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 033 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "00111100", -- | #### | 05 - "00111100", -- | #### | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 034 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 035 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110110", -- | ## ## | 03 - "00110110", -- | ## ## | 04 - "01111111", -- | #######| 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "00110110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 036 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00011000", -- | ## | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00001100", -- | ## | 08 - "00000110", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 037 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01110000", -- | ### | 02 - "11011000", -- |## ## | 03 - "11011010", -- |## ## # | 04 - "01110110", -- | ### ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00110000", -- | ## | 08 - "01101110", -- | ## ### | 09 - "01011011", -- | # ## ##| 10 - "00011011", -- | ## ##| 11 - "00001110", -- | ### | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 038 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "11111111", -- |########| 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 039 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 040 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 041 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00110000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 042 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00110110", -- | ## ## | 05 - "00011100", -- | ### | 06 - "01111111", -- | #######| 07 - "00011100", -- | ### | 08 - "00110110", -- | ## ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 043 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 044 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 045 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 046 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 047 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "01100000", -- | ## | 11 - "01100000", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 048 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011110", -- | #### | 03 - "00110011", -- | ## ##| 04 - "00110111", -- | ## ###| 05 - "00110111", -- | ## ###| 06 - "00110011", -- | ## ##| 07 - "00111011", -- | ### ##| 08 - "00111011", -- | ### ##| 09 - "00110011", -- | ## ##| 10 - "00011110", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 049 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011100", -- | ### | 04 - "01111100", -- | ##### | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 050 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00001100", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 051 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00011100", -- | ### | 07 - "00000110", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 052 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00110000", -- | ## | 04 - "00110110", -- | ## ## | 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00000110", -- | ## | 10 - "00000110", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 053 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "00000110", -- | ## | 08 - "00000110", -- | ## | 09 - "00001100", -- | ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 054 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011100", -- | ### | 03 - "00011000", -- | ## | 04 - "00110000", -- | ## | 05 - "01111100", -- | ##### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 055 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "00000110", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00110000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 056 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01110110", -- | ### ## | 06 - "00111100", -- | #### | 07 - "01101110", -- | ## ### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 057 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "00111110", -- | ##### | 08 - "00001100", -- | ## | 09 - "00011000", -- | ## | 10 - "00111000", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 058 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 059 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 060 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00001100", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "01100000", -- | ## | 07 - "00110000", -- | ## | 08 - "00011000", -- | ## | 09 - "00001100", -- | ## | 10 - "00000110", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 061 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "01111110", -- | ###### | 06 - "00000000", -- | | 07 - "01111110", -- | ###### | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 062 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "00110000", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00000110", -- | ## | 07 - "00001100", -- | ## | 08 - "00011000", -- | ## | 09 - "00110000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 063 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 064 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "11000011", -- |## ##| 04 - "11000011", -- |## ##| 05 - "11001111", -- |## ####| 06 - "11011011", -- |## ## ##| 07 - "11011011", -- |## ## ##| 08 - "11001111", -- |## ####| 09 - "11000000", -- |## | 10 - "01111111", -- | #######| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 065 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 066 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111100", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111100", -- | ##### | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 067 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 068 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111000", -- | #### | 03 - "01101100", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01101100", -- | ## ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 069 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 070 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 071 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01101110", -- | ## ### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 072 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111110", -- | ###### | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 073 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 074 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00000110", -- | ## | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00000110", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 075 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01101100", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "01111000", -- | #### | 07 - "01101100", -- | ## ## | 08 - "01101100", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 076 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 077 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01110111", -- | ### ###| 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "01100011", -- | ## ##| 09 - "01100011", -- | ## ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 078 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01110011", -- | ### ##| 05 - "01111011", -- | #### ##| 06 - "01101111", -- | ## ####| 07 - "01100111", -- | ## ###| 08 - "01100011", -- | ## ##| 09 - "01100011", -- | ## ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 079 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 080 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111100", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 081 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00000110", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 082 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111100", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111100", -- | ##### | 07 - "01101100", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 083 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00001100", -- | ## | 08 - "00000110", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 084 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 085 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 086 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 087 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01100011", -- | ## ##| 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "00110110", -- | ## ## | 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 088 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "00110100", -- | ## # | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00101100", -- | # ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 089 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 090 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "00000110", -- | ## | 04 - "00000110", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00110000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 091 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00110000", -- | ## | 04 - "00110000", -- | ## | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00110000", -- | ## | 11 - "00110000", -- | ## | 12 - "00110000", -- | ## | 13 - "00111100", -- | #### | 14 - "00000000", -- | | 15 - -- ASCII 092 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "00110000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00000110", -- | ## | 11 - "00000110", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 093 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00001100", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00001100", -- | ## | 12 - "00001100", -- | ## | 13 - "00111100", -- | #### | 14 - "00000000", -- | | 15 - -- ASCII 094 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 095 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "11111111", -- |########| 14 - "00000000", -- | | 15 - -- ASCII 096 --------------- - "00000000", -- | | 00 - "00111000", -- | ### | 01 - "00011000", -- | ## | 02 - "00001100", -- | ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 097 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 098 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 099 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 100 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 101 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 102 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011110", -- | #### | 03 - "00110000", -- | ## | 04 - "00110000", -- | ## | 05 - "00110000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00110000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 103 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000110", -- | ## | 12 - "00000110", -- | ## | 13 - "01111100", -- | ##### | 14 - "00000000", -- | | 15 - -- ASCII 104 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 105 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00011000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 106 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00001100", -- | ## | 02 - "00001100", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00001100", -- | ## | 12 - "00001100", -- | ## | 13 - "01111000", -- | #### | 14 - "00000000", -- | | 15 - -- ASCII 107 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01101100", -- | ## ## | 07 - "01111000", -- | #### | 08 - "01101100", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 108 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111000", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 109 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111110", -- | ###### | 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "01101011", -- | ## # ##| 09 - "01101011", -- | ## # ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 110 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 111 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 112 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "01100000", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 113 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000110", -- | ## | 12 - "00000110", -- | ## | 13 - "00000110", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 114 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01101110", -- | ## ### | 06 - "01110000", -- | ### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 115 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "00111100", -- | #### | 08 - "00000110", -- | ## | 09 - "00000110", -- | ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 116 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00110000", -- | ## | 04 - "01111110", -- | ###### | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00011110", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 117 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 118 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 119 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100011", -- | ## ##| 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "01101011", -- | ## # ##| 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 120 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00011000", -- | ## | 08 - "00111100", -- | #### | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 121 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - "00000000", -- | | 15 - -- ASCII 122 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111110", -- | ###### | 05 - "00000110", -- | ## | 06 - "00001100", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 123 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00110000", -- | ## | 07 - "01100000", -- | ## | 08 - "00110000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 124 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00011000", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 125 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00001100", -- | ## | 07 - "00000110", -- | ## | 08 - "00001100", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00110000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 126 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01110001", -- | ### #| 03 - "11011011", -- |## ## ##| 04 - "10001110", -- |# ### | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 127 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 128 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 129 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 130 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 131 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 132 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 133 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 134 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 135 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 136 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 137 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 138 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 139 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 140 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 141 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 142 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 143 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 144 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 145 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 146 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011100", -- | ### | 03 - "00011100", -- | ### | 04 - "00001100", -- | ## | 05 - "00011000", -- | ## | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 147 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 148 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 149 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 150 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 151 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 152 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 153 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 154 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 155 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 156 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 157 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 158 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 159 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 160 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 161 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00111100", -- | #### | 12 - "00111100", -- | #### | 13 - "00011000", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 162 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 163 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "11111100", -- |###### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "11000000", -- |## | 10 - "11111110", -- |####### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 164 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "01100110", -- | ## ## | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "00111100", -- | #### | 08 - "01100110", -- | ## ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 165 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00111100", -- | #### | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "01111110", -- | ###### | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 166 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00011000", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 167 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00111000", -- | ### | 06 - "00111100", -- | #### | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011100", -- | ### | 11 - "00000110", -- | ## | 12 - "01100110", -- | ## ## | 13 - "00111100", -- | #### | 14 - "00000000", -- | | 15 - -- ASCII 168 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 169 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "11000011", -- |## ##| 04 - "10011001", -- |# ## #| 05 - "10100101", -- |# # # #| 06 - "10100001", -- |# # #| 07 - "10100101", -- |# # # #| 08 - "10011001", -- |# ## #| 09 - "11000011", -- |## ##| 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 170 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00000110", -- | ## | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "00111110", -- | ##### | 07 - "00000000", -- | | 08 - "01111110", -- | ###### | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 171 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00110011", -- | ## ##| 07 - "01100110", -- | ## ## | 08 - "11001100", -- |## ## | 09 - "01100110", -- | ## ## | 10 - "00110011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 172 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000110", -- | ## | 08 - "00000110", -- | ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 173 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 174 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "11000011", -- |## ##| 04 - "10111001", -- |# ### #| 05 - "10100101", -- |# # # #| 06 - "10100101", -- |# # # #| 07 - "10111001", -- |# ### #| 08 - "10100101", -- |# # # #| 09 - "11000011", -- |## ##| 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 175 --------------- - "11111111", -- |########| 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 176 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "00111100", -- | #### | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 177 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00000000", -- | | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 178 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111000", -- | ### | 03 - "00001100", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "00111100", -- | #### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 179 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111000", -- | ### | 03 - "00001100", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00111000", -- | ### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 180 --------------- - "00000000", -- | | 00 - "00011100", -- | ### | 01 - "00011000", -- | ## | 02 - "00110000", -- | ## | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 181 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111011", -- | #### ##| 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "11000000", -- |## | 14 - "00000000", -- | | 15 - -- ASCII 182 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011111", -- | #####| 03 - "00111110", -- | ##### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "00111110", -- | ##### | 08 - "00011110", -- | #### | 09 - "00000110", -- | ## | 10 - "00000110", -- | ## | 11 - "00000110", -- | ## | 12 - "00000110", -- | ## | 13 - "00000110", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 183 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00011100", -- | ### | 06 - "00011100", -- | ### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 184 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00111000", -- | ### | 14 - "00000000", -- | | 15 - -- ASCII 185 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111000", -- | ### | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 186 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00000000", -- | | 08 - "01111110", -- | ###### | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 187 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "11001100", -- |## ## | 07 - "01100110", -- | ## ## | 08 - "00110011", -- | ## ##| 09 - "01100110", -- | ## ## | 10 - "11001100", -- |## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 188 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100000", -- | ## | 02 - "11100000", -- |### | 03 - "01100011", -- | ## ##| 04 - "01100110", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "00011000", -- | ## | 07 - "00110111", -- | ## ###| 08 - "01101111", -- | ## ####| 09 - "11011011", -- |## ## ##| 10 - "00011111", -- | #####| 11 - "00000011", -- | ##| 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 189 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100000", -- | ## | 02 - "11100000", -- |### | 03 - "01100011", -- | ## ##| 04 - "01100110", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "00011000", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100011", -- | ## ##| 09 - "11000110", -- |## ## | 10 - "00001100", -- | ## | 11 - "00001111", -- | ####| 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 190 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "11100000", -- |### | 02 - "00110000", -- | ## | 03 - "01100011", -- | ## ##| 04 - "00110110", -- | ## ## | 05 - "11101100", -- |### ## | 06 - "00011000", -- | ## | 07 - "00110111", -- | ## ###| 08 - "01101111", -- | ## ####| 09 - "11011011", -- |## ## ##| 10 - "00011111", -- | #####| 11 - "00000011", -- | ##| 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 191 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00110000", -- | ## | 11 - "01100110", -- | ## ## | 12 - "01100110", -- | ## ## | 13 - "00111100", -- | #### | 14 - "00000000", -- | | 15 - -- ASCII 192 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 193 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 194 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 195 --------------- - "00111011", -- | ### ##| 00 - "01101110", -- | ## ### | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 196 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 197 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00111100", -- | #### | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 198 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001111", -- | ####| 03 - "00011100", -- | ### | 04 - "00111100", -- | #### | 05 - "01101100", -- | ## ## | 06 - "01101111", -- | ## ####| 07 - "01111100", -- | ##### | 08 - "01101100", -- | ## ## | 09 - "01101100", -- | ## ## | 10 - "01101111", -- | ## ####| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 199 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00111000", -- | ### | 14 - "00000000", -- | | 15 - -- ASCII 200 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 201 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 202 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 203 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 204 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 205 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 206 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 207 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 208 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111000", -- | #### | 03 - "01101100", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "11110110", -- |#### ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01101100", -- | ## ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 209 --------------- - "00111011", -- | ### ##| 00 - "01101110", -- | ## ### | 01 - "00000000", -- | | 02 - "01100011", -- | ## ##| 03 - "01100011", -- | ## ##| 04 - "01110011", -- | ### ##| 05 - "01111011", -- | #### ##| 06 - "01101111", -- | ## ####| 07 - "01100111", -- | ## ###| 08 - "01100011", -- | ## ##| 09 - "01100011", -- | ## ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 210 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 211 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 212 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 213 --------------- - "00111011", -- | ### ##| 00 - "01101110", -- | ## ### | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 214 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 215 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "01000010", -- | # # | 04 - "01100110", -- | ## ## | 05 - "00111100", -- | #### | 06 - "00011000", -- | ## | 07 - "00111100", -- | #### | 08 - "01100110", -- | ## ## | 09 - "01000010", -- | # # | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 216 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111110", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01101110", -- | ## ### | 05 - "01101110", -- | ## ### | 06 - "01111110", -- | ###### | 07 - "01110110", -- | ### ## | 08 - "01110110", -- | ### ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 217 --------------- - "00110000", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 218 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 219 --------------- - "00111100", -- | #### | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 220 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 221 --------------- - "00001100", -- | ## | 00 - "00011000", -- | ## | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 222 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01111100", -- | ##### | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 223 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111000", -- | ### | 03 - "01101100", -- | ## ## | 04 - "01101100", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01101100", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 224 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 225 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 226 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 227 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 228 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 229 --------------- - "00000000", -- | | 00 - "00111100", -- | #### | 01 - "01100110", -- | ## ## | 02 - "00111100", -- | #### | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 230 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01101110", -- | ## ### | 05 - "00011011", -- | ## ##| 06 - "00011011", -- | ## ##| 07 - "01111111", -- | #######| 08 - "11011000", -- |## ## | 09 - "11011000", -- |## ## | 10 - "01110111", -- | ### ###| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 231 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00111000", -- | ### | 14 - "00000000", -- | | 15 - -- ASCII 232 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 233 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 234 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 235 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 236 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 237 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 238 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 239 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 240 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110110", -- | ## ## | 03 - "00011000", -- | ## | 04 - "01101100", -- | ## ## | 05 - "00011110", -- | #### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 241 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 242 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 243 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 244 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 245 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 246 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 247 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 248 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01101110", -- | ## ### | 07 - "01111110", -- | ###### | 08 - "01110110", -- | ### ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 249 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 250 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 251 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 252 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 253 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - "00000000", -- | | 15 - -- ASCII 254 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01111100", -- | ##### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "01100000", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 255 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - "00000000", -- | | 15 - -- ASCII 256 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 257 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 258 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 259 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 260 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 261 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 262 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 263 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 264 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 265 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 266 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 267 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 268 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 269 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 270 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 271 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 272 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 273 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 274 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 275 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 276 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 277 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 278 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 279 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 280 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 281 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 282 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 283 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 284 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 285 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 286 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 287 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "11111111", -- |########| 12 - "11111111", -- |########| 13 - "11111111", -- |########| 14 - "00000000" -- | | 15 - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd deleted file mode 100644 index 9b32d16..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd +++ /dev/null @@ -1,4351 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(8 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(8 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 033 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "001111000", -- | #### | 05 - "001111000", -- | #### | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000000000", -- | | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 034 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 035 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001101100", -- | ## ## | 03 - "001101100", -- | ## ## | 04 - "011111110", -- | ####### | 05 - "001101100", -- | ## ## | 06 - "001101100", -- | ## ## | 07 - "001101100", -- | ## ## | 08 - "011111110", -- | ####### | 09 - "001101100", -- | ## ## | 10 - "001101100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 036 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "000110000", -- | ## | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011000000", -- | ## | 05 - "001100000", -- | ## | 06 - "000110000", -- | ## | 07 - "000011000", -- | ## | 08 - "000001100", -- | ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000110000", -- | ## | 12 - "000110000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 037 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011100000", -- | ### | 02 - "110110000", -- |## ## | 03 - "110110100", -- |## ## # | 04 - "011101100", -- | ### ## | 05 - "000011000", -- | ## | 06 - "000110000", -- | ## | 07 - "001100000", -- | ## | 08 - "011011100", -- | ## ### | 09 - "010110110", -- | # ## ## | 10 - "000110110", -- | ## ## | 11 - "000011100", -- | ### | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 038 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "111111110", -- |######## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 039 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 040 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000011000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "001100000", -- | ## | 06 - "001100000", -- | ## | 07 - "001100000", -- | ## | 08 - "001100000", -- | ## | 09 - "001100000", -- | ## | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "000011000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 041 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001100000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000011000", -- | ## | 06 - "000011000", -- | ## | 07 - "000011000", -- | ## | 08 - "000011000", -- | ## | 09 - "000011000", -- | ## | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "001100000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 042 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001101100", -- | ## ## | 05 - "000111000", -- | ### | 06 - "011111110", -- | ####### | 07 - "000111000", -- | ### | 08 - "001101100", -- | ## ## | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 043 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "011111100", -- | ###### | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 044 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000111000", -- | ### | 10 - "000111000", -- | ### | 11 - "000011000", -- | ## | 12 - "000110000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 045 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "011111100", -- | ###### | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 046 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000111000", -- | ### | 10 - "000111000", -- | ### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 047 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000001100", -- | ## | 03 - "000001100", -- | ## | 04 - "000011000", -- | ## | 05 - "000011000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "001100000", -- | ## | 09 - "001100000", -- | ## | 10 - "011000000", -- | ## | 11 - "011000000", -- | ## | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 048 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000111100", -- | #### | 03 - "001100110", -- | ## ## | 04 - "001101110", -- | ## ### | 05 - "001101110", -- | ## ### | 06 - "001100110", -- | ## ## | 07 - "001110110", -- | ### ## | 08 - "001110110", -- | ### ## | 09 - "001100110", -- | ## ## | 10 - "000111100", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 049 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000011000", -- | ## | 03 - "000111000", -- | ### | 04 - "011111000", -- | ##### | 05 - "000011000", -- | ## | 06 - "000011000", -- | ## | 07 - "000011000", -- | ## | 08 - "000011000", -- | ## | 09 - "000011000", -- | ## | 10 - "000011000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 050 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "000001100", -- | ## | 06 - "000011000", -- | ## | 07 - "000110000", -- | ## | 08 - "001100000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 051 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "000001100", -- | ## | 06 - "000111000", -- | ### | 07 - "000001100", -- | ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 052 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001100000", -- | ## | 03 - "001100000", -- | ## | 04 - "001101100", -- | ## ## | 05 - "001101100", -- | ## ## | 06 - "001101100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011111110", -- | ####### | 09 - "000001100", -- | ## | 10 - "000001100", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 053 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011111000", -- | ##### | 07 - "000001100", -- | ## | 08 - "000001100", -- | ## | 09 - "000011000", -- | ## | 10 - "011110000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 054 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000111000", -- | ### | 03 - "000110000", -- | ## | 04 - "001100000", -- | ## | 05 - "011111000", -- | ##### | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 055 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "000001100", -- | ## | 04 - "000011000", -- | ## | 05 - "000011000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "001100000", -- | ## | 09 - "001100000", -- | ## | 10 - "001100000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 056 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011101100", -- | ### ## | 06 - "001111000", -- | #### | 07 - "011011100", -- | ## ### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 057 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "001111100", -- | ##### | 08 - "000011000", -- | ## | 09 - "000110000", -- | ## | 10 - "001110000", -- | ### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 058 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000111000", -- | ### | 05 - "000111000", -- | ### | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000111000", -- | ### | 10 - "000111000", -- | ### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 059 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000111000", -- | ### | 05 - "000111000", -- | ### | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000111000", -- | ### | 10 - "000111000", -- | ### | 11 - "000011000", -- | ## | 12 - "000110000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 060 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000001100", -- | ## | 03 - "000011000", -- | ## | 04 - "000110000", -- | ## | 05 - "001100000", -- | ## | 06 - "011000000", -- | ## | 07 - "001100000", -- | ## | 08 - "000110000", -- | ## | 09 - "000011000", -- | ## | 10 - "000001100", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 061 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "011111100", -- | ###### | 06 - "000000000", -- | | 07 - "011111100", -- | ###### | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 062 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "001100000", -- | ## | 04 - "000110000", -- | ## | 05 - "000011000", -- | ## | 06 - "000001100", -- | ## | 07 - "000011000", -- | ## | 08 - "000110000", -- | ## | 09 - "001100000", -- | ## | 10 - "011000000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 063 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "000011000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000000000", -- | | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 064 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "110000110", -- |## ## | 04 - "110000110", -- |## ## | 05 - "110011110", -- |## #### | 06 - "110110110", -- |## ## ## | 07 - "110110110", -- |## ## ## | 08 - "110011110", -- |## #### | 09 - "110000000", -- |## | 10 - "011111110", -- | ####### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 065 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 066 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111000", -- | ##### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011111000", -- | ##### | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011111000", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 067 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011000000", -- | ## | 06 - "011000000", -- | ## | 07 - "011000000", -- | ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 068 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011110000", -- | #### | 03 - "011011000", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011011000", -- | ## ## | 10 - "011110000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 069 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011111000", -- | ##### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 070 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011111000", -- | ##### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011000000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 071 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011000000", -- | ## | 06 - "011000000", -- | ## | 07 - "011011100", -- | ## ### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 072 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011111100", -- | ###### | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 073 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 074 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000001100", -- | ## | 03 - "000001100", -- | ## | 04 - "000001100", -- | ## | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "000001100", -- | ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 075 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011011000", -- | ## ## | 05 - "011011000", -- | ## ## | 06 - "011110000", -- | #### | 07 - "011011000", -- | ## ## | 08 - "011011000", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 076 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011000000", -- | ## | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 077 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000110", -- | ## ## | 03 - "011000110", -- | ## ## | 04 - "011101110", -- | ### ### | 05 - "011010110", -- | ## # ## | 06 - "011010110", -- | ## # ## | 07 - "011010110", -- | ## # ## | 08 - "011000110", -- | ## ## | 09 - "011000110", -- | ## ## | 10 - "011000110", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 078 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000110", -- | ## ## | 03 - "011000110", -- | ## ## | 04 - "011100110", -- | ### ## | 05 - "011110110", -- | #### ## | 06 - "011011110", -- | ## #### | 07 - "011001110", -- | ## ### | 08 - "011000110", -- | ## ## | 09 - "011000110", -- | ## ## | 10 - "011000110", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 079 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 080 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111000", -- | ##### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011111000", -- | ##### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011000000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 081 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000011000", -- | ## | 12 - "000001100", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 082 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111000", -- | ##### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011111000", -- | ##### | 07 - "011011000", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 083 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011000000", -- | ## | 05 - "001100000", -- | ## | 06 - "000110000", -- | ## | 07 - "000011000", -- | ## | 08 - "000001100", -- | ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 084 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 085 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 086 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "001111000", -- | #### | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 087 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000110", -- | ## ## | 03 - "011000110", -- | ## ## | 04 - "011000110", -- | ## ## | 05 - "011010110", -- | ## # ## | 06 - "011010110", -- | ## # ## | 07 - "011010110", -- | ## # ## | 08 - "001101100", -- | ## ## | 09 - "001101100", -- | ## ## | 10 - "001101100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 088 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "001101000", -- | ## # | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "001011000", -- | # ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 089 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "001111000", -- | #### | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 090 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "000001100", -- | ## | 04 - "000001100", -- | ## | 05 - "000011000", -- | ## | 06 - "000110000", -- | ## | 07 - "001100000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 091 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "001100000", -- | ## | 04 - "001100000", -- | ## | 05 - "001100000", -- | ## | 06 - "001100000", -- | ## | 07 - "001100000", -- | ## | 08 - "001100000", -- | ## | 09 - "001100000", -- | ## | 10 - "001100000", -- | ## | 11 - "001100000", -- | ## | 12 - "001100000", -- | ## | 13 - "001111000", -- | #### | 14 - "000000000", -- | | 15 - -- ASCII 092 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "001100000", -- | ## | 05 - "001100000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000011000", -- | ## | 09 - "000011000", -- | ## | 10 - "000001100", -- | ## | 11 - "000001100", -- | ## | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 093 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "000011000", -- | ## | 04 - "000011000", -- | ## | 05 - "000011000", -- | ## | 06 - "000011000", -- | ## | 07 - "000011000", -- | ## | 08 - "000011000", -- | ## | 09 - "000011000", -- | ## | 10 - "000011000", -- | ## | 11 - "000011000", -- | ## | 12 - "000011000", -- | ## | 13 - "001111000", -- | #### | 14 - "000000000", -- | | 15 - -- ASCII 094 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 095 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "111111110", -- |######## | 14 - "000000000", -- | | 15 - -- ASCII 096 --------------- - "000000000", -- | | 00 - "001110000", -- | ### | 01 - "000110000", -- | ## | 02 - "000011000", -- | ## | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 097 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 098 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "011111000", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011111000", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 099 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011000000", -- | ## | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 100 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000001100", -- | ## | 03 - "000001100", -- | ## | 04 - "001111100", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 101 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 102 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000111100", -- | #### | 03 - "001100000", -- | ## | 04 - "001100000", -- | ## | 05 - "001100000", -- | ## | 06 - "011111100", -- | ###### | 07 - "001100000", -- | ## | 08 - "001100000", -- | ## | 09 - "001100000", -- | ## | 10 - "001100000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 103 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111100", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000001100", -- | ## | 12 - "000001100", -- | ## | 13 - "011111000", -- | ##### | 14 - "000000000", -- | | 15 - -- ASCII 104 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "011111000", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 105 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000110000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011110000", -- | #### | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 106 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000011000", -- | ## | 02 - "000011000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000011000", -- | ## | 06 - "000011000", -- | ## | 07 - "000011000", -- | ## | 08 - "000011000", -- | ## | 09 - "000011000", -- | ## | 10 - "000011000", -- | ## | 11 - "000011000", -- | ## | 12 - "000011000", -- | ## | 13 - "011110000", -- | #### | 14 - "000000000", -- | | 15 - -- ASCII 107 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011011000", -- | ## ## | 07 - "011110000", -- | #### | 08 - "011011000", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 108 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011110000", -- | #### | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 109 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011111100", -- | ###### | 05 - "011010110", -- | ## # ## | 06 - "011010110", -- | ## # ## | 07 - "011010110", -- | ## # ## | 08 - "011010110", -- | ## # ## | 09 - "011010110", -- | ## # ## | 10 - "011000110", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 110 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011111000", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 111 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 112 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011111000", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011111000", -- | ##### | 11 - "011000000", -- | ## | 12 - "011000000", -- | ## | 13 - "011000000", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 113 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111100", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000001100", -- | ## | 12 - "000001100", -- | ## | 13 - "000001100", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 114 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011011100", -- | ## ### | 06 - "011100000", -- | ### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011000000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 115 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111100", -- | ##### | 05 - "011000000", -- | ## | 06 - "011000000", -- | ## | 07 - "001111000", -- | #### | 08 - "000001100", -- | ## | 09 - "000001100", -- | ## | 10 - "011111000", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 116 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001100000", -- | ## | 03 - "001100000", -- | ## | 04 - "011111100", -- | ###### | 05 - "001100000", -- | ## | 06 - "001100000", -- | ## | 07 - "001100000", -- | ## | 08 - "001100000", -- | ## | 09 - "001100000", -- | ## | 10 - "000111100", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 117 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 118 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "001111000", -- | #### | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 119 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011000110", -- | ## ## | 05 - "011010110", -- | ## # ## | 06 - "011010110", -- | ## # ## | 07 - "011010110", -- | ## # ## | 08 - "011010110", -- | ## # ## | 09 - "001101100", -- | ## ## | 10 - "001101100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 120 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "001111000", -- | #### | 07 - "000110000", -- | ## | 08 - "001111000", -- | #### | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 121 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000011000", -- | ## | 12 - "000110000", -- | ## | 13 - "111100000", -- |#### | 14 - "000000000", -- | | 15 - -- ASCII 122 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011111100", -- | ###### | 05 - "000001100", -- | ## | 06 - "000011000", -- | ## | 07 - "000110000", -- | ## | 08 - "001100000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 123 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000011000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "001100000", -- | ## | 07 - "011000000", -- | ## | 08 - "001100000", -- | ## | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "000011000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 124 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "000110000", -- | ## | 13 - "000110000", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 125 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001100000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000011000", -- | ## | 07 - "000001100", -- | ## | 08 - "000011000", -- | ## | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "001100000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 126 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011100010", -- | ### # | 03 - "110110110", -- |## ## ## | 04 - "100011100", -- |# ### | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 127 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 128 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 129 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 130 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 131 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 132 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 133 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 134 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 135 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 136 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 137 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 138 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 139 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 140 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 141 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 142 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 143 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 144 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 145 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000011000", -- | ## | 03 - "000110000", -- | ## | 04 - "000111000", -- | ### | 05 - "000111000", -- | ### | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 146 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000111000", -- | ### | 03 - "000111000", -- | ### | 04 - "000011000", -- | ## | 05 - "000110000", -- | ## | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 147 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 148 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 149 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 150 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 151 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 152 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 153 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 154 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 155 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 156 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 157 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 158 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 159 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 160 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 161 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000000000", -- | | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "001111000", -- | #### | 11 - "001111000", -- | #### | 12 - "001111000", -- | #### | 13 - "000110000", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 162 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "000110000", -- | ## | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011000000", -- | ## | 07 - "011000000", -- | ## | 08 - "011001100", -- | ## ## | 09 - "001111000", -- | #### | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 163 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "111111000", -- |###### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "110000000", -- |## | 10 - "111111100", -- |####### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 164 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "011001100", -- | ## ## | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "001111000", -- | #### | 08 - "011001100", -- | ## ## | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 165 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "001111000", -- | #### | 06 - "011111100", -- | ###### | 07 - "000110000", -- | ## | 08 - "011111100", -- | ###### | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 166 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "000110000", -- | ## | 13 - "000110000", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 167 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011000000", -- | ## | 05 - "001110000", -- | ### | 06 - "001111000", -- | #### | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "001111000", -- | #### | 10 - "000111000", -- | ### | 11 - "000001100", -- | ## | 12 - "011001100", -- | ## ## | 13 - "001111000", -- | #### | 14 - "000000000", -- | | 15 - -- ASCII 168 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 169 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "110000110", -- |## ## | 04 - "100110010", -- |# ## # | 05 - "101001010", -- |# # # # | 06 - "101000010", -- |# # # | 07 - "101001010", -- |# # # # | 08 - "100110010", -- |# ## # | 09 - "110000110", -- |## ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 170 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "000001100", -- | ## | 04 - "001111100", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "001111100", -- | ##### | 07 - "000000000", -- | | 08 - "011111100", -- | ###### | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 171 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "001100110", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "110011000", -- |## ## | 09 - "011001100", -- | ## ## | 10 - "001100110", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 172 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "011111100", -- | ###### | 07 - "000001100", -- | ## | 08 - "000001100", -- | ## | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 173 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "011111100", -- | ###### | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 174 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "110000110", -- |## ## | 04 - "101110010", -- |# ### # | 05 - "101001010", -- |# # # # | 06 - "101001010", -- |# # # # | 07 - "101110010", -- |# ### # | 08 - "101001010", -- |# # # # | 09 - "110000110", -- |## ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 175 --------------- - "111111110", -- |######## | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 176 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "001111000", -- | #### | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 177 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "011111100", -- | ###### | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000000000", -- | | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 178 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001110000", -- | ### | 03 - "000011000", -- | ## | 04 - "000110000", -- | ## | 05 - "001100000", -- | ## | 06 - "001111000", -- | #### | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 179 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001110000", -- | ### | 03 - "000011000", -- | ## | 04 - "000110000", -- | ## | 05 - "000011000", -- | ## | 06 - "001110000", -- | ### | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 180 --------------- - "000000000", -- | | 00 - "000111000", -- | ### | 01 - "000110000", -- | ## | 02 - "001100000", -- | ## | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 181 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011110110", -- | #### ## | 11 - "011000000", -- | ## | 12 - "011000000", -- | ## | 13 - "110000000", -- |## | 14 - "000000000", -- | | 15 - -- ASCII 182 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000111110", -- | ##### | 03 - "001111100", -- | ##### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "001111100", -- | ##### | 08 - "000111100", -- | #### | 09 - "000001100", -- | ## | 10 - "000001100", -- | ## | 11 - "000001100", -- | ## | 12 - "000001100", -- | ## | 13 - "000001100", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 183 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000111000", -- | ### | 06 - "000111000", -- | ### | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 184 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000110000", -- | ## | 12 - "000011000", -- | ## | 13 - "001110000", -- | ### | 14 - "000000000", -- | | 15 - -- ASCII 185 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001110000", -- | ### | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 186 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "001111000", -- | #### | 07 - "000000000", -- | | 08 - "011111100", -- | ###### | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 187 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "110011000", -- |## ## | 07 - "011001100", -- | ## ## | 08 - "001100110", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "110011000", -- |## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 188 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011000000", -- | ## | 02 - "111000000", -- |### | 03 - "011000110", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011011000", -- | ## ## | 06 - "000110000", -- | ## | 07 - "001101110", -- | ## ### | 08 - "011011110", -- | ## #### | 09 - "110110110", -- |## ## ## | 10 - "000111110", -- | ##### | 11 - "000000110", -- | ## | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 189 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011000000", -- | ## | 02 - "111000000", -- |### | 03 - "011000110", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011011000", -- | ## ## | 06 - "000110000", -- | ## | 07 - "001111100", -- | ##### | 08 - "011000110", -- | ## ## | 09 - "110001100", -- |## ## | 10 - "000011000", -- | ## | 11 - "000011110", -- | #### | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 190 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "111000000", -- |### | 02 - "001100000", -- | ## | 03 - "011000110", -- | ## ## | 04 - "001101100", -- | ## ## | 05 - "111011000", -- |### ## | 06 - "000110000", -- | ## | 07 - "001101110", -- | ## ### | 08 - "011011110", -- | ## #### | 09 - "110110110", -- |## ## ## | 10 - "000111110", -- | ##### | 11 - "000000110", -- | ## | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 191 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000000000", -- | | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "001100000", -- | ## | 11 - "011001100", -- | ## ## | 12 - "011001100", -- | ## ## | 13 - "001111000", -- | #### | 14 - "000000000", -- | | 15 - -- ASCII 192 --------------- - "001100000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 193 --------------- - "000011000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 194 --------------- - "001111000", -- | #### | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 195 --------------- - "001110110", -- | ### ## | 00 - "011011100", -- | ## ### | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 196 --------------- - "011001100", -- | ## ## | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 197 --------------- - "001111000", -- | #### | 00 - "011001100", -- | ## ## | 01 - "001111000", -- | #### | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 198 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000011110", -- | #### | 03 - "000111000", -- | ### | 04 - "001111000", -- | #### | 05 - "011011000", -- | ## ## | 06 - "011011110", -- | ## #### | 07 - "011111000", -- | ##### | 08 - "011011000", -- | ## ## | 09 - "011011000", -- | ## ## | 10 - "011011110", -- | ## #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 199 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011000000", -- | ## | 06 - "011000000", -- | ## | 07 - "011000000", -- | ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000110000", -- | ## | 12 - "000011000", -- | ## | 13 - "001110000", -- | ### | 14 - "000000000", -- | | 15 - -- ASCII 200 --------------- - "001100000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011111000", -- | ##### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 201 --------------- - "000011000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011111000", -- | ##### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 202 --------------- - "001111000", -- | #### | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011111000", -- | ##### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 203 --------------- - "011001100", -- | ## ## | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011000000", -- | ## | 06 - "011111000", -- | ##### | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 204 --------------- - "001100000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 205 --------------- - "000011000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 206 --------------- - "001111000", -- | #### | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 207 --------------- - "011001100", -- | ## ## | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 208 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011110000", -- | #### | 03 - "011011000", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "111101100", -- |#### ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011011000", -- | ## ## | 10 - "011110000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 209 --------------- - "001110110", -- | ### ## | 00 - "011011100", -- | ## ### | 01 - "000000000", -- | | 02 - "011000110", -- | ## ## | 03 - "011000110", -- | ## ## | 04 - "011100110", -- | ### ## | 05 - "011110110", -- | #### ## | 06 - "011011110", -- | ## #### | 07 - "011001110", -- | ## ### | 08 - "011000110", -- | ## ## | 09 - "011000110", -- | ## ## | 10 - "011000110", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 210 --------------- - "001100000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 211 --------------- - "000011000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 212 --------------- - "001111000", -- | #### | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 213 --------------- - "001110110", -- | ### ## | 00 - "011011100", -- | ## ### | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 214 --------------- - "011001100", -- | ## ## | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 215 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "010000100", -- | # # | 04 - "011001100", -- | ## ## | 05 - "001111000", -- | #### | 06 - "000110000", -- | ## | 07 - "001111000", -- | #### | 08 - "011001100", -- | ## ## | 09 - "010000100", -- | # # | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 216 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001111100", -- | ##### | 03 - "011001100", -- | ## ## | 04 - "011011100", -- | ## ### | 05 - "011011100", -- | ## ### | 06 - "011111100", -- | ###### | 07 - "011101100", -- | ### ## | 08 - "011101100", -- | ### ## | 09 - "011001100", -- | ## ## | 10 - "011111000", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 217 --------------- - "001100000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 218 --------------- - "000011000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 219 --------------- - "001111000", -- | #### | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 220 --------------- - "011001100", -- | ## ## | 00 - "011001100", -- | ## ## | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 221 --------------- - "000011000", -- | ## | 00 - "000110000", -- | ## | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "001111000", -- | #### | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 222 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "011111000", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011111000", -- | ##### | 09 - "011000000", -- | ## | 10 - "011000000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 223 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001110000", -- | ### | 03 - "011011000", -- | ## ## | 04 - "011011000", -- | ## ## | 05 - "011011000", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011011000", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 224 --------------- - "000000000", -- | | 00 - "011100000", -- | ### | 01 - "001100000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 225 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 226 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 227 --------------- - "000000000", -- | | 00 - "011100010", -- | ### # | 01 - "110110110", -- |## ## ## | 02 - "100011100", -- |# ### | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 228 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 229 --------------- - "000000000", -- | | 00 - "001111000", -- | #### | 01 - "011001100", -- | ## ## | 02 - "001111000", -- | #### | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 230 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011011100", -- | ## ### | 05 - "000110110", -- | ## ## | 06 - "000110110", -- | ## ## | 07 - "011111110", -- | ####### | 08 - "110110000", -- |## ## | 09 - "110110000", -- |## ## | 10 - "011101110", -- | ### ### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 231 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011000000", -- | ## | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000110000", -- | ## | 12 - "000011000", -- | ## | 13 - "001110000", -- | ### | 14 - "000000000", -- | | 15 - -- ASCII 232 --------------- - "000000000", -- | | 00 - "011100000", -- | ### | 01 - "001100000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 233 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 234 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 235 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 236 --------------- - "000000000", -- | | 00 - "011100000", -- | ### | 01 - "001100000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011110000", -- | #### | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 237 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011110000", -- | #### | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 238 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "011110000", -- | #### | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 239 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "011110000", -- | #### | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 240 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001101100", -- | ## ## | 03 - "000110000", -- | ## | 04 - "011011000", -- | ## ## | 05 - "000111100", -- | #### | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 241 --------------- - "000000000", -- | | 00 - "011100010", -- | ### # | 01 - "110110110", -- |## ## ## | 02 - "100011100", -- |# ### | 03 - "000000000", -- | | 04 - "011111000", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 242 --------------- - "000000000", -- | | 00 - "011100000", -- | ### | 01 - "001100000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 243 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 244 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 245 --------------- - "000000000", -- | | 00 - "011100010", -- | ### # | 01 - "110110110", -- |## ## ## | 02 - "100011100", -- |# ### | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 246 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 247 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000000000", -- | | 06 - "011111100", -- | ###### | 07 - "000000000", -- | | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 248 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111100", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011011100", -- | ## ### | 07 - "011111100", -- | ###### | 08 - "011101100", -- | ### ## | 09 - "011001100", -- | ## ## | 10 - "011111000", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 249 --------------- - "000000000", -- | | 00 - "011100000", -- | ### | 01 - "001100000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 250 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 251 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 252 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 253 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000011000", -- | ## | 12 - "000110000", -- | ## | 13 - "111100000", -- |#### | 14 - "000000000", -- | | 15 - -- ASCII 254 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011111000", -- | ##### | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011111000", -- | ##### | 11 - "011000000", -- | ## | 12 - "011000000", -- | ## | 13 - "011000000", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 255 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000011000", -- | ## | 12 - "000110000", -- | ## | 13 - "111100000", -- |#### | 14 - "000000000", -- | | 15 - -- Padding --------------- - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000" -- Padded - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd deleted file mode 100644 index d50d36f..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd +++ /dev/null @@ -1,4382 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(15 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(15 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 033 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0000000000000000", -- | | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 034 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100110000000000", -- |## ## | 03 - "1100110000000000", -- |## ## | 04 - "1100110000000000", -- |## ## | 05 - "1100110000000000", -- |## ## | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 035 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011011000000000", -- | ## ## | 03 - "0011011000000000", -- | ## ## | 04 - "0111111100000000", -- | ####### | 05 - "0011011000000000", -- | ## ## | 06 - "0011011000000000", -- | ## ## | 07 - "0110110000000000", -- | ## ## | 08 - "0110110000000000", -- | ## ## | 09 - "1111111000000000", -- |####### | 10 - "0110110000000000", -- | ## ## | 11 - "0110110000000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 036 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0011110000000000", -- | #### | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110000000000000", -- | ## | 07 - "0011110000000000", -- | #### | 08 - "0000011000000000", -- | ## | 09 - "0000011000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0001100000000000", -- | ## | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 037 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111000001100000", -- | ### ## | 03 - "1101100011000000", -- |## ## ## | 04 - "1101100110000000", -- |## ## ## | 05 - "1101101100000000", -- |## ## ## | 06 - "0111011000000000", -- | ### ## | 07 - "0000110111000000", -- | ## ### | 08 - "0001101101100000", -- | ## ## ## | 09 - "0011001101100000", -- | ## ## ## | 10 - "0110001101100000", -- | ## ## ## | 11 - "1100000111000000", -- |## ### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 038 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "1111000000000000", -- |#### | 14 - "0000000000000000", -- | | 15 - -- ASCII 039 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 040 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0011000000000000", -- | ## | 15 - -- ASCII 041 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100000000000000", -- |## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "1100000000000000", -- |## | 15 - -- ASCII 042 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000000000000", -- | ## | 03 - "1111110000000000", -- |###### | 04 - "0011000000000000", -- | ## | 05 - "0111100000000000", -- | #### | 06 - "0100100000000000", -- | # # | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 043 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0001100000000000", -- | ## | 05 - "0001100000000000", -- | ## | 06 - "0001100000000000", -- | ## | 07 - "0111111000000000", -- | ###### | 08 - "0001100000000000", -- | ## | 09 - "0001100000000000", -- | ## | 10 - "0001100000000000", -- | ## | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 044 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "1100000000000000", -- |## | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 045 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "1111000000000000", -- |#### | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 046 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 047 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0011000000000000", -- | ## | 05 - "0011000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "1100000000000000", -- |## | 11 - "1100000000000000", -- |## | 12 - "1100000000000000", -- |## | 13 - "1100000000000000", -- |## | 14 - "0000000000000000", -- | | 15 - -- ASCII 048 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 049 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0111100000000000", -- | #### | 04 - "0001100000000000", -- | ## | 05 - "0001100000000000", -- | ## | 06 - "0001100000000000", -- | ## | 07 - "0001100000000000", -- | ## | 08 - "0001100000000000", -- | ## | 09 - "0001100000000000", -- | ## | 10 - "0001100000000000", -- | ## | 11 - "0001100000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 050 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0000011000000000", -- | ## | 06 - "0000110000000000", -- | ## | 07 - "0001100000000000", -- | ## | 08 - "0011000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111000000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 051 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0000011000000000", -- | ## | 05 - "0000011000000000", -- | ## | 06 - "0001110000000000", -- | ### | 07 - "0000011000000000", -- | ## | 08 - "0000011000000000", -- | ## | 09 - "0000011000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 052 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000011000000000", -- | ## | 03 - "0000111000000000", -- | ### | 04 - "0001111000000000", -- | #### | 05 - "0001111000000000", -- | #### | 06 - "0011011000000000", -- | ## ## | 07 - "0011011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "0000011000000000", -- | ## | 11 - "0000011000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 053 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111000000000", -- | ###### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111110000000000", -- | ##### | 07 - "0110011000000000", -- | ## ## | 08 - "0000011000000000", -- | ## | 09 - "0000011000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 054 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111110000000000", -- | ##### | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 055 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111000000000", -- | ###### | 03 - "0000011000000000", -- | ## | 04 - "0000110000000000", -- | ## | 05 - "0000110000000000", -- | ## | 06 - "0001100000000000", -- | ## | 07 - "0001100000000000", -- | ## | 08 - "0001100000000000", -- | ## | 09 - "0011000000000000", -- | ## | 10 - "0011000000000000", -- | ## | 11 - "0011000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 056 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0011110000000000", -- | #### | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 057 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0011111000000000", -- | ##### | 08 - "0000011000000000", -- | ## | 09 - "0000011000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 058 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 059 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "1100000000000000", -- |## | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 060 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000011000000000", -- | ## | 04 - "0000110000000000", -- | ## | 05 - "0001100000000000", -- | ## | 06 - "0011000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0011000000000000", -- | ## | 09 - "0001100000000000", -- | ## | 10 - "0000110000000000", -- | ## | 11 - "0000011000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 061 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0111111000000000", -- | ###### | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0111111000000000", -- | ###### | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 062 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0011000000000000", -- | ## | 05 - "0001100000000000", -- | ## | 06 - "0000110000000000", -- | ## | 07 - "0000011000000000", -- | ## | 08 - "0000110000000000", -- | ## | 09 - "0001100000000000", -- | ## | 10 - "0011000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 063 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0000011000000000", -- | ## | 06 - "0000110000000000", -- | ## | 07 - "0001100000000000", -- | ## | 08 - "0001100000000000", -- | ## | 09 - "0000000000000000", -- | | 10 - "0001100000000000", -- | ## | 11 - "0001100000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 064 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000011110000000", -- | #### | 02 - "0001110011100000", -- | ### ### | 03 - "0011000000110000", -- | ## ## | 04 - "0011001110110000", -- | ## ### ## | 05 - "0110011011011000", -- | ## ## ## ## | 06 - "0110011011011000", -- | ## ## ## ## | 07 - "0110110011011000", -- | ## ## ## ## | 08 - "0110110110011000", -- | ## ## ## ## | 09 - "0110110110011000", -- | ## ## ## ## | 10 - "0011011011110000", -- | ## ## #### | 11 - "0011000000000000", -- | ## | 12 - "0001110001110000", -- | ### ### | 13 - "0000011111000000", -- | ##### | 14 - "0000000000000000", -- | | 15 - -- ASCII 065 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0011110000000000", -- | #### | 05 - "0011110000000000", -- | #### | 06 - "0010010000000000", -- | # # | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100001100000000", -- |## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 066 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111100000000", -- | ####### | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0111111100000000", -- | ####### | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0110000110000000", -- | ## ## | 11 - "0111111100000000", -- | ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 067 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000100000000", -- | ## # | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000100000000", -- | ## # | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 068 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111000000000", -- | ###### | 03 - "0110001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0110001100000000", -- | ## ## | 11 - "0111111000000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 069 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111100000000", -- | ####### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111111000000000", -- | ###### | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111100000000", -- | ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 070 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111100000000", -- | ####### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111111000000000", -- | ###### | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 071 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001111100000000", -- | ##### | 03 - "0011000110000000", -- | ## ## | 04 - "0110000010000000", -- | ## # | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110011110000000", -- | ## #### | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011000110000000", -- | ## ## | 11 - "0001111010000000", -- | #### # | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 072 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000110000000", -- | ## ## | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0111111110000000", -- | ######## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0110000110000000", -- | ## ## | 11 - "0110000110000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 073 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 074 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000110000000000", -- | ## | 03 - "0000110000000000", -- | ## | 04 - "0000110000000000", -- | ## | 05 - "0000110000000000", -- | ## | 06 - "0000110000000000", -- | ## | 07 - "0000110000000000", -- | ## | 08 - "0000110000000000", -- | ## | 09 - "1100110000000000", -- |## ## | 10 - "1100110000000000", -- |## ## | 11 - "0111100000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 075 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110001100000000", -- | ## ## | 03 - "0110011000000000", -- | ## ## | 04 - "0110110000000000", -- | ## ## | 05 - "0111100000000000", -- | #### | 06 - "0111000000000000", -- | ### | 07 - "0111100000000000", -- | #### | 08 - "0110110000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110001100000000", -- | ## ## | 11 - "0110000110000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 076 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111100000000", -- | ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 077 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000001100000", -- | ## ## | 03 - "0110000001100000", -- | ## ## | 04 - "0111000011100000", -- | ### ### | 05 - "0111000011100000", -- | ### ### | 06 - "0111100111100000", -- | #### #### | 07 - "0111100111100000", -- | #### #### | 08 - "0110111101100000", -- | ## #### ## | 09 - "0110111101100000", -- | ## #### ## | 10 - "0110011001100000", -- | ## ## ## | 11 - "0110011001100000", -- | ## ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 078 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000110000000", -- | ## ## | 03 - "0111000110000000", -- | ### ## | 04 - "0111100110000000", -- | #### ## | 05 - "0111100110000000", -- | #### ## | 06 - "0110110110000000", -- | ## ## ## | 07 - "0110110110000000", -- | ## ## ## | 08 - "0110011110000000", -- | ## #### | 09 - "0110011110000000", -- | ## #### | 10 - "0110001110000000", -- | ## ### | 11 - "0110000110000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 079 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 080 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111100000000", -- | ####### | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0111111100000000", -- | ####### | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 081 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110011110000000", -- | ## #### | 10 - "0011001100000000", -- | ## ## | 11 - "0001111110000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 082 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111100000000", -- | ####### | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0111111100000000", -- | ####### | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0110000110000000", -- | ## ## | 11 - "0110000011000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 083 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011111000000000", -- | ##### | 03 - "0110001100000000", -- | ## ## | 04 - "0110001100000000", -- | ## ## | 05 - "0110000000000000", -- | ## | 06 - "0011100000000000", -- | ### | 07 - "0000111000000000", -- | ### | 08 - "0000001100000000", -- | ## | 09 - "0110001100000000", -- | ## ## | 10 - "0110001100000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 084 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1111111100000000", -- |######## | 03 - "0001100000000000", -- | ## | 04 - "0001100000000000", -- | ## | 05 - "0001100000000000", -- | ## | 06 - "0001100000000000", -- | ## | 07 - "0001100000000000", -- | ## | 08 - "0001100000000000", -- | ## | 09 - "0001100000000000", -- | ## | 10 - "0001100000000000", -- | ## | 11 - "0001100000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 085 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000110000000", -- | ## ## | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 086 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100001100000000", -- |## ## | 03 - "1100001100000000", -- |## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0010010000000000", -- | # # | 08 - "0011110000000000", -- | #### | 09 - "0011110000000000", -- | #### | 10 - "0001100000000000", -- | ## | 11 - "0001100000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 087 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100001100001100", -- |## ## ## | 03 - "1100001100001100", -- |## ## ## | 04 - "1100001100001100", -- |## ## ## | 05 - "0110011110011000", -- | ## #### ## | 06 - "0110011110011000", -- | ## #### ## | 07 - "0011010010110000", -- | ## # # ## | 08 - "0011110011110000", -- | #### #### | 09 - "0001100001100000", -- | ## ## | 10 - "0001100001100000", -- | ## ## | 11 - "0001100001100000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 088 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100000110000000", -- |## ## | 03 - "1100000110000000", -- |## ## | 04 - "0110001100000000", -- | ## ## | 05 - "0011011000000000", -- | ## ## | 06 - "0001110000000000", -- | ### | 07 - "0001110000000000", -- | ### | 08 - "0011011000000000", -- | ## ## | 09 - "0110001100000000", -- | ## ## | 10 - "1100000110000000", -- |## ## | 11 - "1100000110000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 089 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100000011000000", -- |## ## | 03 - "1100000011000000", -- |## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0011001100000000", -- | ## ## | 06 - "0001111000000000", -- | #### | 07 - "0000110000000000", -- | ## | 08 - "0000110000000000", -- | ## | 09 - "0000110000000000", -- | ## | 10 - "0000110000000000", -- | ## | 11 - "0000110000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 090 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1111111110000000", -- |######### | 03 - "0000000110000000", -- | ## | 04 - "0000001100000000", -- | ## | 05 - "0000011000000000", -- | ## | 06 - "0000110000000000", -- | ## | 07 - "0001100000000000", -- | ## | 08 - "0011000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "1100000000000000", -- |## | 11 - "1111111110000000", -- |######### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 091 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111000000000000", -- | ### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0111000000000000", -- | ### | 15 - -- ASCII 092 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100000000000000", -- |## | 03 - "1100000000000000", -- |## | 04 - "1100000000000000", -- |## | 05 - "1100000000000000", -- |## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0011000000000000", -- | ## | 11 - "0011000000000000", -- | ## | 12 - "0011000000000000", -- | ## | 13 - "0011000000000000", -- | ## | 14 - "0000000000000000", -- | | 15 - -- ASCII 093 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1110000000000000", -- |### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "1110000000000000", -- |### | 15 - -- ASCII 094 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0010000000000000", -- | # | 03 - "0111000000000000", -- | ### | 04 - "1101100000000000", -- |## ## | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 095 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "1111111100000000", -- |######## | 15 - -- ASCII 096 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0111000000000000", -- | ### | 02 - "0011000000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 097 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0001111000000000", -- | #### | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 098 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0111110000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0111110000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 099 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 100 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000011000000000", -- | ## | 03 - "0000011000000000", -- | ## | 04 - "0000011000000000", -- | ## | 05 - "0011111000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 101 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0111111000000000", -- | ###### | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 102 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "1111000000000000", -- |#### | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 103 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011111000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000011000000000", -- | ## | 13 - "0110011000000000", -- | ## ## | 14 - "0011110000000000", -- | #### | 15 - -- ASCII 104 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0111110000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0110011000000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 105 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 106 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "1100000000000000", -- |## | 15 - -- ASCII 107 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110110000000000", -- | ## ## | 07 - "0111100000000000", -- | #### | 08 - "0111000000000000", -- | ### | 09 - "0111100000000000", -- | #### | 10 - "0110110000000000", -- | ## ## | 11 - "0110011000000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 108 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 109 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0111111111000000", -- | ######### | 06 - "0110011001100000", -- | ## ## ## | 07 - "0110011001100000", -- | ## ## ## | 08 - "0110011001100000", -- | ## ## ## | 09 - "0110011001100000", -- | ## ## ## | 10 - "0110011001100000", -- | ## ## ## | 11 - "0110011001100000", -- | ## ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 110 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0111110000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0110011000000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 111 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 112 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0111110000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0111110000000000", -- | ##### | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 113 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011111000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000011000000000", -- | ## | 13 - "0000011000000000", -- | ## | 14 - "0000011000000000", -- | ## | 15 - -- ASCII 114 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0111100000000000", -- | #### | 06 - "0111000000000000", -- | ### | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 115 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110000000000000", -- | ## | 08 - "0011110000000000", -- | #### | 09 - "0000011000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 116 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "1111000000000000", -- |#### | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0011000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 117 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 118 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "1100001100000000", -- |## ## | 06 - "1100001100000000", -- |## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0011110000000000", -- | #### | 10 - "0001100000000000", -- | ## | 11 - "0001100000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 119 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "1100000011000000", -- |## ## | 06 - "1100110011000000", -- |## ## ## | 07 - "0110110110000000", -- | ## ## ## | 08 - "0110110110000000", -- | ## ## ## | 09 - "0111111110000000", -- | ######## | 10 - "0011001100000000", -- | ## ## | 11 - "0011001100000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 120 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "1100001100000000", -- |## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0011110000000000", -- | #### | 08 - "0001100000000000", -- | ## | 09 - "0011110000000000", -- | #### | 10 - "0110011000000000", -- | ## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 121 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "1100001100000000", -- |## ## | 06 - "1100001100000000", -- |## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0011110000000000", -- | #### | 10 - "0011110000000000", -- | #### | 11 - "0001100000000000", -- | ## | 12 - "0001100000000000", -- | ## | 13 - "0011000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 122 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0111111000000000", -- | ###### | 06 - "0000011000000000", -- | ## | 07 - "0000110000000000", -- | ## | 08 - "0001100000000000", -- | ## | 09 - "0011000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111000000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 123 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0011000000000000", -- | ## | 05 - "0011000000000000", -- | ## | 06 - "0011000000000000", -- | ## | 07 - "0011000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0011000000000000", -- | ## | 10 - "0011000000000000", -- | ## | 11 - "0011000000000000", -- | ## | 12 - "0011000000000000", -- | ## | 13 - "0011000000000000", -- | ## | 14 - "0001100000000000", -- | ## | 15 - -- ASCII 124 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 125 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100000000000000", -- |## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0011000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "1100000000000000", -- |## | 15 - -- ASCII 126 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1110100000000000", -- |### # | 03 - "1011100000000000", -- |# ### | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 127 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 128 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 129 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 130 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 131 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 132 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 133 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 134 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 135 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 136 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 137 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 138 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 139 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 140 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 141 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 142 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 143 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 144 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 145 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0011000000000000", -- | ## | 02 - "0110000000000000", -- | ## | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 146 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0110000000000000", -- | ## | 02 - "1100000000000000", -- |## | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 147 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 148 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 149 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 150 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 151 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 152 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 153 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 154 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 155 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 156 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 157 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 158 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 159 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 160 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 161 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 162 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000110000000000", -- | ## | 05 - "0011110000000000", -- | #### | 06 - "0110111000000000", -- | ## ### | 07 - "0110100000000000", -- | ## # | 08 - "0110100000000000", -- | ## # | 09 - "0111000000000000", -- | ### | 10 - "0111011000000000", -- | ### ## | 11 - "0011110000000000", -- | #### | 12 - "0011000000000000", -- | ## | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 163 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011100000000000", -- | ### | 03 - "0110110000000000", -- | ## ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0011000000000000", -- | ## | 07 - "0111100000000000", -- | #### | 08 - "0011000000000000", -- | ## | 09 - "0011000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0111110000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 164 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110011000000000", -- | ## ## | 03 - "0011110000000000", -- | #### | 04 - "0010010000000000", -- | # # | 05 - "0010010000000000", -- | # # | 06 - "0011110000000000", -- | #### | 07 - "0110011000000000", -- | ## ## | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 165 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100001100000000", -- |## ## | 03 - "1100001100000000", -- |## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "1111111100000000", -- |######## | 07 - "0001100000000000", -- | ## | 08 - "1111111100000000", -- |######## | 09 - "0001100000000000", -- | ## | 10 - "0001100000000000", -- | ## | 11 - "0001100000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 166 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0000000000000000", -- | | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 167 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0011100000000000", -- | ### | 05 - "0011100000000000", -- | ### | 06 - "0110110000000000", -- | ## ## | 07 - "0011011000000000", -- | ## ## | 08 - "0001110000000000", -- | ### | 09 - "0001110000000000", -- | ### | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 168 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1101100000000000", -- |## ## | 03 - "1101100000000000", -- |## ## | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 169 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011111100000000", -- | ###### | 03 - "0110000110000000", -- | ## ## | 04 - "1100110011000000", -- |## ## ## | 05 - "1101001011000000", -- |## # # ## | 06 - "1101000011000000", -- |## # ## | 07 - "1101000011000000", -- |## # ## | 08 - "1101001011000000", -- |## # # ## | 09 - "1100110011000000", -- |## ## ## | 10 - "0110000110000000", -- | ## ## | 11 - "0011111100000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 170 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0010000000000000", -- | # | 03 - "0001000000000000", -- | # | 04 - "0011000000000000", -- | ## | 05 - "0101000000000000", -- | # # | 06 - "0011000000000000", -- | ## | 07 - "0000000000000000", -- | | 08 - "0111000000000000", -- | ### | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 171 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0011011000000000", -- | ## ## | 07 - "0110110000000000", -- | ## ## | 08 - "1101100000000000", -- |## ## | 09 - "0110110000000000", -- | ## ## | 10 - "0011011000000000", -- | ## ## | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 172 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0111111000000000", -- | ###### | 07 - "0000011000000000", -- | ## | 08 - "0000011000000000", -- | ## | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 173 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "1111000000000000", -- |#### | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 174 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011111100000000", -- | ###### | 03 - "0110000110000000", -- | ## ## | 04 - "1101110011000000", -- |## ### ## | 05 - "1101001011000000", -- |## # # ## | 06 - "1101001011000000", -- |## # # ## | 07 - "1101110011000000", -- |## ### ## | 08 - "1101010011000000", -- |## # # ## | 09 - "1101001011000000", -- |## # # ## | 10 - "0110000110000000", -- | ## ## | 11 - "0011111100000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 175 --------------- - "0000000000000000", -- | | 00 - "1111111100000000", -- |######## | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 176 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111000000000000", -- | ### | 03 - "0101000000000000", -- | # # | 04 - "0101000000000000", -- | # # | 05 - "0111000000000000", -- | ### | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 177 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0001100000000000", -- | ## | 06 - "0001100000000000", -- | ## | 07 - "0111111000000000", -- | ###### | 08 - "0001100000000000", -- | ## | 09 - "0001100000000000", -- | ## | 10 - "0000000000000000", -- | | 11 - "0111111000000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 178 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "1011000000000000", -- |# ## | 04 - "0011000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "1111000000000000", -- |#### | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 179 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "1011000000000000", -- |# ## | 04 - "0110000000000000", -- | ## | 05 - "1011000000000000", -- |# ## | 06 - "0110000000000000", -- | ## | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 180 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0011100000000000", -- | ### | 02 - "0011000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 181 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0111111100000000", -- | ####### | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 182 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0111110000000000", -- | ##### | 04 - "0111110000000000", -- | ##### | 05 - "0111110000000000", -- | ##### | 06 - "0111110000000000", -- | ##### | 07 - "0011110000000000", -- | #### | 08 - "0000110000000000", -- | ## | 09 - "0000110000000000", -- | ## | 10 - "0000110000000000", -- | ## | 11 - "0000110000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 183 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 184 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0011000000000000", -- | ## | 13 - "0001100000000000", -- | ## | 14 - "0111000000000000", -- | ### | 15 - -- ASCII 185 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "1110000000000000", -- |### | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 186 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111000000000000", -- | ### | 03 - "0101000000000000", -- | # # | 04 - "0101000000000000", -- | # # | 05 - "0101000000000000", -- | # # | 06 - "0111000000000000", -- | ### | 07 - "0000000000000000", -- | | 08 - "0111000000000000", -- | ### | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 187 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "1101100000000000", -- |## ## | 07 - "0110110000000000", -- | ## ## | 08 - "0011011000000000", -- | ## ## | 09 - "0110110000000000", -- | ## ## | 10 - "1101100000000000", -- |## ## | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 188 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000001100000", -- | ## ## | 03 - "0111000011000000", -- | ### ## | 04 - "0011000110000000", -- | ## ## | 05 - "0011001100000000", -- | ## ## | 06 - "0011011000000000", -- | ## ## | 07 - "0000110011000000", -- | ## ## | 08 - "0001100111000000", -- | ## ### | 09 - "0011001101000000", -- | ## ## # | 10 - "0110001111000000", -- | ## #### | 11 - "1100000011000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 189 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000001100000", -- | ## ## | 03 - "0111000011000000", -- | ### ## | 04 - "0011000110000000", -- | ## ## | 05 - "0011001100000000", -- | ## ## | 06 - "0011011000000000", -- | ## ## | 07 - "0000110110000000", -- | ## ## | 08 - "0001101011000000", -- | ## # ## | 09 - "0011000011000000", -- | ## ## | 10 - "0110000110000000", -- | ## ## | 11 - "1100001111000000", -- |## #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 190 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000001100000", -- | ## ## | 03 - "0101100011000000", -- | # ## ## | 04 - "0011000110000000", -- | ## ## | 05 - "0101101100000000", -- | # ## ## | 06 - "0011011000000000", -- | ## ## | 07 - "0000110011000000", -- | ## ## | 08 - "0001100111000000", -- | ## ### | 09 - "0011001101000000", -- | ## ## # | 10 - "0110001111000000", -- | ## #### | 11 - "1100000011000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 191 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0001100000000000", -- | ## | 06 - "0001100000000000", -- | ## | 07 - "0011000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 192 --------------- - "0011100000000000", -- | ### | 00 - "0001100000000000", -- | ## | 01 - "0000110000000000", -- | ## | 02 - "0001100000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0011110000000000", -- | #### | 05 - "0011110000000000", -- | #### | 06 - "0010010000000000", -- | # # | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100001100000000", -- |## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 193 --------------- - "0001110000000000", -- | ### | 00 - "0001100000000000", -- | ## | 01 - "0011000000000000", -- | ## | 02 - "0001100000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0011110000000000", -- | #### | 05 - "0011110000000000", -- | #### | 06 - "0010010000000000", -- | # # | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100001100000000", -- |## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 194 --------------- - "0001100000000000", -- | ## | 00 - "0011110000000000", -- | #### | 01 - "0110011000000000", -- | ## ## | 02 - "0001100000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0011110000000000", -- | #### | 05 - "0011110000000000", -- | #### | 06 - "0010010000000000", -- | # # | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100001100000000", -- |## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 195 --------------- - "0111101000000000", -- | #### # | 00 - "0101111000000000", -- | # #### | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0011110000000000", -- | #### | 05 - "0011110000000000", -- | #### | 06 - "0010010000000000", -- | # # | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100001100000000", -- |## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 196 --------------- - "0110011000000000", -- | ## ## | 00 - "0110011000000000", -- | ## ## | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0001100000000000", -- | ## | 04 - "0011110000000000", -- | #### | 05 - "0011110000000000", -- | #### | 06 - "0010010000000000", -- | # # | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100001100000000", -- |## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 197 --------------- - "0001100000000000", -- | ## | 00 - "0011110000000000", -- | #### | 01 - "0001100000000000", -- | ## | 02 - "0000000000000000", -- | | 03 - "0001100000000000", -- | ## | 04 - "0001100000000000", -- | ## | 05 - "0011110000000000", -- | #### | 06 - "0010010000000000", -- | # # | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100001100000000", -- |## ## | 11 - "1100001100000000", -- |## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 198 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001111111110000", -- | ######### | 03 - "0001111000000000", -- | #### | 04 - "0011011000000000", -- | ## ## | 05 - "0011011000000000", -- | ## ## | 06 - "0011011111100000", -- | ## ###### | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "1100011000000000", -- |## ## | 11 - "1100011111110000", -- |## ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 199 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000100000000", -- | ## # | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000100000000", -- | ## # | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000110000000000", -- | ## | 13 - "0000011000000000", -- | ## | 14 - "0001110000000000", -- | ### | 15 - -- ASCII 200 --------------- - "0001110000000000", -- | ### | 00 - "0000110000000000", -- | ## | 01 - "0000011000000000", -- | ## | 02 - "0111111100000000", -- | ####### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111111000000000", -- | ###### | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111100000000", -- | ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 201 --------------- - "0000111000000000", -- | ### | 00 - "0000110000000000", -- | ## | 01 - "0001100000000000", -- | ## | 02 - "0111111100000000", -- | ####### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111111000000000", -- | ###### | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111100000000", -- | ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 202 --------------- - "0000110000000000", -- | ## | 00 - "0001111000000000", -- | #### | 01 - "0011001100000000", -- | ## ## | 02 - "0111111100000000", -- | ####### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111111000000000", -- | ###### | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111100000000", -- | ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 203 --------------- - "0011001100000000", -- | ## ## | 00 - "0011001100000000", -- | ## ## | 01 - "0000000000000000", -- | | 02 - "0111111100000000", -- | ####### | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0111111000000000", -- | ###### | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111100000000", -- | ####### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 204 --------------- - "1100000000000000", -- |## | 00 - "0110000000000000", -- | ## | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 205 --------------- - "0011000000000000", -- | ## | 00 - "0110000000000000", -- | ## | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 206 --------------- - "0110000000000000", -- | ## | 00 - "1001000000000000", -- |# # | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 207 --------------- - "1001000000000000", -- |# # | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 208 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111111000000000", -- | ###### | 03 - "0110001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "1111100110000000", -- |##### ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0110001100000000", -- | ## ## | 11 - "0111111000000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 209 --------------- - "0011110100000000", -- | #### # | 00 - "0010111100000000", -- | # #### | 01 - "0000000000000000", -- | | 02 - "0110000110000000", -- | ## ## | 03 - "0111000110000000", -- | ### ## | 04 - "0111100110000000", -- | #### ## | 05 - "0111100110000000", -- | #### ## | 06 - "0110110110000000", -- | ## ## ## | 07 - "0110110110000000", -- | ## ## ## | 08 - "0110011110000000", -- | ## #### | 09 - "0110011110000000", -- | ## #### | 10 - "0110001110000000", -- | ## ### | 11 - "0110000110000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 210 --------------- - "0001110000000000", -- | ### | 00 - "0000110000000000", -- | ## | 01 - "0000011000000000", -- | ## | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 211 --------------- - "0000111000000000", -- | ### | 00 - "0000110000000000", -- | ## | 01 - "0001100000000000", -- | ## | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 212 --------------- - "0000110000000000", -- | ## | 00 - "0001111000000000", -- | #### | 01 - "0011001100000000", -- | ## ## | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 213 --------------- - "0011110100000000", -- | #### # | 00 - "0010111100000000", -- | # #### | 01 - "0000000000000000", -- | | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 214 --------------- - "0011001100000000", -- | ## ## | 00 - "0011001100000000", -- | ## ## | 01 - "0000000000000000", -- | | 02 - "0001111000000000", -- | #### | 03 - "0011001100000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 215 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0110011000000000", -- | ## ## | 07 - "0011110000000000", -- | #### | 08 - "0001100000000000", -- | ## | 09 - "0011110000000000", -- | #### | 10 - "0110011000000000", -- | ## ## | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 216 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001111110000000", -- | ###### | 03 - "0011001100000000", -- | ## ## | 04 - "0110001110000000", -- | ## ### | 05 - "0110011110000000", -- | ## #### | 06 - "0110110110000000", -- | ## ## ## | 07 - "0110110110000000", -- | ## ## ## | 08 - "0111100110000000", -- | #### ## | 09 - "0111000110000000", -- | ### ## | 10 - "0011001100000000", -- | ## ## | 11 - "0111111000000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 217 --------------- - "0001110000000000", -- | ### | 00 - "0000110000000000", -- | ## | 01 - "0000011000000000", -- | ## | 02 - "0110000110000000", -- | ## ## | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 218 --------------- - "0000111000000000", -- | ### | 00 - "0000110000000000", -- | ## | 01 - "0001100000000000", -- | ## | 02 - "0110000110000000", -- | ## ## | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 219 --------------- - "0000110000000000", -- | ## | 00 - "0001111000000000", -- | #### | 01 - "0011001100000000", -- | ## ## | 02 - "0000000000000000", -- | | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 220 --------------- - "0011001100000000", -- | ## ## | 00 - "0011001100000000", -- | ## ## | 01 - "0000000000000000", -- | | 02 - "0110000110000000", -- | ## ## | 03 - "0110000110000000", -- | ## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0110000110000000", -- | ## ## | 06 - "0110000110000000", -- | ## ## | 07 - "0110000110000000", -- | ## ## | 08 - "0110000110000000", -- | ## ## | 09 - "0110000110000000", -- | ## ## | 10 - "0011001100000000", -- | ## ## | 11 - "0001111000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 221 --------------- - "0000111000000000", -- | ### | 00 - "0000110000000000", -- | ## | 01 - "0001100000000000", -- | ## | 02 - "1100000011000000", -- |## ## | 03 - "1100000011000000", -- |## ## | 04 - "0110000110000000", -- | ## ## | 05 - "0011001100000000", -- | ## ## | 06 - "0001111000000000", -- | #### | 07 - "0000110000000000", -- | ## | 08 - "0000110000000000", -- | ## | 09 - "0000110000000000", -- | ## | 10 - "0000110000000000", -- | ## | 11 - "0000110000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 222 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0111111000000000", -- | ###### | 05 - "0110001100000000", -- | ## ## | 06 - "0110001100000000", -- | ## ## | 07 - "0110001100000000", -- | ## ## | 08 - "0110001100000000", -- | ## ## | 09 - "0111111000000000", -- | ###### | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 223 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110110000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0110110000000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 224 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0011100000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0000110000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0001111000000000", -- | #### | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 225 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001110000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0001111000000000", -- | #### | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 226 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001100000000000", -- | ## | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0001111000000000", -- | #### | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 227 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111101000000000", -- | #### # | 03 - "0101111000000000", -- | # #### | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0001111000000000", -- | #### | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 228 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110011000000000", -- | ## ## | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0001111000000000", -- | #### | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 229 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001100000000000", -- | ## | 02 - "0011110000000000", -- | #### | 03 - "0001100000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0001111000000000", -- | #### | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 230 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011111111000000", -- | ######## | 06 - "0110011001100000", -- | ## ## ## | 07 - "0001111111100000", -- | ######## | 08 - "0011011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011001100000", -- | ## ## ## | 11 - "0011111111000000", -- | ######## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 231 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0001100000000000", -- | ## | 13 - "0000110000000000", -- | ## | 14 - "0011100000000000", -- | ### | 15 - -- ASCII 232 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0011100000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0000110000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0111111000000000", -- | ###### | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 233 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001110000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0111111000000000", -- | ###### | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 234 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001100000000000", -- | ## | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0111111000000000", -- | ###### | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 235 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110011000000000", -- | ## ## | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0111111000000000", -- | ###### | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 236 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "1110000000000000", -- |### | 02 - "0110000000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 237 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0111000000000000", -- | ### | 02 - "0110000000000000", -- | ## | 03 - "1100000000000000", -- |## | 04 - "0000000000000000", -- | | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 238 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0110000000000000", -- | ## | 02 - "1111000000000000", -- |#### | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 239 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1001000000000000", -- |# # | 03 - "1001000000000000", -- |# # | 04 - "0000000000000000", -- | | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 240 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111011000000000", -- | ### ## | 03 - "0001100000000000", -- | ## | 04 - "0110110000000000", -- | ## ## | 05 - "0000110000000000", -- | ## | 06 - "0011111000000000", -- | ##### | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 241 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111101000000000", -- | #### # | 03 - "0101111000000000", -- | # #### | 04 - "0000000000000000", -- | | 05 - "0111110000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0110011000000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 242 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0011100000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0000110000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 243 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001110000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 244 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001100000000000", -- | ## | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 245 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111101000000000", -- | #### # | 03 - "0101111000000000", -- | # #### | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 246 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110011000000000", -- | ## ## | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0011110000000000", -- | #### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 247 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0011000000000000", -- | ## | 05 - "0011000000000000", -- | ## | 06 - "0000000000000000", -- | | 07 - "0111100000000000", -- | #### | 08 - "0000000000000000", -- | | 09 - "0011000000000000", -- | ## | 10 - "0011000000000000", -- | ## | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 248 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0011111000000000", -- | ##### | 06 - "0110111000000000", -- | ## ### | 07 - "0110111000000000", -- | ## ### | 08 - "0110011000000000", -- | ## ## | 09 - "0111011000000000", -- | ### ## | 10 - "0111011000000000", -- | ### ## | 11 - "0111110000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 249 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0011100000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0000110000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 250 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001110000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 251 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001100000000000", -- | ## | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 252 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110011000000000", -- | ## ## | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011111000000000", -- | ##### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 253 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0001110000000000", -- | ### | 02 - "0001100000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0000000000000000", -- | | 05 - "1100001100000000", -- |## ## | 06 - "1100001100000000", -- |## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0011110000000000", -- | #### | 10 - "0011110000000000", -- | #### | 11 - "0001100000000000", -- | ## | 12 - "0001100000000000", -- | ## | 13 - "0011000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 254 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0111110000000000", -- | ##### | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0111110000000000", -- | ##### | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 255 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110011000000000", -- | ## ## | 03 - "0110011000000000", -- | ## ## | 04 - "0000000000000000", -- | | 05 - "1100001100000000", -- |## ## | 06 - "1100001100000000", -- |## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0011110000000000", -- | #### | 10 - "0011110000000000", -- | #### | 11 - "0001100000000000", -- | ## | 12 - "0001100000000000", -- | ## | 13 - "0011000000000000", -- | ## | 14 - "0110000000000000", -- | ## | 15 - -- ASCII 256 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 257 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 258 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 259 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 260 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 261 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 262 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 263 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 264 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 265 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 266 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 267 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 268 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 269 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 270 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 271 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 272 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 273 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 274 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 275 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 276 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 277 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 278 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 279 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 280 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 281 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 282 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 283 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 284 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 285 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 286 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 287 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000" -- | | 15 - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd b/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd deleted file mode 100644 index f5bbcc5..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"00",x"00",x"01",x"03",x"07",x"0F",x"0F",x"0F", -- 0x0000 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0008 - x"00",x"00",x"E0",x"F0",x"F8",x"FC",x"FC",x"FC", -- 0x0010 - x"00",x"00",x"01",x"07",x"1F",x"3F",x"7F",x"7F", -- 0x0018 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0020 - x"00",x"00",x"E0",x"F0",x"F8",x"F8",x"F8",x"F8", -- 0x0028 - x"00",x"00",x"07",x"1F",x"7F",x"FF",x"FF",x"FF", -- 0x0030 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"8F", -- 0x0038 - x"00",x"00",x"C3",x"E3",x"F1",x"F1",x"F1",x"F1", -- 0x0040 - x"00",x"00",x"F8",x"FC",x"FE",x"FE",x"FE",x"FE", -- 0x0048 - x"00",x"00",x"1F",x"1F",x"0F",x"0F",x"0F",x"0F", -- 0x0050 - x"00",x"00",x"81",x"C3",x"E2",x"E2",x"E2",x"E2", -- 0x0058 - x"00",x"00",x"FC",x"06",x"FA",x"72",x"DA",x"FA", -- 0x0060 - x"00",x"00",x"03",x"0F",x"3F",x"7F",x"7F",x"7F", -- 0x0068 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"C7", -- 0x0070 - x"00",x"00",x"E0",x"F0",x"F8",x"F8",x"F8",x"F8", -- 0x0078 - x"00",x"00",x"07",x"1F",x"7F",x"FF",x"FF",x"FF", -- 0x0080 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0088 - x"00",x"00",x"80",x"C0",x"C0",x"E0",x"E0",x"F0", -- 0x0090 - x"00",x"00",x"3F",x"3F",x"06",x"06",x"06",x"06", -- 0x0098 - x"00",x"00",x"D8",x"D8",x"18",x"1F",x"1F",x"18", -- 0x00A0 - x"00",x"00",x"DF",x"DF",x"D8",x"DE",x"DE",x"D8", -- 0x00A8 - x"00",x"00",x"80",x"80",x"00",x"00",x"00",x"00", -- 0x00B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"3F", -- 0x0100 - x"C1",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"80", -- 0x0108 - x"FC",x"F8",x"F0",x"00",x"00",x"00",x"00",x"00", -- 0x0110 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0118 - x"FF",x"C3",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0120 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0128 - x"FF",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0130 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0138 - x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0140 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0148 - x"0F",x"0F",x"0F",x"8F",x"8F",x"8F",x"DF",x"FF", -- 0x0150 - x"E3",x"E3",x"E1",x"E0",x"E1",x"E1",x"E1",x"E3", -- 0x0158 - x"56",x"8E",x"FC",x"00",x"FF",x"FE",x"FE",x"FC", -- 0x0160 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0168 - x"83",x"03",x"03",x"0F",x"3F",x"FF",x"FF",x"FC", -- 0x0170 - x"F8",x"F8",x"F8",x"F8",x"F0",x"C0",x"00",x"00", -- 0x0178 - x"FF",x"FF",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0180 - x"E7",x"87",x"07",x"07",x"07",x"00",x"00",x"FF", -- 0x0188 - x"F0",x"F0",x"F0",x"E0",x"80",x"00",x"00",x"80", -- 0x0190 - x"06",x"06",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0198 - x"18",x"18",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A0 - x"DF",x"DF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A8 - x"80",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F8 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"7F",x"7F", -- 0x0200 - x"80",x"80",x"80",x"83",x"87",x"87",x"07",x"06", -- 0x0208 - x"00",x"1C",x"7C",x"FC",x"FC",x"FC",x"F0",x"F0", -- 0x0210 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0218 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0220 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0228 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0230 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"0F", -- 0x0238 - x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0240 - x"FF",x"FF",x"FF",x"FF",x"FE",x"FC",x"FC",x"FC", -- 0x0248 - x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"7F",x"7F", -- 0x0250 - x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3", -- 0x0258 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0260 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0268 - x"F0",x"C0",x"03",x"07",x"07",x"07",x"03",x"01", -- 0x0270 - x"18",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0278 - x"FF",x"FF",x"FF",x"FC",x"E0",x"06",x"1E",x"FE", -- 0x0280 - x"FF",x"FF",x"FF",x"0F",x"07",x"07",x"07",x"07", -- 0x0288 - x"C0",x"C0",x"E0",x"E0",x"F0",x"F0",x"F0",x"F0", -- 0x0290 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0298 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8 - x"7F",x"7F",x"7F",x"7F",x"7F",x"3F",x"1F",x"0F", -- 0x0300 - x"00",x"00",x"00",x"80",x"FF",x"FF",x"FF",x"FF", -- 0x0308 - x"F0",x"78",x"7C",x"FC",x"FC",x"F8",x"F0",x"E0", -- 0x0310 - x"7F",x"7F",x"7F",x"7F",x"3F",x"1F",x"0F",x"07", -- 0x0318 - x"8F",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0320 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F0",x"E0",x"C0", -- 0x0328 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"3F", -- 0x0330 - x"1F",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0338 - x"F1",x"F1",x"F1",x"F1",x"E1",x"C1",x"81",x"03", -- 0x0340 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FE",x"FF", -- 0x0348 - x"7F",x"3F",x"3F",x"3F",x"3F",x"1F",x"1F",x"1F", -- 0x0350 - x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"C7", -- 0x0358 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"F8",x"F0", -- 0x0360 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0368 - x"01",x"03",x"07",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0370 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0378 - x"FE",x"FE",x"FE",x"FF",x"FF",x"7F",x"1F",x"07", -- 0x0380 - x"07",x"07",x"0F",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0388 - x"F0",x"F0",x"F0",x"F0",x"FF",x"EF",x"C3",x"83", -- 0x0390 - x"00",x"00",x"00",x"00",x"DB",x"DF",x"1F",x"1B", -- 0x0398 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0410 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0420 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0450 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0460 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0480 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0618 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0650 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0658 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0668 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0698 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/make_rom.bat b/lib/VGA_ctrl/src/fonts/make_rom.bat deleted file mode 100644 index 9cfa61b..0000000 --- a/lib/VGA_ctrl/src/fonts/make_rom.bat +++ /dev/null @@ -1,6 +0,0 @@ -@echo off - -bff2rom fixedsys_8x15.bff y >char_rom_fixedsys_8x15.vhd -bff2rom fixedsys_8x16.bff y >char_rom_fixedsys_8x16.vhd -bff2rom fixedsys_9x16.bff y >char_rom_fixedsys_9x16.vhd -bff2rom System_16x16.bff y >char_rom_system_16x16.vhd diff --git a/lib/VGA_ctrl/src/linefifo.vhd b/lib/VGA_ctrl/src/linefifo.vhd deleted file mode 100644 index 4336ede..0000000 --- a/lib/VGA_ctrl/src/linefifo.vhd +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity linefifo is - Generic - ( - depth : natural := 64; - almost_full_thresh : natural := 60; - almost_empty_thresh : natural := 4 - ); - Port - ( - rst : in STD_LOGIC; - clk_w : in STD_LOGIC; - clk_r : in STD_LOGIC; - we_w : in STD_LOGIC; - re_r : in STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC; - color_w : in color_t; - color_r : out color_t - ); -end linefifo; - -architecture Behavioral of linefifo is - - constant data_width : integer := 8; - constant addr_width : integer := NextExpBaseTwo(depth); - - signal buf_we_w : STD_LOGIC; - signal ptr_w : unsigned (ADDR_WIDTH-1 downto 0); - signal ptr_r : unsigned (ADDR_WIDTH-1 downto 0); - signal full : STD_LOGIC; - signal empty : STD_LOGIC; - signal almost_full : STD_LOGIC; - signal almost_empty : STD_LOGIC; - -begin - - buf_we_w <= we_w; - fifo_full <= full; - fifo_empty <= empty; - fifo_afull <= almost_full; - fifo_aempty <= almost_empty; - -gen_line: - for c in color_range_t generate - begin - inst_dpram: entity work.dpram - GENERIC MAP - ( - addr_width => addr_width, - data_width => data_width - ) - PORT MAP( - clka => clk_w, - clkb => clk_r, - en_a => '1', - en_b => '1', - we_a => buf_we_w, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => color_w(c), - dout_b => color_r(c) - ); - end generate; - - inst_fifo_ctrl: entity work.async_fifo_ctrl - GENERIC MAP - ( - addr_width => ADDR_WIDTH, - almost_full_thresh => almost_full_thresh, - almost_empty_thresh => almost_empty_thresh - ) - PORT MAP - ( - rst => rst, - clk_w => clk_w, - clk_r => clk_r, - we => we_w, - re => re_r, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => full, - fifo_empty => empty, - fifo_afull => almost_full, - fifo_aempty => almost_empty - - ); - -end Behavioral; - diff --git a/lib/VGA_ctrl/src/vga_backend.vhd b/lib/VGA_ctrl/src/vga_backend.vhd deleted file mode 100644 index 2994eec..0000000 --- a/lib/VGA_ctrl/src/vga_backend.vhd +++ /dev/null @@ -1,223 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_backend - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity vga_backend is - Generic - ( - sys_freq : integer := 100E6; - fifo_depth : integer := 2048; - fifo_almost_full_thresh : natural := 2000; - fifo_almost_empty_thresh : natural := 48; - tsvga : vga_timespec_t := ts_vga_800_600_72 - ); - Port - ( - -- System signals - sys_rst : in std_logic; - sys_clk : in std_logic; - vga_ready : out std_logic; - - -- Buffered channel (Graphics plane) - color_in : in color_t; - color_fifo_we : in std_logic; - color_fifo_full : out std_logic; - color_fifo_afull : out std_logic; - - -- Direct channel (Character plane) - direct_color_in : in color_t; - direct_draw_en : in std_logic; - - -- Status signals - stat_hsync : out std_logic; - stat_vsync : out std_logic; - stat_hready : out std_logic; - stat_vready : out std_logic; - stat_hscan : out std_logic; - stat_vscan : out std_logic; - stat_hpos : out natural range 0 to tsvga.ts_h.ncyc_scan-1; - stat_vpos : out natural range 0 to tsvga.ts_v.ncyc_scan-1; - - -- VGA domain signals - vga_clk_out : out std_logic; - vga_color_out : out color_t; - vga_blank_n : out std_logic; - vga_sync_n : out std_logic; - vga_hsync : out std_logic; - vga_vsync : out std_logic - ); -end vga_backend; - -architecture Behavioral of vga_backend is - - signal scan_enable : std_logic; - signal fifo_full : std_logic; - signal fifo_empty : std_logic; - signal fifo_almost_empty : std_logic; - signal fifo_almost_full : std_logic; - signal is_scan : std_logic; - signal is_hscan : std_logic; - signal is_vscan : std_logic; - signal hsync : std_logic; - signal vsync : std_logic; - signal hready : std_logic; - signal vready : std_logic; - signal color : color_t; - signal vga_clk : std_logic; - signal dcm_locked : std_logic; - signal rst : std_logic; - -begin - - vga_clk_out <= vga_clk; - vga_ready <= dcm_locked; - - inst_clkgen: entity work.clkgen - GENERIC MAP - ( - sys_freq => sys_freq, - tsvga => tsvga - ) - PORT MAP - ( - rst => sys_rst, - clk => sys_clk, - vga_clk => vga_clk, - dcm_locked => dcm_locked - ); - - inst_vga_timing: entity work.vga_timing - GENERIC MAP - ( - tsvga => tsvga - ) - PORT MAP - ( - sys_rst => sys_rst, - vga_clk => vga_clk, - vga_ce => dcm_locked, - sync_h => hsync, - sync_v => vsync, - scan_pos_h => stat_hpos, - scan_pos_v => stat_vpos, - is_scan_h => is_hscan, - is_scan_v => is_vscan, - scan_rdy_h => hready, - scan_rdy_v => vready - ); - - inst_linefifo: entity work.linefifo - GENERIC MAP - ( - depth => fifo_depth, - almost_full_thresh => fifo_almost_full_thresh, - almost_empty_thresh => fifo_almost_empty_thresh - ) - PORT MAP( - rst => sys_rst, - clk_w => sys_clk, - clk_r => vga_clk, - we_w => color_fifo_we, - re_r => is_scan, - color_w => color_in, - color_r => color, - fifo_full => fifo_full, - fifo_empty => fifo_empty, - fifo_afull => fifo_almost_full, - fifo_aempty => fifo_almost_empty - - ); - - --------------------------------------------------------------------------------------------- - rst <= not dcm_locked; - stat_hsync <= hsync; - stat_vsync <= vsync; - stat_hscan <= is_hscan; - stat_vscan <= is_vscan; - stat_hready <= hready; - stat_vready <= vready; - - vga_blank_n <= '1'; - vga_sync_n <= '0'; - is_scan <= is_hscan and is_vscan and scan_enable; - - color_fifo_full <= fifo_full; - color_fifo_afull <= fifo_almost_full; - - --------------------------------------------------------------------------------------------- - proc_vga_start: - process (rst, vga_clk) - begin - if rst = '1' then - scan_enable <= '0'; - elsif rising_edge(vga_clk) then - if vsync = '1' then - if fifo_empty = '0' then - scan_enable <= '1'; - else - scan_enable <= '0'; - end if; - end if; - end if; - end process; - - proc_vga_color_out: - process (rst, vga_clk) - variable do_scan : std_logic; - begin - if rst = '1' then - do_scan := '0'; - elsif rising_edge(vga_clk) then - vga_color_out <= (X"00", X"00", X"00"); - if do_scan = '1' then - if direct_draw_en = '1' then - vga_color_out <= direct_color_in; - else - vga_color_out <= color; - end if; - end if; - do_scan := is_scan; - end if; - end process; - - --------------------------------------------------------------------------------------------- - proc_vga_sync_out: - process (rst, vga_clk) - variable hsync_r : std_logic; - variable vsync_r : std_logic; - begin - if rst = '1' then - vga_hsync <= tsvga.ts_h.sync_polarity; - vga_vsync <= tsvga.ts_v.sync_polarity; - hsync_r := tsvga.ts_h.sync_polarity; - vsync_r := tsvga.ts_v.sync_polarity; - elsif rising_edge(vga_clk) then - vga_hsync <= hsync_r; - vga_vsync <= vsync_r; - hsync_r := hsync xor (not tsvga.ts_h.sync_polarity); - vsync_r := vsync xor (not tsvga.ts_v.sync_polarity); - end if; - end process; - -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_sync.vhd b/lib/VGA_ctrl/src/vga_sync.vhd deleted file mode 100644 index 56e4384..0000000 --- a/lib/VGA_ctrl/src/vga_sync.vhd +++ /dev/null @@ -1,127 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:15:39 10/21/05 --- Design Name: --- Module Name: fsm_scan - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity vga_sync is - Generic - ( - ts : scan_timespec_t := (4,2,1,3,'0') - ); - Port - ( - rst : in std_logic; - clk : in std_logic; - ce : in std_logic; - pos : out natural range 0 to ts.ncyc_scan-1; - sync : out std_logic; - is_scan : out std_logic; - rdy_scan : out std_logic - ); - end vga_sync; - -architecture Behavioral of vga_sync is - - type timing_state_t is (st_init, st_scan, st_front, st_sync, st_back); - - -- Counter - signal state, next_state : timing_state_t; - signal count_srst : std_logic; - signal count : natural range 0 to ts.ncyc_scan-1; - -begin - - pos <= count; - ---------------------------------------------------------------------------------------------- -counter: - process (clk) - begin - if rising_edge(clk) then - if ce = '1' then - if count_srst = '1' then - count <= 0; - else - count <= count + 1; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------------------------- -SYNC_TIMING: -process (state, count) - begin - count_srst <= '0'; - rdy_scan <= '0'; - is_scan <= '0'; - sync <= '0'; - - next_state <= state; --default is to stay in current state - - case (state) is - - when st_init => - count_srst <= '1'; - next_state <= st_front; - when st_front => - if count = ts.ncyc_porch_front - 1 then - count_srst <= '1'; - next_state <= st_sync; - end if; - when st_sync => - sync <= '1'; - if count = ts.ncyc_sync_pulse - 1 then - count_srst <= '1'; - next_state <= st_back; - end if; - when st_back => - if count = ts.ncyc_porch_back - 1 then - count_srst <= '1'; - next_state <= st_scan; - end if; - when st_scan => - is_scan <= '1'; - if count = ts.ncyc_scan - 1 then - count_srst <= '1'; - rdy_scan <= '1'; - next_state <= st_front; - end if; - when others => - next_state <= st_init; - - end case; - end process; - -SYNC_TIMING_NEXT: - process (rst, clk) - begin - if rst = '1' then - state <= st_init; - elsif rising_edge(clk) and ce = '1' then - state <= next_state; - end if; - end process; - ---------------------------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_timing.vhd b/lib/VGA_ctrl/src/vga_timing.vhd deleted file mode 100644 index c110652..0000000 --- a/lib/VGA_ctrl/src/vga_timing.vhd +++ /dev/null @@ -1,102 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_ctrl_core - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity vga_timing is - Generic - ( - tsvga : vga_timespec_t := ts_vga_800_600_72 - ); - Port - ( - sys_rst : in std_logic; - vga_clk : in std_logic; - vga_ce : in std_logic; - sync_h : out std_logic; - sync_v : out std_logic; - scan_pos_h : out natural range 0 to tsvga.ts_h.ncyc_scan-1; - scan_pos_v : out natural range 0 to tsvga.ts_v.ncyc_scan-1; - is_scan_h : out std_logic; - is_scan_v : out std_logic; - scan_rdy_h : out std_logic; - scan_rdy_v : out std_logic - ); -end vga_timing; - -architecture Behavioral of vga_timing is - - --------------------------------------------------------------------------------------------- - signal is_scan_h_i : std_logic; - signal is_scan_v_i : std_logic; - signal scan_rdy_h_i : std_logic; - signal scan_rdy_v_i : std_logic; - signal sync_h_i : std_logic; - signal sync_v_i : std_logic; - - --------------------------------------------------------------------------------------------- -begin - - is_scan_h <= is_scan_h_i; - is_scan_v <= is_scan_v_i; - scan_rdy_h <= scan_rdy_h_i; - scan_rdy_v <= scan_rdy_v_i; - sync_h <= sync_h_i; - sync_v <= sync_v_i; - - --------------------------------------------------------------------------------------------- - inst_vga_sync_h: entity work.vga_sync - GENERIC MAP - ( - ts => tsvga.ts_h - ) - PORT MAP - ( - rst => sys_rst, - clk => vga_clk, - ce => vga_ce, - pos => scan_pos_h, - sync => sync_h_i, - is_scan => is_scan_h_i, - rdy_scan => scan_rdy_h_i - ); - - inst_vga_sync_v: entity work.vga_sync - GENERIC MAP - ( - ts => tsvga.ts_v - ) - PORT MAP - ( - rst => sys_rst, - clk => vga_clk, - ce => scan_rdy_h_i, - pos => scan_pos_v, - sync => sync_v_i, - is_scan => is_scan_v_i, - rdy_scan => scan_rdy_v_i - ); - ---------------------------------------------------------------------------------------------- - -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_types.vhd b/lib/VGA_ctrl/src/vga_types.vhd deleted file mode 100644 index 44cecbd..0000000 --- a/lib/VGA_ctrl/src/vga_types.vhd +++ /dev/null @@ -1,213 +0,0 @@ --- Package File Template --- --- Purpose: This package defines supplemental types, subtypes, --- constants, and functions - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - -package vga_types is - - -- Constants - - -- Types - type color_range_t is (r, g, b); - type color_t is array (color_range_t) of unsigned(7 downto 0); - - type scan_timespec_t is - record - ncyc_scan : integer; - ncyc_porch_front : integer; - ncyc_sync_pulse : integer; - ncyc_porch_back : integer; - sync_polarity : std_logic; - end record; - - type vga_timespec_t is - record - f_pxl_clk : integer; - nfps : integer; - ts_h : scan_timespec_t; - ts_v : scan_timespec_t; - end record; - - ----------------------------------------------------------------------- - -- Common timimg specifications - ----------------------------------------------------------------------- - -- For test bench (not for H/W use) - constant ts_vga_testbench : vga_timespec_t := - ( - f_pxl_clk => 100E6, - nfps => 6, - ts_h => (8,5,2,3,'0'), - ts_v => (6,4,2,3,'0') - ); - - -- 640 x 480 @ 60 Hz (not recommended) - constant ts_vga_640_480_60 : vga_timespec_t := - ( - f_pxl_clk => 25175000, - nfps => 60, - ts_h => (640,16,96,48,'0'), - ts_v => (480,11,2,31,'0') - ); - - -- 640 x 480 @ 72 Hz (not recommended) - constant ts_vga_640_480_72 : vga_timespec_t := - ( - f_pxl_clk => 31500000, - nfps => 72, - ts_h => (640,24,40,128,'0'), - ts_v => (480,9,3,28,'0') - ); - - -- 800 x 600 @ 60 Hz (OK) - constant ts_vga_800_600_60 : vga_timespec_t := - ( - f_pxl_clk => 40000000, - nfps => 60, - ts_h => (800,40,128,88,'0'), - ts_v => (600,1,4,23,'0') - ); - - -- 800 x 600 @ 72 Hz (OK) - constant ts_vga_800_600_72 : vga_timespec_t := - ( - f_pxl_clk => 50000000, - nfps => 72, - ts_h => (800,56,120,64,'0'), - ts_v => (600,37,6,23,'0') - ); - - -- 1024 x 768 @ 60 Hz (Noisy) - constant ts_vga_1024_768_60 : vga_timespec_t := - ( - f_pxl_clk => 65000000, - nfps => 60, - ts_h => (1024,24,136,160,'0'), - ts_v => (768,3,6,29,'0') - ); - - -- 1024 x 768 @ 70 Hz (OK) - constant ts_vga_1024_768_70 : vga_timespec_t := - ( - f_pxl_clk => 75000000, - nfps => 70, - ts_h => (1024,24,136,144,'0'), - ts_v => (768,3,6,29,'0') - ); - - -- 1280 x 1024 @ 70 Hz (Noisy) - constant ts_vga_1280_1024_70 : vga_timespec_t := - ( - f_pxl_clk => 125000000, - nfps => 70, - ts_h => (1280,16,176,192,'0'), - ts_v => (1024,3,3,42,'0') - ); - - -- 1280 x 1024 @ 72 Hz (OK) - constant ts_vga_1280_1024_72 : vga_timespec_t := - ( - f_pxl_clk => 130000000, - nfps => 72, - ts_h => (1280,32,160,224,'0'), - ts_v => (1024,2,2,33,'0') - ); - - -- Functions - function NextPowerOfTwo(x : natural) return natural; - function NextExpBaseTwo(x : natural) return natural; - function GCD(a, b : natural) return natural; - function LCM(a, b : natural) return natural; - function DCM_PERIOD(f_sys_hz : natural) return real; - function DCM_FREQ_M(f_sys_hz, f_vga_hz : natural) return natural; - function DCM_FREQ_D(f_sys_hz, f_vga_hz : natural) return natural; - -end vga_types; - - -package body vga_types is - - function NextExpBaseTwo(x : natural) return natural is - begin - return natural(ceil(log2(real(x)))); - end NextExpBaseTwo; - - function NextPowerOfTwo(x : natural) return natural is - begin - - return 2**NextExpBaseTwo(x); - end NextPowerOfTwo; - - function GCD(a, b : natural) return natural is - variable aa : natural; - variable bb : natural; - begin - aa := a; - bb := b; - while bb /= 0 loop - if aa > bb then - aa := aa - bb; - else - bb := bb - aa; - end if; - end loop; - - return aa; - - end GCD; - - function LCM(a, b : natural) return natural is - begin - - return (a * b)/GCD(a, b); - - end LCM; - - function DCM_FREQ_M(f_sys_hz, f_vga_hz : natural) return natural is - variable f_sys_mhz : natural; - variable f_vga_mhz : natural; - variable m : natural; - begin - f_sys_mhz := f_sys_hz/1E6; - f_vga_mhz := f_vga_hz/1E6; - m := f_vga_mhz/GCD(f_sys_mhz, f_vga_mhz); - - if m = 1 then - m := 2; - end if; - - return m; - - end DCM_FREQ_M; - - function DCM_FREQ_D(f_sys_hz, f_vga_hz : natural) return natural is - variable f_sys_mhz : natural; - variable f_vga_mhz : natural; - variable m : natural; - variable d : natural; - begin - m := DCM_FREQ_M(f_sys_hz, f_vga_hz); - f_sys_mhz := f_sys_hz/1E6; - f_vga_mhz := f_vga_hz/1E6; - d := m*f_sys_mhz/f_vga_mhz; - - return d; - - end DCM_FREQ_D; - - function DCM_PERIOD(f_sys_hz : natural) return real is - begin - - return 1.0E9/real(f_sys_hz); - - end DCM_PERIOD; - - -end vga_types; - - diff --git a/lib/filter/sim/eval_lowpass.m b/lib/filter/sim/eval_lowpass.m deleted file mode 100644 index ccac021..0000000 --- a/lib/filter/sim/eval_lowpass.m +++ /dev/null @@ -1,37 +0,0 @@ -function eval_filter(N) -omega_lp = 0.15 -omega_hp = 0.05 - -omega_bp_m = 0.02; -bw2_bp = 0.02; - -lp = lowpass(N, omega_lp, 1.0); -coef_lp = hann(N)'.*lp./sum(lp.^2); - -hp = lowpass(N, 0.5-omega_hp, 1.0).*cos(pi*(0:N-1)); -coef_hp = hp./sum(hp.^2).*hann(N)'; - -bp = lowpass(N, bw2_bp/2, 1.0).*cos(2*pi*omega_bp_m*(0:N-1)); -coef_bp = bp./sum(bp.^2).*hann(N)'; - -abs_lp = 20*log10(abs(fft(coef_lp))); -abs_hp = 20*log10(abs(fft(coef_hp))); -abs_bp = 20*log10(abs(fft(coef_bp))); - -close all; -plot((0:N/2)/N, abs_lp(1:N/2+1));grid; -figure -plot((0:N/2)/N, abs_hp(1:N/2+1));grid; -figure -plot((0:N/2)/N, abs_bp(1:N/2+1));grid; - -figure -plot((0:N-1), coef_lp);grid; -figure -plot((0:N-1), coef_hp);grid; -figure -plot((0:N-1), coef_bp);grid; - -mean_lp = mean(coef_lp-mean(coef_lp)) -mean_hp = mean(coef_hp) -mean_bp = mean(coef_bp) diff --git a/lib/filter/sim/lowpass.m b/lib/filter/sim/lowpass.m deleted file mode 100644 index 292964d..0000000 --- a/lib/filter/sim/lowpass.m +++ /dev/null @@ -1,20 +0,0 @@ -function coef = lowpass(N, omega, scale) - -phi = 0; -dphi = 2*omega; -if (mod(N, 2) == 0) - M = N/2; - for i=0:M-1, - phi = phi + dphi; - coef(M+i+1) = scale*sinc(phi); - coef(M-i-1+1) = coef(M+i+1); - end; -else - M = (N-1)/2; - for i=1:M, - phi = phi + dphi; - coef(M+i+1) = scale*sinc(phi); - coef(M-i+1) = coef(M+i+1); - end; - coef(M+1) = scale*Sinc(0.0); -end; diff --git a/lib/filter/sim/tb_fir_iterative.fdo b/lib/filter/sim/tb_fir_iterative.fdo deleted file mode 100644 index d4f35ff..0000000 --- a/lib/filter/sim/tb_fir_iterative.fdo +++ /dev/null @@ -1,16 +0,0 @@ -vlib work -vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/filter_pkg.vhd" -vcom -explicit -93 "../src/fir_stage_pkg.vhd" -vcom -explicit -93 "../src/fir_stage.vhd" -vcom -explicit -93 "../src/fir_iterative_pkg.vhd" -vcom -explicit -93 "../src/fir_iterative.vhd" -vcom -explicit -93 "../src/tb_fir_iterative.vhd" -vsim -t 1ps -lib work tb_fir_iterative -do {tb_fir_iterative.wdo} -view wave -view structure -view signals -run 20us diff --git a/lib/filter/sim/tb_fir_iterative.wdo b/lib/filter/sim/tb_fir_iterative.wdo deleted file mode 100644 index 1832c4e..0000000 --- a/lib/filter/sim/tb_fir_iterative.wdo +++ /dev/null @@ -1,86 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Literal /tb_fir_iterative/xi -add wave -noupdate -format Literal /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem -add wave -noupdate -divider {Xmem Dual} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Logic /tb_fir_iterative/y_valid -add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -divider {FIR Stage} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/in_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out_clr -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/p_valid -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/out_valid -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1892287 ps} 0} -configure wave -namecolwidth 140 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {1750644 ps} {2771198 ps} diff --git a/lib/filter/sim/tb_fir_parallel b/lib/filter/sim/tb_fir_parallel deleted file mode 100644 index f784c1a898ebf425293acc60146ab6ba80a1f4cd..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1354927 zcmeEv4PabFwf`nfOVB`rR4rJvV1f2Qu}H<%6b#ra1zTL8fhu5I`auinhiw7{8wjS0 z*=|>&CRikDN`pqNkMJk>@=B^piA}($L8=BU5H;!z2@*9tq6YH+{mz-Wdv~*G(k}!h z?cO^x_s-0jGv{-@?(NRpkEf-j1?*pXU{rvys;^{ZPRD)PJ;%wT>4AxXqXUxzrv=_0 z7=si(n_i4}@SBJX{EbFh27aUPn~(VXJ2Eo)J05ZV_zcPN!z~a%Uj8QEkCO3Y{y?@q zm$VNZn>iW3_M-xU<_`y?UOrF9YqRkFEIi|{9dZ5$7wh0}1u9yBy7`-kIDht8@DBw` z7gZk}STyO_O#aTqGyd%J%kUi0L4N>4-YI@(#VnJ`(Oe;|M5bsxxIIyHag>cS0Y ztzUE22Q?j_OWQBHG*7a#9fbL4{62=?r|{$76?zMtjC;_8KZ^V1_+4h=AICk%gx`(( z`|vvkzYm$TOU#|OOMT%J5oV8`YSPZZeGYyX;+JXC0B&G5eplkR0KZS*$G=bNEpWEE z6Xx^qI}N`X_|3=f6#UM|?``1UWJyDADH+%lG4W}#Tm^qX(!=6(S&&$?+Y_H$rlI7$sfqT`+E;Uq%G2p z|L=4YAzzR#-izNmP1*;{ojmpt6DFNZGvQ-#pJ~G9;yw<)x8p~?y8yo_`0;Nle(%C> z0)BJx`!D?Xcd_15UT-t0>{H_D%cfEHoA_!IXFu}!I3W8Q-_8;qe+RI3GUBuD&&nh% zFh0e+UuoX|JnsA>{W1Spct5QwEAwY~kMDn(5AjF1`TUQJ;I9ck#_z$8JdYdb_%8#q zkbm;MS(y(Z&ioNmpDlkKU&P-n_%T0m#lJHA7=OvUf3k^RVB%A8=kqxzzixY0W~s!p z0yiU#e?|E5`IUIyUXhhK2L#9Z=a~G9&GV3nFOmF#z(TzLAn?ULyZC4M^)~Z9bq(wL6ylS8 z^!p+69ONj^>rI?`P2e~251RNM#2bNM<%eSfJIwR{#hvf3$B%zj{=E$NF88&M`qTbR zMBq{rxeIsZKMF#)4D#;*DK9HQk4?mL>O1~f`Xt=^TZSL=2Vgra%~zvgY5uZx>(;Cb zEX`kk%c{V_OKw_t`LgR*t}j@&?qm6j*RNl;KCp1%^{dvbUbwzs@w$SA3-RKbwaZqs zh*d1%+(7=C>jUdQyRIOxWZBC6!1DYxC~a}U;?*CN>x#g#4Qm67*RNb1SiEG-`W12w z6s#*;y@X}l$}-LlTz{(+x^VWVF1=vh#UBeST)BE>0aBObuUWq=uy8q|h~2zyWx+Ds z*A^B?<|P(@)z{y!YHeWsE$f%8S-m{4zF_H^!h%5I>g$)`z4a@vU$$y(!7b~T6$Dl- zTeWJsQ{oEU+Ar^?Y&3+FJt4m#tYIShYAm ze~py0IKKc`SaM@v`SSciG-cJQ#c0}fYuI*{#G290b;~pd3n5r5uV0MEYgPxA7k?6+f(jQFu3xqk z-2`+lG2OIkG2lSi`RJ*emYc?+df;-|Qgja9zHa?`eHlrsmj-THyK>>GB}*4d6^sC) zh0-V+xoL5J;WBxTk5IUT0p!B?ll4m$qeA3fXNYJaIt6%Ul7WIjLb7npbvGlUN?8NSI^){4ceLBn2#)r-*&d`Ht4UUv&`5H;_;6&XQ&As@-k1hNl$kB$x7^1gAe5nn}DLkX_hNiGI`YU>+4X8D!&BrDjw{qn%v<}~m zqOuXsmiXwv$t)UweE-L|^I81;F-h-_N_d~Tlkf9S%g;!9KizwO!nwz0j=3@*Ho|Ba zp|lM~!s z9gfZp-l05dd52P|;~h>`J@4lR0u8*wNRROjhpdtJS@2hRKR*y?;T_IfEAP3`&%9p{ z2(#w1?P z_;|)^CEmdJM8>Nm9%Fnm<7E@Ng?_hi_;{l1gjBjAPr=RWbX1tj3c8T{eUdni@ z#CsVpV>~ADKE}5)UMul_#;X{wk~leYMGfO+5+{eQsAarZ;^fp7^^C8TI5~DjjPXT? zpZ(%z!oMx)=n2lhe8nQztt)y?IVSV6D_3Ow@a>uILUdqnSs8fy3U+Yd>N_60;=ZE; zmq$uiQYcoCKG3@0>c<}|i~p${C_e8@`alI)T@y-T8QUkL%7I^O<1LaM`bA;ap3!`s zhMfBTwi$4_QQpa<(*OeFn=&Rb&26~xpRYv4iHQD)&sZ7qJpLFicXXE`W!sK#ACpMP_}c_#Mu-MW*`;`Y8Y39vm_l?gtH}#E5hR>jBDoR z;CO^fc}4gH3FC_Ji4w*Y;rB=wSA-`>7*~W(k}$3)b0WfFUJ;%oVO$ZOEMZ&`o+e>l zOJZk+oze*Y=VnB5vmR|vm&X0!R&CsFJVC?Eds~oMGL%J}EzH1%m1)kIy9})j|a$x={DWn|pvBhJ?FxY7Zq zvg>&Pb%ub-Ye{T+*r|%(e*&lH7P*N3%bv3FrZcw)LN5) zpzdgL>J-$v9A^hXt&5;UfLbS@)(WU~2Gm>umDiHktgurb!T$tM?^2wEfz^5gD&A`l zP!Whl5H_I3Qh<78&^^b3+CWg7O$LJ6*yOY*s4Y28BSCG6phSS$BA_-4s4WK6*#auA zAcnaT=Cvd?C+xIF@IL|UHm#Ikw;HhV-d+J4fwl<32JE&JU@r)|8*erk-b=9CO$LI! zugU39usd>`eFVEBf)W9Chk)HKV0Rd>=L@L3mc)W#$Bp2B0;p5tpt=TByw@$DBG3~- z*nrxT0@P0h-6wA{pmr0~K9hl<_BJ{F3Tl6j(@RkMBPbD|_6w+e0&0KP^WdO?!cFeo zSDKPG1>OJo=fFToV@66ra*HD8-&2rODmqC!2PsH$3k@2Nv>^G5Rzy$_Qjk;>7*LP2 zAo+M4)PocxFRVA9zMg{QF2&Cw2$FLw*hgBBbZA8c^&kaF={keqLlz|SE;l7XkgR@X zXhAZ~!2EA%kzAqZJOn}V%36cQBP~d3J}VU+f*_e|K|RufOHHF8NKXA*T#%G>k8g75Leu?;ixBI_tt6IZYxv6lNex}&<3O$WGD--#-?`Di)z@_=;o9hf>s$Yj zTwSuO193%T;p+eiyq3grQ+YXm zRRGvPktzD#UTGjQv<>0q*d|;Qbnm{wu-75VlsN(_t^hkIVO~pOb5nUdIdQOEdOZ4G zw}6cdJwtdr7VL|I?(-`R*oP=z>fF2DXG*G*L4^Cn>B%9moLt zSiGi8_p5&!&0&?K)SVas@}*X_o_}m6L{HY9(F~=zzkY2r25WS9#}t&Vz$B#}n+TJ6 zw`-07F7HA2J!#_%lUV-}V?roa(oLq_;P4 z?1|4ZPnKs0Wo6qC19%^4<1l5Qq4AJG8k*p}HxWrp+mkyLhk?a4h&W2ftF@)${+ zk|s^*cdz=Z;7?+G?&mS4CU}!^tdedKKE?sg@*LnXdz_a7U6+#J#G6LTJjvXbo?kT}+!5~aiuhM3Y z)3Xk!>VZP(LQA^E%{EE_Rrjtt1&Mg60Fd*36RLPVz3XCJ16?1(HLdGB53G#zQs*@v zWTno)X6Ln!I0FUa^loy$U2+SU_iT2aH(){#dY}Q!Yzs12sAm)*b4!ZcKp{rovf1=Z za$9ypM*E-zI$uR^0qZwpyQlnIsEIm~I-)mxVFs@lOvvk_J8>a|THl`B%z%{lPDGkG zcz-(s&|@fvs79g^g*yl0r@y4AKdtB(RuFJsSf+f&;`*g@gI_!jy4!!I)kBa8jBHdG z!zt(lNY-|atYA0;k~s@;ywqOOopIUaLHFI)X{pk3jLc{TywDxZNEZRP&t%NjjBO_4 zbBiUTLE~E_Mglz|B*x(vE4KT&)LL}W=Jdd5KfAk!PNLEz`w>iyhO=+8;E zCX;}#$Q%@dy^5h;$e#5RBJ;q~y^KaJswpMy~BYz!rT~#elZxy?(fc>X7@dP0^x` z$9=ds#1#8T|>q;n6& z+Qi7b9wVK{p?nq0J(SJQ(du%#y)h2F-o5@t3~Au4JsH^n4pDTXf>+vnRd{dHCWWjV zQ56uNd~a-0*+y{)Xi zp%%NRw9+pDmOvUdIh==yKp8CSg5@NnG-W8t6SC=E*JcQ{>*sb2!dpi2>tG~*?a?G& zIUqlbRIooIIp8i?Amxi!H`ooEU}}dNI3PEyY`&Iyz;4)8n$hseTNL&>P}qzg9Z3pH zbJNTcg4Ax<&L3*+2TEaQ+4)2caU6)F|MF#0p-`Bt!;%3vkJ60Wg+j3yC}~Uy^&FWo zB@_%vtriEuP&^zadc%z=DVRE@q+pI@OsO3*h!$X``?H2&C=JNRm{PiqDZ$3-+Y_J} zwI??%(Dg2fil0v{3v~-Eej%J!^(5gSW7sI))UZEl%1AM6)c#3<3_5Z@)Fc^`hK;_h z8I$Ez3M#tEK+4$wV_SL@_G$Z!)+Zpq5S7dn99C+ZVd}LWlC1=kCtb>P?OUy!=FbR* z3|}+do9(`|^N4k?nB^W~q^s{Rwe6>?nTz9u#O2_j!tQy)_c=@8fT1ZNsq??9C78}% zu*Z2M-hU;1X=6hV0XN#CvM`Qa8^%&Lr)6_4NB-Z&b!`~hXzarDV~ad&j5v+5EG@n2ApK}1v3iW9@PEdR10J;p@wVJ?;|nW=uu zqZns*BY7R1R2>z?;Ey)Ih50@92Qit~?Lfb8E?$HdmpYFK@EJ3meFa#5+OB|Mv}<4I zhcR9~FmGSy2XNc$JW}dBu-SP)I`c{lf#pV=38S2GXk3)2g;z$g9Ok%pkB)nH2MS?o z_tRBL~v{@{y*wwJldWyr7^sW z#NZ`>OoTR?{fiAJ6r2(%Y>r%u2J578N6=kZB)tp2C*!>XPDj_TnjBe*EdJE^f)C;z z$;$?|;Kxo(%LxQp`v>J9i1NfzKsEh?N&#Kb?#pwvZ=8{X zR-6plX!ikI%E&=uDfh*bEBA9o@~K_-JS&xJi~SSKGNC zqwP3NQ!PU))#M+mjlfSx#kDkyW!6xQ5IAL#yi)TVQfzm@yR7tD@i6KLx_|kEpfMWC zm&$6ep4nDrG#D$Zk;-bcGF5S?2B}$*&<4p^PK}59wni$L;OW1FD!G(C=-y_lyhd{F zh+ti{ncMQUZ--R5BdL8zMU^WgV*i+~ltHujQ`AFcjBu zRO#?f9fyB>uoz6BE$7r1&pakG9GZ_BnnDY3ZA2V13M&e5zhP8Vo&??B=?rq`&6u-` zhP0s#W-&v(tYJ_caFy>lg%b5gJ%<@uAjd=tL9xUvDeR*PwQoRBb?E$^k@(cEGo5xT z@#8(sy$eD2s7s8hYNuAr+lxi^80HsBZYwEjJ9=GmhF@K5GGG|2)e;C~t*mhtAj$C} zJ^Bm?Jpw}SP#|owB|=p}a=KXDZ$ZGAP4{3Bt}q$$T1DEVwTczh8krY^dfr?{F^EpX zkd-bAnd#IQKp)k2eh2g1wxdBNRpHQFbd~9d5Vu-IC56*mGDmycgVI*gx{g`)(}rLS zcROJ;+A#<*hNT!!v;8^IH|81h_Jbi{EMW=>C0u@4&~2P81&A!Yqnq1JqS&0_95@F! zW!N`iIDBg)ugs&?1a{ja{XSMnF&ZjBvt>U+tz|bKht~?b)h2N`Qo-lNVQj@v_O6QL z6{qHHs_CG6-$l~GXlSWa29~O`mHGGyD{nIJB#F0?3f^8T8LJ`6l6jk57?E!C@pe3s zdpk_-`X+}fO9G&Z9FPQf8@yMeyxp)L-fkD(Cbu?)7U4SSBg)%*4R7;F&>f>>&^cXr zR~st43-JfKY^3=?`)-`?IoX+<8zXOn_4ewLBXGD-Kszlf`xtEDibd!euA;>_)9Dz@ zRjq>avp#Of65?QABo9Ku>pg~TrT&q#tyb_;OZQ+~j1{-3<~MVNRm#C)EVf1F zHN(2Lj9DX$34Fk0jFB;8o!!EiULV(}BsJtB@>C_L$C!WkzBF$CjG2Fd!GNDJzvs^h z-0qJt&(H!4W2*L5y;cS3k%EG&go3M*C>W_=7jSf`;ms|w7tBz80&hMoUAJBZLe%Ia zQoXIr$D0YNUeZ~OsCvWHWrjV=BNgQG)ExSZR2i^UQhCXKC{N-0I5a`wOFFAmg|8I9 z6=asoq13zk)xMPxBN(ugsutjYLu;{4?*iT0H@ zI!3I0e=lecUua0w)4p4*>PyzXnqh&>pxReW9?Ql8!pPZJOB`cM^t5le1tD4cYKC7L zwo2B%P`%=Ti0#l4nFrz8vbl_QE&5P+p6f+tI(6jvy3Vf&&wEr;84k@sFGYphtzu@1 z$Mb*r&IovZ!+9xq{(t;AhvE4TYXJ$$7@DpIWNvwIWDMbKp_#4bc6lUkOKN5Of{?-I za|Pcb>$NXCKPC*V4Hbq4!-G0Gf+H&V{l4eqaq8R#GJLBH`m~7A-590C({5CC08b>Wa#5Kx9*M1gH+pVxwTrj z73cxCHjrBzI-eD8%@FwKb)z$E_dx)(E)uiJ2+5^=N-i^u+!&bXW^W z(9p^Xex>On=me$d5ws}Hk@?4*Wyk){S%zU1BYx@NW7q_B=`pOT%MF4oSnI?4#~c6- zx}ULCUL!gEGQ!us1R3GAPi4fv(mxL5B>Km>h|@prH4ID78N21RJKq@oF^_-=x_|nJ zAyH3559uFkh9B4rhrvJA5|`Q%Jq_(y^2r)nGn`{GBx`8nA9ED#@c74{xo-qa{)Z2x zVDd@+oWn4AwHA<|l3`6BI0uZ(KR#Ca{iPX(!;h?gJXR|Eyshj_=^rl=-lkYm|G3KV zb`W=3-+U5u|ERtA2Jnx$jUwnC`(ZVq@i(OI{rksrKWG5-`^OP~&S4ny?OH&B_Eo(`t1yMRe8~PWkDLs;S12jHKK?OJ zqYS$3(*;+?Jvj(>z<9V@|0Vu$OgNPGnfk{WvsC-m8V*(ec(!)u8^b?7L(snR97Cd> z_8rnc)(kUjhQr_=Yl(lfT;ge8&uCB9zMA1-lOb9A(my7LA1VL%$*+xo=NFung6F^L z&p8awzgr7PP{#0!{1&j!98Iu*J#$nn;F0;q9~3gU?rg(-YeB+^n%`$`C)mE8xqZO? zF^?4vx-U&LRlX_x~ZT6@Q>gBRcY(~HS~A?%OJ$Bp*!#PajEirTjiV5KQ0!Ar59}Gj}5~X7=~5<_&)8-w zNkMzl8HPkX4LziPtQqdM84iPgtR>F2C3+g#v*eRCv}QQoWJuP~#y>7TZ2s~2U-7Xj zCpS~gAOH9?gF!!&XZUjt!{nQ^fCQC%1pVVHrQd%(#c=qM^^ds{BIsUcD|=J=$L+$~ zasPPId1n6D@V5HLd$bqd0RHhJ!TFz0H)QE4V~?v2)j!q>qPBum$~dKetc-a${NwxY z8UbUT`Ti7)d80q)FpSxCiWHEbeUGevyk5HQ93`dK$3NzYJV7^hsxL2HVBNOJ2 z4Tnz0JwAUtN$KH@;U5VZ6<782n=`agXH^Py2dCd$RV`3>79r zvi7BaOb$O%{_%qm!PWjP?iueh2=y!DoBcV5;rUnID+MGd<0I%FZxS-NPz8;hL-db~ z`^@db8dNN~Nv)=hn^dF$nQ<>*HVWQqTNFE$s!vzV;yS7RZI#tZIKeAnFT?$G>m#x_+_&f=o+u|xBP&jT=0dgrmO0=A zXs)nn0#^!VZavBLr>9G5hgyrI87{UNy16uR9+psc*hLKWvWNljV-Z6O7csPS z&LWBo{_1g(vNX0-mRgzxztND7c7}4;#+{IY>aOtT9ER$i8ZQMTP+iqQ(ZUW{xg%6p z7s(R>l+A4kRCk}?_PrCN(kLfEvDl+A1=TeQ)iowj9a2Gc;EH+>$^lay*4ZE{_SD4B z9d9Ppfwmfy>RL#30E+8hNp+w;oD{ArbM6zW!$Z5uu9Z~RVOQCK_S&LY$1NubaMg}H z9y!&0OE8mRrHD$sZmdDJROd$Kf!5>JjZ;d(@L6Z?fi_;lwzj=OFX41TcTV{ zVrXh+$p~mF_O28(HSl>~&S7Zkb}c|?%6Ebr#vD`-y|vr+d4ro79!g|iof=3PN<$;q zj@b^9chMc%JwqO^1>_&vZrj(26A6G_Ddg`vq%GBM+jZj%HL-ERJj{T-2mV9a zQth^#sTtp*BAy30vU31|Ur3CDr=k;YKhjiGf7`)P(V6c!NGkfXz#`& zO-1WW4YC&s%4npr=#OI$l8U~s84VR>Y<92>^|j)n*G3hb!t2eMxTY6mcb$m)m;%O* zD#+~0+T#oa^bY?9rR#y*b*VG>sJl+J4JkXCM=#JLCZ25lc* z9ttZ2%QeN;8hUe8I=&Z&{ol$tb{SFJ8<5&+SX+%(8~0E8Ytz~BV%c3aXeT2b(}+yp z`mFqTqI~)WSyOJLFxwchk-`E-i!OQh!z9>5ViMCei3HBTfynWV56x!p5tmNSbQ%Zm zJsP9!R{@|KC1jfw$Bs)w3juxcE?!3!%r}9X->!l5f_HW0Yj8|~Njs|GtgZzX*jDjM z1RmIA7{8*yNGFB1q_i#mF8vY%yK5I|ci4SUd^fG@Oj~XbJr-?epY>P7666V3Rhyk` z9A!m3*}V(%>N@vvHMH3Phh2nR1Z+x^75sME(-?p=Zc*M8&Kb(7_)(T&6Td6_+6G@v z5RG|8O+IKB;cZ%gu*)6YN1oENrKg*fNi8n_gD9O}0S~&($C_?yFUTC#Z4>gb*Mtvmh zu0Krx_=>WsNLh$re^v5*je4)D`lPDr#TSPr+7WSfB>UoA->=)7eYzo@C_@Fv+R)_0 z(9i(Hdk(gDz!!(4uhl&_G5X@rj~EkbrebL1-T2}>m?Y`|J5~^b4QSTGnHKG{S0QBNryap)y8AvNQqbn%DSYeL(1`Bfnp5Ar3yl5pkUQCqa zJiV4Lj*{lUd2fXCKCiKJDlx{f2cWYyEQ4oKP_f-wZzT9l>qkJ>uZ~GU*R%XNhoS2R zEx-_?4n|f>ANVPxk;K^OQ3ywC{KTlEHMNF@(S`N0iPDsiFfMeCbjg^v3E0xJ=yrcq z&8(`~tExGvs%9ZZ&^@GHLozYOM;?8|7*CYZE@W+Ka=4oq#MqjHVLA|FE9g>*v6aLK zdLxmM7@_amEHU!i;&DaP`Ym@C-n?D zKc^YKV>9^Y=O&%Y{f7rNKlkFw5l~&ht0}1NA%D(csO}ss;Ps-qC4$@A0!D6Ojy3j% znHB!mQr-1}nWa{WKy(d5b(-NEo8d4~-ObmJfa+fRM+&Mt&!2M`s@tUn2-V?pQhM4S zzqjH)0Bf~i_5hDr8krNjPGI<%GKu(0^0IvDC+4Clq(Bu#&+-=KdaR^QaF`Ef7S z);N?OJ0i|^rPBW_f-I4yUub2|n~xyhbKM9C^1hc-5ae$c`*IFLkc+hdD_dpA@WtYy7iGxs z#k7KByTy|EB!?XT)^9I*5>%X`asHgc z5OcW}@On{QmEiVy<)F8y&PR3Cf|(!p8sRj&d8!%8ZHB`{b#2#-fa(_Zq!6Ls@aG(c z>fWmbSP`1qJpGcLshW{*U;2~-HbSq%qeAd7*pB@1z zm%o^Tl%M*PFXu3%e1#V9dJ$xU^vXAsfBv%wGA2#m{*vjiHy=T6yvj#bLuvF;T`36i zLVwO-2y*ueQh=4M2Wg%*3$lBSkU(0udVfLkg-JxXhPx7^=Hn3$P+IwR!3aM#k9&dZVZ0sn^RI z=oT2tl*|6JtbrbBdWFh|k*xuGV~w7!{-lo}hq4A<{#^=Ep6<^%3@O)X0k0Q9{#|-y zK>6oCiy&W>re|2$^X4;8pPf4bf?V33f*`m1a}Gn0@7DsXY&}Txbo3}Ln7vGiJJ~$N zgckT5&lMLvmwEH?(2dVUGD5xB>psxF z$9X=jYl;AkEoOzcqwDOv}fg ze@HFQC@#uWG-d*gvrJ(FX^N!_b2v6EGnxQoJh0Oy4l33D{hL6LI zcJ~6i_8X~pbhm+C>K9#rvqbJyIr>@4#9Ft^DsQ1GeX~ zaz5O~kgYt;RL(S8d6UU83u*E)9LTOye|bw383FF=Q)0%2duYTlr5-j=4yamrdndQoVZ{Q%&VhJfkgdm&(hVoUJ`lc{x@S zYUQ6dMJ+(4oqV{BAzS%o%`a)T@}S8vpOy1vQ+bP2&Qw$RJX3k#LK57TCZ{YLA@QJE zwer!Xs71)MlMlBsWGg?$RL(S8`BTp+uC76vylg7xaRR%yG1XMw`n0xuqEx=A$tj&C zm170zUah>;6tx1GcJkpihHT|!nqSgv9OEwb+9^KA@S5RNe*FwKJS)U(?De5A?C1_Z8O-o1^fw*76|{zU=; z&roZU@5!tcDD+IVeG0|xrpyhLU`1WGt-pS|N7_v~L87P=$p=dHWHX==4Hc;@3r@OZ? z)j-ksYsE#CK(SPy;I@TYfr4?USA}A|DYF#0ck=l*hAb4H(}E<;LSZD^_DzI>FB>R2 z1PZ1aD9$%f!~}|K1PY%0+A2^m4t1(fyr?|Cy$rc`^7%G~EEF&QN}3~S7K%qqjxBi4 zKAW#qWdlX8K*3Z4#c2kLT!CViK#_}UP@rHOMx8?OOO*)QYms{=pKoKx zLh1yc3An!?Aw()s8=vck=e_Px)3;u!0rG9%+7^ZLTgPqwEuKiZz2)*Rmb z=L~UAiP;#TOnQo!0tfd-yTQXWvU}j*bhVzCfD1GMcZTFyv-K z#YqZ;Vz+1@TK2txf!n~yboZj!^wcj|s&yH?K7d`hlazDEu6N?S6w(ehjU^Wegz9y%C8bavX6)yW73+wuV z?!Z$j%+Z~e)7u2CPM|>>em|-FqMt0TWW6b=plebFjux*79Xzqi;!3Wgzjy0m48_xJ1zSs7q1mv)9G|ofFe0jYgB+ z4%DHDXRmGUI{Mkst_JbOKBxKVqF*hKIKQgPS`IVk=~a7wb8YL>tA2&0h{4}vOo}d@ zlz{?SP;rM-+?zYLg6=N7;XuKe^|dGm=xcI%S`i}Bt8piqx`XcKUkK8Pruwd_zkyTS zor&W5o}Dnsy$$=hfvSD;VAObtQ?4@jtAEz1H~3p1-P9&n+=mk_WTW3W04lh9`f&?b zf3AnXv_c@ZH8o=U1z;j}yrTg37=VG;r=RoyuI>Ca5bNt7M~c@`0ARQkZ6b#26EM6M zWdilY@CFUyjeSn+>7t(j!#@)Yw>-V7azt3=@!Irqyqey2(H&|*% zt03#y(X~iRVuY$I2Q$J9Kfg&wVo(Ad*#TZj>?laCFB=}NO zTQ2Sf?~nX+2wc45vSDz+CZaAC71S?N>tkL`uBmBjyr#>Bs;N0eO)IJzUyIPio!Q)L0uT8A~#2IKBt-M$D>rp?Ix#fvQ)m;^IQx?Z*O7ce7KDv zTX~MDoN2c5G*fvq(&S}h8>;8RR8#qDj|=4WGofoeaN(v54SO7 zE5E>0&NN&3Q6@(l(&S}Rx%w$gHI-+W$~Q>m++JTQl{a|qNrRHv_6}s)$%oq*vXwVB zYo9aCR=(NfXh)j7Y${jxgsGd$ zoefK_FURR$#~0GNrt$??#C@By(wSX?8R;_~g(;$Jtp$x9aQeD_jCJ3p(n-F8u|3?> zEBns7bDW-a&}0wtGK6~o-Uv>->!*z)ZuV;Zv=N#T$wS+E!xzHO=%ovo z2RFk5?m>t039jE(o*C+*h!RuBW7^$Gnr~UT@#wgdB!+;EF=< zq75As5M#fo!nN=c*fP1)S4Dj$Yr1=;&Duv6&vP*z;=T_9GKl&_#wa(#zK6v;ZdVOT zGVMe&x(Po#X5OR$J$@L_nw~U24Bd$^WVkhrrdv@d&I0R64Z~=+*uDoCdI&?ez;NXi zcXVf?$ttO!#^!`W(;yC`p^3Qa_XZ*r99NA_FvsS!DIMUtVF^bV=_BnFF` z^#fleyEr}^xFt(J?Z>uu9ivCYy2np~}h-M-n3yO!i=f@;tsi za0xwu%o{ca-RG6WqoHic%<=F@gfSnK|*q zaA=NX)nW<|);S|q9g*3i9Qkf(!T3nU26>b3%UL?|wCkD8&bZRhCne)XTs5Phz$wHD;BRHj;IA1=0&HVj^&mt$S2_IV zWz!{Eqj6Cv1DY+yN=7D_IPb`vl7Np`d*1M+VAvtW~g3x-z?E38zOa z;ci?_k**ZkJyelvZIRF}F`iH+{joU<-O=Fhj>{mKz;YNMDSa%GS8rZR?5Q8>3*kMH zygGkguPeWH`ZK1`72{ zm?G7-o^)}Z^Me%VLf)d>lC#yCAg*uJoZ zQNrcG%PK7(x~%W&&-`2HBP?_>l>9|uj=8%8Lx$i~zr2A}QXG69UKVtt4F>$Tw9@OQ zmC6P4$3J3N>u_i#Eiz`g^>AnxZO(xK_dzA*{lVhRUcRLk+n4 z3y=h8I=OoWI^R+QUEVj3sYH!q)QA^KcJV3(dW-@5(J^8o40I+%DkQsv#Xzq_VmMUA zM{-Rz(2HN?6JC7=dOR^4s+O!;Of$kwp%z?ObwolrA*RwmXL>~5R|B2#u4kg5V%)=_ zRzCH{6OCm6lwy$oT|FeMOr9hzuMs(X-9ru|iX17$JoX`{4KI}J;#H8dmjQzuCIUH3 zid0B;2@7(zATb=O;Ul>wBWIH!hgTnR;)&tV4#}#;>_fOI)Q+nnhoPJhQ;8hLBJ#c> zhjAijE$-n^2cKHx2p*V1Jn-(}ff2!jzKVfidCo&iLmQbPREw+efa@5nV6s=To|S4W zj%@%l=su&=-xR9Hi%2Q1Z~FwsXF@9wZ3^Y%x({)8CB8}&4!MZJ6dNea#D^FW4n{+Z zcym|0z#h!jXgJi3#E4#X{5n*Ll$pE7hN7s#JPAZ9s*%d_9FkEc`Zl0S9W2a6vM*Mh3NzGwCkBjNQ$r6fplpLK}1^~eL%&^{RCXmi!ujn zkJCbmh(ih^S1f81lZEy-t+VfC%6oE!Gt-ZNILM(lN0a z;uCl)+G`0ij&(fyJOEj1kQ3pFa zQZbQ@ldK#?mt++Q@&KG7_qe>AjQ2}+@hT!=5(D_7yksIo0+VdH42wvZFOYET#met9 zC9DumV-^`~;?R}E0=AVh_!QzbtfNm7rf>MDd6oKORE3O8X&F39d+b+ZM>k{TeB73< z1(;aB{-DxNC=QV_jQV@gjP!6Q7rB031QBiIz0h3h25qoK(Ng%g|!b`Qsh zt^u^3bYVnM$`BhU_c%(IBKaW3x28+=vsk8(CE!Nb68LNhD~NOC9j35$iFxRqE6;c} z!;G?s)1X&gRrChqW$X{VzccI^@EfU@xnn2;*AqX79g{w`2qU)ZOu*Q2Q1CE!6I&y&D+jxLOY-H%|H%j*p`TN9|#}#3U0bau#12ZU9ccXkpk9 zn>>nQfm@DlavFr~kHRjETpqKE%ua)_dcRarYTAqwu1%$75oZfaD}!WK_)_`LK+!i>Q;YcXQKMNx}jpxI)e1sG^%DNeIsV4sv*Y1q=KGCb*2M?+d= zO~k2Yu{Cj2?1(t<-fD3*sHichKvMM(sQ7=<$7^;NRM=|yNr76yLo)y|b%t6H7WQId zFd8BUj(=Mv1e|#>oM#= zIAW*vQ4Knok8!J&dQR^ViK-ULdR8+U!c~<|NFo;|>!BB)@ zA^@NHNyk@Rtm1dJs!y?%oW2#XSR$$_DXJ0yQfUQ96$D776j3Pxgz_KaT0IWTs#J(V zu#QZEyRlp7>_(*xI0}-pI+9myz^V4YG2f~Z!2^lnfwQBeXorAPW5L-0aPVak6j3AK zmJczJHZC;18DSfoDc77wm(notqQM+`= zKHDMf=n#BYq78E|(jj85QEHY#T3H%&ZLQs$PeGYn`(_kv52jOum1R-|E$TKc0(ZOn zZP9VsB8tSkUhH-N$5yak+$riQ)g8JV$#^(P24pTwA`-%g4TIFYp_hC76UEQtK}HY1Dt15STD#y5cioS0`m z&W}%nEY||wxV-)|p|RVmrJa_L|8003z2k98>W_gOgfV)Axt=>cFxRHUZut*f4^9=i zg}chFH#o0rJ5JSh94N1!^^Ig+*W!Mq{B(f4K3%^uw0~ZIOP8GgyAT6Po9TpW0vgVRfbIHNsC~|kO>np zWFpSB5vvS~ke|kY4tYTH!$F>fgh&OGJsTv!6nI96aZ!~K591_1&F@HsTy+oy;4|id z&xnFAF9CeH$HAvbQL>9y0iPUY!Dk}CXOgW$7>>(tCL&RXBy_4h*>q?W^ORSg=@3t} zt6#Jj4v{p8Th6N0LC*;>l_QAauFEW#(NinU5VxL7)T2fRh7Re^*c{u&0ut+vVFb08dz_GWpS%>+gr4Szd zeyzCd@c8||L)Ag|^UAkT9iVrr`29Rf*9@|WVklN=Q>xgMDqmA-N{VWvDIAy%bfGCV zXbO~QRm7>5rf}Su=D6@176%zY0GHZS3d6OQ#nRt3_7&{YdimH)J^e!TW1X?D8u)JN zfedZXgO!F4zJiHcBSXp&j4X^hK%#AXV zF`Xz#_xJXcRu1_(jq;HN^BFj?d11_YR;LVWY&fZFl4r3gfY}P5_}17hVX>Ax<`H16 zG9blSg%-dQHSTg=M2{fNvY9unR-S+H0J6uwrJ^RevN*4DMlZnEVq!5+~FoR*4 z9E(Z{m%NIk`m=tS$dgp!3`-1MZY}0QQ;D^Tkrg!M&xzjJpT#^~3m8I+&H$ho=M`{8 zrx-QFbZSwiS(W1GiHB!Ok)LOJl$m_&=3}=leu%c-q6-${(JrjV> zmzaVc%UC);Z~U+2LqhVc+x0 zF4AhaB8F?pE?xr#6Lc2+91#fEVxAR=@};yWA4haLT}m(6MWZQDII;7i(085)($0u} zRp97k*I|GkSCur83UZ6rBPPazr~*VXXrIVy=o7ie`^2w6u_$^2GTJ`jBlHQAY%L5+ zpNwNbY&OhAFwAivfr>*mqC7XnMO>+P>2PyPjcV9rL>!W!V^fZC{{>(K-Mf{$Fcb@9 z@sr}lLY%=mjRG&H0x!2@=#;D0E2o$(_X+pPlA=n{dRwJ|(0Y~7dKk4ThfHe=O z_eDc((oFFxt?=G{mqTCPO&Fqj$_S*i(sM2J%)4`~c*5A#MBJ}?ujw)%}9{Gyt z|Bm>m5+R6)&4~V=#8D;F|8`*M;rXWj?~=^Eu_Y~Zxfa@mrMrHyNg~p9GN!*|p$eu& zq{T*G{_vkt=Kl4iqZNBPQS{{|e@@_MfBG^*3;4Ivm;VrAeZlgi2*m$TeR*nBi0EIa zFSRqSEfY9W=u7HGqc2r~sKstnqg5ksV$B)ANKVkbM)}ODu5xc@2Ims6NyC~5ZvuU( z4T^kGdX%ngYJCYWaY%jn#m$o0Dye#z=ocdbUSgagj3TM`KE(%@G4+URg6>oRUr^FF zUgD5z1CG4zOcMgQTEVfptIabJ4%-yW>!mNXJ&`S@{|`oAez8_2oOYVoxWEzMSvRIgGyC`vs{*^kqr+f+ziP4jDx+nu^>PXx(|I2o>61=ze{sE&i=P* z&Sq^6R+5#+q>HdAw-?4uRK~aU^iLgFZK4wu@W@&g7SmxQ8OW+FcwzQ2=s*{8F|a~R z(R@+Dye5xZ(X&(+$mh++6Lo;q6oX+~M}}iD1dFNjf_FsnHmM^ogW%4lu0PrX7)#-N zTA0nr6NDMF$K;Drg;pMrYLN<17YL{Y0uZmspwiBZi2LgUHJ)f(XDvpKj8&AC-wWGHJnj8t+K3$sDdAG8j}K%3J!S6&;-$jp^2R(Mj(P?xB4X8`&Iv| z+~|5h7hXt#Y!C{(f=MWlwM&6)912{i1)9!=p2hzFx2e}~6$D&gr-uGJR*YaY8LN@1 z?P{bGyUy~4E423K?o@gEc`tp6K($BHBMx@4R@#bcIY2BG=@>Ewmt_nY70JM{Q#W{R zkrsEeEv}9`Sg*zUksaFqvi%ezd5_LS6LnJ$(I;C?sqQ((%(Io*x@N9fqm*klt&2(P z8V6VUU($wjTWO3A*%dSyHpZID4+XYWwOJrpwCh|N4Lk!!Jxutf>O zw&B$oUK`kB(gu!BQRbVqH|-GqIz$#V6C?EaxJ{LEyTc;dg`}t4?x5UuMQ(Qp{ktN! zJ49|H9UOr4tf=mNhmH_J746Uymc*#pT0Tvx!Ac5L(`$JRdZLfj^s<^hsis$|>62=D zr5dE88l;PQkV1n|8RZMQqozuWMGQr*wP!KB>2=?kXG*hXrH#G&E$RA3m#){`mRh>b z6dCZ^9V*`rK)SwN3$(m=aMD$4FE+KurE9K0wL;SmUAk&o9B3K_z#h;_v7>D(1{|3taKf`uCpwPC{!4)x1SG%N*g9=E=vs9uKp zWw|9Mxa)H{zRn`*WT;&!~$h^6(9_D}iU%sYMsdaT>Us6E;Pa znsYHO=QMUEms~{e#+&t{&p(#?-%vL8zu`IqGp5+?hLHF1hM9j9@{c=}GCvI~f@7+7 z(lU07;Sn>?Do&;OCXwcZ;`I%};!KUi(++Oe0y_B(GuQpYX!v@tg0y$G>Pb25ezE#l zX&N?U0ZJ(7MZCFJjZWu|6TAMd1d)#maRKgTs59nFtKwdv1!jY_@vNF{zfTKW-e?G zRiZ!aES1z_rYwSjah!O@1uab-Nf;M5Itk;KZb*Ugs6S^S#(8W%rt;%US&q>HI@bVL zZ?&qLV+oD!kyWbQaLno8=XIb3Z1kwHp?lG0cNVIoe{M)n8>n-F+CUnH^tWZY6a7Uy z5PRE^SFp{fIP!f-{WY1ET0(zaeX}%K`m5J{<@XZvxfxdo+F!m^)4!hx5=>T1Qz}Ta zB+L|VYW@l>El%aB7PCHcQwp4);Ln+ebF+*+j`Mr80PDzR0APTXJ7mfpb#ys#DQSjv@fG>9se5bgis8|3e z{|ex5!`v*OX55~T#IT4@cBxtOrZOUF-z>*CbsoznMB|C(v?{Z@XcN9?!W!Xr=Qx|_ z8J9*x&ZsCYr4v7m6=FXWbcSspJZf|Fm$OCnfNZVW;?o1=B}L_;2g;;H&;#Yr17)Il z%0|?XOlb(OzJ|mT&8i5~kgZLQY-hmCa*nf=4Z#YkrO2xdsqFgWp3semj`FB5Sv5?? z(hp$08l)xA*U4%-td!NE( zySG*sm1$=utSYOc-iC)y_nru~dLV{=_4L4E;f$rq^qnj4npwZ5i!&u-ScYpX+f2Ya zb^^OWk^H~UB_X*X1(I{ur9krS{+x-DsUaE31D}-wIwwQ_S}VfPIL0AhPBf0aD<93V zm=OgVID;d!)Rc1A{9ZF!0nLlCnAX9=3(Eu_^9v2ESYgm?%cE+=(k_+<4bw5Qq#a$#UG2<4F@#cG~yZLKvAF1zIW_3Ow07h1DTt9FZyW3**da7bZagxcW!Yh7r9C8!S%Gz8%d&{t3dR41E0i0zK5g2Yoz|D#+wc zxtVK=LNA-Svb29fF|N0E9w{z*Bv5#q*KPjfv75v@$Pn*fJ}}!P*7jua4j9Kcqe`du zJd;Flsif0=t5Oi$Z=d$%1R8zb!650hSPSTUoGRc6WW;Ex2yqgXsDatI2i>&)5j7y% z!3^E$5Ma=q_Oj6sV&8CZm41vk2qYbK5a5Ml;awlnvvn{w=x%w~kMuLy5jy4@ zbRYSfLHcy0icF^~BS@z?KKD2U*s`8$9F%KVo{5$lnEHubAf|`Llm6?Vv zVMg30@a9hVjwl{8YHk-O&+|h{!b;@@?OmCojmP_QCbn^q7xWb^K)j&+>W&w_^_K1! zej~6)!*3|vp(9Jw6{u_{U!lTzCBUa)I0Ej!P8a!=XFw6fri|$O#o=2cSD{&~Ht}#aJrc z@t0*OkUq_yGZE>7bVscgpt|D(WE?_w++X8IdV=l<{pG-Q$4sr(=#F1LDXlmhx+5$| z|Jn*E&?sz=?}pbMFSkm@IMP$;j*UxGApH@4&P1dS(j7Tkfa;EFWIRH;V{J;^ahxC0 zp>)UAB`MnY>!16uli0>Vy5lM>z^vAp?CwHd89p?|EzF4EKw);&af9wX-?YTVD9uEt zC+L3SZ>ssY_ui~CzS0lCP@q41T?)`A_;U^edZiZNfu3$bH-3|X4j=*gbKkI_o5l#} zWq%z6`n~#b~q(%7e@0)4SR=P;oEcCobG1N|c89SZ9o-)2GgW1VNAaJ<)t_4c3o zx_v0DU#~SM8dTr%=Nty~(~>~ng1iEH3am$}Ea-l$U-`-)&`1SdBR6Cq_$Lc()piBL2X6;oQc#n z$WD6oS}CCOcl5EBBjXTu($~LjnS_&Y33gHo4vLXUow;J>HIBr`zEi6;cG4*d@ZqqN z9u$@RC*`37_pvX0JPGNk?4-x9NrCiCf6hdt53-X=wSdl5^s)caOr)puu_u4akMsmP z>8cKc^yz~1c3pM5e;@let=8B{-$%XDZQ@mPxh~ga=>p3G^s(y%>FX9MDIKtn{nMr- zq^Giz=3kux>0j~ZOho!1JLz~WppzdGb2lR60oq9!K(zI-GZB{AO(q77uk9ZDed&`M zMx}PXzj=>p6kW1rt&r9|NsUjX%CGu#ipJmV&zacxK?c;jw1DB2%BruvrBwcno$u=! zlc+6~Qt7-Z1+`7~=S-xwK}w}Y3s9wU95N22RKDhyZwX4J==Vmx9e`3fTdOrn<)@EH zD-MTJ*)8(z%gRFsu2f#!orLsMN~Pe+6i9!_pED8ZgOtiST7W8*N@N^Lsodj7dV*5P z{GCDi0VtJ*Jb~LNl?4j$;c&ixEJ#1;Q&RkaJKq}~O+tDqr7|!-1=7#==S)QUAf@s{ zEkKpZ>BxB4mC7e}N}mj+RGvwxR6Z9=YJ4iClAfyZ7x;4~Hhz#&dGrdY#q$qON8X|Q z!%=0H>iquU34^`z*pEg4`bAoEqJMa&Kj$!@k4XYOA9;uJ59i!vLHGNIpBe0xkM;vF zlz+J8@)RWZlOOsTJq+ld&;mTHKZv|TVZHWC7IZ(>`v$wVm-qn~3iKy0O96VeKj$!@ zmuUeW=>NBCXso~N5sV+}=M4t^E))VgcK>4`?@9%Fop#L%`wO9iRhPyZ2jU`;| zoUXMq;fQlbqS@81vo#gtVJJrAJuc~D%+7vGMAt;gOR&M^?oETs@m(dmxW+|RMsX^K z^VK}Bgo#)j#iWR-gJGE)-v=P{g9ZdOV7^&U!DJ8ige6^_B5}W`tPwRQf=rU4<*H{c z0er?h@EK9?*`U1$?ST3qBJ8 zK9g)6qB#kEgJ3_t;2?R1zYk~RVtoRxz8U^_qWxfk7BdSqG|8MWtJZ@da%8m^&s@u8 z{qm^;nf90W_~DHz0b#a4Cs(fn8S^l}h+;rq0tVzB$G}{?U=D@h2P@|wYB9h^zyOoX z@ktUE`r9GZ2lz-%cuK}VzhHn@9|q!yVL5-oo|+s)G4XF@>S=vBvILJ9m@k!N;Hns4 zoEXq^ix=>zUBpN^VFm$lmWk{a9xD)vf2}5;AnXS#d`_(J?qP)y z#foG%k9}AvzzYYl{B(<8B^#Ob{JLbUWC&Jx^w`@c_M`qJW zD~##JPNfybc|u|0I+>E6k+YgZA`+h&3-Lm;9<%*tl)U)Vrhmr0;TRJ6@K@4 z0jDfMoa-5M@@W;TWvA0W3Jbxg2WnZR840VgJ5Q_Sba1SvW%Fgh z3AQMgI`jafPK?XmFml@fo=6*T8o6zxAyScL z@kV(Cy#4$lCDr>CfJ(MNq?r9aPY@|q?9P`kQ?M*b`Qi5uN&dL4)|`SLZZMVDwPDDL zZ_@g6Ch|jbGCxew0y-CPO#92o$Yopdt%0z9jz~|#G~bqyZV1f=n2H%r$YI+8;<(M> z&8<>f)O?2q8)>q(`0S!jzR%&}|N5;3-Q@SI?G+5aQ5x~+OqEkz=LAq7}%&rV0!3R{)gY&YyUd8e4I z3Z027P^ll60VbIrw;8;-yMBp>+_%H1?&q}#B~1aLXUUECw0f;VKN3OmYvS4yEBkCdqSblU`kjW}d70G-I2d(lE84jC0MtIq;zdj4G9 zurjFUt7pdn?R9e%P^_6oPZylx1Nc?xnsW`n-yCrEb{>biQguN#(rp)vlQ2`f`RqGu zrN%gOrE>a@QLqv{=ehoz+1@jjG|1_1`IyvV93dCbd#V$TPY*%2_7&o^+3|f7f|=k5 z@x9m05$cxe`*8IZ1bf19N@Mtb_Bfm_T)kvK>m^!KT#K0mN^cS`MR|BK;yL2-(70gC zZ;CTcldBb_>5g^t#dg(!@TJaVdG_1!jHr3V5S4`7<3{InB$w>sRh*G&4B(HhAQNGV zGs)J$u+J47+7u`G<16in7>FlYQ+%JaVg^dZx3_Rr3^0@2QQcdqv@5*M%1E$kAMm$S?`EpK}Cze zk;z9X?Qb$V{Ayf%#1K!k_O})@7sWJ*7ow;LBAz3AsfY^3R57ak%{Wm}DSD^|zEEW|^1S-UbF>VsWf{F%#BOB4wM)xE^1+P9- z#1pO2t;H-tF-@|!MNzR7@f>lIhziF1MmOX3!-7;^vJ;|s7q>?Q3dcr-JCf7KZu%yQ zHk( BLdbX{V|xNe_QOXC*(){rL*y=`(y>!n{kU&NUw^TgPg<j zjLycRph8bUUfp9S`b3tgR{^-7``ssuE@9N1nre?hm5Eyl7^uGM%;BghZ0t{JO*ALu z+-cYSu7L0Ez}=pXj%~6WG7D{$TBqAu8P)w5J|p@VSR6sO{sJkb6Q3bQFKy)2m^b8j zfOMlt1xOiqik5k%bi;X)S3uf;XKtQ?WTZYV-GRLy^eW1X$xMErAP?6SKMZJi&1{ANIsM&Tt)E&62`8h`cxKr|3{=P zq~F3icPn6lVQP+?jR@7w!R#fxAvj6NCi?M0hPNtHc10}7H_I1{&cHYL#8r?@BmCwl zPb`AN0~5VvFqOSi$~w!6qZa!yJWJBnMBn`_Vr#E;sQq2L7A>`1TY#_~gj5MXPP%`E zyrUW@A7S9q`_L`(1EU*wbFXa0Lz?J}>h^al6xau9qGJ+rFbRHlW*nn?-H!ual;g8_ zwWYIFZghRy?YW;Vf;YmRN;J_IAjRs-YY-NZYCg(phX_iqGF`uj*?A_Nx7);YJxp}& zHW_51r}+Tg=YAbv08s7e1QY$;(luXE&gz1R-XJEr?QXhZaS7LB_oc|^ozUa1^mzB+ z9zQ{fon;u-+h{+?DQm4JetJ{&_#DAcj13RX#WfWUbLAcF@!1GVk24Wn&HT6pd2@gJ ztm$z^6Mda{kN2hO@%j(Pd%V}34|o%M{6uN#<;wJ3-%iz%8K~3J?kov2#q({xyIsnR zi=|Y)&Djb@qAp+S&xzhOA}ghD({rxW;>}N8iM&Hit$lF4kR7qB<)KC z{U6(WjUEQ{TeScW>+Q%p6xN?Fu%P>~{@K4M<@%Nx-{J>gD9{6`K>w&e=P;oEXnG>S zoN7T&f%Qoq=zgsKpl1;1KdkcMZYakg!=ChM;ljfzOD7&k&t(xyQlJNAf{@KSJ%VX)F_%g}FYRL9yUG zR40IczJUK83w{p;qB*@|Ewg&qXUqei5d~jf0{C)|gTDbUlZP^$&h76COV_3@ev>U;r} zS07g6iRJ_vo%>Jre*o$Z9T`zjckrmv#96zCii;jfF>5Eu3A1+ffB+x(#Z_nR7>5s{ zKG1phCJEp=QdZKyLE~BSQlbDJ<-DX#EAV3cP?X(hr293}&tD&E|kx;NZTcs2S496l~G z?V_`#9y4p_ZOJDy0anb~aZA2@XiH!ve*)Iae6Ysc7w?fWqGn{FH3DY~!mbBp*jc+a z?2)%8m9)rtrn68|+-LtuanVl_XYDQ$@M@+hcsgs>&JxwHK=~3gvx43P3{Ec52^I2u zQu*;Qfoo8Zeikj6E&e}y-veJ~QLLTP0tJGNTCoaxt5iiOTu{_P5F&E4LMsPopg`po zEK;>dfffp11Hm+s^dwRxl?c^F2@)h~l%Nq)2@sk9QKJTp5Hv!-H>OIIc!}Ohzvp>o z-+$+vv`tgE3Ag>F@1H&I?#|54?99&Y>@L(Vyhg+#Of2V=Opm}AY)cGTuQ`;T7^F`C zyOnH#Kw#Exh(3WWwrP{-#?AtCd(&*8le)tIP(ik2!)^Pt4n_OJ>?%Do1vZ$;!;#g> z9~$4B14);M#v`l}-@ujy`@$`eoN;-;Kq5YieWex9zksHQQxm3b*l6V%=)1-)tpIrO zE}Vq-{RL{GQu7yNBD*Sr>}r)0?X(uCoaOqa1y?9TJu?OT&CIwJ+pUZ@?=M%O*)VW) zGw#+;vq#OGakrs%FskYLN`yQkS$gLmo`tZtMsvmqn=xbaW-GwW*eu1QXwYq9hDM#Q z-_hfpT!#Q3T-`z7>ud0gewQgQmH6f>0lk>5p^rcV-2*+W&Z}e-`zqNQwS2%o+8RuR zt-+*}tAo!{&PhI$ie1gpTdc2`9KaqkmAG3)(i=2J$37Iw&)zb%URR+-@c9;i&ldw< z9|3&bL+~5%LCGdw1%3k`9QaHG_)PNa;IqIl;6v#W{$!TkQhmkbK&QsQFBJI4_~6e{ z{w8J8HK0D<0`U1_;OirRuX_l73qEkie{qVW8LvM0{0ZPQDYahN%>6>s=x8Lum(HJb zP4BI0w(=KVBfV9a2pd&dt(aCkx9R*pR&6H%=9e;+^8)SqlHW_G>pM=7Oh<|xU6`^J ze?bFw;Fo{`d@%~}iQT{MAqBdST(XH*HDD(n@Q?h*L{NZ9ejR*P1J2}wBp(Jap3^B% zD+=%$p+J}jPdrQ2EK<47Y-&^IU=--VZ~00k1^5QT8&{(M-${WfxcduBBNn6SA0XO` z-vc`EMRYKG2=%>v>I19@o`PZrB1l;8o@=0mAsZ$7Avb2(}(9aEh;ixJiO;? zSs`)ZTS}dy;lg*~GK4jLZuzO-(`ez{7W~fHF5UxN_+q&Dwx!wX#3hFrT+hA+&*`|- z3m0A^xP*zOMEqg~S*vCP43{Ci=gWQ|E__Q#=@>42CoX-$WthME#;0&$3UT2*z=bbq z?V|69%b*IXU_sJn>9{lq7hWT{D6x{)^2&9}YQ=12ts3AOE;&#?`BI|9g>NZ&{tXwt z6PGT5FonOy+Jz~^h4%m#zNEE_z7w;lpeg~xYdS8C!iCoeE@7fsmEc(wGnKV!nWN#t zadW=rYKaTqQnEq~7rqZXvAJ|3stpyJZEIEfdi+?tiPxN!(*qnce~e8nb^waD(oS4$ zYLV|Y*J&6Lub<4(W@wgi;91SY+D9W`Uy$wcah%aZ8 za?r304=^a(-zFqDXt;L1$hpO-Ykm{Mms{?-~>LK{+1-^a(_^XgA@K@jg;O`d!pRju0 ztW<&6`bluwa7R}NfzsTXgV6ioyf^NYgV}^(y{=Mz!4RPI2>epKiB}FZt_)@{FBB#x z%`!~hkKcWzSHQBg7J~Y0Iw6XzcyPxm+u8Zf#%!vf zNx$$K5z{cy9l-813WxVQT9G{u-#|JB3J*1=#aXDuvM1U zf))I2UHPfMPwQf2hQ)|qD@&{NO&zWlvrGY$qs~{IOIee)`XU{dFe~m#g{f@`d|(RC zgHQ^OgmB-Wi&iF{KVbkZ#Fy3u9Gnuo!H6huaHcs4Hon#HiVcc>zc!LN-UYCR^l{Po zR!09_Sl#P$=yHB%e!VmfU8P@mjjk|=Z!Ao4CXZlBaVB`ey9@xi4R&L;AHRdP6}e3^ z%J8hXXC^{sD|qwXaVJtaRk#|jSo>`0+F%V+|0o&B2*c!$rNy{9R~?rDl(E^gDgcdy z?bvWxr-M2wbWq1S9n?{wgF287Hxts)9#&CtN++XhmX~S}u7i9gLFCr~bTJt9D;Vsc zw}|HIu~vgP-uKFtV0vRx|F6+u1hRRFWb^i!`eNYL%F-nS9j-gcwiXR+0IwmjvUCA| zDqV^zR~HbO8rMklpVbnp8e&x|tZIZ+t+1*QR!9d{NC#F{O%>NHyZ+2!HPbC)PRFX? z5Cd^W0QzSHx@Y1vaIfoAuwyO$;=Ktb+_{%+LyAXh)ujsS%m{US@n-VHIc3f%#ctI% zhuOiv`6=YpIhD@EvzUU3N$j4*o0oToV~P{-iWziE*ZDTw2ELTZ*h`Qet@vJA5@{U4jT(~PmrN1|zJ?Yi+?<6MIc#%yC4%BY=`f+xB}{t!X6WTa zG_dI*O1(mS#bfAQEpk&o_(zWF{!l49?(0b!^l#Y6HI!7!Q=)W=kAGkMe zcaov7q7AV6hHW0$3o^ef9Dl=}Z2RDM0^lrXbJXE|%#@)0v4?#-32TIA6eNEN#4xEZeJLJZI z1lJ9CkB@dtb@ZqfgQ^$L=oTtVnTTqb8@DaIc@<5LWBF>Ut9_~yS1=M5C1a*PQ++kf z2pOr*TL1v#^WRsh4bF7ZdM6BT)iCG?hq-+mK%_(%YW%6R8&|G?rXUPEjfSG8@Dh@R99kJhTTv#*6Gv{zdC>5k*Kp#M;%eGBh1eG z+E7x|pgA5blHwds1Lkg;I}YQqM{w4oHA4F?V&;U2JX(WU8`~01fIkNdhw>AR zbhS32r`D(=(S&`02{BH|BE-#vxH*8h*&uEv#B{{_5Vw{TwF=@EmP?3R0dY&J5S>=b z_8_L~-B$QUAPy6CCK@1aZ%cHrWb~K$iFQKVkWMLO~CXq23C=g*6^jUFsxy}mcKP~E&JT6f^?Tb7%ht}!| zL_M(qcn7F+wsDRq!fTLRu4&0sB@@f%cc~4#+Y&uSksdC*2Ss|Y1|My>*S16tDbkfH zMgv19Zj##MzuEg%4W9-QlF2JJ!xl5;I;}mlip<)xN#O=(ODTu zpDj)!XroTPo}Bt60k=pUvEuR=z2Wx}vpt3qk+CcPC&2OwX| z(G{pSkmjih#(zkQoy76W*9(3LwC7!FFnPzQib0=DHSRzQl8MfAb+;TVXe&M$%1N*6 z59$n%$B4I(zuPG;N$)+MaIneT$E?P|fq7G+j&wikWBNaeTw-s!RKaxAY z;&sMjvG#rJx(H{)+c(3Vf0`8#p~@Oj`jwIEx0o_9oo29bc*2noVO6FzevSU1(CE=hf$p7Pas(UZo$$xbmbPa5AD z2rIX1L9WgO*@%p$BrH%x;UzX@J{zCgsL^`2eOE_#m;>w8EI(6cq^4yNfJgsdBy&sv zte7;l@lh+IAKtMXuK{^+1_1lGd&$RIaz6|Aq*r;GlT*HO%YQ8rVQ(Q>XHQ2AnGCaz z+@Mk@)fgZA@ihWUQd8^|8HnD8R9%@*V}9!&pOcGcpM~;VVO)vNbo3q5dGjisKrNgu zWK&z;q96P{y5GCd!F&jQ$6EP_px-1x-`_fb{{O`97!bSe&mqJ}M1|)jt@Lg8I%K9t zkSX&Tu62#z8v8i)0Mj-Qub5LJ-wotp_H@Gd5%Pm7 zALH)!^!~OHzobfejdV6)BF5-GbUkf}UJ^F|(r+ARs}GhG4GM}renlt-0YzVmXTErC zi7m>T*pi>{xOl1;2CUg=z1tF7u*}D;@c@h+<(f%z^=g(&zK0$FnZ!&JZ{A6{5+N{A z>JGLiSSe@4QB5rxF?J!LP1A3Ec!vNkt;d~_=lmtl@haA z*BMJHX1W4`6I&wVvCXia02j*%$77c%anE?{e{DRb{qr>*)7(>JJXW_N((W`aJG1E4 z|D2kIV?GzniQZv*XG+FGAj>nc@OdcqUU_6$8vZ#;o*z=gu)Od^*7TmwY#-{q#GX>)@8n_&f@g59D z_+o<*KEVR8Jb?wIS+`x-!RcsLW?q%7OTITy_h~zkhcZtGm$rlfZld58COHH>9{Aox4^L{dx)>mIZCvZ240wAUn>>o!r*njga9f4n zyuA#!pyxPFBQTBDQpH87_-O4O)&J~dl`&A_u(df>^sm*7D&XnY)h;4+9S19ks?7Mr zMisQd3R16Z=bjSWaI}_Mn@E)<7;25tT0OF0It9e!(9Q{LVnf=1WrLLM1{<(!;DBXA zD5yB)v#3@>g&GbDI8>-Dpi3Tym|~ukqqSj`zlNi=y0ASHb$-nl)@ib!9-~u#u0YeA znDT6Jqcw~VHCjUw<`lAy*6ua@_cHPDYjqn+BpNkZS}lG_X+3SED+&`aS>Z$1 z(U#~WaRVUJMr*w#MZNJcV=th9N4*Pyz;Tayk(s!I!>*(a z7n9x%IC~kL5BN282U&-kykTINGoMq59Jbj?)meClKrS6}14I6j^qzQW3Nw2JpQfFH zfniiPP$^kVz=!N4CihYBypSN#%NBE zDq`km3=H>m1q1`bS7-cRt2oNFn;*2YgnZ*RB$0J7ZsY$R7WfAn+xejn%LTr!d*c80 z#Q$+FG|8T3Py8QT$Ga*1?~`eLaMt+0|IX3}Pmbn{_raO*e^!8t|GS7fW!K~X{OwOT z6U0>sT6Q3FnwBk=u8bJ}_Ya{#TN7)bz6vm?;yxj8T6Q`9ugIx34uoL7M6BbVsZaap zKUM2!!X5@TLD(BxhV6GHjA7t$+y_|92wD%?Z6s!Y)ONR=Tb4mg$)(frF~+f(Us=S}<__ z-?I?*)@aT+VKW?5Z?*#5lC0|JN}IWE+nCU5mm0xZN`k5Am(=<)JY$BFDKM4z7Ifp~Bub3Q+2x8#(2>fGw@DEXbd6E3d8O0c>I|Y=y2T1V6Mw6Py z;oP>qA=gyz1-p|eJ&F&^-KpYya%}O#c1W;hQb?HeC2lT()Z2Y7>8rwF^^-3-19gd`W8;eMelT zGQ)P_3zrKQUL&}KiGF;c71PXG)yWtxEqKq@Ad|T8EgE0QcjB@|xNu|}u%z0BDa3{M z02jWbwTr$ZE$I(yv_&o#SsDFxxp1mJhP)O^YJ04>-qFHh70Bmz+T8#d z+FujecuZokGjHAztDI5RA)I=Fll^4Jm87)JfPF20hm%5Ib>eDH79#0(lkY=Ty>8)y z+vg29MRgl8F#lWv28YO-Li|Bs~4)XkpYq1cy@GSGU(RG zoA<(1j&8MhEq7}&_>;dc@K$6e-S~TDEG}u7zmRS@9JI^HtXF!IExM9)L8N5YtI%@{f;nCXy^*?)j68sZCgF->TeQj-hMjF{SZzzp}CQm8;oI~_0am`wL7$>({ z9oI5^h>k1hyEx!prC)drlF=mxiEg83r?HMkeQk2sTbFh$-t*-GSG zNM__OWJaZu2bI7FridAtB4)I2z>M|{n2}Z5grRkpFPs(W@mPrFVlunStN&zp#Rd;Q zjAo8^mntT$yL_*e(SHqg;q^I`10Y-CNZg_vx=_FHYRi=Uq0l_0Yb9VT9;%Uxsd?&{ zg(dpYY)e!MIoYil)oM^I?G))3i5kmAdVR^RU>UOb;4N2nT>&0{A?fu_VkvHDi&Jb6b-cO6v+M@pAPbMb=Ren?$mTRh&7;{*WE%>ZV7_M_I!}+l)po-0k zaj81LsUqEA8Lg8u155P zNQC_Jr_!0YVqQ%6H~E#yg9Ox@h<~&2Zxa5^!oNxQBOUl7-Pn(XCNcZLoA+AmB`x-w z!b%wa$Mi7#kI7iBx0Mhmo@~tFe^ya_N=rW@T5jbrOv<9(_If7ZtCe-$*H0Hy#Unxg zt|s~FbJkR~pbi0M+#l&}yW(PF3nW@d87vJvW1dXZ?D47DJKDHEtESTyc|~ynH!1Ef zT~)vT>2z)y66n7-*3;j1iVBC26-+!}d9jErMdzQ*JJh({#uj|EGH zi5U!}mfnzq`n*K|5G)^&=wY?Nc}~*rtSsH28U`IvT-+ZMp*s1KHr2s|sn}=OK|lJq zKdZ*Y{arRMu7lxAL}#8hUit4o2$NveP~N-uMRVo_zcKF?Xb!A-o|-~<-;^`Yz+Sah zfO9foIhG&y_l~!Uy3FLpXNddT_bp7soGVQToC1TZe?|dQu+B-E8ND9w!7!9B8ip#F zog!0+jPhA?X0R}= zwVKH%?`^#lvpgJT#5{?0krCn)xPg=2{U){jXW@75ybuQ#p(N|5IN4NDU>|uh?Di_W zivc7m3EJ;C3AGj{Z7eR@7+;*Ux2m0M)iRVse4n5_1ENDuBb0*yCG~D`Qf-Qhlj<@T zC+(wxw*B67CGHnFiRaZ7R0EkP*BRFR?q&SX3wl%#SqByA1g*f+Mj+&SfP8nVu#59-M4qk?+qnU~M9@)i$lR{} zgV!LrTz);<5e{L;K6Jfp2?dD+K>Cg2pcpDC8WI$q55*9m@UZ--Jh7!MG00S?(EP*} zhLZHbU_v*8aNoXdi9v>v1Tc1*Kg-oCmz0K49)L_%%EOZMhJFW4#uY=ir0!sQf|a;p zXt9itUL>^1Z&v1349&%zo;UuI^y;1vdwQ=)P>zS=a!jeR?dN#=wvyS zidIQ_Z+g4yUb>MQOd{QMN?I3~ZI$yu-A+*4svzn2!f4LCn10WgM0)(UD!>mcJ%!#l z-=7~WWIpa7^*30^{LVMQ`*^9Xl_iT@WAd}z)@NDwBDUBP=(Po@-DoF+S8 zDJp97r1$J=9cPaLDb96WA+TlMYy&nBqln_< zaiVd>d624|X4Qs@vu4yWm~T`;n@yadcKsMkc1NM&%o2l{hYu8k=@jSgj=`iA<6}m&ERf!JJ|E|Hk@5+ix2l9y=S&#b8oXyJ{7?Tj>`6A_mhTzq?~FrwDoI z`-~XO(8i9)WtgZK%wg$+Fb2~BnMbySCE*n3SYt2)7!iXxs1{PanplwHWFka})Ju9l z!GWSuoQT0>d-^e$Qk+z=ZPK`&Q=HXKaZ34mm;GAJ<2{Z;g0$2&D#xZcsRMmE?!j{) zMy5FVGhi`2+>7n3WC!y#SZaH=oj|0auy_~h59n~9H&2M%w;K5<~EdpIyu&$)?L zt!3cALk1L5j#3{v5*zcm@{+j7Y<-hP2m;gCN;$9Bs=G6h7-0 z!=`J~pj}p)p7OP~1m{8);#XViZ39ETb8LJV?ru9kp9G7T1RQw}NWd2(0iQ?$-9r*A zL2}6^UPXe%e84}hMqwgIz@*fAWz(~)+8vRgRwUpxLV_^SKPtkCS&ACkG-x*xaQL1t zHvmbX!Mx^Ej0Aj79~*B(Mt2G#l~$W#q-?sH?|$eFhsReQAGZx{ZUF>IbN{^fvn*Wx z{%GbHms>GugXDXxjQ(#j2Ivsvwcs8pYcj6J$un?=A$y>cN5019BisO#q~iQ!9Z+=> z5EzFRAXUYkz*5fiK4djg_usn$N!}C3nfm`a?*8mWwDDMgO~(36HN}c_*1jx~sVv;< z^ml1se(O^7gQs>htlUd z)DS{xHGcE`^$a250oD@XxD>r#d5Z2S@$2{)}x+*FphvAF2QAoPbSfJ1R7rsa=7A>SwB!VYRq?}Y2{i!I2C z^gv;v=3l50G0gT4ANPUu8^;+5eI-SG@iBfMpy<{@+Q7g_^yVjeRv`38Ju{ra_yabs zs37!bh}+u1nVlGN{I-SUP7G%9+icPM7{3=nz>t^14qkyQYv?%naYg?k%h5iKO zXz_>9LeZ_(nHmh9&7}AOBA#TA+?cw9tOKs)Kz`=O8T!+X1Y34A7w-`FrNho1;V((= z508oyyaWym(?CAjt5AmheM3YL4I~3{Sm)8ia%?GR(!1jT*LiS!6%6Dz9~%sa8AG&2mg3i_ zLB{tnL?l0ZOq{`ksf#pgr1m7-2B>(oI5H}*?Ew>YrfAH z_~j3%vHighm7RZD=uA8_N{DHJF~}D)2K6b7LES@RkSb-*iKJU7bm z4l6Rq3ln`elZx4MA}KuvT!7jkswP2C^K+(Cb%ChLYlNy{qCfAYV*b}oB)$8ck)D)m zZL>urzvsRzeemVcobf(5BO>{4KUM)2k$fI9jv*rXNB%ZH4W$2QB9cFAP|%J>MDo4{ zzxUWX2u{ncMkF8RgTv8LJR*QKZbar}k?iF*SnBB5-Cz75c@D6g|y-FgIZ~T$5>aIp4-*#x4JY<`?dAqA5 zW|LeP%^8=644dSSKXg37#SZ2Kl=s!&OsWjb;VZ!kJX=_k--XlR@xOE;>G^xP;bOG& zBWGJcr@5i9+EDN>#WnCjo&5GR!e;Y9J#w$LUW~9)qdDV*&G12$Spjab=v1t#3%q4> zu^gPF^w*Z)Jy&2_e4sk!_0~P}JK7q23v3O(n606YAbz@sw#FiSP_l_v%>gas1O9Oi zh=~P$tg*6Lcpay~rr@`7oqR=5;Z2y1gw%Q_2e8LNdY4FUFR%`xQXz$K`6!dF78ncg z`4)iB7Xx1(0esy<@Yz}=n|KxYOZecxXClC7Qfj@j=~=GhAuaNr!Jj}`fPaX-Vsb$0 z82A?p{Ea3;aBV9;83uDyyxMYdfX}x8e7+d?`Uv3b9)iCDA7FJVt^$8K9~}5h1o%wy z>)^9_zE%B9{-i@S)0KG6R{p|kM2Uxq2m@2rJ{7YH&sd#`E33AkRjf|MJAGbEw?p6D z>QuaQ60%)+i}|Yp<)Df1O#Wk9KmooO1@tK>pnFJxGJH_7iC0lz4Idl@m&t(XctwpfH zVyaoI_MkLeHsC#9Vfn;`Z)o|fEaj6psHT>1@X?7;UUMnhy0&~i|Y*ayWSdijN z({afaF1$u?2@^51uB=u}EuME2VbAXkmpVKVmui7f&vIhz!W6a(??JopC9Pfb9g(V4 zK?N*Gr#GhKk|$hvjo_lhN?yw=Pf=DYrh&EYAi|#C8!nA_A}(bDp^4?h+Jz~^h4%m# zz8Ee+yXZSHn+lrCf=YQ!$7Q;3;WdIwnCSM!aM8TYtaS$w_VWmgmh`vaiBaii;T|eB z7nRR6Zw&}ZKauO%y@aC;Q z&iS19>P};}Gnw6lc^}fb6u?d-?F8XCZ$1lmddlyei3cnNc)vkKL;T(jBzeDhlSty- zjJpN!BLZ4g%wQ2NT4^y-eBHbR&kjN+1Hz@ec`wXy5c1VR@FTwU<LD(uw7m5&hDuSQJ!`k^Pjt0^< zi*Us;bo>$ms2F%(-5jFqx`K{c`+~dP8Az)HJ}^bGv`kUBuYH3q+P=y40pfIzbphoE zrF8-PDa-uvfex>j?LIG>Io<`Rn6xh7k-LmX_C0`+*5XF3L9#e|4tb*-I-7tfp1oY_ z1z^7*rCbYcQ|sw4G;@nQg6P%LG1&5+!dXV;ijfD`i>#D$`wnxTBDd9h0-m+_kcp7l z0^Yov--A>Jz8sBLn=G}TqAS^G2J?5U{nb~;;u=P%J4f6Jj*K>cZC4;j{~Yy^X0_R7 zO5g)i)Obu$AUsqz-^VKGlbwgRmk4JU(ims7gu{nM}b4#>cuP+n0KdP6`px| zjj$au#vb^dZ>ld=;kp9MXs@+YzwqjO?{?6ytrlFrNWc2M7C7>w^vefc+$f0SF3FnT8F`K z{BG8ZV}EUnE*Fl^M37G)_23$u3+!l$wkpaNAnhpg2*9;RJ5C7Yz}# zcYu~_!KqsBVh9>=Ut2JBP0PyHasgdoeXuNVU>cXo6*dG3SeU0XC+pn8E-d21!mirP zg_MVvrIZHG)HE9C08rWcPhifz5 zaTHMoS=QkK%0$qDxpAxE&HJt$vS6=T57^{)yDSwvk9`7~$nfc=z!TpL z7=C4=cNG8xY5U&=%z_TLL}*_AE#skDpYHb;7u`Q;WnnhB%K(%QcLkoCI)rdB9%1R@ z+KG2{BTNDo%#idhzTHh1vuM!lankI2IND3T@l5h8M=rmb6?o3Zp-c6Rap*EUi-b%> zt;~U4@cdv#kmxPCh%VQV%L-tvu*ge~5C0WV3|7u8v%BH>ZixeV0WP!{VI z-Ix{#_Ryb>doS(*pZ4NJPoFKj$)`OyJ}O8^Auf^omUlZo?G&GOW%B74RC|MU0$Nqj z!HV;6;8e(`j};d^HbQeQ27!D!FTrzDubOiq9@|P6;o9dnCzC)?W=MKp`G#vw7LDda z%tVgYo6F|x%hptLk;@+>&%<*z&MMG1)=`{-XEi4iQ7iM~mgLRba1wr`k;K>dz6Y*3 z{qv5~C8B*}*qnXd62OacBKscPC~97GyNLt#J(!~!23=p~_B~)CmXPwN(i3n^h5H@| z`qA%uVAZ&N53W8yV1?@zu=+G(MEug%1!J&e62^4W`(QL@Uho@B%Gmc{lNI1x*$ctZ z9K_+g<0GF^7tBmYd%)xy;?|aZF z67U)!L73=I4;u+qi3F>0wE-xfUY>mqZk?LO+zc>CclW$)Ll)*<9L*VL?u>m8dT&z! zcFg9-ka2{458jD@aP=gIu{B}c;m;`s5{CYdji3mVpp+mXV4jK3<9j3A ztnTY}lWcd)=DIjSJZ3ZN-U#2hRU{KK72e0(0cL&|5DD?zSe(8$LY1nWZPkV$o=}CO z+#6xN3VP;iuJw0*Z-g9?;^o^LAy?&VZ-iz@lxsttOJX&*?4G?5zGC=0?pFjS!(Lp7 zr|pd}tol{0W_IBPL<)@sKg4r)?~O2|@?lnVq<6DT_{Ch?kv=9&)ZPdN-OIfuB$0Yaue;h=FW4J_?dkSL$T^)M72QZ^(^;Lf@D2f7Is_Al{$Kur zV{pGJ_VoTfnR1?WZ-jPy=*xKro&!y4;>@1`OQ(wacdrv?z6R6TSE6tTd1wPh9OH2-Ce7{ptD9AZSp)gV>u=^j zK2|)%EZmdc42!gKK@FolbbFcAA_ZFPO*Ig`j%`y=9o$AyZl(Qzz| z?MK%+Yao8;c7dz`s62Fv)ci}FHE=BMvS$Z?ql5W;qu3wg+NejfH4(MN#|Mc{`ND60&NUfK9MybKbD5M(&T=W8$J}R6$V0y z?jr9XLn#>RYfyvc@@0BmRZNL0Ed$8h7BJYA90;Wi|moD z5O*xwd)yA@3I=akH+)$11wj(bLLe(P$d2ZW_0%XMZP<3O72ta(vTyj%^pNkJSf(d9 zaM%y}f$1FK?b+}lB*8-J05=U27-UR*Ic8~&W@Rq$geGFT`>+N)wG%sVSusmcz>a2V zIL407(gXumZOu$izT19^gXQfVK|l1ocsF41kv4o-Rg#6re-zCebEPsAYUQ1AM5so>kC4IiGnA;gV{c-Q~cHIbHDW3`9+hY^mT|C#E) z$m$=-zj?EWrF?kZ20g}sWVIB8$Pti zENPWlLKCFVnI(j;Zvr>Ti70%BZjy(KTz?RC zlT3-`jCI+WZjv>wfWS?{wG)ArgRs8^=yrlp5Z>X9-S+KglDe z7r*0(CDiLr@(hyB1`d+}&Jb_jDLy!S#iV(}Ao{a};+IAOcj`FS0vfDr7Ql)ae=ILV z0H_Zu?H<7T!DYi}9CjiuGprL-~4hoyL&At)fQF+#``7rwPq zd@&bywk3Z_dQ+|yLOx%#f;GJh`q&Vdlb7h3^RJX`XpvO@sF3b_wW@U^T`UjhV5!(k zO|_)#=n*G7gtJ_G7x|m5QPo9?ke0(?P%7eZD?;lIl;W3t)qiWSS~57PEP>qMp<(Y2 z&j^jRiEU-#@U^-|mgNOPHU3r0KgAA*TEmPZ)$%XFl``24dZV~%Ir5%8swLF#6J52m zs0#^I%dqQ0YF!s%s^x)|u`WcaL4|?+|a36ze zdHy8_PNr(v8@pE|y{oQLJ)=}D#aD!|c6f&vth-mW>?81gYc15jyHv}}GiY*zs$~J* z(Ty*iihHP9?y{zcsg}vVAG2z?1ZOXSH^!n`W?2!Ls^xhY7brWXTGrShOW9RRlT1=) zn9W5nO(pl(Zb=nlEn_|H&z8XcY%%+@h4yDl#QtnADQcJfN!_bmuiFbKIxM1<_9ugF z8qECXQB!q6*BdkZU$2(_i_yFir<}r)D(rAjbOcaz7!)0Zq9X!DS4mNqpup-KgQ5#i zV6#IM(J3gZEovs+_|>el=AI+QZczZN$c`b8d+@sbj7*aTF7s}D!elQ|4V17}8e3%3#!h;l`nE|_!kW0*9dgW*au?$R ziOC`(on;t;;hiofpFrtIlbEn!)~b1&1vY-ff*QvrCdaD9reCIVASN|LIwB@r4)roa-HFNU zOZB~v{Z~UV>8Q&hCI^-jP0g9MQ9KJ#S@hcxMCF3fiptmioGB{rLFqdX73Xq#c{K_h zT~4E9b8&rGgul%QIRQn*;ba;m=PX}T=HQ9ON?#}{+ddOx7HO1oA0M@-JUBQ?jdJ}` z)vNxy*E<+Bj!jhNsm1zD03j-iiF8C%svPQbai^WefjeT;~HloO0IY9H?xSzYhZ;j?AWQ45oP6XI4CHqth_Li ztelF07vv%~NcjUw8Btay*whNf(il=7YRoo{{9jiKu9UGsU}LBGzpxrZ5x(XVorMmT zv1gbRv8bLsQ!5i`YNc2mL+Jl%avj4G*D*N%*F~;lu&I^bacbq@pHZrJd1_^q=eo$z z`@a?o7~lWZp*ODr_c8dt`v2s>$@G6=uAKg_PpY2L`oI1wgcbfTgLU`%zpyF@;QiKG zXt(*ldc_x^|7&`o8>u_K;4ewVobmbk6EjXBfauv!S!B)YXrUW_*eJnl~>QaN&)(d z=#>2`*MH2yod&1rl}|5{?D_qN^vXk<$D~)@`P{DRm9BHczPi<04lvLMdB+NzU7oVP z<=GMS3U)7mu)g&Zs%MmX<**2>9bW6hDr5KR73|Ug@UFKO+HHEJMtl+Kl`h8@WsWaQ zubgq75c2s#dgbocG3%9Sw~bk^bYM`#k;xXgmSa=)$Nefzuly(A^~WnTn_~0zuwm@Mqb@Lq`dr+@vHeSD$FRS}AKOp$F1}fu z8=q9c*nVm_wqNEQi4&2cWB6cZCHG4vQ#(Dga>CEk1Z5vPY-zktt2`vKUuH}+(FLW2 zJY!BU$1SzSEfkbrFNm><1m(#4M=dBDem_bjdTbpXzN4f`ZW&G}tB+KRUtA zi3`dCyvqrOdnhQ6pB2MCA}A|w+6h6K0g3?Q*BN}D;LO1v~)ZL^?eKLmqSA30<>%G1*5R`CI1@n)&!TjU0 z5uL@Y_r>KWm{_?T`{VnTS8S?&0EY_Thfq%LMG?N`HNrgoc#xA9MD@2C4^4DADFBO@ zoUC%pG7ER~s+5z@e>}!1l9QgMQOn6`-J_I~z2>Q2CnsM=jbpRCwyMRJne;(UYKU}1 zPP!cGWrn(wlQr{W*hl1KR{5^W$%Y?|ASYiRNltEgI89C}QN)OHGQm7w*l-tJ*e{LL zf-6zN@_QF-StT=zKY8I>nKB4E@{wt80q40H?L@d9VpJzqa};AGCI;7lC|#jI0R z&nP`#M@3-m@E-kv%J79|_XMjPEbvOLg?5|gYq9tu^n6u2zLdpUMVTwqgP%%Gb%0WKSI5-)%72BuKzH-@|6O>XpwI z2pFeV-U=|NSDvmXIJ>M@5eDD}#3P6}b|@U8%ifOYrkmG=w0BOQ3V zEmGw?+8d!>S%`Pq8@afLdS#n6h0hn7Q8^dBf4Zv1pjS5CAl?{@Ub)ta$kZ!|pQeph zp8B>LCHqYM_?c1pu$uWJA2JSN@Wez8Qz3WB|JCgHYN_#+{9h*uM}Gyn9K};`64EGV zR4#3G9n8+os2qNR>h=9!c7V|s{9p6bVpY}y(EmlGBjfrR=bK1%80xw_`uBaY(N zUn|bt{*20#cbfG1D~N*`mHVzXncC?YmAUt&2}&c1_6@KR9AM)ip6h&({Vm2s6VL$` zn|dq&kC>pWcHD9p?#=;rLw<}^Bq&ebF=|0M_2E$p%B16>g7P)gNTtRuY1gJ6m#D=) zYvM--7?F+$O1DG3!ccdDQgVC@`-q?%deu${$`5Ks5R}Hz3d##VN)wb6ir#^sj0aEg zl_L9)k#WKaN=Z?D&Nat0c1_CnbnUrh45to}_ zCgt4AMI~8Wv6+-@+S(v8lk!;D~(QfEv;ORK>6)VH)G zAGdBCwS4S%|0w07lQwTj>&8|~e>N*AUbRBuL>lADTMSHT`cq>JEmuFD=?seVc zsAo{Bj}$P@({(JsK)2uxf0f|uvZt%i2Pf0h^#cjT(?)_(db+mE4q@%^$^aw#blc#I zN09D@?Y{02cprA)?JiGOulOSLbj`TH4a*&0*bK@WjuJw?rwhJ?9PhGf>*~kg>AG&E zcw;P{u6!#Z)6@0tJET`);f{m12#xH{t_h}E9uPYmYYj7wRLg^cYlF$|2&(18OZKRi zSI;C$0lJLnT{R}va??G#s#-qyE&=0I%kOU1oA))` z$Dmqrd~h;V%g-bfHy*BfMyXo9^v)304(~{Vb@!^4p9?(CT4=XT&ew=9LeP6YwPOm$4Q{_ZPiG4dRb)wU1HrP2{UlMW(#tZr8``>^#cTZx6+_*Siii zj%{?`rxu%ModCUGL^|sIa;VS4JsjOHnH9r6vX9YYi^aV0d6cw$jHm>{D{g6BK)t7kP}^0TF5o#2y^^WXZ%7@`GB!(OjN#9F=|oC zsUM}N{OCWTqH-2$9Gj?YRg1mtP?bYR*y6aTEX2DUVYr8)a@^bWy^noFRDQQ;$D;D- z)Ci*T+0ly1JjH6q_h&f?rSCvg#=~670sC<6VVx0j0*Z>Gq1!}~Tw}BIj$f7M zBg)DIbA+9!<~hQcZ5%nmP7+)<8yf^8m-xP4?_0pOaopsO>G#aBOwc)&oQv2ogmWx& z@UBs*>ln-t_Q*l5V~9kl9C`z#dY9)|igB0@?E#&zGO8n0j-4)GoFlBWSZ`hx?qhI- z{mr%nu@hF}N2;7Ep}6jis%Mmru(H>Ouy%N}3|3!gcF!EkX#(#L)#xIhHps5^s!Uj^(%KhpHvEKg+w;O0|ShDmPuH zCd%#wn_zn7T=BxMtyRX6UO7*2L8Fu|gt?NHbuUwud z+4K7kMX5Y??U?k+QMNJDF6fn>1H-<$)msHHpr5=G1kNtc-EV|%Mrtl|g5_cf#XDcC zdPb>Nj*h_E;dNZ2GIp6MwEq`eX9l?8aGy)hN{P_LZ(8X@HKh4jij ztH!KX-gx?$^-9;rN6;%@Uz4U+J^*zK;+{aQyq*acUSsYW%s(q{Yj*x4%OJ8_uGn*CI-8{5xBjqDJ1eewNj zwb)+`8~VYBbYyHleTj)wyP@vJ_WK+V!~Vru2XBjY$gB_)clHVRI387TmJn2fA)j4}&%-~Tl=#wC)G zAR|?3u}4kv=>HoV{N(~l zNk(3?Dou~vi6TankqPGK`i+`pz{os~{9L~kTxS_vBlx-gaXcHw^|bzweb4;K1f4%A zR)-M!xtd&uu*7u;=I1K^_hibR`7o}oe{%W%#P~unDvw=kUHus5Po6kgjWL$_lUuBa%!R~%S}wg3i&2>e zkbTvX;p&=Ts^xEDhjrF4<4CpqU2qMXJdB`PZasF7YI*fcp%kFYh)&I~a$U$Q+-Yl? zYB}n~SQnxgm9h)Rq*?}wcU84~bttM@-Ul$KTK>71;Ow$$S>%J0sapOmp?JnfFiO?( zmlr}C-717^oEHu%@q=g(~4lu_nwZW~;?+FyW&E?9*{ES%7yrz;F-6JFlwxv>&B;4nSz^3GFV6VjzZnASSuq@7@)N zNyc0Xw8@BbDPJs%i%&3@a_Kunq0F$9H(r=2ChnxN@jm5vmWckW5pkl6NdY*-#AKD@ zm07r>OQo26%-GdJxSY{-`&pwFlh<82N-=rlxu}?2j2g!#CX3W!@BOn%g_zV3>4=zg zIn>JxbtfjLc_WF*z@fV)CYPK!f|z`IBr&=Ff=n?fL@6U^laei~0v`=R^rlr-!cuIS za^h>y#vN^m&cjYUaB5|uqdd_CH|%Hfyv8$Blp-z4lT%WOt`r;@5907W+@W7TlXqs) z%YRmMu*6hBF0v-QYoj^yg5Q|8E0t6J08?^M!kK3zy?^zofd13C^y!nxSf1#vOf<`M z&vi?gkk(w8s4q{nq_8duKqR~r7CG_34@L6IQO}kX!Sn>|mbJ;LcrN1=>A6Y=cvH5m zgzeFstW2~fy`xVO1uGM^<%vP0lqZH#_(OfQm5HkIL|rN|sA`6p%=)&b@Q12~S>IOG zH>~=$s=i^>hji43^jwwPWAt2-OrvKHOH8BZz%yCsd3ZEuoSr@D^!&CJ@W?}j<_K{;_NjmPK>MAO1Ajnwjkh@Y4IyQo<`4XE&k6xW@+&` z(VTI5X0&*d6|kKa-#d`;IcYN9IX?};Y%P9HHVD5G%^8OMvFiF zA9KwtiFR%iv#qUDKSF*)hPkRMh{M#Q%qi41jKjw)n zExtUOGfvNp79afGj#_+VJw7#B&q%iVO;$m?#ebfN;1-84qs2dN1z3y!2pM0=7XRkS zuV9Neof4r6>6xv?PwLLn;@3rU#_5^S;xGMn*IWFcXgwpf_}8q0c#HSgAwQKq4nnsz3v~NtgU+2vl#MI5 zrbD;6D<(G)D!yHyc1Eb!p7i?u?%-?>d>h>b5n7BSJ^y9Z#HHu!(VTHAW=PLlt$_ZI z)3=y(tR6Em5DldIL7MRNF`kRR3@6>-e^gB|9svdUL*HLOX%LHsZ6YclVj}e z4V3KM8>J_uku+PEnfvQ3jCoo#XPl%N0`%CgqD>zapm(8^3;}xauNeaL)QM?uW)q+# zR!zL=Z;$4T!8fIomV z0ZNif|A>R5u+;?E2fPY*A)1%U4{0rxi3Y9>MKT>>h)+}lTd*PO>!nAmPad&edBpnU z5$lyl4C(NQAwBTGwSYw-n`i&UkpL3lA;o$0P+wgoXP@igw^MzCbmOsNdFW8pAnO}a zeS@lRNc9b>KBS{Qq@y22$groXLfpD&PSoorKv+_S)E{OASkr$A z88e!GUD8YXj0rJxedj6BI!0>x$9|Coy8WX$G(A0vT2}FD?DgN z`8QglIpfe}Q1KKiAPW_1P)bHObofw4H*|KiHnw&)Dn9kIEUkS=G-n*n3@UE00*s1# z3$#osUiXiTZm8+FouJ}L*`T{Fnllbv1{GiG5PDgtcpgg0pyJ;%t)aYVZ6i_f7ON)S z+P|3-!7vVI1{Ke?0*s3HBV&d{!y3BCm*|ieuZY$$l0^UWu`F#oCz>-3T?Q4Ktbi<3 zoGwt)Y|3>nWbopnb~@4aCHjnPaITByjKi5h#XKv(sCW%BW}{+`-`|8(oE@!WBr4wX zXcj8|{rw}haRwEyumVKI8@9B=?hW{5Zh4}tvUC;JmX#-JQiV0CL|OS>sYFd1EINHx zv$3=eP$~UXV((r*cw-)f!GzCC~Kcw~Nc5F1D>~_47msbF z^Kh+pR5=BAV!~gN-sVRHPFteK2-{O$Dyop(e5m?plz}|Gnla5S8P2)t`cz`WIRcg&&f>+4rmQd8XoXuGDw9{vL~#YwzeQVJ zVf%aE@C)0D!fdYgxJ2)Yy|>Np9k?Mie}gq&O5i$?^9VE-h1CX9P?_9DK>;(@1}t7{ zEG`3#HeM}kJS{yzH5<}-cLvCmD&;l8yI~^5nMP(^TLOD7lQrw}6Ln%HIjh)d~~Q5wmDZR+qA;vJPQoq{|0j=v z)X4QC#NYKVDZO$*+`k3w;=On@o5b^Zr>4C06jaE1BwcE%N~I+$C4))tii_le)Pf~S zC4N}IoA(Xv6P8yge&$$P>A`SY$(5zE@ojl&0j^^mcSB;WuB12rpTg|LZfL13>X^bDWUD;tPIFkQu@IZd8eilO_Z;uK)#wxzM9yGO<+c!omxtYTBJhM#Z#BH z6wqlw#%h)>tJ7$$K3xV^6W>x^BQh8!LMosZ(S5fi+9@ySbMq6eltHjcgUMh!We`JA zsIk2Gx|OQ7M76D3!D@{Tc4T?p)}ta?pY}or(MVfoQSzWzI23KJTX`^=6Zl6)c^&9O zA7F~VZslYvp#KqYJ{Hdy=%6b2y)!@2HSMOq3z^1}-btk`E6)|hdo+|jf}%iHwods0 z??1`_90t?5=pv`x+_GQinwE(6zfdB2vk5+V9|Q2hZlld!1LvsVEgT%9n?}Jy7)gKw zadib_)Qo}$GYh^*1t0GhJV;?EgglVwlT(F_<((*DQs*zx>kpR{4ZFVm0Po>eM>_m~ z9*fwnn7S>|+5Z~0F$|4qRV@g`0}}6ODrSF@sAx;9t9L!gQtL?)6-jU3hg?C%ISuGk zg-sdOmj&awqmE2#&1~bjdt0)!=Fsd&&UkBPSbr<50Ex(1H*Bdw+X)ERYLt=eI;fU1 zQX7$xdL1VVd#{e{KpClrjMSwHYsuoY_tupssD!bpEz_-l{#j6lB}KX5B>+1az!tpN4R`~?5$z6*1@p0G+D!w(w8jMJ zd^HEU1XyH8aCulKIFB|}f?P@gY8Rh(Wb*lH@%fp)z<1D8oZkwwZf#;?*_8bUE>Y2t zsBTwuucQpZ+Utsj#|t9VlUek2D*D9-9Cdmq{-2<;2}LKpQ&;|*-g^R9T{e9N^ms(1 zY79+EPILboBsn!X)7H0?CH_=g^rxJa?-NuKY|wU%-wg-iJ?M)o4azx*jbYXmM>X|Q z>>_G>>ZPW}n@#wf8o$wRRpZKPr+!hHbg!?UhmBG0cy}733}@+9XK%{FD4&hyj5Eq` zI-?9UTLGWg>eST?S{Bm3h7foL^`b#&910QWFGJN0$Mj-aOrOF&wD0&JV_yaa3(B#P zM`}HjgOX!|uP>^Jr(6Hv6ue9$^$a#D1OTg0fUiUKA^_||_j9D9C@v`~&bcPHO`=GN z9@syXC@v`1dulxkGnL6sL*_`i21hAf(={w(5L2bRMtYAhv0Nh(SB&gd)`+oVeqzmv z*QE-}tmi?mzt^@z*}!w|OK`2DG?sb(W06R35-y+A^*54x$^QBD+>IjrCHT> zUwDl)vl1(LEuUZIw{dka)ZUPvsGhdw>uPVdrbbt4R@lA`DQGX;p+sue7EE2!vhuYY za1=K9olX6~G?)W41>A799vY1bEm7}!Mrc3ujCGkk<5wg$PdRC(fmefJADadAs98IG zFKEHC>FE46^q&n}@s?W8R^dqJUSf~I&L2P%nz46~CMBDeAr-Tw&#Oa_Ep6i(t;nWB zW;YnIa%}kB-wCJ?%EB4$P%uy&fF2sirw7yz)JZ3XkLFkv}bsURWAEG7Njv zY0MDtT`9R%U~jrU6q78jN~ji(#lmp((HZ2F2`$J$ht3v<4wAg>qBG=+L0_tHXc83j zaB4jvFdq?yva?e2ktCA_vrAL@T+RbcohyEiC_GP3=ChQ-zdIQlA>|cmxj>E2E(qNzLU_X0r!Y*h-g9F`W z<=Zh*s4SIYGf&WZa$-u)WKIKixzATZQD3O}vW#R`3D;C_GFA|1l}G zUfIlAB>$;Pao!sfgw^=Wft4sW8;zZ4aoCBjkypPASJ#OayG|5#7ITl#kJd@->hE=G zp$RR-IRV2OgFjTV&c`>g&eXy>RxPW<>F4T_qH3uH4q!C^t%h2tN)@hyf>n3Ws&Xq* zwv!JXy)yt4v~y*tRap!5%wlO7_|q72&_MUsIgF_FspXJ_>5i;g&d_2rt9E(#6C*T!op|`=<`(|)Lpc$;(QY&}h`<11h5Nh-Z)kxkT zN|nh;FlMwcpwXz+NVMo*_3>&hDQXtAxMzc?)eLIEEe3#yg<0MN?!t~CrPK4t%(%FTHv_muq zz#z0O(M^lk}p6DSL z_5@tmV|3-2?6wxf@k?JxQJ?7AOCV^R^ntFusX`8^Mb|!-YyMVKFf>c7vfX5s+%0;3 z;s=I~<91je(tFzLJupg)`-XfgHtd9)fDJJp*g4Set$Y(b@LiRO z8oB@BxatLiK#tHGx#el_iek*t$7DWu&Svc+@SfKG^hv}$t^MiK+8?9?bfjag(Nq+k z#1bIPS$s*(m`Y5UCbno%(4gkFB6GVHktIe!*xxX@dx-T7tG*%CH>~=GR3Fk&AJTJG zxEx9FP>6oeWTkYN%ej;)Y^B+|vIS$C$@OYwsLpLGyS$Av#27xoTipl*3$CP#DoyM8 z3xy80ufys3Y_{z;@6N(Te|%$v0fEx?*yutlVBp}O@BN`lV> zEc?_#z++9~F$^dhFv?8lF)9I@AB^x=n5a=JvNpH5Dd9v*exjK?28L}k9%})Qy%rdA z3`c(I0CeU!B#*7DOccu-+acEK0+;GR?FZU)vCX^H=3Q#@Znb%r+8pUrNt<3$$i^eT;FS|X; z+*9*L!`y48MU0D)*6AH!6$HJrd^8nzld1ufVuOmfJo2%dog#DNzDXd?iQRT z^y;*^*RC43%>DSSQRcpU-_bDlU-pTx=tySC3acQ_-1kIt?tr=9YXwA@dqB+nq%nPz zxyP|b?wP&G+^>*FuDQtgZJc=IF0T%GtjjwPl+Y4dbAj%_BUe6UCwMH+Dv0yg>Cv1! z;IUual5QOgiN~(KP3ch{YahQJx$ALo(W|oqP0b&-9cb11khxpEqxTw32UtM=$jOp8CQZqrA`{932ewFszr=LD< znfr;GqRf5O*3mHc-~UHnZ=boZu?phM-4xBa1LmG%1w@!TSIpgOOg}-G+xyq6mASus z{X#P4RgQ2zTQ4_Z?FpD%>CqWL@ai|+~->X5$2vQ=AOJxWlRv}J^&cM zI&JQA7LQxzp1C&4+|Bnx|wdxrM&bHC0foMF!yy=Kh$8WystmTc$hxK<}VdClyS=lK6c#C!Wt4xXS+x>wWAutao+4o#+3C zd=AWM-+K^CS=tiAaKK>I*KmGf>lG|$(!i1Y1~3n=%|)z=;$Vi?PT6bD13|c~Rk-)I z#PGnwYZK3FaaGBdIj-IixLj4T1q+U}6bF^-p}^7yvBYOGBEM~Shm{BOSCWd$new!p zX)2a8^}hu8(0YiM?y&QtxHzbADpv%Zj1mz;Je(@TDj`p=!>6aVCv1q(dWp)13FH|(p%AkFo%Ru|8#+?jqBkF5^1Uxeh96$fM{FRhjp?< z6EQW6TEN%6SYC7nR?a`N#xVww*1|#N#0Oijf>XN*^r!?Z9rR1cvk$m=AxpT?N^tbe z+no5HoM}Gp=a2C4`x-Vo%AMPSSmpMJw6OsmweAi2@6$uS{oYE(^J z-i(@*&N`5aYlY&pNIUEVQ&{1C=VI+hZ25fE^Z~0W00vP6Uq>A3Pl}6vlEaWNS7S7J z#qmuAh$$`CLN^OzT;*a+XW-7QB35AmU(!3YRIRnS^fJ8W^#5KVG8+hd1t2-TsYa!6 z*?pUqI`+6y%3LY@CFwn7E#{X}%@8oRqOZdu*APG1L0nq~_HzOMTDgh^g8Hx%tNZlf z3Vhhf58L@+r&x%K+MqxbklQ-#ruX`#_j1`OShV@wSh?;|6u5rRR{6YO>Lv6yc)zy#v z!chP4NcCUj7l$Z)+peYFuYa(lXfU(>V_b&9E{VXT&dCf0!?MUO<9-Y2-_Nzdz#ENR z7Qg&6ta7#=CaqOVzfz*|Dbe~WV~>|rR4!3Xxqj#4MmTrlO z%J2=_7nQ{-B@~qnu9UgBQ{YTgeh@EZe2dCeBI=Jm?|Sq;e{YKsMa43F!Ot*OQL*Aa z;1{=JQLzmBxC|3YREkCG(~Lb{R#CY@HT|*Jwd$xurA16m-CJ^;Llx6|3ns)%3%ntfKNzanVCr3@|0HIHswXOr9ui zORQ;f?7hs`J5ikU?*4x<3HiG0u3Fk%RkFK!nK@#;9kSdcq}_^e*4xGLQWnZG0^wy9 zXvYAUQ(b{M)fF|T6pzr25Q@O=!u~1^tPOL|7Kn}{y$rq=!g(a&YGn>2lIVW`~t$8nst!>i_? zsXB<;ss`_2v=tct)#5!Ek82QsnjTZ5NVn~6ayMHbXb%R4P6?+)cs-m1W;2DFCjPz`0nabxt<0?*sek0LhqmY*Lfna;NK7th9>{rn=09yYF0eiy;LK)Piit`@<~cXSFi7H)Z3pHfaZ zN=C>lS(zAKIzSZI3yy8SW@o=#tmJ2;9e zY&B-tYv5@ATlNAD_FfE}Ogh+$6rv*`V@)2I0;-JUqF66*-|y2JyDm#F@S!WRG+U*zzolaY;01oG~(bfj?cQ0-S$x zMokWmZ^Y(Imu%jfPm{dK-}(18C7MfSZ?6kIRa;_^I=d|~#2aj!{KOzscVcLBF^`7B z)?P#0f?0m)w!~KZXls6Am>+H3T+Dp}@zK_S{zo2Kw@!zL&hWl*@#LJ_r{b5U;mc`k z4kPE3D-N7`pRymwU!W8#6T`_f&+vZtX@Tu6W2RhYnvPFlCjq9J%mnK(Cv_lyQKms= zsX>H<}%8Q52zu^C~_x|y5 z9@V|@%9ay3QIL{2!2}l!nBtHhnBulJGQCRh7E|nY6XMow9b&))H#O7^Qewb@4bnrj zT5n&yw_0kz0nsW&1wqte7rmh6DnVF+>Md%c7A44uLIio16+|t92rAJ1e!pkt*+)N| zq~%`T_m8WOKC?4tX3jHn&Y77rXMWuxilYSU-0)2`-t{(6OOT_KC>?fjxY2>+C{ufm zcK%XD=?%=o0e|moX7ryXD_~DvmD_-^4dee3Xk`V8_r_GX3jD)n)2Lwh3|0YVOP_2@ zma^_9yz)W-zYMLI=5LIFcINk482n!W@|%+L&4)~i&uQ>SwPD?_GK2qR2n;2#7Y{-; z2fdSAEY%4phQjh+&tVd`Ki7Qh0sK_eeBACZ)y2|@Fz?y}R}<#7njqaMRUMH>3RKdS zN~#xH2noM*VW6Ca3KhwW)P7;0_pobsq)fCh06t7dAChVgZ3HU>i%~6EA$XgiaxHMz zP;wHLM%$X=4>*YlNsf99*bs6qF`Z4|FmwmXWS0_5vws0#;6=Rq>zDh&cd;RiwA`&Ar=HVX7C|JeZ3rI*C6)I>zkuP z$+1KOA9luE$~_^q%hKvV{48k&BI52`Q*LkjV@JgiDpv=x;uq^AmL(?aOy#P?g3^^9 z##ID>WP;;xa{<$2f_C_`=7M>Qfv8xRln@|Q*<2vm5;ZM7=xlO9J(C6HOK%)`^9Es3 zb}&j{lvM=r$rDkQ*RnJh=!&wu?Z#7?%Znod24M=>_CUj>ef2gn-S&o5_yyN=6i+c`2DC1_OD7l*61tgSF!FQWcfX+| zPaat9ZdFp=_=QZ1KJ`20R;s(dvgX=#4gu?iJ8^!+K{-}gz1Y(AZGS@!>yNvF>fbK0 zDqR+@PU$uS{#BY!+XZ;H2VC2t;*YTSY6aIrMhQaKP;M7~q`eYfQ!Kegk12XbjKroV^Y+l*zwl+4A9RT9)SGtpEMQj&NM8}z2cM-8?3?>lt6_`{M zAz~%up`yl#tNP=mx2*E+cXbRTg7tsC3G^GDGpH_xVp9K;osw zo^~}`y0HsX%D_x8tuO3QNoL><>GmjV)UycJ1%$FuGn7?&%+)t8C|&8{Y|b!T}0>|J|f%~0Qc+}dV zUGmQ!gc-^Lw^2ywW^_kjHlW`LoW5WJXE$Rh@5%y)PhI3bg?n^#i>2LV$x)MrJ=P69 z$geu6dJxr4!a@9AI9PuO$Isp(;V6FNeA@C{pLjY+l*z@-X%q8&sG>a6R+3 zF`2!FLs8m+pf7X1q6iW57+lIckl>51eb}=QU>-A+3%XNC=(;OJb!nPop1xqr+og2M zyE60esg(N^nYUZ%W~mM#=&5m7QG|&3 z3@&9p)aEa}Rn^VvDmAuTW+*fNh>*~A*Hg-L?wGGH81oyHPI*^mK0fuv=u@c3(xIY5 zLj~Q~P*DcjI#D(-N*u%2@RR^a2lHv2uD9Yf;%U1|QzJw&U3xs5JF0StN)jTL(+d&l z2_c$)lTqMa(zWiJt?eys>Dc-M_UaZ)l%ZX-3tp`KtZ%_QrBAe& zdc568lL`6(&E@%ds8(>jdi;B?kOF%3c(u>f7p12vwsi62l5AcH_?!^*;bdp&JFf5G zn_`U83t-2=eVl`Zb6mA)MFk_(_w`bJXOy-pi?@)BEPK1qBq)~9c#~Zc{bZMN$L{WY z#wRI)dEyO@0Ff_Pui4?TSda_st9@MDf)bnTTPnrBmkQ?&7!R>Nf%4VD0-+X?XFEsLVNKkOhN~|OtB7- zsqXzMPfRZb(l;8?(tWvLQiL4#h>yQ1Ib?uHn-C*19s$w^q7>n2-~3s`f#O`*Ny_D&1x%<8~C<+e9n~QM{^d`$UTE^0NsR< zo7*hWG8Rs=4j}jTKU_*~jNnt&WJ>qRgfT0Ffs6?+^UR&~CJb626jfc0G82aK&UvYP zdW%9g$UT(oBGsFlx-M+Eh)rVWnjD&3SLu5gnDB;*yA|KBZtguXq#pkQky5n{CmepBmExcQy5M z^zx>*MLFN@bM|8sC$95vOMbC+=VdwG4cxG%SczU(Pq5r*#T(GWPAXnyShTi-MzyGT z!_7^@@#2BQtNcfXt(B74+~N$Yl3p$ug|Wys3b0ogW!E;Q)-sB&&9B+b!bplz@bdmy zXIiAiT1(nmq?dWh$+tZ)hu3vv!)Du>2X(Pa87Su1wz!x_8(S^yU2gS!l5&f0$Jz;6 z7uE>TTBcmL#KysP0uVP1uhcCaO@$YG((o&IC@GiB;YMQ(-R@%=o);R|VXZOc9v%ZJ zQsG*A<5&cl7I9{1xkIU@NtPLrWg290_Qri_ypYpyyNEe1!yUSaad){SGUyuKN#&YA zuD*?^FBW8nk|Ueo^98``%E+4vv(w-=9|Hr1DPdzr!LLv8>t?XTZK;)|Bl;pr2tiCwIFK*Qr`|xbfj`$bdv*XY6U!0aT5ZIos?ZU9_46C>{xPlFL3bOP# z8tzo-d$8g|%JBqV*p{q@5I^pVh{`-|5p&7MvDXB~&)x9?j)ElPm@$D9W0Tgb#Ua``CDBK3#9--8R4>$Qc^eIvAuZ?=X4fkY|JznR59~YV9 zBYf%<!wPZ4s+5@o}y*6Pw0O*#sEkx#H1>j3G7wFs2 zaJhRUsb$U8j9Ji3t@N0^c!ZK6AwQCM_obk5F1H!}+pY;mVb=hun+u$f$MAdGs+?kQ{^5<{=#ahiaeWP!Oo$SHeN^a$7C*!cyY+>PD z=UawE+da(Jde1unOc&_Fw5!+U&h_zX|M6~Q%;bCEy6L#Sles_h;8PDZKbUyxo0(iM zliYI(?wR0Ya4WJ3Y`=%Oj=jXJ(A#B@fB$o`c_!a3!~7j6A2TG{a{Ot{v1DxlT`i?H zCd z=)VQb$lfE{!9D%R+gzZVc=vfvDQG79)wTsr8j3wlMn&X-y9y2b0x)>3?s9J%IrLpX zQ{kVP7+9XxfJbT~akFz5sc=6Y)BxK}C;f0#+o=8(|Bw}PpL(p~!OX)~>T-mSnQzqG_v4D6fe!zg`S%Py!(6Y@r}ddvmeVi6`3i?qX{{G2euKSg)buxo z{{mA6*bwz8n4F|Lv_FAQg}6Jx(>5~Pam-!@*@e64o10pza5Ttw=-j7~3O{s%>(E=d zTWxPkw4R-9--O*1+4M%ZtOBVWqttT@uRU_dqk8yY<#w~!R4wSY)Z$EHct6ngAK>*s z^-1%WfH_Wv#X2G(~``{Hfvw6!x6b?azu>WJ5E z4I;7rm2!2%erdiFiV8#BJD%Os9@Vm9cnvFvxp4H2RM=pjh_H7yH+9CbpC|15J@!tU z|FNsa%a444+V9O+5&Pv!uyYO<$9}%B|IA1LEd<&DUj0NSVDHNA>0SZ*j*Sg(ib~tp z+|(DxS0#L(_4xWQ<-=Q_hOalf2XC>uog^!kmJd&{&2!xD&$&lH24sDa9zs2X8vLM? zr2!~uIjuTjLI9=0saEz}6<^%uWB{%ySX0U~RaUU3o13O(;*e&}Y1niw(h*RQu#nJ zo6c(9y(auqpL`yvG8Jx{#5Qyy(s{<`(c@C*nSjTcIqquess}9^Q2eelEo*k8MlyCh zF%;~AA5n=uRD9tJ3ky%ez*i4gCchIdo=iqu8V|6dQ|g2_aW>!w9{T>n#YZQ9G?;8y zReFh98uLJn$>Mz}kjbT*JbMq}rS(`PWwG)sQyl+Uee0p`KlD}NOHU=!^YuVkZQo54 z`5K{16PCZY6VWU#Hn%^;gSsh>1XOG`)x&&!q4C?YJ@VCud`7<=ta10ko)e`nyHC(O z)p%kNg0C5Y9fE&5yJibIH7ntd2G>Mru>`{`cl`ByRX+4j)b32{+h@5!Z&RY;0!)RD{;# z=h97|t7zPcy!Fjt%`&3>>u$-QqqVpJ?xL=i6WzLf6`P@x-KC(+^0$R2Y*^KEQkRz_ zt_k075l`KG!sO=^!l;U94dZWJvaja&Cs8{X$of8${pKNB#j49zvD_F1I2eIT)e$>R z;DhOnfJ}ZAZgYWdqG6rIHP2iS47~gN=77)(vN`@__VnxJCbgZl;jjLdYiel490lwZ zT{}F3`S-_LlV5I2ez`UIK)UIHMB@eSg=!aWuyKn7UTEwL|C&)L$-RDfF&p!)6OI@yA3@HAJ*SE#d_m+afAF>~;THQIrS5Xa z`e9JdOm!6L@0N)V{#)vySO z`C#d58Zt(5!5qoT8R*m5>_R1?O~?-!>}Yf&gOGA2<3_u*g){%FWx1cnTf zC>6fuAva`zP}81nGf!*I+m_jb2f1vc=$^4`MfQeD%*!)-Cm#C#+2pwOfNRh}UU+uR zHdOxX&6B0IXV=u57bzx^lMgk0|JH2s`=_dJ#aADC$MiREo_pvW--qc&69)`H7x*cI z+Qj+ci(VHSe!dBgB*)Gse0RqV{uN*o1~1yZ9FFn&wxY zrpVY%9JwC%MN4tlwCqBujMtc3yDDr%_T~azSN#ja-}a~pU0i+W0>Li>nl8|-s0qG^ zdPlfuvAU~3cS(`IE^=)5c$p%;t;ZMH$ni4fFVKyXV=KaUX(P>wxX)hinJU~{;M&WR z9=DN$Sla@+@p>d0%4FY$xaI;~M~~|8H#}}ajUJ^Jt3Rp^-}$ThF7{sIz6!RYiW002 zYEHRe9m0M$4J~DUFeB-+dA4Zo(q#+>HF-3y$;a7{dHm=mE5Lu@Vcv}@#twW2g~l%3 zzq9&)1Bl4wSxRiAf{W&&V~3-!al|B$mIF4{V?NiWC_U#;vh87qHLybzAPe-F#g7~M zEHPoWOP4-u=wo+K4{t7D0(+n_s~tz|RTzU=q=iWa0aBGi+8Dym3~9R-ec0qH4Eu$x zTK)s@n^}t36!Lu(lZmo|#`>t5man1j&ACkqhlGKyqq? zv^D&)I`WX3-2=YAQw|V>dCGcDT9)+|xHdI5i;>NaTU_FmC&-5Wt%g1qXukn=mB6^- zwv8OmMg&V9H;v6Uog6QJp0*lI@@0?VB)?4(uTWck}&Tu$I4^Igs=(CMrK0G&LCRlq9!PLJ{guwi|p z8(S54qBhUM8W*vn;XrmzkK>+FwfGGUHE!*;*a-A)Z#cHDsH3?an^@SS7Ii&~FOce${e@dyoH9+*kyvv|Uju9U zz?xH7=f{*otf46&Bg=@?`+nFr#F_#B^+DK!#G1jSteKE({<7<7U@!t}2Fl+a)=fzx za2;#7wnc*tKm+GsjiG#ShlmOTjO2!vA1{w%R)4MPjhQ^!P61vl;3_?VE0a{|abM{P zR2s|hKs2sOhr){$-$|+%{yS5cF0c-<<^PaoDy?d{I-GNxOu5Ng9cru&P#sOL;e*CA zV5EeLM2B!)o82=*dP}mR*L7zQ3CVg63_8$p(glq~jemm2Wxb)-zVMkkB`AH$NV3|! zF+AJcH0#E_i^AWuG|=C@j%6)yPRyp3%?d9$cT>FmM+*ziszhrcluAe=X*r~a)y-EO z!D^jPL&8o8E+hT0NeI5;20|#BIQmo`7j`jLowyx^eHv6ttY_8Jc8s=#3jMCkC<%x)r94Ywpnit+drl*5kzxNdJd zY-rvf$$rK?IFAL*Rj&R_%@`>i^w>bA#6B)+5E`1A3x|6f=0sESYPKR6M0T-Y{uY~jz2U_%1t92_0IRXW~21%2Q-A*HEt}6^|5t= zmQN9I>@=l=J{}F)%ED<2RnAP;rW=?GT2eV6O{E)<5(3bMy-7JWaOUMMAtzxXCp|_^ zB_k4fqW&e_+>{m}IU0+QxGNwHDr$5#aKSsfYC|1tt1A+R+g5e3$Cq}n z|E>=9E5B|siG*kmtr1(b>s61^w!6;hxa(j$m~7<%-%#G}P}**F+eVJXBK1QZ90#3E z+-SxD$5B3c!mQ%l)uu6AkGo=^t=85Th-`KS97@+I8fdqGYt45X0$=~GoSiqK%F#`JbV1tSgOtFFw%a5X^puL(m)+Y( zlYFez;;ncl<$XgH_#p;tbd6q_AJG0fY+KW|5vo!H7`pm}r(fbUAj~~RfKMBpZJ$Ff z&#&5vEZ-u(`bt;*VMe*?H~L(IQF>NCIXILYR$ELC*ChwBP1_ENC5LS{@-TNJtNkT= zb2{TiO#=U@0~HhaShZeM5c4KVJ=SG7*e@o)hzKxZ1kkn?tlmTf7;A1C)7U+#h6MtQ zfdHezGb#dXRC}uT?P(liI`eZ)#y&ckO-`siO)hOu|DpEOxYf0%|N36P@?dW$U+hro zw2V!QSS+=tQ0=J)q;>@idgV7tLOWoTZBRo!)Sh@y7aYN6C$*=V@cq_QuzF@OY)@{Z z?R3$IXFIy0nxB1JcQ!)K z>Uks@DRJEJDGXX%tV8-K<)tP^%u|%q*gnQL3IDWSy`KSr9qo{4hAGWF&3%l(zsvCV zrou^RNWzcwIK$lgOq&ANr<>PBl=7EjR z#{S7g=T!JNu6-xxVgH2jvo-l-3CkGRfcRwjQs6_Vq6RentOdgc$RgLrVCC3CZdC@t zgI#6VMvR6#OoCwv*740Yu(P!~zO^QY(oI9Ub<7x6ZCgPM+)%CWu1yqIq1}nhqm%_U zRNN81=Ed@Mrw}0_!Os)`nb$$}Zd7zl@4I=MYV-=6PvWK$a2rP+Mm=*!$ZhoZV-Y~>Ov7*;w+F@T;pN<> zF|)xPZo7f z5FE(gtL}4^?KR!UcZg~k+Y z?>tr90U_gRERTj0G}|u7;+o~LPSZ9{la2@#Cp+3ytm#wf;WNS80YSA@HmG(o zKQ?R2pfe5BhF4u>?L=`lO?8IpM(en%DvEE$g1zUs!|ABR8BueAu0wcn_^{F4W=rne zrRyWom>;3l+XRUl%dDHY7@EK9CR%UC;Ock(Ek+g5s0)<-wLEpi?Me89IH7(UhRSW^Kq*!-Y#RUgu zv)-hW^AL`b-JTZcTX`cGI@n})L<`I=PWh_$k`^%Q^+fmQ^n~xcnP|zA?Yq zePd8lntq$5Q*cXf@!uFVZ87@BxcXF#7UQlS-1W6RIkx;8ck3G`{5Qtj>_e6Sd;`m6 zZ1eR{9AqApW_?NcQlEapNvw=8yP##_%!L!}OT&eixsp#>L-Bl>!YLG&XkGZQPc-F> zCI#Aa5)Ic<_%Vn``WrSPWGuYUHdPkqp+_v_XgetW8&wL+RufFIy-RaL*=cF=eF~d< zMm9O$XYC*cK{S^5E(wFmqKU+1;jj5J`knz?3n5wev#;Qwmf4_p_oF~^}e$FSpv7T%bJ`brstrZ)48!y8ngiBx#`;^7TB&+(nM9TKqfJHTHHx&H5oYW9EW0x?zA+}(v>&EE@ewle5JSr#UN3d>B&DVJy) z6ePNg?j(Zkj1YXHMKKJSh+UC2P(IDXW**liN8FG{ST@fr@fe6UA$BK{{MPX78)$oq zS>F8m)%>3KQWG5|vV+2~G4ey`H;&+!UCKr+YyUAq=>pwEP4KwMdM0RPT60;|b_K1f zC*>CeRqc#IQB?)XGnuc@3HVu6Wz91_9+TCLNEy3FNq$#VeS=l)K#t{AEvTy3nt-?~ znsfz`D>$lp92qf^bar7E_cl&)TLad#O>S#&8~o`4UDW*%U-vGA?YM=cr$<4nd!PJ* zpzi%qD5|?ac_#BUJOw}NuB>^+$7AfEL`Jp<^Siq18?1XTaxAa=msIy(aXo|*`74%G zeAK-g8Oi3gsx~XxrV6Xs)wFzRt(sCMc3Y9ED+`s~vZDpF=xQOmUq?rIqUw$VYc@Xy z*H>y3epZ*TY@YG)7&G#@V?Z+ax#~K**mhao7y8KWNTP3$BvpuCPLh8RNnX9tk%Wo-Qj&@f zk|Y50Bsu^4Mv~jr2Fle=G*la1Ru%sqi#+LqMh_)=KC-6^bmO$yfUvu)hvGtmyr&Jv z<*Y$Ko2^kO5*LB;Oy((YHTX1EMpc|(RwH|i|4r#MfL6e)5 z{DOcsH$|a{HUjBZ7*B!SNJQEws~tRZ62%y=f$fU?jyC!RX~UT1w0TgpS@i-(8zyr0 zVOw>9+|&c+Y4deEY`mjUv?*6RlAG1V_hC*JmzzIC_H==6oHqLrcKc^Yn}Z4(ZH~w< z2x!v~g(BJrq^YH+&0!=WZIm_7_;`%1BKny#(>mJd8>G!4z?ReIUqqYlY;d$;B0u+4 z@j)A^x}G+lv-8M14vRMBYC~>5hAEZF&FbQtGznw7ik}t(ZT{BxH^+d~G*#KHDbUv)q&&3uCmGFoMmBOOGgC2+*EVN<5pwNVKF;tU0&C3s;)nIzSR}C zw_r|S(_u`s(!PqLMQa*wQx)Hfa@v8qM8kX8Q*!m~CiaV3eY2CvoT#0orMgpA^^>qv z)Ang?wGVC?@Kq`2U_0iXoJV^ zf02dyJF3yQp66<`$U^OE^u;G)LZRZKMm?SZn4s;JNX$Ibe94IfQ{y6*?>LdL37Vle z$HZxoNF+*I{UiocT1r_1PTd~FuaO3`S^|r|j2YlUPTuFk>nC}_RrT}P4{!T-SN8C~ zYWyD2%#SxdOuCuhfSdW@4vc#)7c*Rm*W1d>tlyx{i-~7x{fHgOx;%X3xsHMJZo*h) z6UHH&aXnLsQl}P&V7J%JIjc)qta>z{{UkCl6gb|Y2 zTZ5m0=IH`mSeV|fMr(n)r_mn*r`Hg+5)p?48$F5FZ`2V4-`cHjF%%660_Arxu^SXQ z?r}&UEUP2I@fh3S<3~ECbwh%_!6AX8-tum;28B(94;lyDrct{w&lDUC3EPlSM!E%6 zneH_WZ%Y^CxpT95HrBNKK;tB#S2euaplfSd&H`GjQy0LfEj1swHVSONW2>d>tZ6yT zbeAH^_)}5r0>GGr@8j?}$zD6UB#pp0f#P5WvcLqzEk z8p?2B+1n|El`;NKIr?2yg_Ko23fS_hV(NmbX4ko@GLh{#a>Ybdsmrjc;TFtP@5b3d zF_MPhR;dN;j(;3$+u8kh;@1j~0j)D;cRs-Z4VLLnS8|%JG15YfIN{WScBus&%gc#* zG|Kt-rLOmY`T97&j{)ttXTu%;VQj$a1A7m?b1IML$c1R^u74@+GVaKP+of9c_*(R3 zVGTwt`tcjpf*VVGp--_EuqpRP04><{!gaOiQ7w9x*8+BQ)Z&+XEns+ta?!5qhJD#!-sQDuTooRU$~GQb0~}@9uu3@Y%QlKZT1(WUu5809+sN{=U9Ga+ zb%~?!hz!;=V`Kf%3Hmy-AiCLAo>VR$&J(Tu>57YOzICO5Mc&?HfC>YoeHABiI>({C z3K-I%KuqzAlho6uq^C`KJ&hf(rA~!y|LO)d!rU+wk(zYp8S|)ePEtV|NOF*2fk;ZRS+IW#`ssw_U zD#r*Gh_Fx?pRFT`#%i7y1coZZz+IP*Vp&Ctim1w5PBG`S1g8rca~tql!7?Ip&lQ0Q zH~#NJ(2e5pMNcd*fH6=&L^g7U?3odJrj0$Z6?@o|zvFkLn9_p$=hC+JPN04ntk_R3 zUa?P+(8-aZKVfA75IS!LImlR@e38|H- z{8{r+7J@@ai8WQa7$T`mx{%X#PF!S$@>>vdUd`Qm5rmMd<*b#(|G1ET@)MRz(zl`*0%WW@hjreFds4-3 zrwbN#Mj`8XV5t-67hs+Lkcivvx&xW;?Ja>N)_K?YKX+DrZt9zrn{o#?Ri3?P3yN-a zUsasOxpQClE>%e`1*=CvtGi6>20`8X6~p+b?gIS+tn(*T_l^r)U)qZ@oWnZr)Sg>o z%pFj<<+6gq3R(rn7q|+JsDgv#f}`ayGzr-(zaSvZ)ln#t z5P|Yc=1H>&ev(F6b#r_?#*|8LLuXn?8hwML(M;ga?d7EMX5`O`H2L!#X{5+X5q0Y% zAj5hf)41}KB!n(T2fk*UE-j>zu_qHmBOj9D%#y&_1tyWmkkC|bBA4AP?wvY038j+svyk^*Y72@&SeNMCQ3 z6o1*DHk>>+JhjFZX15B%gv9`wG_L!D7si_hwFbhmx3YLR9`OZ4c;cs!8Fv^Vkzd^) z#M>SA!H+3}X7f->&Gx`uYd0~GGZ0gD4F#^N{hAttJAow2fX9A-xSsiVO^(B6xB*2h zUJ@(kLFJaqR&&^bD)v$N1%Z$pi$al*2&B_AUPu~{h(e;QdB(?M%)H>I`AqACMBkv0 z906>(kUStExuw$ag^9eGMg<1}4*{lDb3TfmF3{axbN7|tjs>>7>(|V4Rl{@4b4|m= z#kGjHu4GN|FQJf|2J958HO2pnI=YQNuzTPi6vEu!`deBLc+`isgjOR7tPa@i7Og$B zb54xaiD*AuyRJ=z{XoZou(1br3@k<*UtZ&{s>bhFZ8hc+Mhm}>2~3M`3W<^=0__@g zwMv{!5w2JW94^0iO#JySgQQ}khjY^C?X}yj~$sU%tH@0i7C(B*euod(er;wi| z?p|KvQI+_Mt6Yh@WsNz>5_hu1X2bci<{mpJUEC?hox9uu?20!+vjd7Zir=VsJXqq3 zH_YPU#7eXkc^Kx1XScuYpH;jKzIcN)v*by+vK`^eED*}u??n{3D^%C z0Yl!(@P+wRG7?x4XJxq6=c{EtA4My}G~@*s2nPmQ8Q$#?n3T=9_gl`j3)|5b9b&>i z&4?ExD>HlMvRFsBz8bUditL`bw(Bm&F3@YUH_v5XTeZT4X0Nsq;&8~>1n$z=J9qYq z(#w%AdmYUHi!VQWj!S#<+}YKnw`1QG@VB90&(gbzeGv=hIyg$$>{31gDCg>ZxGCl0?9&wXBYgzlayS54Y^YU5GZ zlZ4SclOKc|%YnI&z1E#pz+iyGKa1Q+%=wG=^sr8){(M}f(JKzSzf zBXlMF9J`e@&-i!@cJ&aV=Yh=c#%_IsV|N1a%g2S^MDLIa|H`*YCc^RLa=|fnGo-Qm zgYcvabhqF6`{vnF(|i`vVS%e^TK)wDbAdabYo4_YZ#NHax9+~$|c{~$9leRl3x(;eRC9w_%4ucjPcy% zphUhaYo77(7}%}}QI~Fh$9H{$eBXfh<$V7G@%__3aosr+xqjb@55BYC$5^}LnnrA{ zXB&m$MUqw&f5-2|yBbNb20@oK-KwBTc)k3Bpr$*cP*hWa@=WII!y$n+RaRY|8ISRr z`!=CsT31tjgEeK$@|xbFn%-}`#Ofy!;lVK>QNdADhN7CXBXBi6ulP3Xy)&^ozvk|> z7sthFpTtTG-z98vNrseyMuz?J3j#76h(Zw=1j;j+uk1efNd{%jGd>>UULn#1$^4EC z`Uc5x6LKsk!ykzZUzl?YXCh3m;9{>QY8=1n0DeI!G z*^I&ThH2d{Z~7gD^bJy|0kGv1dWR@<;weWVCh|MSReTWSFklpvEx5nAHD1+*^AtKu;5Qk%pyuwcJSQ$gN6RwQ3e?N?Z5xG7Dyp3>DAXB+A_@ug3$P3y z6NT>hk)u!tN^%a%@DAI6bvII^3v}bc(4`v4r7-j;XjSc#Ul3HaKMF-v73ddW2)3$b zf9R^(i;|qf5WGWoyaw^Awmgbu0b~D~;)^l08PZ;D3=%d#460soNq`XrjR52F3jzX6 zM4^ZP0xjB}J%&VV4a%Blyl*Fru?^ksh6io#cCA6*U~3pfs^zWW1LAettRnyuIg_^T zl{YgnJBeY$_)g-62h>Tlw)_$`G^4=U;zno)cA+EYF-CzYl}s)vFs-0bV9xw>L4o-w z6j4ARy&&rAIg3Q3fU@QpACIy79^Dm9vOhZt=&Pi_400@|0F6qiu=NLy0!-v~g5NU< zzda>O3WNxG3jEIf%PDYyAN{GB7B2x2?51~+#i&t<2}11Q)oKNe8tdg31k~6Ng(7MQ zlxH$u=XLOt8p@hyd_2Z1nce`+w2m732B}dC*m7!QM2+|SyQ2mZxn<>h67aj?gBn!` zd1_oYu$&qfmR@Jd)Q(j+w^!$SNv}j>;>?P3;!GXes)>m+fyKX`1@4@@ABERkGosUt|K{k#XnWr@e)ZEfK-C*)b9pwmm8q6qI?rdUnGm-(vNgF= zFy)h#*mK!T2~s&xp4~`mw$gZcKCALPFyqR@M7FDJNTy=8NL*nKsM=<}9=>dDCsVCd z9wuB~p0}ygvfZb${jx6`qsu|f zWkn#9WZYcDB$lKtpc^MjqNZgns2nk@0r7UGI9|5DQ`s)|Wn&^|lC>S>o(PLxqlitg zZCZ^Jj}+fs*d~q3mg4xiF)tPV?f0$jc%Mnu;2{~1t-42%F{|^G%c@I?H&)xsngUb0 z!2HUn88S_DoGIgf`vXmQ6N8iR3Qfvka#83?3vKXi3vHfdZ9p^UZ}B7Zq#m24op=h` zWe{g;T`esO!cK+Lsh#hx!{HVUQ^B=H*7fjgR>LBc5LQn7=~#^){|7f1k$@B zny@k-=bVXV>J}MeJ22eAew*yDJ`cv~uGo&aleDd3&s>-5%Vj>6ar>n8-#~=UJ9%Px z&;6hnJ}~VVj*WHg{5bg3u4(<)2?lJt9dpy z{6P`8UE*sR-eh1*=|2Q$@t>k7P3f5xQ~EkU+X4pMl>Spp`_d>ar}TfJkc>Jt!M7OS z2d7PD9y@`Gqd<(VD1ICfeJz^Q_W&>y^uq0Mllr4>QqP!FnE0;fP{i$m8hm-g8~gIW z37Fl%i2-caBPRy&8*u`g?FT&J`^kxc*mnGW*ra7Ix3?mhpPcAh&WXpxiC-%@PW0)i z$sTf|H=0!>Kb>y+bfOU#^3woyp$uxc6b3_?#b949n89hMj*qM4qbfP<+oLS`Bz~ik zPr?Z3OFqt$Ph|H_Mu2C1HhfAYKW4O(H65z~cDs!q>udfQ%p9z>N08V=qGrTLkO;6x zkSbKAi)ABR{OAu`oolPFerj1;^}PO^WYLMmKOoT8E5>&r_mG}59&n8Ba*St8Dm*_l z#=jQ*R$Pc~?VC{klgi%-ciQD2b@>^S3WuJs{Hu|_uL=`4oO@N46L8lfOas!q%fgsc z*x|D9DlT;cxCo`C0hffh1u0w-(o*~$wx=%aX(@gizv+T(p$#v{ib%LW40zD5{d3}} zhar zbjkfF-W=aNy(?zvjSBg58My;n+4;GR+`Z(IjNF5cKVA5BM((G+Eq=P=2E*2Ep(g6((#FUjvaj2u_JRmN|w%W$U${a z`gO%l|6vR&ox0DBtBTtmXejS@;Bs>+yccI^wDVItj(LNh`)W7#AL|Z`ZjLcn&*AbS zFQ7%Ai3>JXd@;yS-sn+Uv3TDw)>C_QlN;4M|8yZWtDJ45=Siq)QjpJA_R_--*adFu z!!H@P$~UqAT`#brQ003UHei(STUbxwm==($V?L!_+x_HCA1U82^4dj$5f`XDSe{gP z{ij?*K+XY=2qVHEQ4A2ppim5eX~l1g$I=ejB?}=^43~L)6?u%7IV>IzQ*K=EIgEOG zYL7NIjq2vU5zpgM@EGf)hZDHji;XH;1k9oLyv!o*k#Fcm?#tQZ~O( zZ2r=eqs};MF;Qmoq^<*-g6r5k;n)n2ZU&2xwe0u{gjMF<&lvKE{ z+i`kYyPgR==f+~Up?TYX@t%ziJBPrX&b&qnTh!-QzCL)_JsXqi$9T`itn0_dTt9|= z(XV(+q;Q2h)LDzi+gb){g6E)5I`+Hw8tr+NuTKgn)l^a1I?7sgngF^P3X~F@^omXA%Z}Y z_~6HY=CfD+3(!mp%}n3rLNnvh{KLf4&}J5j0nr?K8PI%h@Q1HNSZL<@o+mVO9!*Px zrf&mcFwGfCc3%yjU8ZKc54M{e|5Xbl_6v;s1bswNi+uyv84AHDsC9<`R$Nzcv{5f_3 z)FtO{XM&0n-(6=9I@eacirM9@T(#|f9GJECWr*Vi0QiI z%=9be?($o|m*%gip`j{$fjnhq{#b4t(O#Ri)R%O_W{>x1#i#s92S&@CbIS zWUa{sJc<44+ISKI*%-SkX|-TI-+foW^SQU14)mm}q=HqfqrK z4s*2{4XZdBejkN4hJMQ)uHg-PIAeno8P`|R%u(MFJ{%>P8%m&CdOtmC zv+2?c1O&!3GVHpB9`>5dKQD9|Y@ImV?!JfdLWLrMb#$l-^1xZq6o)la7&xe~%~3kO z^N@txs;X^5%zy;b9K^VJNaG{up6R2><@e#nwT|_4LtVvzqUWy=Du6* zMC~KK(;(b>4}+thn|T%;2(J-k2eL8z#PvTXvlFGOeFuUuF5CqIG&jw=`{okiZLZ-j z=}uVgGSM{BJlB=vX~clJ(7~vx%lnuQ;Hr*ik_TcyPvbEx>1^r^!~YQs2u3SzjRZCS z>m$q43PweEgKNFdEEqqt_h>j;oNLT^dcpW3+;8*q3C7C|gAiyI}aeehPf22=@4X_MOpGmhO>8gd~bg4L$oUugql45ce8VVE5 zo=Imc(JT{5MHx!+;cQ@Ig-JvLd_FFGx#ce%Vgi)}LcRko zpTf*XKsGN|I2`e{u7`a5jfl^H5nrWr(J|uF5b|su7E^W|ns`>k?-%ju#)w}A`lCrk z{05d-YiAOE`Ra5*1BrhWv35G&h|e&IUx{Bktl?ijH>DdxL>VwD(Fa}J&VWQBnmpdzbX*3dR!Jt#Wgmw@sWq#EA233TCbcTi z7P!7Z?XHwunrf$t&y^`}ht$OkC*8#i80Wa^M2jFm?eOAW`@gW~E-&qyd>?J%RkvN1 z3Saxr>gB?J!&5d`?4seBZ&7lmMk>7ElNj&^Yb_Yvyr3JQSva5!K8OlrVSS{%PshMu z~<&ogH1?lO~Uq^_{PA!9YA(lMNV5$ zQaNoC!EW{2e#$is3&IkLC!}JvdI#3F5LI(Xe?W9a^PCImTF@sHCF#B*F+JxsYHumi!dOd_i4(5mxtsqcQA8GCFc!ll!K&Hj(xeHo{Z6fP0QoVgKz;<`~pUnlx38)x)5UzHO%GMEF|w zIj79ZAj#V{P+sV0K+m^$KJgD_uJ(qnv8Ts84W_+k4(e#s*5}BO88T!}44J_YoK0Ls zBfvbyP--`vF5{l8(0Y=#%Gw>PYdWZFwA$0ZcTM-jM%7-{#UA5vqvHf1cI9N$u?vI_ zTD!*3u`3LDuzNpUKHJ|!*Te^Xi$KUX4j=~vg_(~4yD!wXnz@dB6kv8){Pj|$fOS~} zv&+&i(6~{RTdA&3BECQ%;s#~{@f9W!3CL=r9ERHU2#|FAjY!9U zk&Zr+PQPW+Z3eixKv$$=SMNzjAV^10R{Qj9XO85yN97)Y>&tyLlKJ{@WV4pfFDm2* zV$(|HI(=AvTfecS8kh6i$~ac;PhW=hzptt93g3uFlH9g7H$b02$x`8^f9X0)2IHza zdrEYf+QEwv?_i{}W0W35THC+o2WnOmJ>{KeqMq{f4wNpe#b-6hS`*qO3Yh;Um7cCO zg)2&%qcIQ#pZ=;)72g>pLzgP`oBUN~@^`nQi5K0gEkU{a#r6T_FQiY&zmut413nP* zAEsZLWF$`l;d=)W#qTN1?-5`cv%ktqn2_|SVi+v{} zKUo}a<>am1W#Yy5I3P}eYK0f$Y&(C#&%VVePz+L?)hS&G4G}_U_7Vg&X&6DNN$kI& zCZz_;VsZ=x3yby$QTQ4BVr4$3Lj+JJT@iQ+);;YI*OabIg=dC@snpE-I+3-DLvFW* zT^2fDs}$_NL2T)NL8 z0NporR>A8&gr{;kT!D=&M_hAG3k5XyNcTC(7R_&)?o$!I&V4Sf`*1OTk?wQv0}-nl zTf*yJq2}y$Q0RE3$&Nt1w6+6fbcBo;BqK(|2q=7mTGQ4EV<^4l6UI2k7(Hclj%&<@ zvE#{F0XAl#_{r#Pqq6*84f+3y$v+PzLoHPo!&mRj6T(6ml`mxZCRx5v<(s6|3Gl)%fz%@|K4$zt(?wO6#OrGwS2=(O$gaLCJ?|hxH?F^7?$b>GRk< zdly73XV*YsfkCLWrHbNvxaV^ch zlnOU@RIn@FvC4{qb(^;2=UZ3FwshBYD;8yQIxh!B2it~BaQvCW1gqiA01SYHIy)#u zhhg@ObIhj~qA}JI37eh-LsuHQ1v zk0Jpc^nxpzH_(GWb}j^h<^*}X^gk<_9~aH(#%Nv!;sUD}&5r@=kcN4qc^ct5sS2by zLzuWDz0sUuzIFC(KyX}*SKs013I2HEw<-(Wi1-45Y%Rg2CEiQ_}8yYE@Mlz?tjXMuq1q(i1KkrChv(XD)RqkIA( zU#H8bF!K>$uj+AqMwO3llusb!8*up)WB^xjvd>38M>Wi<1_Oc}?@Q<7U#;jLegY(OPdapsuCNkuitV#cG0y8?lj^GHS} zC`@7!;Hy!qd~~CH0wG@lK;~1J`3Mjb=vg>TG~x6+A||jnWgT-JlGq8zh`Ry-aV4UN zSYaY2z!ym79vOY2d;%d~mCL6v^AVr|(X()xXu|g_DG;TCB{QiI$siT_1q#QcjYL$S zE2-E(kCO@l>%HYl*<{6%RO}ZUW`W(aVG~k&_H2gVEKr;b=&U2Egk9m~sS*GL0M@1FowAO~RFOOfyLdnLlg}yI?r%*rUQzrz*v})A5=!&o&nrRc zgSp@+@|tnYPkMH!I&wjhZLB_i6(&Okpob7qmk`djTpF0lEDby@!afbxbEzJQ{a1Iw zZ`L&7VQ?vz{uuVJzju{&@mT1=$r0s6xrnda;&&lb!jU^c5vx=YLmBHx#!0fQ_JJPpD= z1J`qEKN9<|9)RDO&d6v6mvZU|4is3)qj=+#@}gYCSLW0~gvcpD5vx=Yrx@#vi-#h= zDW`z>M#EhC zg3~TtgR5yd$jdOA*5Ni4z6XJ)LDu1ho_Xkmc&X9NkSPH+2gV)>_U>6qa0G}Ljh2_=?h8~mtRPQX-7`SJ5QfK%bG zpGD+gZJUCvQksh&LLGeZ8b~~|j>yibfui9enK#YyTY|wwmlQfXFmuo%eH6bsYt-V6 zt;YzFao4|4%=TgHf5D6JQM_^pfS;?em&05ht{<NlU7xj^=KMQcF=4_OQH_9!sK}sEuEb-v$}^JTC;mw zjl-@=zb(wQ_!P{u9&>LN$0BJ^Y5?Y5V(up9USaOe?(K%?Wv%pRvv&+uz*OFY~VMDdjcx{q;OP#GHK^SvRPF$Nd)v za)A|j5cW!98;lyU&Sq*EUr+nOTsnvmkmlVHrj57A%Y6@bs11XADtzwWx=!7FEvu8t zFqEogR-p*)vq3fdGTsrG3jgU&*B~0-y_oeT9(*O&i$?+(7N;@sn2n{GgJ0r7U<$i4 z?B{%a>*WtS@nF!2M@D_IT3d3=eTmzyC&ff=L6{^H$H|pRaRqi>oEN$(IiA7RNgg_! zfSHy17xs=?6L#Y93SeGbT&q$TEABM>i_=(@CSz%);8&FhM3tByKR@74_Iu7ETb~jn7ce_M zHLUoXcFnUZ=^Gd30l;wG9NcMym5Csq8q%grFSJaEKh%kIoI_j0wV#o|XhTUDK41?i zrJL5niu^;A-;I?GzuTrht2Oy#y6MS8<8N5cZYSx@`h~|#@g+Zmo`PS}MPMp?SEKK4 z`7GFzIM!e^N*824sAk41G!jgKI%{m-Pr844CE05>(+3tB!2h-TMD@o za|RRD)jU&Cgn#)I^@X3Zc5|;4Al^TkBy{7$z5(>ePYCw}>-Ni6*_%nWl@q!FZ0P74 zxY+`~pt_EseBp2GBW{DRokRJtJqTnuYb}FXJ8@{O1P2O$f%`<>Z3z5s&G1p=h3Ou# z3ytd*8f$aOFcq%(6|K;qTy4n>skY?$6v5oZlAK9}M?wnfM);$$-x)8#xyt^t?iI@Z znt0AjxgRd?ilr|cM zFlB&iHX4R$BwdGJ7{D0oCfXg4#n5k==v_$AT%aqWchcjCP9TU*kjG2Eh`y1Y zU~^fD0YpRyX7Zup0S9=Jwy`sxBgNpyxVO@eDgXP88<#4mbC#yV>C z(;v`{s3j1nbqYXIOJP!rfNWm5B-Vp}Z@rp&5Z6_pib= zn$uSo5K5Xegy|<-qdCK6nvXHo(R@-V=|(gc2-F&9CeU1AQi}k*ajhKmmuWsF7~P2G z0s+eefW)FOu@K;~&@Y-3snJ~ML390}xmc}S0=If0-#K^`yt&x+q4wSE%602aEF3fxJGmO>I5at8NxynT%$R|Tn$L!7s~)Q*w2mj^G5!79?TeE~l=)rSgxS|E_5rnDGY``xS8pfo;o4edV zWs3q;7^Sh@3~t0Mf$+Hmfc%`o{2T$ksa7i=-6)?x$XDs|Da?EXU^^b%I{CFIKoa;4 zcD)kNjp{5AkktanLMTjR1o%R1P(Hd*K7o*Loy(^%^AP~v!L5^DivnbTFT^G$a6SGO zC8ir876^zp1IPj?OvD7hga;R+kNm=fq&uRJ(FivW3zTOvZ-?9pKQ|;PYo77(7>t61 z1Xsf~KaCMEnx%m4 zTfiPhsXGKvrvd@LmVpaPW5{Gdhc<^?rJ+=Tk{h z6#W8)vsxcU0^GO;S3Tb$dhkcJiokkki}>*srC&W?f?N)6g6m6v1W}%*4a^b{LeWqt zvWOj399?K^k>6Rwl+-L@7AG7l&%eJRiTsOCh^M*Wq`27vjJ`x2!cI5hra+))D}dyK z!lWkwFm@^j{bg>R5R7hwMIc}~4j{28Oe_TWub)&tx=}uXkgwh4Q<(V(5I5;rI88L+ zH*Si!$zq9{^cXi)QqWevWo~vM0rWMvrmxZCxJe+m*@+)tQToNrZqY8y;3SkEwNHkY zw%jho(2cd+G7wj;B9mvuF#JQo2wWDylO;qLyTjo|WDy8t83mB!RG4HTz&EOC<)a(r z6A1anTt0=Fj{yI@8RerJglHLqK~zbXJh_ufhpby0IB7$b zY&`5ll{4x@`-F!s*5@O?>qM2*I#G+`_s(I&w6ERhzqYvaTHqrJ*)osC_{0TqvKM=_iSqx(0qN2)md(kncT?>#&Cg3PzsX(^bjJ>5~2kvOM`VOO9Ri0ug`zDklMAHVM!U;?A@BC;_T(%Txy4=9#t?9;j*w+(rq( zDWBjwWXQWeZ1B&g3!3ZHwEVT~*kdAUJwN5_Ejv{cxu`K?$TEe=DFNsqL@XmjEVDG= zl%;`ZQrP#$Shfp^acoWS-SA^N?C~(Tlx2^JWu+62WiE-aOxaO1A}F&gg%DXLC}Nc= zVi{wx77G_jSmbvsQ&MA@#RLD7u2t#p@07)5UH_`rR5b8>3sxxeIT%ti+6) zKt)fNeef?%W6ancOOt|M%pee4V1E4E!k_Rld%~+tL1RX-3Lo}$Zb#X?|D?)HH>$rt zsDB55tiQsnKLN1q(nb9lg8nNQUF_VGpDt8)`tx#S!u9oE%lfmoYM#Ri4No@X=4u32 z)dX)-TwDk_^kDjmN_pDsgnuR4Y>TDY0l#QNAc(^J_;~|=!moVA2`Yn*Hq%w*Qeb%} z_$11nF3?TX1dpjd+>F#P-2mhX*T)KK!8;C$>*dQO!lrddhArEvU)_kpVhLYG-UL@GcLb)wH@-#6DsCCS&&RNr z1dH82W|CPX@x@4RKb;=Yii#l+iZO>|EQZ1?1_4VBxp*{{LPIx_c7cFq-l0*LXb6Cv zmhS)lLoQX|1ZJ7|m@jHA3h61aPQ@mK(ymY>?dugs*PS%c2@ogkN@~)+p^Rf?X+Iww z4fa2@J83VM$V)phNZMz?9$&OM_$BQGroy+~B5B{Tn!6yDccr0nnix;Rzc`JF@nkH` z6#Non0wKT5kDnj#Cw$L<6JrLQ7=J=rS?mLwSY9{QZ&B^(MvNB-jNc3(Bdjxm|Ek+_zDzbaowyLkD;W#NaOG?PGj{SiKQ8ZU-c&t6=#0@ zJj$Q&JvJG`ZQ2O>`r|5g8{hmQDSIl+)R4qW)-e2H8G)(r?{0Q1Q*Ts8(wu@{^&=1!V}AU6nLpu2zU27JpsOF}df}Bn zS_QuCKp7X~HyU>$wWo0x{40^;gwkvhX->i~auA5e`0!FRW-6@@pvQI{_Ko33e?vVs zii*ZbnQZVP^E}n0_!0XKl%5V2aGxQ>|)pD8s^ORw``z zp#a4(j6c!#r01%69zCw8(ntG_YcZ!CUmXfM;C3S%)*z>yT3Wg_rd6dKu`AIB6;9Vc z-v9x|DHxRBjxG6O98p%fQ85HUF%AL9VkpdF5PBLdg-3SCU zhY>|I3KIxQ7UOw44PJ@2=w~;MS7=I9YccV0$piUN9l1|6@m5G^N1ghmwstg zhgIX<2>PO?4>=;i#p=#4av^Dq?vZM=iq0nQ8 zn45E0$ND)%(#3>?gRnOv^#SB7GYCKQWw=pg1VUx{0c2$qW@QL~)(+P{ZbnQnMc8#O zI{ji|iS@=&M&(DC*h$tf{9JD&3}*5rG43$5yX}Q(DFW{N4>_)w&T1sp1H-M)LbXRCE7s95SF3?@lUU(+SQ)dJGu;RmwN>Mc-h1Va)ROa;@4+ zro~a4iSSY}kyv}7m+i&+5K^NppxYX(hMO+XjoQl=Nzc^)dHQUF-;TpX^brV^-hwF7 zM`6;3fUKTMLwg~Ta(me!G<2i(A`sAQ1(0YICK>|VU14@}4$o2(owXPGD82eEx0js& zHy7xtz0}j=+6#g8P`U8q@zSsMvO_hlM9|lGm;6SF-OQp(Bl$&zqV|$f99<|Hk>9l! zCAIcqam0F#_F^0y`heqLxkSFb5QEywW)wCTI3~fb_CjDPyv!EgT(?N3wu!;kM%vU; zT7z!27rKeYTfIGtwuL`LhID~$MdNj5^7Z@pXzs=QMW0?L|0e%w0-=7}Dw~rq;%E~- z`&^qoYFc?@X?+Kem&lxkV@P^Ix zSB~OvM{`rRj$cGi+;rFL1PQOn8A_gH#c{5rE_tHiGMyheib`vfPO^0&d9w6)yxuTU zBNkVJNxDn~Ho$)-sDXK96JGOI zh#agv6Z{9L20Z-1um%@zdOAGHOpwo&3uYJ!XZ})|Ex7nLBsWQWwT=rdpP^mLTi-b?Nl@4#dtny3A$I_}Z;DM#s}x!@GV0gvxEmh@$leG%jO$dX>N1Q#w= z@$Q=jtoR~ zo?#^>SP8p0XTqoAg^N*DXPHV@0L`kZlQ^5Q>ndDwiQW25bE?pkuh1MSG^GX)q2VBYMXTJ>@ zO^!&$m=iL_6!;nAPk6l3$ryvW3v?94*Nt0F#EwU{DiwZ)@V+PMAjPshx^uK(57>s3NSFaO>1#JB5_muwi1o$wrd?I z-!`DG$|LA>ZrA|2Di&Dvp%ZZI@#w-XEJ@1{4Oi5HHKzs{&z!2&PObQSuqWWuIhgTK zVKB(WIas#UZJc;$bR@}je%KI}*bZl6JItuFVAwdtFgb-*f;mp1lSMv&&1Iv36$0Bm zII)mpi`ceujFTK=DrTHprUD2@w1dGhjCRJ=G$xL5Exbe07;aNL6sJN_5$4GFhYz@B zV<9--5xZkiIl|UztWje!z{#1e3qQpULz=k@f3!45H@L&jteI0cxWE8pc7r~)KDG`6 zISOpQPxOk%X(vF#W#any>;iB>qYK>NNAB!hV4C3 zWdc0NxGoTkBzm0fW`OZ$XqZ95s|it{p(KDi*MZYB!7;(3v4QuMyhizygnYDah=!h- zj|pZtEf9=kVy{EP<6{c-YJLX<^oxwnRK5(!<-2&5LQTC{j1g18Oe}J{V!CZp`C1Cf za^ASz!&l%wgInH0#|fq(aZT||JzAo-;|&b006Se;TvWD3p)3Rjpv&@*-7k)+x1)FW z$SURcJ+g**xBY^Gs^q8)FJ4bBd3M<@-kiF);!1QBdpK!v#Yzadk>fcZao?P^(MA z9bIA6I9rG4$<}F1**cBBoR%85Pbt6BhNMmWszv44*7!|RrH$cvzMNA;0Sz&o(-$F` zy~y1f3aY%*@M&~qY51y2+f-?5_=D%gtHP1ss{-NIZH){FT-F|R63K2M35!7dLyO#_ zuX_1a7r*M&S6$F57H|oDT3ZZY$#;|mi@%|aFw20l^t*jLgP)dd`)OY3^L;tcFKi!s zl5B{Xw1^x#ZlVDPvF$xYy=5v{T)vA0oBGh9Q^^$NOiL6dUU6a-m@Li!EZLmUT5*;7 zGVDA}5VW}EOBp%)th#8!BJ)8d&D94T#uayf)R;2KusgSy%!w7~&rFa$<2G7SMYVYn zCepz*BHiX>I~8eW!S?mdIRx9E2Inr=-faM$6l~~N?8Z+DwtWZ!R<-5k$33#wz6tFBH6bK9dN z-8|4xP1|g(F>h`Q+&H+SkD*1LhE}d`2wJ$ff$31zk&Y`oB+zpkGtHxQ6ml{_W9CsR zQJX^{Yg&wX>MKa zWO=Bn(pzP~xD)1WvV_|&L2c~y+H4>9phx|BS;;?^KcdbJhM>WvEt;TZxwaX+Eb++;YmOq+!d>uglE5}airUp9zA+|o z4xj&a~H1ad$5EkTGA4@dM+4`=+XU?Augbn07n`jHfD?!nz(5a|Ox~fM9>o&^hBiXeWQo zJXYqt#ldz%S3cRIcur7breWRnW&!ZS8dQ%o<_GW4tC$tO-YyZgTqmh(l^kG`(9E{aecVYjHx(j;lfuGh18a1$+GPwc0DmK#@;|8fj zwmq}<_5^*#4f+a$UUGxJ8tmQ1qYQ&Sx|z!~yJ4N5W~KTwD>$G*+^<1Aph4WPL5%c# z4jEp_=8^&EHz+_Dg@gK%c4pe@$sTphkJwoDc4#S1tJZlCgCLx9JP(f^2_Qs*W7Q{O zP-<#u*mXLi9j7D1r2RUrK1_T`0Yl2k&tMG^TMGWii@i4?N;xa4lFp`IR@i zF=Y+iY_sL0s=QeUoQn_BpW7)zGmnxtc#!d7`ssL1)Mut)`fmnc^q7d18aZ#X(KB)k zQ1W9qdNj&F_g{YyYv}37eYF)CaWLrs--+j(1?R#T&ex3b z@MW*s%JFV{WX;W`?oOzcHag$hi)X_+2Rj|d*$#Hg1HlV5QZmTqT2waXTDAZltt7H7CJeU6MTs!ESnh=dK@<0+ zfU;8H!L`-|t&vvMO07z#jkQupP^WFI37VyZH<}XONFm+Gw~lD-<=fgtv^Gz)b`T9w zImp>2ifsTb>|8ltXos&=Clx;cq&nx|b-@ciw_F&Y2C~XPVozw1VT@$p zE(B7AxMeALuHIpBlUimqu8}_G5r5SBn3WdO$7K0XCBt%`NG03B*)zZLm+!x4j(qvjI9k*3HuW&;r6{8Ym^rx;xH zi8+eF&)piM=ya%`m<#ny@tm`u9$utUBGg}vyjkSFYWEz;{lItUfODx88TAqMpZ0jp zS#Ul*hVwOJm{o=tw82+|p5uhsOi>Z%;xkTHujA)nz7~$KL%DUI+A1=^PZS1Wd>wL5 zNtmc+ECQkEnNXNeo;Qg8rbE#$kr8;u%0*g$K~lv#MC5{JY3#O z4y@vh#kA|1DLIEQsb^=!#3W}b(N4B-Gn*2IJ+jwWv;{*HDwQz_m$7_>Qdmp^pS2II zP`DgdPya3YlGlh@N&>Yg=}9d;lUhtj6Dq5aU;_4(MJ8bNO)~Ka!a?zlV%D0Od@dHj zz&!($gks3-Sd5-ojJTgduT8^HqY#`m3hy8@EkZlhDAbFvx(!z~%2wXEMqwfvg-I6D z?ShRFpQhy%7GvX34a)p%Zv{hp(Xkoh;Dj^PEkz(yIqv{M9^@UU<+r)L0|^P|KidfK z6UcB7Qc^nMoTB5NL!EGb1c46}&h^nDr}d_Q)DtB|LO7fn%eOU30g)y}t*sFXNJC9A z%4kr>D?r5&9AQPm#p98Hd!R|)1qOVl`A`h!v;DAdVwsGOa79uFlOwCek)hd<0ooM8 z$#aJ68OYHK#cuozc6%h8TNSz20e#5U93>TvgYCuGXzomaPLFsOx8w&(oup8goF$!d zmUO8)opP2SJ)fV@Sz`0$ZFUv`)79?g1m-~nIR1FG3aa&jnK~2%^Hmo(eASH^u5330 zJ}M&332b$Iiq&!SdOEhin)_1m5`B!d!2bDt76oC^zS8zgZyNS(GzNu41CqYMF+$lx zC}ZS(E^v9G#a^eKkFncKx zY5;}uY}5yq9^6UX=>LLlB8R6T9XU*T;mBdnk4`7~EWAwX-~7Pmaz4C#5O>cvV>#1_%gG6xh_NWz6#sGqFmf3rd3XmhqEja614h4vn|+*K zO{5_N7jD}o-*3@l$JK!!rE)F*WdYzPl0kDK{Mxv58{DfihXARe-bH2m8=_FiiJe~M z>&C>+&R42xpwLw5p727eXpD{(qGMGusEDQrez`M7jp=l`OAT(+5v3P3#&f3Aac?Fa zml=SVUJY+3Mqan|{*mL*d;ZmW@W%EG%IE6AzdcVMrBnX+c+PanXZ7IE8360Shauy^ z?7@GVc(gtEFRzIA;E#R7)gGJ!Tp64oM-N_NAIOomgP?5kLIMb%Rw(&(!mI#lv&M1DhGy+fr z$JGl##@&OEW4lGQyY7X$oxFU-_`Cy=k6hjvg0fp$oGlTw;MN=2_k6aA47rw7eb}jW_wpxpM z4hc}E0tm4^SdOWcW$;%o#WWDM5J9$t&5R|&AKk|>w%kvYxvA%=ug1FebZq_Fm%HH= z*FAm^&pFGW2n>MZ+>;=^`u$Ss0$5%l500OZZ}g!>RH`GDFWa$M+;qMim;UqCn#bC4 z=}aB2DvHL%iQUz=(44?3GF+o%EX<4&Woe)ncJu_D90nM$g+T|WgE0>4Y`An{I@pC} zbomNFGwX}$-^c#jO_jG#8bfzYF+S|3mCrC>Q=IiR9pC-@x|d(~>m?Qg;p<*;i!S39 zvKPAe)^UqL25WKY61U8evwN_JLx(vBWH!-WwDqi+6j-9l@*1N+Dv|6=)+W^Eo?w{p zF?I@rArfI2R+$lD7!fkpe?^kVo0XV|-3X{Yc7kTR`nfw(NG}spJC`ASYA3r>Qfw;` z!Vd>+cey>Lt3_2XbJl1|7z=kbW^17meXdA-+^Ixo0}U}5!o2GN;{`#r0WJNYVScRr^E0GYJRYF3j67{IW?w6)2F&2IR=m7Kx9q|#)s2KFA5*v`CUkaBC zXRx6N=hFe*lqZE6v z{sMIB@a`|M<FuW9C8>1G1$mI>`YH!rBMjkM07|P$t}ukdb5&(sJZE}Uvb3?j zH7X^|WI#u6LgSHQU1&TiK-8R?=sRha@1#k-lV4beb3d0?BfbeLO zwcN>%`XE(|{ln?e2V2jx^=>*n!2kQA1d0u=nC*5>k52T$GlQ;dr^hcfBwuL*SJq*N zp(l+Bqyy`gUbP3mQQ=(d>dP8p;aEw#CrW@4C0EaoE1de+nZe+6h4=YEivt$>W3&lX zd2lTlwiq4wjmn>c$7c+T)0Gcn8Rd^nSN=L*KEGT1)u4YtFh)!+5GBxI`sw=#8tM3v zQ|?TJeIAWlLub)c&^GewN5HEtXd8J2etqwOXP`{22s@=L;$!dm{2a!_gJ#qBZe(i)zqv~kCaPGIoF+g4oi+po+mKwKfZ7>Ur(x?{2TWik0<>AH*Q5Dbdy_$=N_5 zs*sQd$xx(1V&WdxM&pUlgBnI zc^YiY1CfVqT-rS4S}Ao9aMB(n)X*W^f~({DoSr!|XvyaK6B^#HUG2J4i&GU)sU|S` zsvT3{;bpscT~+cfyLrLlil3u_?BTSMLq=YN-czgWB z7Q`vdp^k8~B3~eM3z(n2zyX?r6vhLNn0+EO26QGrkO1@=>0DejF5Trd?YaP+i} zE>Vh#y)C5M<0#eOD8)C4aQ=%O{^%ockknDyy0y`ewsj-ir+n&yx)JVlzFpn5e0&~G z;6AM*?;~spPFMA4b@~cCLyz4wLHP4*ekKuq?sS8{gTvY;RpEV;vniaoiOTO_Qk%#z zR#}s>a6>3adBTtFV8Tr7396M7u_3*;eA`|PX?j33r1xS-Q(=L*r14C16ZV9s{ID+y z8rCqO?ZE(X_BvD`7zR*fLbd~DBle&jcs@6hG>`SY#h>bWYA>puiiZW$m|7Y`!2@APNgcWy6@AnZn<2K{cdZQ?q zGEy|hkzu5~=moABou;Chg7?I8qP8(DhSMi$GcJE#B>;|NH;7|%R+E&)Mpi)9?iNOO ztc<1QySt>DQ(cZ{<1r$kn*;|-<_q7ddN7Wy@7?QE^Qu#o?^;RVAIR@fPh)uugJ2?N z+}ZhRb||~eo05myzLF__Q6>-HOubQC+{So#D$#GgXkb#qheg|DWTEV5hC!@i`C7Xz zmM&YGCuSZ^oNupWXt`&$w(o@aJ4kQgC6Fkx+-@HF*4T-a0ro6kLpD?SH+A9m7h3nR&_0VH0j_8h@>6c=c&au*WsQ>B zhSkNOn81?UbbE5Z>1i$&WTrSJko82CFO&e`9SqC9=iCtOE4T4e^Y5S z3o9qUXs3qDcBz*^Bo>JgbFbZ=%3fSII!1gtekl_9CK3MI^VP&7XGtV7FGOM=%`PrpH z+f`@>u6tae?JN}XlW!8?TU?<#@>!_BoY=n>htT1%Y?nC9;)<7}?QDy-qt#1P+HjNxh&gS=q>fp)C0t9k6g>?n{dG zZLYru9lj_yfeu8xv{mO#zQ4HAYIZDP8!9*#CkFuqSFCpTmdBcjiDYFff5IPsT|3{~ zqg+$H=ymc~vqj(*{tt!wFuKSfGsuaqL^<#gU3Bb;BB-43ZQ=jy&{NDwYP{|+HpNQ*O7l=Mf=fQjv|Tt&Fw-yDWpWN*bwP3l9rT=Qq6%HT z7=E{QzyD1ejmVNx24pwptpQmue9!NX=5-ud!cn>0u88jQ|k_zWgNC- zDqa+CGcNONRo1?qKzkFy8CV$f(WBd6gRMm6(e0NCvfKXVk-H|)dTie z$LA-QHEET5y#*6G`Oi}WgdhC4b#yv@hXLKsL09?dTnHJ3g#@8?`5UW&WdJ&aB+-~m z^H2u)n4H?7oZ3i7<&lm>PK)4;Okm+-BK)fzMPakY=tEj#3Ik<=Y78|Gw<^*EV=912 zh7P=q_(PeKEO@U9o>akmRq&(=Mmh>cdcH4Z$a?C#uaEUN&PETh9WzXa$rU+z>KXBz zC^}|33<2>p)8ShN;K`o)=z8h}>ZvdBd?KT#zU2h#sr?^2Xg&2+CpdY-UU`svYR^aK z&{JQ1e2$))jOU!Crygzq)KkmHmWJ;|UQGsKD>sZ-%&dJ(Gi#VW&e!9+UZSLk5slnLt)YF*6ju)!aUn1J1Y-nKpP7-4Tkk`2}s@ zJpTna)39c26vPX5VPU=W;q8ru=1$Ou2hYe}XUBm3xIh{0iVBu6Mot=xXY0~$Q$PK< z=Mv+Z{a++*sNMcckB_h~5~CePT+!XnRa5N_2Jg9T_oahEAMT}Lx|jBtK!ST|c;v9=R@~ZF2Ru%41yX$J?emo-@5|vijS(24F7z?Gx&6KR?cun9<)JI@+br)Zb2u zV>Vq-t+Cx3HYt(pMyrMU$7{+ zwBVa%qB)d#2LWXnAxF){FKxSg7quHXlzx*gwcdwliHAe zO;~&G)rbb_6^N>CiV`?I2`5z0;Cys-l798sdPS2u=1Yvr&|AeAKl(v~T9ba4x%StR z{M3Y5n_^X3adjoMsD#$+5_s|^;=cS~gO%4@Q`~GODCqlwsiY_;?mY- znvR?O_L+_^#<|(?@to+V?i~&4EN=EW1K_yXRy0;p2iw_%pba#TLfmX2(F42UZ^X^` zVBCy%w_U&Eh-zw<+!5Fzh0g~&@(d*lVQJD&1pcN6X|sbl+a zVh?L!+|3S1vnvR~H>BG#eu0*>1l}-(4icr%N8-Lg{gsJRP<^UFDtIH45cK)k$&WEY zC^0E_U~;cMFfhweU}}oePF^e26ekI>f(UAnC2Z`{UbWtSoG{CA(_F?ZLV=8tP?;!8Hd75r;^g< zGtb3q&c3bX$2<7mOK`ri8Bl-z08@;$n8*cp(QwaZFx_G>KXSw{o)FE-f(WYtNxW=v z`P`bNCL$*y|OdxwTTB^rE_jm8gz#>+h#{K!pi?nnp}#}~TE zsZ&W7HkBk9r$p}X``cjoN*R#xo1fHip$K|^r;BZG5_*>lj;?OLfSnZc1(#R=27IDB z*m-Gn?BoD|;qm7JF+3W~JE?7iH7JWVbEP%oCZzR9C*mkI)v8d>+m?^uShiF|{Et<^ zw=7ZikrL$dBboP>lhcXj@Pxd=yd2+Hhgib(@Wo}m!LP=P(Pwb+dvQfP&Ce!o6-a*N zsIM|eeZI-2{!fJ54~}$o<40~v*mh3QAk~4qrI)!LK((ZnDuCLastr_?I$WJZtCd8n z%P#AuD(m&GEQVTD>6kLtz>sK!7$+q)5E6RiM|k0jr)8Wf9&Ybu>0`~V_(m1qlwJIQ ziog3AR#gOBbIpE(ogQi$2#fCtT2P>8uuxKbtSvku?bIf86j-}7kT$P*wG;-ei)$B1 zsBykjDiQ2cC?}oLS{{Sw=|NTJFkhW6A8y5toY7!VP2f%S4F>fF>Izh(S!1N{QV}gr zcN80>e+82dUV`}s3s`-sAT1*gtDV|J0>otx+exQfMKtUM`M#fRY)>j)86VU@_h(h zWsd6l{VL*WUxZiJMVA+->Tvh=(cSAT8n}D=Mjk{*n!2EGg$n-~|T7R3BbV(m}K;2~eoS5Q?4&g$W)C@2k&&QcIv_5ePi; z>lfcU|HgWJP`-;-Sp-xk*l%eOFcC_cGz^Cw?`093!kd_?moYSMX=h_893?eC^k|8G z%OL|peI^y_ZRT5{R3R$D8}ZiEO;d#VJbHKewt~FUOF<`hx~j!$In{+=p}IWJVz#Kd zoQ@Q!E~{_@)#Z#uYQ&M};i%VWUEWtwajbtkOs_^;S;XS%Pa!e3Y99wV!|Sn2vusNa$yX?y&6D; z4#68DMs{XUusC@MzD&xF@{8E551G2dYt$2!gbHmzBKwe@*@u`=3uI3wg zJ))kdBtR)~Q1nbFOz=>6ub#LWH`Wt*N841tQBMq}4Yt>JF4%q3NkZea*rO(m}}E|p4z zE6wAyrzZ#vkAk(F{dH%zjxmj8^6b_zO~;M*1QYhV;pQ>d`BloIHM>L7rL1`^tPP-pgFgIgPzjiIx)$K9fA&Yyg}*u97^af^X4>o_~R8 zXlh;~E~q5%FA8sRK|PayF`;G$iRr@7BQAJ~(s+%ypppP(1riBG&xFDR4~6&Qf&^+@ zP~gD@^&53(xmC({k-U<}6j$nFkjG3cazfW($JgrPi+Cd+o_X>z<#7cFQd7xmtf!|E z{ay(MhTWt`ih??_?h3_pDUa9St!=en@|e#IU_T1K5uwiIM^1Dkl!4cX^hyHJ)*_Ka z(=&<21k;SXmqd{8=|;WblaU@?ASLbCfTXxKLoX21Omm38@s8hh0<|7j=KxR{bO7*8 zwpIKzupsPzWTVDMh)Zch4bgZQa+-Np(M2S7QA|5X(p2*@lxQObX)sDGciVg zfHac=5&5inqJOe-fCWA}&4dU2g8BznF&P$~QcP-b>l&Z&(^iA&6%(uQx;!T!4uoQ2 zARn|&UE>sv2I3S`OiYvsI|fw_?4OF$FKG~|I1xrzxJM7O zE2Xj-_o5OLJ$cMGln9@ByrWVBUZ$%y9A0Uv4H;ETwc)^nYV)T56Z<5)D(wv)dYg5f zTiEeps*Ux6zdWpOsoIbadhtoX)s=O~;Rdn`yJt!?A^0kTJhN)^zYnT_NPUrN^YnPm zg6JI~WlacPZvdWjH9V1B4Sjz%iGF-sqVJSMfA>Sy1LLlSBQMV_(b+{4Vbvep2(cc! z35m|BknZ}3Npz}>(lAyL!bRa4!zU%tfALn6=-0$0`f(CA{WhFp5?uoQbrR?{Q2uEJ z`ZAE~v2`^p7mYXDAoq4U0%Ho!cQU#$vVNyK>7luNTeGa+CaUVRM4MrWGTMfY2+rLv zWHsV`fvjC~D4}Mwf?GUpsoe%?1rL>P8&cU?dcm@XPh865EL;Cc-fMKsL(6}}&5snwdEvIch%q`6JMBXa6s9lgQcVgpwN01(* zTL7zk9yso>)3(~Xi06;c&rTMa~(*ha|$QvG@Wv`3`(9!7c)1* zm)}H;?EH{H;|MtHb zC)^h|!>w-=;)C*Cyvof$tyByIZU!b6S%ip(E2WjpWHa8uIKvfN@Z*}PZPsGlD&k*o zjky_8iEs@otAT05eUByu#3^)FsJTkI8QS$Fzc)7npLtwB0>9PLs*UCt6f|m-!oVJK zGtV~lV17e-L**mmdrsFJxbIQ$k=3OO z&xLZtvMzjr^Bh;J3!hVU>E>JcN_<_I!n*J`stX@7>Z0%FQkQzwh1XbJQi;`-WyHae zq?e`2im|%%;ki)0KGua#HTvG_!e_dFuEp>C+bgf*Px$IfsKoT+-Upp5#eE_?;zvlK z?~;$zG5~Ar>RN}?gqr_)mx`GZVkY&4Z3OjY+XE3-*~tRJXQ3=I7UyjmLYlu1d9Tnh z8%M{Eo*Yf~oGRh_$3F?$$on8A?Mn{TVdUc=Q+^IICOB(R&R7eHuReqSX;iCuC{0W(bbk8*|`+1z4x-c^Cd)3HF$6yP_`D*1oQ@Cd8KvgHXS3lWdxph?hoD4McH~uY1Ye}ClIIZ2^iVFxrwI8K z4(GCT?V`esMdw@SV8n&_)+DRG1EKYslC10SLHRCTC0W<<2LCvr&cq_;uNi8^aN#=sjN`bz9q|Rk|oGfqmaYx;`dbxpEf1%Q&=(Z3sf+wgt_!FqLJdU$=CfP zP}e3MlE@U^I98?#(yq9Q^hVG^P-S9Hv$>e2ji&mhI}4CG?I6H~LSQ}6^oqg;-K$VH zg}@ZD$Bq2;inoOi=<4@qxeV`33AazBhr1(y1Op>A$JFPG)zLmR>PBe_BNJs7O=h6qcUg*4y&YZ&S0GHAxqsuW-}r7%x{N ze_VjB`Mprncwt%LFD`bPIeT5%E=uqP*k&24%~GKeR;$}=sEyVpD_4=y3~aP%<|de% zCPdJknn2c|fvX~$*m}{qKVH8Lnrr;Farm0sfCP>Fx>;Yt00!7b^@Qop7lOm2Ri-ER zIFQ-fTEqx+ZV0N9MhW_snQ8V0lk<2NtLs3~VjSp%N z$m+Y}0PfKk+^dDjXxBmhgg-7j(pwdyYB+A}ZZ-6i!joLCr9@zLcGgIeNG31RX&OQTo{tG`|l|0>AE8N9Z+{ z(93q~C9K(I|B=&X|4$))&YdeF;#3%ibjX!00LTq&9Xz@jw2AbX4Sl>b`+J<<<{t59 zsw3QD!z#Qu!HzJIt0Q!%B@;rZ6Zg4VyG`F%Yq#TGoPdc5OeNS)7k|Q6T<=<&k6O(= z>06ssMr&iI7p&Z)eQvEi?pwPK@6p;X`faMUC&Hh;My(z5l3Ts*_?f=LqQ$Gip(fZ6up4Z4SR?_~DhciBi;ByKZg0=`z_n{prd`<>!Vu39cON8}4aiL2ApXb*} zMIa=?ypI`McMVf-8ZNu1)J6?%>a{+D?dyUaysmYHNm5V~!50+PIFsNPZrt-xtZE$f zA(szoG3fn)1oag8rFGEP*Zn#*%*Vp;RmRjGLOVyc@GHc@erw}s^ef@V@DX^JC%{S- z-14n70xVbJCww9Zpp>MHC}6uv@28TP1Xzl65rEc?2*4DdA*nEvMEK@PSIgCSna15z z%avkn5cg3n-*!)`mJ{K8t7VLttyLBCTov2=P(h0nc!ZYl#sVmPl)5`pY-R>Fx;qC0 zJL&wnGq5iifV2oE_6iGu3FiTnDWxfPL$Y8`|96W@e$6m@gv|!oV1bgWB;=;DOAA-e z=>AHO3V1o*gzm_l8U@psY78b<^-2~@?J`xcHEZn_SMce0=fXx6vtis01>*yGJ=u3z zu%1~k6I3wahOb8vbl$jv`I0P9!^h054M+kbw2&SEFhMO=UcPH9UdqfOza{IUnZ?8+ zABC#yvQf;;!n^pskeQs4%ChNgF;1CEbURqelAFd%!c+&=DXm92#yHDHf9u&;EqYzV z#%jsNs>sG_#gD4Ww^ikF!_45ivTfJRD_!Ne7*tx@T$fy|p1JCnt6sTe5-t8Lb8Qc< zs|v0y+jeb?ab~OKl5M7z>yS?6y`gN|4Y3kiphQP_D#*2&C7MLkjFa%ZVS8|cD{*l} z2N~z<&LiJw^@9kCcD@!wU^TQGXKwdM4mHhffDvP6qeFFpu<4@6>tx{PTu#uWi$i)Y z>{`klmcld`OMIg+9GkX~(CSqw{g5>*Mf(EwYj>wmn!lqBVV<8><6zSO31DuUO z6ILtyECuq3@U%}ljeT9LOR?F_Tj&-L%XKFh!v;f{9j^>Oa-D_|-gD*Ua>8}|Gkm_^ z*O$!KGzp+DWu66s(?hgErKs7#GRX#aCYb-CaN}JmPS_ew2FCC2K>I}ee!ZCCUxxJI zXmj{ke1ti>q^+Li#xQ6%3SCmPOB8JrMd@&cxD_EGK;3p{6t1A?9=2O3itZ6bLs4{( zD2jAY6zTa%Eir|BMF)5C3#GKElm?a3s#3;O$^_@{D6c2U@=<`c6`WKl6Dnm=rA(+4 zq@xt1Te}e`D9Re(r#?M6e+z8KW2_j~co zM=c?vF%xgM(`4ynw_Ed_sdgI(i_TTM#U$8k)o5q`${OtpJ`Rzs?gJaEP^PZ{O}eDp z&Ctc;e)8opnKa${m}3o%NaY5vPJ|odInfA_{XiD!yxa-XhbO|2kXx(g$fqsmvn=$lsn?s4o z>{Q|$t()*OIDJgg#Ed9thSVLTs#1Gu`V4l7+WyQ>wrcU>3`JSa4Ht`Khx4$sl1oAho3bxYl@*Q zwt{C|BA}fqpk;~h3Jn0f-I$t2FqJF{Y3j{M5oa0XSU? z`@eUHDyncw3+sQ#Xcg0Q-W11aIz8uieK~6L+<4AeYIBPLaBAby@Gy_?ELzxYc2LmF zv|gJFyX)dPXTk0%Y1nNF{~z)~U?+LbHAXDVC746n^s_g~2)@3UafEpTh^#S&Euxe; zZwHNfqgi?r$)F#q*Ci$>xwpVLQX~Q=$eP=d+@_;FW+qLjyuDP-QQjn#3GDW~khf|* zDHB<{Kojy1`rwrX;XCcPpcF}E@IlvSPep&x5to1cQH};bJ)Se2q(eX!@r;XVc;xd% zn0{zC0ItC|g-0Xr!6fPDFFS}NJ;n}~nwg}Z`(X}}-uvQd)qyOMzS#gcl5P!qkoPeq zsd=_w38GCUGJ>{5_{u}HcQKN%sVcg!>%#xH!OYQ zRAaBt)rDW!n}go(j^~`E3;(G{03v$74tWngz4soPlis&qdJySd_@X(``+K+Np!d9Z z&ROVvjR6q7uNhlSTi8N2u>X^rf3EYpPSRUiM+PY$Yn^x^_EN%!RjK*sdhc6hoVa|e zwJG0ft-eNJ3A#^(si76*s1=0e)KK|Qd17~iyw8Y%Z!A*41IlTT$C+;KxQ9GbAEo!G z#zG~#7T*>wylogx@>HVpW6KK8CMvFDT3bd$;2RGYKy{TX`q?^VQ~Jv#Te>AY%Ys=ZGEfz9UCd6ob*wR0;< zgz~%e`x>dT%DTgLltoSTmLbq9e2+@r<0l8H{wBhj8>BX-_aSx%TUF3`)Oy`NqSrwa!lkI|Bf{1yMCbR zkMyvAFa*RLxE#tP+)vaoF`;ay_K9#ZI4%l*eOrofd%~+uGs4;EwK*`Gi_$6$$GqG| z81z_0?t@V~2Pma4>}A)_P{H0~g+(p`SrA`~=fs$C)&=ustuK6m0f^PV)9T-C_0L0v zpJcW*PcqwoU1qz4%=W`4&CG0n{owvE+b{1*@r>^9Jd~AUwuh+X3})Ngu>Z`q<>G%l zv*i{NiEwk*zB1eQbfyTmCp_ZBePy;ETB)2fGuuO~u!y0G*`6EEISaGx{*JJXG233N z|E*U47_+4^sRJo`!-XgTItAUTr_y^Ev?Rh8ueJ7v-&J!4k*^jmEVv%1!E(|Ow-Vq3 z;a~pUNaLa}!>{5Qrcw%MQz9Hb&jD?=d4R}Qt9UB~YuR+KKOp6%7|@x6G{f?3p;Wa! zsF$L3!y-CNh|V6WYMAnue>hV=qrkO5=9qq#O4Mu(vgSPdqucaMoc$4YJ&)D(;Y{>) zKe9oUb-`Q#T-9Sf1x9Nbj8=CN*HfV*VKm}HxEYb$fK3XDl~*?FBqybvE3q@>N}QxC zk-FJbX&1DqAN^0NpH75t12*#eS*5#8<7RU!&fa?|-JI=j>`#QNsX)HnOB)2CdC*Nj!jy!Yc<}QGKYy!@d|M?W*6RoV^z#UJ>`V>*f$%?% zcY}XU^9c7nXAXjCvlWm&_`e*_Im_Tb*#N`_|F1Ooe~y?gFsjtx=R86Q0H@C*eEnik zMcl3+isr~Mk8o5RCwZbNq%v%po7z=qdTn+ukI`Y4+FWV?oKJ3L_{v@q z=a>D=*K?5cuH#}k(@C1;2YO4ctGoAg&h>gQW^1~RjS*%#lAiaq z93;Iqo^uwG9%=v_Nw_`WaQ#7~_plxBGc{@*$1{rPy# zS?K*d10Z@|Gqyof3km1|&j0Ra7s}v7Hf!r}+|eny72k})f+?dc(~~&`Eet(1(}4Ma z3NxvYvw}J49c4~UC+NxNl;0Gy4ssRB{jEEA!0i_$x#@@6@@=)Utg5_aRa?ZxwL3}x zoHHHtgKtzdE@O&C-)BU`w8;z3Ys|_@CHnQS0u$8r1obQn(iyjCa8I24$m zu_tIURGSKeMxxqe#-yRzL{v=`ZB9qEnW#2LGZ4)-1JTSGh-NmkBmT6DPyx;@LREFP z@H*_aWtI~-vsxXh7O$~tr4l*G?=Vd*(TdGO^p|hzS1;&hbvYH%k6zHtK&T+KWm6xH z03#8)Fe7905M9__pYsrFA~f;J&I@woX*XLw1+36EE><+ ztT_Drvsm(gcjTwXt!Gach*87uuy1keKH%DVC(*P6jGP%GFTQ9%M}ER^!cRUv#CoPz z8pqUn0NFlFPX#)1hmWLfh-tfy?DyOTAwpopwECm40bL?|xK;EVc^}@JpGd*!9Nnq8 z4aP!gsk>T&tOIV01z$|H#6b92e;QGoy&&EXROwS?jC*n>Gim2$`9)QWEoX|M=bGF2 zWJ?Z){);6sRR^PSrn!w`0}!kKQmg-$t^P50+mqb>NpAlnx5vOe1;cj+Zm+qJ_u{Cd znYjJWhxdouf3`WrW7@+)cdU|e`v-C4&=Z5(_dX7|{R!fBi@#vp?$LAmXWpD@3B?~f0AciAc7-WbGA>xl$tK+Pb7oEM7ZI3lKd2;oW2=E>M-_keGRl6E+-m> zGJx75>T>e%SaoT~k5SjmaF2cXzj6@jyYZaqVv###rbS(zZ2+8IxiV}JS23_{Kg2wNluQM*#}w$IG0~H}bbXsJ!T!jH}7V1h_sOzL}Nh6gqWLBlc zS(%+$U=K7nH{)Y2#l9N9>{?1N%ZFzxW?Hs1TT+%SpEzB%lQ&a42`jw+wdxkAw@fx# zP1MMEI%B4>OM5hB?3#5-3r0IZ+2PZrFpR6>CUupNq=Bu1c{8<>S;LDm3P%4E24*XZ z9H_T`QG_$srrSMghmp@VklFz7{;UZqwwab%NUd2KddyNwCHljt1SY6=VS%u23xj&v zUJYh}n*rKD15_=@UHpx5ZLq+s;Si9RwPT2HEQGjmW7&!>206BaW{CX5q_4u`f@V^y zv>B@y!dDji2C_Z>t&C`S4}%_Ib74tPYI%=~8`QFFo)lEk#jiT~l@LQ3h@=uR<>wI@?g=!*j#>4>V3_;2z}6iyTYnD` z8HyQo4w2J5B19nk#??jpX;uQ+ss}!w1!oiDqWP+-X@8#@+_dtnaOkU z0%Fc2nygJW5v|QybOk2E+RUWTj?aifvirmE1wafEDE#Z8L~uMELDNG{0ZfnJD%@uy z$S*YCqcF-uxCa;u!PD^qNt!a`5s~mz7`)QR`q;j@RirQ(^9?a4l5WZ~rv4WE9x##AbjGwIX}!4b*`G4*`{+f|xt~x@VLu)Y zPw6Ra#xLx@bg42|k@Ql(-QB*3r1_RPTO|FcEJGxnZn)+WNyQ?{iJvs0WQe5lv87@6 zBdVYDRmAYYn4SLu$x)@i;zi2Y4=N=k1HX?<5Va`KS)SPP0s1aCFag2zaoP(A&PCxB ze>S+|^RnL!O-}y~(I}Mb<+<{GIQ`u3?=NdT3qQy*_L7W(pOmq=W$Z=g`38FI zWb9905i8?K89PTA+m#e!`NzxHGdv=av7ddAOft+R1ZdQG)1nCX*;ZAi+4oVbTHANC z@1|N&$jR8305KX)k4zH517!C7;WUR}w%NB`;^gj+snmTi`-W>$*pG)-18ZVmB<%N5 z#=Zb19)P5`&0NjC35!_Gma)(J_Y4`^Z^sAalCd=+$`3wjM9Gk`j}MV_**TsY9b}Qz z`?BCMbfQBo=%UQNLmvw<4KV;N0D^ubsE?Ic#+h6twTg2DgQ4AP$Zpy(*B5~ z!wfMelD=T)fQ9eC?*S7@Up#SIk@QJ%-}9=C`#yTJ?}AF@bY|bkpY#-d1;6`j_N|3| zxX&W#Fw2}Rl798P43Tt};hIY%eM&@mVU-ajLnP7cy8~we`Dslv`wp`ccxN*E`s^T~ zl-aj5tc<}iWAXdPtMbGjwj&L{znO8DG9N3_;XFP>q4b|UiM;$=K3BIhU~pH?P5^N$yi*L>I^A`v-)GlmYB)i(H?{SlGjhlH3DkrhCU zcF$TNcz~?7GdzOXR@>Jl4OVt!BI&g_KL(k`thQq8U=3A5Dbq~WJu52E&ATlPe~M#%y!B_f z4v*kWYqk9ZnNU>9`m;$t&F%fi40C&5nPF~^F*Za$*W6xWhIa*frq6fX{nNjDWPJK} zC;cho-G(F=h#@e*0x^fNE-DHt)TS?Khiox|V2JA(2ctE7gSIeEd)8~i85e0e?S3x+ zVf(%GE6Cc)9TOVk2m{l`wBx{G_4i7i6>Z73;7~4GdWGXN2o^(_DffeOg-!6h51tM( z;ZE#B=r#_fSWt{4#Np;VqtihC#l{%o^BgvLjNqN**_=2Tk+kVba%UR16U&BS^^a7P zZ?0uazkaViN)Kc|E}j$EGYnHm=Gc<$CIjHQa@0hFJ$dLZ2tvzfD+Xsy*H+xO^58Vl zA~n&??{jrO5KUwt6CUK;nrP=eb7-P9@5#|bSH*MA(nJrvTL3bfD5GT+xjfzmTUDS<8GLy=bBpeqaILA-6*>5ZIrYq( zN=PjHul%!*pt=NH2qF=_KQ9fJW+Zy(ErO^kAn^?$>X{IgKwOIWrm|Hz4VO0M)D=1S zhB@`joJv5uZ&tgn#_OKSHMm~QcJCZyySL*}?asH>?yGngKIN&gc2|-ifF6-vlMa0D zaqGl=O{K2DgKvnBo{5hVT)VU2a5HdFyRYP@?qIboy6?udrczgc=wcdv^-NGoz>TdE z(K_)OT}@%brvn6l8usFsi+uFVMLtYmH<{YWI~*^EYa+a=Agz7+qF3>~r`enNhN$%8 zmxl;g0^4Uf-&77Nr&VHz-`HNu$iX+vsZ{1vLSiA2xpJlDPlW${WEvvF0%xH22%N3} z!#4z{XM$4#5n0MNT9e}k=a_QpiX5TKsb}U?0&Z*+5giU9g2BnFi_`EKN1`ubLQr)D zRK6iTdL~pQ5T63R(aI8!&tB!!6*(qdPCYZH5*%SpwET&1NBU@{`sYC}q$a5Ckl8|f zLqwEHa7rK|i-gD`<=most_iTiZQ~Au5#+l|WqbRQ^)sG+bcaBd4y&!8gpQXXaD_Msux3^CXUy?x_SCQ;i(W4-9ZL zFGn7YX1=x2JkGoD%tK$Iz*SGH`&cKBfX@C|FV2EQ83N?`j8s}kobr?t;oexn13n3HdqQ>mlg? z`LT&;`si6Fa0WUdaJm8v-w>Rh2~G(_WKf8#S58A@gL3MM9DKu^dS*@~cxuA3a>JQ$ z65%HfOQXz2fwdwo6IfjVj&BH7&jhOkBGfO0E>})NXp?g4iX42yoO)(XC8UNk^C!aF zk4Qsgv%neXEdr-2!0-*h>6ze^Kty_lNQrV9B3qSHSLEOu=F~HDDj{t+6GS4s8{w2kv!!DlB{u#ccx@omBJj-~siyG%p%5X}Af#G7Qf*x6iCnF$N}F=EB3DeOVunO` z!r#+K(Vna{KpkAgiL5#}p+ouGkv~~kr*b-dIbB$1$?r1G*X`(2YgOUnp2}KWhuB)R zKP5%Dhi$TwudKDoco*J1^?&R?Mi?boS&8s}(^2g8IP~$XLloW1D)tG*UQd|ra6QTr zVYUK1&P((N58xyP=IUpz0p;rVxe#^%riffE27ruw*IpMou7QRQ{4dc65t1v?%O#U^kRYK$!AT4)9 z){yzfls{BCoAi3zmqY&*%Ngf)6Z&pEy&PspgwIVcXA;JT0PUrDhOCp!pE~F1u`{d2 z)LkxvJU6pyFT2a7IE!osv#RCcSdZC2ox+<{O=;DVt+cOZ)#1QF-6$blqZU_3qH^lH2|vuYWh z!z+Hwc5g>wPP3}*p;)`G!dGZ_B9I7M(reOzM2}l1?jMa=^-SQPc3+8%|5&qX#ey^` z-=|s`TK%e(uAna8kji={m6gEuS*}V9D(4p658?V~&8pYgnNYrohXu|+%YZU73JCBG z5qXTws>9N~C*#6rDa$qk%C5kJZ-~zXe#s0Ev{`j_`e@FR?o%K{7UKS(npGG5F>N## z2$w~|Wr=Xn6~y2h5=GA>iW1mc^7Qpm<+R?iOgVK$4!&VdJu{~gFq%)%Xr6=!F|%q7 zNAss}p4kj$)o=bD8_naCO5UuxJG~|=gpc92Quyc!JotwA=$ZH^A#PTk2OKn-Ly9-q zO1>Ab5-42(;uHr;&jh6e+#E2o>a|m8?XwyMn#Fan&8q73(X&p742wPq(L`6!gl|Y* zJ(DI%U`H9$*XxzjI?4v+)D=1ShB@`joJ#Q2%rvXkJd#G4jRI>$$bd343gGyLU>_^9 z>Rt2F817~v(yzL1!M!u1fB@eR5v8(zN+4x=^>vAI8fCUBr>@AsH_WML=2SwOCP)y8 zuzWO)C|3)jpdTQ!YMsVx2MRN@Y9q(&Z@*7PJ-1o)f{ECGZ6lK2tUA#)Qg$P2u4dJj zQI^JL3u!jHS#_Rp%P^~+{j%xIs`@kn&eg1XmPe{VNIhz^s&6FTY{3CDt2V2(s?=IE ztFC5iz4&` zzL0*yPhszM)T+Bs4eXIt*vRg3Xcq=0^wi6}U)#X$MM{lrU4$x4@;!c)N=B)KlnBYEl@1O>IEnB< z?sFcqf4szZ$tbT5AZ&{MkT-Z`eLcB`Qi_`_uwZwVc+z zudG#0U6JElms8Kosf3h&oB0!Ap7%x?BI}UJgH8yXt^mh3L`2U7rvxHWAw@VPvO&nDrcEAZeO;-hEcqlA=u zoB0#r@6$)~W`Q%%TLey5fZ-d0(=)*-frKd$A|=XcgxRW`x*`YPFsGiGQweFKnIID3 zL-(c;V%|wCjZIwT*d%I6V_HumOqv(Vo4%th-ozlbj%Es$PVf4lOW8+mx z$x4=$2>zc(smvX6o}Q~hx_lws*yEnxb@97yeb?A7h@{(@=`*;UPuJ^VU!y&4 zT)#pud;PaVHNjByEzk79?)B)NL;7}*9(zn3m~qcd{P*ySVgBOy`N_P+*M1WU*l3>r z0)!Y=TqrkEg<~AyrP|H%>GYBpPe$RRm|jKnXz|`C0fb?MxW$tqAXGu5!T91&bUn2n zJ8q@|Q!5p&^_2@W7U{sp4jMoYJu%$AaQ>PFB`c>cK;?kn!ZWcQHyXhD7dCPV23-RTx(4WS4FF0kQg_KO3>IxW6alw-+MDb3hq7L;R&MlF zV2SI$ocV~KFnD@BXD9@u?p@5nDO z9?G`;EwAM5W!wIqSMoyQa4&)0d(VTIHFNW2Ve=glPWIx5_~@S7c3(ONMj*s{gI0m zfQBvxHl%}YDkzI8q9FMS3zF9t995Vg&v#0cDM7ksZu+_mMVZ$&w&`ms(Va?Ux>!)v z6L2F{u)f;Dpo;qp*P3=@`wZ8P{_gh5tB8AqX!+#4ZTXfsf8^^6^76vQuTg!e^E2S9 z@OdKq@*6ZQ?+>4;r&8kfK&2LV=J!g^WD@p2r7niPXxl?$f7?6HRY%lxd|min0EfO} z)kfJRM~`lZ;`<-cD1O^oeKOkUsoH2$^|sroi}i1=!PI)tR1-8o>CtY=EO-0Df-2Q- zBt#IYFJ%7W%8!619$cGEvYSKFf$N}x0o?>M=Ru4Au+vnJv~s(3luj4*3}{Qmtw!DL z`2{?+RC*|I0O>AFgg<{!UC$x(x(K0UVqSGWRw&Ht|JfuWn1u&d8mKp64iEJJi?7+S z0XH^Jj?-~XIX(w`xz~D8FQrQ_+Q3Vz=;)t5b^w3$PoIv~?bD{plr#QhSpo+$^2LEq zX?`82y?A(FT0@c(LvA$%)^%t##W26ky_#bFQ@B9mmRGnoP8H~np&C|2SE6uNvMfaO z4MZa%F%e$BS3ajI4YZ^gZ4gB|3+Q|ZB8;dV8}TJ?C8dlSnxCh5_1KSEeqgh-lE$X!`IoQ(`7w#*2y1p>Z zo=yeuX|<@+)TGN_`p?0hR{rT2IKUfP)RL)CLVh7p!I#2H$^ybJ+Ex^I3@BH8P=Z48=g(Y{1esZ zEEKptIf3#s48|*HqNGg4)Zw4013{LR9A8t~TXQLN;e1ta50(M_r(vI0weYy9V9)3; zdjhG>P?rmXr6n)KZ%uIlyjgI3ElzVn6XDJ9B7#0u z3zAn%Uh+m~e=iMBy*ZQ6Z#XKA(9iv=e@uis|6tr8BKir){lq2up_}%H=x<5Sos;OF z%1!hRoc)#FyYKVcB3SQ!>K`+D_qUPbiA(4k-?l%5elR_EPC`%9yI<3kN$9JW`0gw= z()0)ah*4ydL#Z7!0_1+;5`EM zE}?II>;4e>n9I|0=Opwrz5Crb6)ByK-1PJ`LKjTfIB@Qc}J95#)H{68hfD_J`1Cy*Vv+PC`%9yFc-n zOhT_p@7*9PNGlKyNhr^;Gqe<^Dnsm_xqo<%EJ**=t8Lnjv#J0V8A2^)w^TPg>f-h)$1>E_o zZyR2KFB0Lk*Bb&Lgs>zrt1<5i3V~k@Ga3jn4f#JX`1wf0m&2Imzwn|&_}3K%T?A0H z3v=OvF@V<|dV>}k6agr(_k#{Vy8&=iU6j^kZay!g%iPkQ(Pb`t{X=#*+r`(6Edfax zY@?k|7;j^Hp#)3a`M$w2J73pMQms}*t;N+k+7;)YpNg~9Ym(iP*m9P`&kSqszI+!a zr1L(I-=jzYl4$gBo7OL?w&2|zoC$a5_Q3g9$(Rbz#-g5U6#Jav#k*w!jvHJ1nDXUW zsJ^aPek+iKgq^K$#S&~>)j+x{RBFj{Yi?wEO_JYt;J=G2T6kCW`nwiR>C@3Wu#OjR zK)k#TLijc>7Oq{rgHG4ohpa}3(NL0Z%H20IM1kJD;dzx^iz^RfWJ7U&DyBgJ!sWX* z5#l!Wzy7Kr$_}k|?Y_CQE zF2d%<65P{Ux|0N%+DSaZ&*y8);-MrLI9QDN?q!1xJwy#FZo#T|V!vX7c&@n%I;rEH z6+tboh8VsFRzYnxN+%@3ghMH)Rao*0l+MT(#f3zbM?wU>NwG1AooRB=8w9;EC-gu2 zA>3GvD4t6zYKrTvHpwOZHS=pOT4?>J+Io$Z>YAwHHE91S;W2U%semDr>I*o7d|R{Y z1@ptTzL;iPH`x&lyOoA_F;HpRuSM@>2&|p*X={PSDFdXhdK3*IbGN*868_ zRS~}g5s@t;A4WrZTp$G)UZXZTv0svoqK)ib<4LmN%plB0;gm%9>Ej)hLyD10Au<-F zI1FUR6;I7Y<#1^Y)wl61PDv(Ktu;5E1uR7h#E3iH8pm?Fv$DhW;2hB5>=BaHB<+pc zg%70@WiZ2hAnEvoU%_0acIgo(!tk<$|`D%uz%)qQ!@S2ZlNKdV!=kPex{`-g@}8U}|M1za;_NTK#wt+iUuMylg-F@p+hZb^PHV z_hXbi&zGE|A0JY{ivKXPKi__%`tx1k9QyE{x%ABFya zfKq+98O-S*^J1yu(z#>2IF)$ddGXSj`|zvwvkw<1!fzez8tCBiVw8NAFF8jazLD04 zVjIMZpLT=e#mlX0AF`6a_gWVR7ar`ww|*JK?$5Z7SLx#+nIc0;LY#qZ@0?4QKkg&3 zUOS!oamzDvclmpv7DMXUc$rI=-{=6jE?+*j61-ljTRsG(7vkeDg`+`>Ov1Y!NO?ad zic05?9wicvO_he>Q8xUCN<*x^fU|)MrLa7xc+c)&II`Sp;i!QJ=-As2;oZFO)zW3HB+=W^yRjdx5Z{WcCkstx+b5D_;Tw`g zsicMyc*7Ktg()J7eFL=Y8{Dj5Zd*C6Yi8Ze>gF}ZPL(KwygF%q7l8@NdV&g5M=J`0 zGOmrOFn5lvjj0&@ow@U5lGj4_=BnRX=z>~OI07qoG%x({hiI78`7fb5Lzi#i0u>~; z;y2Pcu{xy1tC-EyIa{z?Buc0WnzekT+3B2((m9(_I_GNe9t^%Kk4}Weo*y*9INyHw zXRbPY(e`6MjVrMLAE-|*`JRk)e1GA^Q>8FrlG=_S5gz>$xAkEGDJk=SHVfOHM8UG1 z3t%yD*$ycMt7U3u0ykK;v;65|Hn5teO6$VTZH^_GstpUAW;cx(n%E%F`;Q*^9ArsH z4DFlXj03wGt#O?Xt9NZFZx!|ZZm7IkxY+F|&?yRZWm8~TBD~l@Y1K`Kf#YzbP0=Q! zp_kaegy@aPKUh;d;HlkD@(u}%_;zAmDUixwt{>vj>-TBetuLd0p zXx#&irK0Jua2SKRK^(>ppxNPR2?AW?ageCHprfXE$olT~B^X>B;Z;k}9nct9-`K|W zjqOGWSQKp|S7CrmUC=i2UWq7lX?#@0k7}cjsz#oJjcKMXs2ce<{Q4G~pnZ(aLMu7W zhghKBZo^ntK2nmls|JH6^RHYUzVIs1Ev4Q~qF_DYm!|e|nA-nygd?tO5Ef;|2uqV^ zdhCNSDCq1tz9Y;@5I@cIzRUqm$-eOW0Hw*dg;S+VFiesGA{WOSv~3jd;UoPA4DS5W zgBT5P9&jnI4t-f3zBP^r7#P+LXIJO`!)K|^v2iHVS7&c#b*?wSk)W-M1TF98g*_|Ok8(66 zu<+&v+;$A=%YmL?a7bT56AWQa`jQ>=<}QA@Mqjq}1Z_q7vQ^8!&?+}~>r1x%&Aqtwy393W zy^t+Zuj-TZ(Kg7b0{M_@m*I}GBx_gE6IAu#4xMik;XaNp$)LgpM{Oef;3au^*L2sZ zzV(n|s&8{m&`e>}#7VAZO>#BK!G?OaByHblIe5+W#ZNPKIqn!DQKVV)NClXD+>?e( zLrx|DV100gvmb&c@e{oG6JBnVeD)jIacVq67hgh(v&ZD^`FCDiL6! z-}}C2X7}z&vJD@73eWS)CoseFt|YTs@f`ZKT;DNt$fc0q)B>XX&b6@qdlC66STzuGEP;TkSdNt6*KE4Jq~ni zrEbHYi}XmcNpGj5_v=>_qz8T{J^Si(!83QsqWh(hnp7L4yy#pUnHts*0Bv#_2dn^? zMl92=$3&@;v!^p#B(p7&*;f2+{d18SNj900%~ziLB>MS9JAF+WI)iuL;0Hr80i0mk8sE|;;E2?XU7M{AkNnB2 zn@j)+Hf1A|v0%scg0OmI0*v|7m;kv0PGbTlB%vLW5PO5UKY0mhRAbxhO-5uh7Hqht zAR{vY#{M5{0yuG1^vNkqK>2%UK-rNEs{5$-j$W&itf8UDWwTG7HuE1|3cR7BS<({7>t895o^pOx{2s}L$ zedKx3`T8pR>q?)m(h7jP{ZRCw(f~N{4>IW-!atFDCIN60u&(qK;B?c!w^=@BZgt>o zVE`P2j{vyk*fEI!IG)pWBCK;I>d?n+lc$wLSDZ6?Bq9U6|+M|JS12|CknKZ9^ox zvNP5qXd4vkOtt7W4g)++OU6kqrbYMv_7Bve+pXXqRf|#;xA+#HD!XOV@6#8-yyW{L zGROpMCiG30Oo}w?B1ugQ&$fs>@=$RR?%hLS& zF6+tiebH?0kJlG5a@6{wci3*v-%E>d_!YHieeQXDh^z;Yc@V3~d-*ZY&pJW-#9{ip8);8)<{laY|OsXy_x{ z))ohebs;W+JtlWBvkUHGF5B&o1s}2ol>3PC&vFqZaw)q=jyKKoOjYKQ4r4sHF8cX+ zw$4I#D*xO#vXM&#%f&(p@F*9c!izl`|x{d?McXiS_lH z@cSGb7x=uqjBkns&zlq2se_ORAZ>-{DX({1^23-J4d*U)NOKhkH%9fvr#`3V(YF<~ zHyE8ZWukSeY`sm@3$ZO$T_@dQAr=&{SUBew3or2m?MNPg*j5pq? z>b@i#6xYmZWL0# z{yYeM=PyMGhwfO#Vdngw0MX5OTfls(ZUVvE6U%Wp;RNa;!)#L8*`~(X^WIY6wG$s= z!BOAXXVoju9NMyCv?cmbyz!yx`Wnm=nu7I}cSE1J8zo%&Ln?jHmv+q|RhEbxx}ba+ zb)cB}L(vB}KMRdQt^D}I-$~XDbG!i(hv6}H5?QO(%mK)5K+)PAdN!>(BHE>%(^%}t zL7a~k`sRXVw<^vDJCh*wajHS?FEb4bvVA8V&W2owzeRpFLTK;;-1Up#e(M6Di6WrF zO`wDx0*VS^%3yS+On+ugS7&OXvj^)lOuN)pC>u|fh3e)@_z(-8_}@+sC0%y%rX>%= z8y}D!KH&6l#y6Xol~@*?rXG$z3Se?om}vqX`nkj5$E`HP z7Yiog!c0Dx1b5gGA%aL$BwgjkX)Wx6TRgYX7VCmr*b}yJPU<&@G&Qy<;=5J6A>z9Y zl5b7bwP4v^{K$PDiWw^9=OkVIx`Lz7Yuk++`nB^$-E{=f_Q7Ze5y7Ed6K!X3jN4lR ze%8-NJ90nrN56LF2Y@umo#du7&rPRsqd5W%N~gl7HcRsR@#}@s<)L-Mijehg*iy%N z4?<6)}7!i>O|JjkWP#@ zHI7RsxGbSv0OQaJM!Im_i#one2u8e^Cp=1+2rY?WT;s(YppVtCT4C=HGq?Cr%+t)f zxR}2!hQBytVz%(Hy6I&Ya?Kd-rn$0)$6@$5-!KzwvctEw!kEH#JnF{Bp?7t|qrC>` zpaIH#p(K5`L%=PN!>KF#(ZwHXL*!Grh0ZC|1yzEvPajsbuI!t-MXDZd;B1OXMd<%9SV&OZny^Lk>(NYyj_4Lq*y$oD%$!UeP#Dbr-=&QZbq-pEsHbBI{#)ip@ zg@tfK$=7pEG0h`|L$~0Ox+q){O5nZ`(t_}h_Zk3aY_>YPfaAlK)n9-<`NWnLxyU@a z?VqA?!faz`kdYahFtbb@ijHSmWQH)Tg$W#kXLKfbx$zT;Yxrt=F|9b)hO9WBYGg%NoNp*z!Tj@j%Z(3ednt3< z3N_7rVVh*rv3VXo%7y?43qH67cARP6aRBA)f|2l+mz=;dkwqM0Q~yK|*R zcD1tgv-uR*?1RW+wzWDmpjeJlvEZv1jG%(tCE#XcB`s_OMKDWKV{>?jXJu}8WpLOz zj}?_+j>Zqgw?aKznlD}lbg9Fnv#@2*KpHdkj}6m`E&SR%Gj$~j;Q9#`OAJ5;gNY&h zwo*?M6-w<_Y8JnpRL`O9RL>UZcG@nTN~>HftqW_>789;*_o0Lf0EO{juV2ggU~4Lp zK1^w|b=0DDEW_b=kcD)oCHNq~^R2Neq9gs^7jJxD1ap~{sH=RpJq-f++%;}-8UpD>w%A?3v@gUX?`I>Ky=TPsAcLTex6#H34?lNdqN9Wm8`*-Eqke_FRc zCv`8B6oiS;42dG0i1RJ@uUqo{7~{`eGS`s2I}uwdt{shaEm-9opt5Gn9ygfF( z+b%Zv_Xl!^yb``yBIYmlcjFf^=J=Ho{uS87_(ekJC$EIN`5e6KW~YSP@hWfZtlL7r z++ttPQh>j9RnKbNG;4Z@kW~m9-WIQib`}DrG;j-;9-f3A&fz);Ob?}pyM%(Vj>GCi z4CN#TMG!wDd!0%Lf54~-o97_u_x#xPo(>nbB&K!OGxcyA@Vjf35-~hWBus=JN*Z=U zQ7rhoc!?fvu}r*LC>FfTzWSSnW=s!1`SOr9Q8bL5EY-vHKUhQ$-yAMktcNqDdieA2 z3xG4M8^JTiBDLwm^j%Qd>5%w}e-`lJF{IfP^_L z$Dft_6P$CCQ#-zLH@w|+K~qpgQ_xOR@G^WOQ&nK;;0?P?g&`B|H?j!^4O+goCKh6|%omXTE%7Phqf@qoHky9Bn1z!Ln zf2%?FM*?->90I5d@8-Ot8(p{|>$axTt)>(1cbgh})rHe5r7pY|O$S>Ux;abZl!Jj* zHf}()tjT?&B-h6d4@fxYa;=9`DjI-j#`WUp5!H($3A43Dr*{8G;=0Ol7($n-!;Fd* z&jwUZzU;aPjQ|cwrCJj6XcuYy+L<7OIuJy?Pv15wLRN~v;?RJI{h3u`dgP!}1ioSt zXN_qmNhjh>UEL~O+WS)K5;i`RrBxidG>LrpGsZu`zrDlh5?}K( zo|Pz7q)Vk+3OGQx?YoQU(l@UNm4r}2y0l>Kc&!0&9Wza!#Vp(Caxg;WLO%>Omh>>< zRQ+{W{pDRbNUcak;~41U=Au$x6Wfnnsv7b&6%w_T3KP>#^lHQ-NbtzKk?#@sv>>?o zhGul8pM(n(BJmV*WVj7VfUb&l-&Lslo-_3lH9R5rocu8SC93^0s2-3^y$Mw3KfO$! zrd-RVn~naV^x?N46TAB5pzeH6-7X}WkEuj{=@_DEj!1xi@L3Kn6ucFtuT;*Q+@#dO zh2&gFgkAGaDD$YE{^;_NAb&CB3p$;@P4ybKrQBJ-60NQ32JuPF=**4{4 z!HzSvc?E9AB#L1lxLp7?qCw>-eqHMvcC8ahLrb(ybdeY;?S9ayd<$G#XpwMn*`+^{ z4E%qIyTlhfU$o=%4Xvn~H-E=z4l67iH!d)S2yGI9o9Cd3T2|GjkUU>H{b!n~a%VtZ?v1vA$@ihhTq<4spStuLgcN z6wUV^D2nYJ;gW@Kw0P`$izXkxfhUqJ>0_`{nb$2Lh}-KW&gN`o^ZgJ3R(8lI`tvsV z4flbWrn&Pg6Ys}I?94h8T}j`R_4~2lU+t`BZwA~sF5lQv!X6go7O=O|s4Hgg1L2az z>~YFa#NOi_dz@93)La&|NzONe`poVnIREgCc}04|5?Kyf7An%-C9=FSpM{E4+5BND zf1#6Tvw^Qy5)Oa8+ZP6jy3liZiLkULRx%NNHhky{bm2|mlEuPWu;cD$-!zHbM)I7Y zXz@N+4iSjaqxP9F zOL}tXyU7?t>7m#jx^L(bw~MtMg2Ug^K05=GpGxpI)MpnGlj>7pfc^1j`w7X6q+qkZ zOR38B1$%Yb3A5k3i|Ekx)qg{h_bgG?HaR*7jdCZV`DHXec#@~jx$@wd)2sE<=Ge1= z6h07IxVJ8{r@Pc&_qk?Li>&!(vRj{ScTLb;+7_2deKGQRlbRWIv~NJ74K7M5LMF9Y zc8fPCLbsYVrfe>ln%1VqR@to<$Vqmq6?O~O17npI*)5WGs>MJ03sZ6phAOF$Xq&G5 ziCAsux)!mmZKAQwXlxUWZ3P-Tni@MqW4ouZ12ne7gwg9q+saI5YpM(%aXz4-#Miy%4ODVk>#EplWMAzS(_QO?p9+YO zTVdkZzlg>9m-{5#;*M_W`Js|fg3w@}W49uU^>+qfYBPcZGVfhNV&(skH^?xC=nAdv zW#K+-M-jO3sB2im^tv{rWlW6mhTKpNlV0f>lCn$a+CFRl*1S!PFh*nym?8lNwWv;X z!KL7j{z=MOQ*T>7vWZmiHY1j@)(TS5{3>{*eYNQp=fg61pW7Ug7>$ZnQA-To3q}@^ zbz`_>v8+c+W&OLa3Bc3{2S43Q$h!0I^Rh-S9SL3l1RT(69f+Y6YHGzp4zXmraQtHg<~0UIW5EZ)C5t(vpR-7t9`88(*}@i;#ZWFk{`vS4 z%zya$JoAil3|<7>+OKE|$LOmbDcm1pW`BbeZmrSf6>e5*{N=H9ViY}mEa?9}dNcN3 zeASGd1EhC9uSA-Q4UjJU&qeg*%5ceIX)YKbef6s*vMzS5MZ*Tos^kpzHhcu+nR__z zE%-j1J4GGHVk4!$GaSWL-V-iaOyq)*(pm%H*GEArwtidSnYYWK{-;MKug6TD(mAz9 zDtc5nKfw=m_Q;+F^*^ zH7s$8yd#6rz9DJSAMA208rR^s6Bx>Ir~Ws9TUsHauWRL zD@KQJmVqR7SuV?Pv~UnanMb8m z!W$)F{)Wafg+#1@xw(RZ=lnn>RI9@xZP-W~7HPu;W1uCWw_`O0{il&O3erYWbub1a zB8_8eYz|e;jCov|dPDif3Xmq~@xz2SI^oR9xHBtA8e77w#3laAd|T{5_#?+Jfj?@O zV&V9OiwK;s)^$l?I-xLEe%UF^Ew*4~i~Jd=jlTqVnm$JKqiUR)G4*OO%8`?9K491~ z9einz8@Bv1^PMHKeB82>M}HY_{AC2Hb!}dMjDee7Ul0Y*P+h`*Pe(=CbjMc0c{wr@ zG3>ZsotK@RJJkV6WX6{u;Autxf~0DS!E+$&!EeDcY=ZNA1Sh^822WRV=D{VvpV;j> z_WH}X=zzsGiyW9czu~cfINvZEyy6>SXgO3zi3nW#%?)HGmcX*B1k0Sqvdm$b3(opx z7)xRymQ~hE0L%B6!19~ddtP2BUQQOUTq0gh29FJ639af|UEXC4J~wEmXoCh!n>ItX z>O}Kh@up}6mTg?ennA7;iJOoKT8gGu4$WE_e3cb4z%yKQj7w!=2OM~Q>shm9)ag^4 z`>=Oy&YyS0iG&}nweq~9Hk{#{Pk<{?KG;?^G>n6q*}9@F3qzQD)x3USEk%c0#fcy7 zHjaIZEu#34ep?bR2et8I{C!$w^S`2?z3i-CG4&J-iHuw=HkBuF>{)@$AHleRO*n)S zZ&OBYnNVLwNyyl6qQm1t{z&I(6(R*cBL(>N>k;H}6Y*I7Sg`+14joF3cp&h!jPlcU)cM18lKfPiGov#bLN3oKFD2h1da0&4N|KK=AsW}hiBppa7K1b9iMf;qrSrO`~ zmXoe^S_Jcn#AN`926;LE49YvKW{k>r9kNEO>X1`P2_H)bg!%%Uc32%b*z8hJtEM*3# z*FoOCr+K}Qg?gHESLAyd3v^aq?~`I>lWwZEJJGO~2R%N{`G*egCr!4>E6-SNl?85D z6n6NF^QyVPWeydrPcp3Nmh@#|&-4v7+$&DVhFkbt;XFo2gYF5nU{>WJRcKT2td_*j z(b>e0@%P1*?|wG=)5^P*hRp_(un6-LCa7g5oV<2UeGMf%7;R!O3#YjA@RI8TqU$qX zbaWl0Ak2lPn-dDVDg4a?w#h*gVH)64ysrRWHH^56aN~koT)lS-HM^Ob-6GAVQ!M!D zvpA<}wQC6uNrPcas?2kQaE3`W(4x=oo57C-&$!k#Bw%UtNMT&siLQ<4+J%n(Eg8ht zpchEhxfM670qgeBr+P ze_!Wl2bLa>6n3MRwD%BQuh3yiVzhS$GwT+mz1-7_I<{61A@k5Nul@XcR{#N_cJ z9@?u7@XoB$T8LOVRK(g%>}ub^orF%~P`wOgRqbsB6SaSC30slm8ATR*F>@-@ zu#j;%k%HJYj&ZXO2Iye zsop&yO#3cEL%$z9q?N5uAAIu#6gOAglZg&w!ax+i$warFm4ZIFC;w)HKlH&$I?Qao zr)BUW`(PD4%24AVTkBo!cs8K$1sA*=1hVu!qz1@Tv@oGK_GR)*=4a&J>^{yG=sVS>jM zXiUP8$sXhgw7HK@!eqdW_O~Nv(=q;PH)f0v_>WhhF%g1il5O&^>5+Vddxd{JKRJuH z0neVUjZBwUSVx5O6`Hv5cxcPtbEPPoj=CCD32;g%1>!af4u37q$NVzX#Cz=~B=|wF zW_q|*`BWCFxyS}X!}gVX9JXTWdD)$oan!YJ2WOs-9eC!{)ndD2R$;N=u9s?P;_GY+ zu=~2Cr_ZK1GEXHpYO?yd)tNVSTPZ;I;v`M1s zem_2y*8THT_s@qDO|6$%C@n%M)O|hQEKbelV|sRVuOe3W2b51`7q5H6_O;JBY{k^8 z?g>J5zX6;%$t5=8+3KFDsC!lgPQ2b)RQCs2RG+v(3je?d(>QgBbLwJmeAt0xxBcw= zdA&`o21t`39eUc%QrX<1ieHCMn$M}$wG;!`rSmyVnUt?Db(j^~bbPsUYjG5+#=&=B zkM>!0_h~xSmlrdZw;TJlQbCudRx0{y=_0G^W3V?@D%J`^hpX#or^nev_Z}UCU8VK= zeAVxDcbmkcT_l_yK^I2eor-qLOZa<)J{ZXJ9LO+Dx~j5A)mH^d9d(ISc(&?eDyokH zjRn7Xak%;rBdT<_-xy?;9BQoDQ#PHbKw)hJ&f2D6ax}m?9+ErV-gfUDQBZ8q-8(9I&z;L&av1;3GSTzU)0z7?tt^dXpew*rs z&X_4e<#C0_8KKIcz0cJGw)q@H_Nfm&%yz}crtESHCU==v25$|F843H ztd9yd`>f+G>x;u#Cz={3T-J+%NBOK1E^7v}?hpwKDR-G49ZX_Bqr^4oGN}}N zby=%|dwkZwW!=TBobO`hSq28Rd-l{$NjdPCHx@j!rD(!w0G66?7Aop~<8IN4y4!#A z73F58I}qM6n22HUgUXBJEK7Sr8hRJisC`AP!uHf64IW7RVkJq>JMfDRg}>-;_=Pq= z@9b%mz(y~}d}6P1^Vf!h$f_ia6n7#Ks}1(fc`FmR;&vAwbT}%p$AVAINQ*rIyO8J! z+l^-!ApQa}zmOQclNcq)yRNe^>2-O@OSNQUizLlIT?O5xr*@x!ZXkffeu7g9yq0>_ zF97ok5$K%=l)wkd6TVse%6~#p!If44FD##euTF^t5A^^N?Gv;I&rnGI0y4i4gWd^P z349=I42bZH#RA99s^GvCVRoMA*@+_?!d_LR8NaCnQ!ozHvwneuUx-Za#G!-&JL~a% zzG0OK-q<0?Snx>T*fFTBNc7m+@Qgt%e*u|ah(YfJtOPy~b}2ingHLV^v-9%DxY}t) zW^}G9(t%&N3-sKnXZ->RzYv+;i9-nmcGlqge8cK6I|LaEp6%H&s9i|(*t+oyR|tOr znO}%O?*yy_J`i>(JJrE=UJ_;}eu-nJ2bt4}l`7JUUwC2kd_>Rs1rmNCGQAUr5(@0B z!uR=x>M%P584Gs(*wv0f?L(r+mccUuO8E=O{6Y+RCtxM;fv`*2SreRJ#Lj0fcI@;c zGdevL$>JBmka`}_vwneuUx-Za#G!-&I~Djo->@dk4nf9(fBKPQ$Dj@&(PJCNb1I=< zK;{=>&^rMufe(aT%Ffzg^NYi^^ZhEv&WI4qon(NxVH6NYU<81xIs{6Y+RCtxM;fv`*2Sr`06G|bMUJv);^ zFfDchAz%u&D(P9jK*BFXrg!2{LV=xGl%H={7iNbbW5F*cUF{gu8Nk6lCSjWu2K@pu zzYv4o30MhyAna0h)(0Qj5@u)1qh0OH3BiPloD>44V22*;C?vyQAmJAx(>rk}p}>L8LbwAAr)C81WbXOLC^XH5`G~vy%UEL3ha!CosD63 z2oiVATL@k%VNllrPC8-O)(eAv0hwQjLGJ{t1U?XUDLb2k=Uf)9oo}sl>}(K%eihj$ z1WbXQ*Ry_sgkOkE@5G^m0y_g@XLFbxg2erY-*dHNP-_7voiJ=$gh9W6%rC^CcLG)d z9|*gYo!a1aFAB3$?%CNY1V>b4n-DMs#r3RTAmJAx(>rk}p}UO|MCk)#TVbCui^9wQPoq(0V2f{98XG`$D+AuqtDqZdD6oPIQ*(C%_LA<@5^$R5Y zLS%X;4kZ-W=@mO$!t4-aEO@ME$Dr;7oOHsl?Gpz50y4i4gWd^P349>zQg*fm11}7- zbNz*mo&7@4p(6D{z!WS9>sh}*!Y@Rocj8b&ft@a~vo*{PLB@iYKICf0pdJLAbi%O3 zg+af7%rC^CcLG)d9|*gYoo&H?zaY%c2ec4{5p}Z=w5mvp5HQ6%$6J{KB>X~TdM6Gg z6xeAOJKMtS5G3ZP4?1=XY8&9B6Naswux)J#kokoeluE!#-~(ZovJ(rQUc}BYmz+33 z=n#UqigXGAQ<7Q@gJhTjB>X~TdM6Gg6xeAIJFzf31Q`o@zw6jBsNH~*P8hZx!nSof zK;{=>P$~f{fe(aT%Fg!S70(aX&hO55?DPsjy^0(W0;ag7BU?ZM5`H1FKIR|}B^1~> zD0a4o*&)bS@ZE98jzP_!JX{mP)=yZr&IQQ)LJUeJU?uQ@uuIw55wvU$v-6jpovaY- zRgnQ9V2WRv8)6EO@C%XYoj8{51i2KUs2*?Fzj-k@xwLazQg(I)KY3o5owjqGvIRmA zQ;}&QU`kRusQd=WeMmOFM%3c(f?iGU_MDKTkFVD<|n{6b`9%t0JVD6q2) z<>woAhuI-WoNxAR#}4uM<0%YVg|O)tkjotgy%Vq!_(0gD?CcG;Z3@@UFSx+Po^2(- zU;(RO5jzL|IZ1Cd>+Xlk2RU|;>7h+H<0V{zIgk8$c{@~Nk4YRYI>wB!7jY3eZ zBAbPPDSk<+mMK8OFGQwy;!r|?owX=G->^T-4ng87oo~6?F{oRR4LgAG$$}S8znlcg zDR&Gru7YE#K6vQ=gxN_bL=fz36M`x$f@fPLEQ)ai8!>z#JKLESHm zLy)mxk40O1s5_7in+An#Ct)S@3&{LJ40GGLkR_T%7Ajd z;b52@f{X=&qfXg~2WwV{3?nK=DK> zotP2CR>hyUF_ax3TM4&~lE-6#&N*bovWfiMTcN(@;Us`qu-cKzJDS@))DA=>5?(vu z6>e{XK_Sv&-|St@r1RT<9j5aptW8mExQ@k;T}3x`E_oN4_bN||PQnX|lmKvogKfOP z8kd3?4Qemel1OJs5F;$=B6M=!bMTxZI={sg9nyIuofs3HeWwau_jFE(PQnY*NdU26 z_P@cAu5XB+AK-gClqz8guB=U6(C6`kXXWSm$cTHdWD42e#{3)4vevEbl+ zPM!$5pY%|JC4%P@gkY+T)1a%LC-yOHqlC#pe zqYw+x`0cW`R=VqreZN_N(5|;aqSlKm+};g$1W^|^igkb#?&84S!X9lE>&8~Gr?iW1 z?O^NINjh9fvlVQ&D$acy_+qQ#c@mKd65DM5VkwC`MIwJgBo-32h>W7#hYf6z+$z6g z>iQiBhQ_%X5VH;(K?A9YX6q|cbpvSAcI5a#Zb}jz#-cEm%6atkFi6$q^#mtgd?Og* z73|R8ac)J9j$3FJcS&Pc(AdJDtc=#iJ_E7>ii!&GPxMA+;3%KXx$`LfALv8)IKm$DKjAzh~GoFWdbLo&Bv=VtQPwY7e z2@Xc%Wq9$jKH}^i!sBJhf^R+&fe`FOE?TOXUBin%w5qY7`q^sS_L|>g`!1A%kPDmi z7u#dI;=N7|2!3abgj&Ita7l>7eIuj=du#{(NdW##+QKD9?Vn6rcx5cO+?wbAN?SOt zws7zJ{#b3n;N9Tioq1cR3b%z-r)mpd{_UyTLe;v(+QM5<>a=a)*S9Xx7B+@Uo~A8i z48WgBTR6|C{gY`6ufkQ@);#}L+QP8f!d)2MKvDh(cERB7@$k;PEvyZ|QD3;#ZM z>b6k+%*EQm8&K-BZQ-Y>McTr;aLLoO1srfdEUqnZV3OwUsSJiEi;R&n8i2U7xAOxK zq+$SK;c-2s0}#z!HG>TeKnjT(wP1|I5f4q9AQi?){Tw6pYK+u_G14Q4L~WY0t1Kn~ zi;$QViSCSpJc&pJi5UDHfuS!Yk=EH}z9A9|i5fAY=m5^RE*T@eIu=}N&C|67oLf4; zF%m{XeKtlK;ur}M9bwEIh6flcjrcLrMPn2xCjAJgPa_~uhY`>)M?k|< zuYqVXo2lu#WV}{tZer}SQ4i}vqod$k|6NdX&g^4p+~sZi{xLs#y3=ub8uDYGTTtY* zI(}}_@fRNZYz>!$S8+nArv{Sjz8@m7t!(E;gYA(@kyLRQP6Ry5ND3) zZE#r%7Kd<>^BB7>^d&XXQQqG&hWlHN<9PG2T<%2l>(%IbI3d$DYReifxVdo{x#N|G zaa{y&R*Tf1gIv#g_&UIwFnA302fT@z=wxNj}B-U zTZ?fZI|0GpcKgGP&B;2Qr&oU=-kWC5OJv_())Z|$FLh;W^2*tgYv2szXRVpI2_U<* z8F$6UmWz+4t^}dYZ+ycW-T=Sg!&CSEW_fbx-nl3FVD8~2@W*rBNjCL~=+|4Kcc!Cv!fN2GA04{<%b9%rM~|R`%i#a+Sn%Q}Tg^w0!$&t5?b?mv zFk0zor@mw28VjD{^Pu~52T?Ww+G$neJUH->Dc{9u>UTxBWZ~PQQ@<}Y6;z{XdSj+V zTu$SLw^lq=-c3EBkvJ6RL>MQ~rlUW=bb2rvh~-F#wJjsM4D!8O&6WjK-?JAFSt z19obRnqqd|5iWTec7Ah9F*}`kcDhQ~VT)hD&U1juP12(wcAB5GfSn)y>e*w_qQh(!6!g9j^MaFnqd%7CSra{+mU9F=dYm zmn^1i!P#N|WB{hvnPdh;3{OuR5-~x(*8lydXCS8NV#G9uOBNHez<*I@05nde5|8DD zGmfW2(TbMnkJHf~qk92~(%Y?o?khTg&d%Wfahyf>1Xs}*EjhhCIei8kG{qMY=kajK z({ON^0q`8;>jgtSbgIiBNG#aln~XD@f?y| z=NX-tdNn#vm}bY?)-*f#31qP0IXWzEJzs%LuCtra7@c?N(t>Dxh35detv2-BX?M>g zc-QWppjPfZfSly+9v&D2Mv@`3O890vLuM#Hhs;LDkf~&Y zlL%)Z8y;yYF)zM3%Rv5>2kEKNrk*)&>WL1BsG&5^({W06+fU9w$)5PGMU?Eia7j>q zs-f<88wJ4C#43#eP=zZYr{KAOg9brgf8F%;k-fE-RYq{w|9fv;PWys2ST&O1^Vk!E zcl9@p_6MfUfcDoJ>O6h2Qy&SJJPqwnE~34>YZ#XvLFJxsVg;X;1$Vr8eqM>%gHgXC zz)~B|yJ~BzOa2hlcddW^h1`LU^T$>M6CeJ~d{=)c;lrOnLIiMpj{7QpH{Z1~lo0lar_tybmTPR@`hxd22h7#WK#uAEn4vcT$$q8vGY75u0SLSDy&m2hZ8G{Pv6KwV; z6-M4&vc-7ViK-fmo@5h1^R9``-T2tlm1yQ@_PD6N?GS`HgZbKg^knWK$$Y2tAaAv| z{B4ir$=EjJwWi#ZjX@PqHN22ExboGHu&Td%9Zu34(Oj@R74HK^j9spRYFyf5>bS=@ z?TrPdcK;qs9rR2c_kK%3Q5iTCU)MuGOl5cBe&bsoOj}x8{%(}7|Dgr@KR2q(~vKUsuT=kolYIrBiI;*>*mJCVCJAxC9|ojHlBf2)dDw2 z?t8=++k)R@+njQ%g@OgNu0-J>smWwbbe#OzI@y@`n-G7K z#$Q|9I7_yb8Of>IQ#L=cxKAurI2OzCSN%*tdTT2@i%+(yAd7*qXgR0FB6^1z+T;R@ z2Z~t4+z~8(;T?`e4Swca0kSw7?j~o+qIHuqVsTC^p3Hqu{qi;F*@SfSA#`$BE&kTC zG#sqFd&H7qNYL@E`G7-Kp4z%DwPQUO4CcyQd6!KhFXL8(W{MU6*{Y^3Iv$w<_=a^|D7E{@${0CVyeL-el#E5`}1}we&7q zpFnh9ml?fgm20SaOSXtCypSkS%GO+W5wxCyVWX1Rj2c%foVMDz|UBtk?iC zwUGyN6PB(Aoe@pt^7;;(v80_k46F_caK9zF{Qz&4iLtdyX8% zAk->%i&gFyEH`P8a#-r?A#SP?QfoJ>_P%W(g8ko%L@*YjY4M*fZI|XEb$RZg;G@Ve zwH$$;1wC@8b{MLAszAb->Cre~fsD+q576&RcgTJ`LCSl#GlZT*`Q3p>ybIV zXZF>vd95G#glK&C`$S_)G#78oEo*o*KgF9t$f3yQvvh4~?oc$>68%ZM@hARsJp7p- zaK_Ae%borueN#gO_I6wWH(Qvxl^g^ zAdaIOQ8#?UNFLf(9{gz5!fX_(I9R(b{?8qe!P@l{K(OvX;81X&k7Qiw9%?JDj_K?W zjAUcM<|l|D`_`1*;P0f^j;|K1NOo2RwQm(+=uQeDidy5r49%sXdnX&bUTotH%58bg zQUDCjIWVF460j6@M2Kt&Qw5Ue#alY%!s|$b{enln?_$7XaPxN^0tUKBF!!wLkOs%D zzACt)NnbPZ|0pY0Yav|`tS-H-T_1>v1(UJO_Fxd!7a*JyhQOxnAyk(_s0~BdR)Fxu zTb7{VL0gnB(6Ge|KZecbWN!aB>(0VB7044S)Exy9!_gkd7YmZVv9kdzDpnDhb~Xt* zv3%es<5Uz{O4yv1E1yn5VM+@|!d4PvU>6+9;1j#RK3D}>*kM^XEaohE(QVDA`H`cO z={Emio9g`R`VyJ%vhODIg9VAb@8%*@yL_OjL;%b_LWlZ|h|n6n-?%PyUEC^~>AsrY z{@y%Ng`ie-%tzz7FBxVv>E__v2iOc-9JR4(PxfjjV@5p3f~Wo3$#^TphdZ0`5B+yD zM>(x>Z1BKLJj*%JOmQ;3f>~k`WJ61E|96U5W5?r!wcBIO&wSj6z5c^qNipk;cD~?2 z`)*R~ElBaoco8b}j%^+iI>`3HD2xT=*HIH~hrzq9W1;Xi+u}cnM9di_*OB{L7~4<* z+e7I1Xh;^cw7Ir?1*oO9fviXvNKgRs{xFbmWBY6=5E>Q(;$}LX3UBR7MY{&^$$!Lo zw7N60OEuGFUZ^frR#(9>)YH`1BQI1pOXki&Xjv_z0P6s*J4r88XHyn_mEPc?F>1;Y zC&w6$Co`R_a+!yXThu5_wcK>hl*DFqdUjbc#lro2$ch;dvlcf^o7WlfanA9iT6?T>&Ff^_k-Q*H zyH;cJ3{Kgz{@kWA!B@XUiDaE1w&HVnhEl``I{U(_W8vqkun9u)xf6H$@T5+|ACe+F zG-a`qiLuWG;)M|0LB+VB0RL=|=V)#AjsPZ0iGw#)-k$Qh@P_ zC18BM6b7+4Y4qdqXe(gcbMn^n%2OYtPNR;m3GVuOh+OY3g7v;L9!{qtYs|@+zAXB< z0TEpb+{WWKJ}y-^!QnJV&nWxwsLIYqCvp#l@gE`n``%N8|8I)%lVrhocDx8by0%G= zA6*-l1q}amO*A0>X?T-8{~@y@RdLzBu(H63LE%5XMt}-Ujm0u?j>2_R-=H=dwc;IT!ug6ywb@j! z%$=}&)z!g@*M|rijB|>_!Kjx;t;7`x6DU8!jL(4TDj6z6TyC7KvIFMAnUBu->PppO zwtaWFxyry>7vTgTttL76sN~gR_WKdbT_+4Pgdk-K9DSNE5GAcCyTwv z+g~UrwS3fDi^^_h*|3lLx9=|j_N-E1=KxsONXP^Iwg`%Zebh08pC2vzkfs8u+I2Rs z{OUU;nWL+G`g%*h%hENE+29TdLx+eiaLDzj_E6Fhx*o6kp7n%RhbjMv8WN|$uQQPB z-^Pw^^Y|cpx>cefe6?;2-ud2Rhw{T2yoybqMA9;t^nU7B9#yCf+#fns* z4ie!_z=Wav!|-Nml~^c-4v#XGdI>q@9A&HoX%l5 zX&4SW3?0JY5_fyb=5oi}bQq>!C0t?hfX~7q#&J`H7Kw`7`?K{=k>3i{e*SOb?f)I>j-{clwM8`z5kNFuc<{uXdm{Q!WQz8{eI_?2!-6{b7Uo$t)uBA7 zkiEnK*XVZfvDc3?n6!gHAe6aO*)6u{(UfI}V>wS*Ze^idfb1$ajoRQ^2G@6k=O#7A zvL&9gNp=nkBy&@*Ko4;!`jC^|R@DfZlL}TDqw-jdpT)IB-8Mu|Q56wZaD-N+;b8?v zXj8m^g&o(*VBkNcWK`ff3>a{eI7a#tTB?M;j%tuN$>Al=wu>}e40|&e0VOx_p|*@_ zmRqMpKB55CSZkloNs!(n_}bSH2zWl85i;K1lr6&;PQBFg93|8(l3QWqrZ7;TE8s@% zjTr#Duz9RkHSr3%iiiDZ#{o>(yajU z`$Jpo{-vR=rA%y?syYa_ts&LFJ}=p}I1Qon;&D8w6mRG`JZfO%Yvu5fdlssEo^7|LhbDSFB>IGw6iz*mT<~; zMu3aAvnSaAaEW$yu7`f6?JR_-q@CSuLoSO?SkTV8O552E`d)jfY>^cK)ej?gywI7k z;A%B^EtiN}espG6rxxh0-yaKRcUj-Y?O;Pe=a&d{SQzMLzA*#0I7ATqS-DxW@_q;~c@7-CC$$HWmy$#jP)7 zwb&6_nTx>gVcLm?4mqXVI^mGaoU9wa7uLTqn+%ELhp&}5a-T+JaIGI}4Wn$sC;eIj zdP5FFVC^u-N}vzG=!RngTWc5&ZbctL&%mBu?;RdMMI9agm|NNABtUgmf#0MC&w2$8 zyvqN~8m-c6wa>gtuWRhpFIKPhueMnIO#f<&)qi2HC*qglfhbSJarudR!rd#5jCF#% z-ZFCygk)^+ubcI{(Z6odYpuPm*o?nPol0$IQ?pkstToJEXumWjkx!k9lx;m+9(WTYZdL%XB4xo*wW*dGy-yvf3Hh;1RPF?gOn+>Wynt zX};O%0;pDfOI6)s2NiIEQYpDFgSwPoh)=d{bqsG2!#f2*zeNlW7-?jfA8G!}ZL&J@ z5loqauDp9DW=nzmZXoF_w=)9JD$KiXivmJm&i+ApeT^l0glpt`hr8p0d|T)qe1iFa zNDkfg^mPbAE?dAW=QXHk23UW=lhRyO$SJ+BDh?rgEI7K;G~Ha_D1T5~`0}g@I(4yG zQ$*7h%=a6gop*lgUOBDc#c^B^OZ$fPD|3|48+?Lwaq59A7r=KSTe2cGZHhP~;$l^}x>|WCi)~h|NR`!(Lt^kK6U4zjc6KPLPw2SNPJ*hf$ zxNTZz@1`0@dt9i*R*7Z1iRFyOEEHzFO6_#Q+#zB1reJxBg!y%&kYgZuPs>-BAFrQ& z&B((Tzz@I&rro`L4;x98*{Jmp!(dAmanfWqjajg4=CqU9q+}K>lo>pkklA0q(#b5a(ZC8rJuaDz zOJ;EIVTw0_$k0>C%)m|VaNx!%vsqV$GAo&qLuR&WJ0Y3PN@jDAne))xJUs^FN2|Nd z@L_QbnjUeMP4Q%SR!l) zdrhM3h&Q5-Q>|nCrnX|2I{>dOh1jd_eq^(7hyx3mRn)Vog=Ix+(wBwGf#5nQ$0e_@ z+EgaHdeD>0SsR-jl24bzsKeRSnoy z*;zF-^=|q7lvQIWR(TWxh~^A4t4DQ7ex;ViAFZU>t<*j)b!D?I`w%X6hjBIS=G+6J zT7W^mYUw#JA_dtaLH5e7G-WG}YFxM) zgG0A$x6$Um3&(O--6({V7Q`AO-7Agw-=m{q-85yl%d#FRu8ng|JcNJ5*M`~hEYYwo z!uONIg(TZPed zIJrerR10o}jlym-tRPYTS__2yN97mqm;6U0|53B+zrO%?iFWu%$2i?qjr)#d$S9%! z$GiZ|um@g%K|yV>STinJze)8JvUsr+BWLt}W zU9Hzv|5~lrHhc9`+jjqIQ`^J-)uy)pY_BKcx8VVGjqvTY_-$$H@cA%p$LsC(>WqI| zr+-~9lwJOHvtGO1tFyi`G*TGqB-$hKcAhIv7Q`Oh8^`n)ftfLT>NsYX=QRZMFF>wE3=69?FIlc z!L%}kgYXKNBZyCv0VcTKdD1_zNbnk>@bbg9GZwhr%1=g|F5bQzJ{1G81!*Nq!76kU&r&J1^k zy|<=)S(pp;=2<5#^v{r1|3Yb)b18!FtGYx%G=;+ibAb zcvwd$sv%c^UE5MS4Eofyg?AXNI0)7kSm*cK)NP@4{_Nk2eACUgtcfob?*eZwtrd@C zMron0q^*q~xPznJa$s+Zlm39DKVt4zh|gP^*BE~U>~<+w&QZaqF33KG+@V5RWJQON z3sIggby6Rtq$cuHRmF%*A`3`9?Op{9Mv`qKj_P4i9WWldsJZpLEH9$KH87L(o+e1V2VOMnWB(S%Y%?l%Ts|>#`(LB;A`+S&_YME!_SpoJ#w+vr+HO# zA9mP>rfhvu$8-n(`Wf=mPdcm!!@Y|6>A=TWaN=u@pH93cb=9q1atjIPj{wgS4%x^s z6Cao&ewZSDED!jxJjM?R2!3m(Ok6} z{BI>tKvf|J;RvMSsFjZ8Y{gM`89dcBPdE=Yfx*0NR}sPKucgPR6BKJ>hHzL3O5g)iR2xiDZCD=EhUKx^AOXSIpe0lraS9~g zL!7cX8SQR(I!hvS%({=P>qk!aTx+YqBlenX>nVIH%C=vN#rbT#g=`8wm3}=sY87i& z3=5aIj?Lc{!T59jF0vZjAX5M@RvD5~x=uZ1N5S8c%|kVPoGj?$Ke#EX(`n}P_aRGw zaq^T*Q~>6n4sgdScwCA18l~QNFr^!p?NE3ujQE?Gt$19;SE=}F{9187)#!wGsx#jf zs} z+R^MZ6a+=hUP}yAXeIE0Dbj4FNV6>uRKW6>X0O55U>#`rf70w>$!;BqP(bryn$54$ zY(AJ~s{o1BLte8tAVbqJ{z|jg^8x=+vzZ9ZW>V^~O4%9m1YJ15oq z{EX5RkvaWg_Lf3o&54X-fdLt>ppZ{B^6yf!`Q{G0r)F={s}+x{cnm3nauHkc?JCYx zYBt{%YWAhOjB98%0ZOx(lbTJ0MVgHv-43J$|AHRG&5NzAF4XM(((EssaGG5&&EAE= z&ZP{ECMasQQmG?K-~&^n*-VjUTOMe(Hn}vm7_Y&oZgXPN=ah9zdVj-OpW}`rX8uexH&A?Nn=`XYJ}S3*;=iZ zxwR(R!fiaQ3$?Z(yd=#H39Y%Waoziaj>nULz}-R7wngd`JAa^L(Kgj4GU+AcwrFbX z(B7GLlEJ+*9kq00)B#+3-oUyY@ts)aMr2@eRABBl z808oXa_H3DzPqxyfpfsR?tFPzm}r+`4z)aOn!FrNgA<6kL^(S%=R86HgS|N%X#-e@ zTI@|lyLs{p{`Ms4d+wpL`~a%!o}qt5`1*A?fs*?lJ{oE*ZXF*Ef}RwMaK+ax;`d`Y zTA@h&&KrT1V|XJn-WyRA4)wzt1BxRNxRXe=?^f<@0v+Sj+yTAzW1^4e#XUG5 z?Vh5U1vaPssR!7jqaPx+6?-+s9>)@{JD$_nv9TNCy{IhXra9x%94`4fq48Q}Y0d;0 zq~=UQa}Zw(aEPyULos*;CIxv-qK_SWA)rb0KghE^(?bbf- z5N|HX?oxNdFPE>|+*vkzi}ndry%I70;e7&Mza9zUvuswJDA{!I(1j)Y1YSP!>-nQw zKJK;!R3nTG^T)f*J92b~PhVr{A9CsSK7FmF|D&bLce2jiKEWo0c0-M#v#Vz?ia8_O z=aHId&yCghv=T<$krZ%zhI59F?d*?@UTYQwt_8aEg4ZzHwp=0 zTS32`WWtWSWaGjM9EKTT2n_87p0df@ zF-bp0rN%#?nGJcPNgTRU_qN!2JIK?mh~h=3EqRl z)B`AyjCSE$Q}!T~8Nxc(!O#>XGx6lNyA1K3Py{XXWnAlZmCk z5hQB2;2j*jmS6ue_(A@UM4N-2Bl2gM@tqlZ2}gWEODb;zV19y}q4R+`BEsGTdpa1NCmLlwtpqEHE1tuTwP z6+M=4S`45;c>kPE@tD>YIv#*Q=}$`f)47KZUHtxc;y}I&ZpSaF+)*J~DF|54SUTE< z|2twq3ilpkzo*VCrmZ-&gl8meQv|;^jr%d3gs+SRAKQ?ZuugY?gvTl2IWOTkJLmy) zAcFRCiv!>eHjAJg4YqyINw~#_5<&gxyQ8&G8+K)@ex0L+MfW>@1)ujN<-!=0 zQ-B(0?tvPmGUPO(p{Rb%%b}W*H;0v_au#w5Sk_c_sIK;f+sRJz|2VG}Tgxuo|Ic4lO-+pTMq4BH{9&l4e8XY&~cpj7!qNM%c_JuG0mDTQN za3?pi)#%E)8#kJZh;w|Vx|%-BXLo;|Z&BA+=)}D8<&Mhy%3pQu2dvibU`?^ccC*GR zkZKp)kvMY=mQ>nSRT_Uol~zb}ZWEU70Xs?UQWP+bUz2h#3~E;=nZ-@U;;I_ItUA7> z4(rznTGdq{Syjg`R&{ZKQ|;NR4lyz5`F^n!+krIm=Bgrx!H6nyln=qf z-*y$r*P<)^@)ap8sLQ_)SH|R8((Ng*tMdlsdjPUBMpq(R&}{err0!r%=1;?MP6`ftUScJuj-Kt>Ec(&P zyU_tdazmh#Jyk4tvgKl`?`V@KKo!{wzyUYACGC|*;=ZJrM1)%3+|IozuI1%7sq@#dEF>(GT+GQ zqi~^mPzgDTpb|{=D#2$9Qp}spH@TUQ@;Q~*fNa4Hx4A~nnqv*_!{6W;NX>^PG-WsY z199Xif!TBmZby)Jq4B&U#$?@f9jd`XqOIJy^)nYg=O7hD+Jl1qAaPKR1FJ#05NhPz zU=8vuby&X^mtkGOJ|wFK`Q;31uovW_2K)FYsQjwgUcLIbi`_(&uR-6sdE}t)!VWM8 zU#$z{7|uo6hw5=xELim{tH)0jycGz(7kn7xxHri0y!*mz@}0K8ui$%i&^v)3xa+X1 zJJ#9M+0L%+$4l@Ae6lzPwm%>3mkeL6ys+hMM@hRlJXCLm#H4OscK0u1)MUUo5^7`k z1MqbWMq$s{b#&H5+c*yGOx1P5#oQ0i$*M{1Y z9bLBH2CZyN4Etlh8}3>6#Dd!|HSuGrfI$6jjx}3362jG3c5Yb@93=Thv&no=4BfYp zP;+n@>;EAWGUyN2C<7q)_(M3LZcs9p+*@Hr|2e>n&6U=#45?nEWC-9rgGugRqz>?>)$+0(@&vpWv_ES@@U?KT39e%mpPJA3JI@} z=wgX6SdVs#SF}|4MS4wK2+-}JxGX@o+li|~;_7uf4o^88M?{#-mu)Q0X&W@N4bVYN zo**1Ed`B(&YYheR$$s>}PYPuAox4rft!Iz+4MsCYZKfvLM`|;vx(r*SRc@!K&A6%d z8IM45*Qoi&^TSVC6b(OV#h?TD&x69Dv!H?aKq-%# zd;3$QKhmc5;NtfF>!I4mZeCXZxT*KSJ(8cF-hlg`pRRnl6u~)f%HGTJ6Ua&! zHhu9ENSoAaU>7vrN^OL141`dPN-KH`QEN~as^~(ZwnCxk0E&8NMOM$gCv#p2RJ83! zqAP-}IID^taTTpHHq{^%B8O?=sm2j~$mYjYEBcUNBP&%jZMx}5dzQm!$$pR9xJ-K!6=sj!{)Cc7QBCr2^#(IcujPS=1&JQjeGM4Z-e=@=?Hk9 zEymB|NP9DX{lVpFSEC#p7bXzHz+_W{v#re3tDPf8${|+?6lVh2@-&tZ52qihA&VRZ zhe~MZ^yXOb-KXY>*EvPckdtLX7d8!r&MYG7H*Hbg`RH`+J^^MAR525RLI=T(=8-+ z0wbc}t*N~JF7PYvX~tHPg7#|~H zHh_mn2aewq}jWZ2@C-GNO zR|2KZ6iJ;alDg%A)Gd!meF9&D_k)&#)cul&lW)DFuV~@JeLLXAbwIMe<%xOjRcS72 zlFugoxq|pB))nDwg@}`i0t}-wXZN67%~lCBfK?+GI4gl~3oGFVoAYD@$e>DKPG1Sm zWjTwa;O`T}JBP<5tDy%UV?p!BTs8FK)jZ}F`p0S@C|1Ks!lCq)zz3$N8knMLuso;+ z%VX6*0)j__mQXcxQzTyh%_nP`uEDh*D_KoA&nzXKiqlK0`uN4_ydbPTdho^gwE9@n zlWz_OZPw|f&zwmYSZGj1j{NL{a+)IpVA0oJqg2)h-xk)#HE#VJyhM;e^}(F^`mmv0 z1(JdXnuwSFS6?4h?x7YlJ#|K1U=ruPe8km9H(q^gVHL}v9teu{p?6k;68OLr)dy2l zAC?F8VR@`RNI=j8T0-@arAYGi(JS^%H2hLh9~!>8>f*EN<8_ZOsgHp?5UY>vh5DFY zTZEiBz5Bd?)K&xRTtj3)eN=<+8oByeAADO_A79v%Cu0>ds6Lp}*N4%vuRzN#qh%qa zw-+FhD0j1o*ft=|1t5=K3dn|1AhdK==_@!*JK6&v_Zap7{nXFwx`p{@rZ_*v`cp z6Zq};HTL-A&a?q|zPU4P9QaRJZ!|AAe*yduN=v}0aBsye+H%#KW1j-vC5Sut>jcdC z;-F@SMggadHQJp|0rSm8KRODY=_%l+JOxe@+KR<#tGMqhPBcw;LpV{ZJ9~vnzaW&Z zhT=`_`;fBGi_cUNTCe;nF2Bi3Q?z8>Mj{x0z8 zzwlW~^!1BHa-mP34CR`@GaPqC2btHeaxmJIGum;YYZTC}Xl%x_0)q2y zy77S7JoY$tF(M8#olY<0>@%E@yBTI@eLH(Vk@zwD=+d3`U35?-e4=UJ@51u;>yPNs zepr-FUm_MttyhCPu{RuM)l1TjFapu3)+enj1FZ6-^@ycDPbnEwgjGKtz+pcltN^B; z@mCH^{wUXe4@S|BM?0xT(di;J>Uw*KH#aZL244grjK?y<7phU4)aZM+J2h&T8VxZL z25OYWNB~c;{&?i?kklwEH9|Vnh_`w}-t!Fu!L3E|vQXN*(GSR@t0O+Ej#?irk_&2d zGL%ab%DkiB++zhbQqJgzsnLj6Bh4)}!v)jhZl=q*CHzzqfDJL@?CUX#d4jy>?(O@nCpjv^%LscQHL-45t}mV!mwb zV|=PvF^b=Jtq8sepy|t(H4T)#`noUR@MLAat~_`x(m%qS>9SgceV(;q$8+(#bvE_r zWNbEdd0FyBWvR={lP@aImz=+V*#!iX?~gElvTRMT=|2!mtkQspr@ct$ljh{i$Wpb% zM7=2dodpJ0Fc*srig5UR9Vk9E%`L}OgcW!aP(k#}RDFbu)~I~r+SJ8_mXa{iFFh|^ zcG0GxM%-DPJick{;LkqBtRG_z6*A77o=;994V7f(mH!@ze2nk8$0f4$mn65WDa$kZ zdjGBI`Qowu3BG96AoATulFQb-08WSC9As@8s4|Ir83?gR2wnu^D}bjR=2Nd2;od0QNVME_-!R-CV-Dd9mu|#jKmub#tkPlgVjcDX4!ZiE||I+(pH5 z{}MU|^OZDBR{>?>fp?u7{0kB{jWu49c^ODQx*I=`L~{F@vfx8#*b`6X)F5(s5Jzr4uHHq1V6;_o59}zX}YTR-tR9z>tbo%OJ@f!n+3}VL9a+& zRfbK~EmxJFc+t7bLiAQpE-!%WST~t=V(AKD`T0e-9_VhwB%(H$^IGH#lYgT2cafkU z*f)(eJSDdxSW7~B@sr5D>!L6x@dLk$)K7$2&GZmiCWP!3AhY{2nqbGGt)B;Ag%rpdY0f1cCRwdZCqO5Cl3jTn48_g>2B}i}5-61#0zN z`q%USwk(lt*hsN_8E?rGd_S-@xf7y7jx7Nh&4-2$3mPw`%#fd%Se%`>29`t zWC&Ic^#!Zhurj%)7rKc!#mkdpi3i@kB10mZvQKQ9n0e+vddr$8B?p^+Ji};FAUq(k z;{x?Py*w-+GIhaOsCpFNT9Not{bPL~-CLH=w`_Ud{H8D0pLJR8XD7DQ%txAj zdtSq4h`anea*xVf)^fT7u_@U6{Ix%_Iv|y zz5{Tf1F*jUU|9&jTL@tG9s_WQ02+@ht6$CEo63dkyximPcX|DVxr~ zTaDlUo4X`4L5YUj)r(hB&HK`2SLa)I{J_abJx<#GHcr~c@9R!PzZ1dr;8JC<_Vo9l z&Z0fwP7-6MIHmjNilL+q%q8Y4o4X-B3M8hQ7KQssZDryRzF>d@uoaZxB~Ad8HuQ2W z2n`;95Sr#LsXreSCacy2zdeajv=vF#uPLX%nVs;DAnT@?%H|D(YPr9P+*51;$vxf4 zFC>1oh#Ej2lF_ausDQVd>TyYHF%fSCSbPf8Ok$b!^T>++;C!c8+emI*5Bjf)kQ##F zJmm=5V7bqxAkyzpQK1@epO54@J{KU8Gs$oB8)`igx#H~?CXXkwF6T=RYzco$9)Eb` z-nl0|`S?pW-PiD>S@ygqdSH3s9@pzudPy7}{?!iePMLIyT z(Z8cb5UJe-=X&5`{n%0;oi775}vU;pr}k zK*+)-lH2QAY}IPDDg`UP=X<3}aYd>L&}>v{qfiYPY_zoAxT%eT5FpR|KA)L;ckgb( zzyA6D-h2MZ-aGfqnKNh3%$zxM=FFrlZF9q6RO5i^=}~Kpxt@1p;-*ZU6{KWrm=dFA z^NvYLWh^CvbyykLNynZau=-o@7xQO-1FPDChnMY>aOm*N~d-J2Kdl2(3Ca)OWPcolqEh zGq%eLax&CPyIQ07S2ohhg9cy35Q>ynkfI9$`Y$`L6o&d$VlF!)u!XejGtn}L{Ho{< zrHNrnP4?!cSlnOwj)0D7p|3F~^9)u>)aYU8m>wG&@4vqR5!;|B$*}?{7lMfTkKLD% z#9mP_8o!GLn`f=ngQyKI4o_LZe5tRQduUjfG5Ad#0W#(3r^^t4tk(f(0yC5y?N9sl z7f~Br#8A1_N@WYLL3!UpSnjywp$3A0Y&cmqSiRrs{Hpd0p+i!nbZTqr4@;W##?(vdP;ls|2E8xcvB{GfxERXA<_Xjw zbgg-65^9yeTHk@Ez+`^UGkw2;-?6{~z>)z0MhO7Hx9bT|L=2@S4BsSTc(|6I%40w6 z!6$};tJr6d(}I-1b%Zk$@d{FX-^RHw#-G}x`h!qi?)H5f@4mwKZG!un&@F-4%rW0o zs24dxHwA8C`kkiqJDFY_Sj6;dQ+hemFA8{L;U_bFRA3d;A2z{fB0ca}Z0ca7vVWA? zuU34SssXuLZcf2xvwN8{Xs zLbH5F6Wo`CN&}6=(Qd-=I|y@VW?&!Fdrj%TX8Pp;>wh9W9e<4G{~6QI3}iBWk}16& z>Fn zEhf^w;8H-28{Z|0I|*PGUUw{ty9nVmp?EQZ;$1xUC-WfzAm+Po3DA$s6j_Go`Z=hO zY-mmoZ#JNyw*-$TWhu+BP96$a9P1L3dWB7?Xjg)Vf_!sd4r9=vd)ndCgh2ytm`}kU z!?SN9E+Fcd*fOZuJ?hP;h)guFj;s;nC_Omp?6)Q>!T0;9mbN>7`2o;|UIMzPk=?X% z#BkE;)dwtJmoemo=l&TdT$it)ItpGAcXvvJ- z+FlNcDfJ&zk2$zC&K=+WHV*%ia9qyx{t>settIsN-nLNbp*_d>y!*@DZ}0u|j~#n= zKkGStN&4Qlz^iP{?WWfJPpo%#YoC0@gS`_p6^HxGLWji;CY(O)o&T^{yi?Z+Ja%Jc{uI98nGLA<@hmc?Ye_FdEOF0p znVrTFWd^2e@cdG2-WqJt{seRY5#RCcKJ&L=^tZqM+LZ4<@Quj+&6EL*=ftK@D%GIF zC?@*LO~w~pJ7%YzS9=(n8{I<5a2-Gs`#Nb;0?k(KBEXwX8+uQpvBVhEv@=L+n)f>} zr46maUvq^QY>E&bP02189JC7}cx-DXVMu1Z_To!m2b*=5sad&mZPdv-^#wM9$F4O2 zL31MC;-b-eBH)H}ONHjH6M~vyhnk8wrXpbX7ikfzir9?F&X8ib2@_q7T`hykl#0yh&942(p5eI^*^|9T z;@ozcO7>fv?|Cvqrz=M$?oqlYwlHPTR?jfnL&P^Le&e9F?vGsz>D)22L{6?oBbn90 zs?)-1VbJR1@F!KmFLjj=Z1|^Q(pA-9K9;eVAM(@rBNPr46a8`E)L=gBM5mU;K!lM) zST2+lrPSI_dk*3%wSf>z1N<>cJx&&*)NrK+h827;U_l`y!dsIXw^$lr1}4=252KDk zB9=e{Rdj$4x(vgKMjfMJ9{`Pjy%IjT%n(c@6nb7CP~i#Q z9y%&7o~H6o)Q(7)5>5hZm?KwUsJTE*BR*N>=pB(#Y>E7JEnyV_BeMCeR17V?siFdM zQ>5qxY>M#Rv?(GOf!fYAzWJt#igHs#W;Jh$4BH69;@9h_bw@TuBuo9%;?^>!l1552 zC#ozsfr?l$-sFn5k~<=>Lt}QeOHQXg=`*&pWOvsqoGdttjSsRU+_Ik;_AChS=EjZw!1r128s=>3NKk?aQ+vT1-`{M?C;sbf zz9Y$t(+&m6M3|5hlw=9lz*rGalK1y32VBF0?#YoqEGC1T7FOyqZofc5u=QSqt2h=nN; zBE}rK0s}YQh))$;p1u??JCZ1apz z3+?Lc6m@3G#P=^PwhwA@TVJt+E(Ca8qdN&lbuvSuRmOp5(4KE$m+yNXJ+?6Q6-#b$ zswe)HxR`Au)Sg-?Y@XCCJkTs;(GPfY?NxW<4OMfqYLb$4ostw#l3Q#?;}xdl7N@wU zfsTB@uo$c7^3WxCR%hGPnKn{t9n?ff=5VJ2a+Hn@X{?v1g(NK_O9d(VZtCo4ZjTMK zag28g)Kqnvjoh|DKN%c;j$*1!%Yjv1`vDXzF`!Ym$j?8RA3wqIc%$gjYckO(9Gmjv zvm8bjH_QpPwfrXXi52JqtU$5S!T}_uV!K)c%Tq;aL&aOl!i}$|g5TaFiHn^LtvN$p zXNS&18qo&9VmVe6OKpZ*STF>P4i*!GC6p4BA417`iZ%>} zb>Gx+sD{O}SU(5H&8am2hkRt|`klRk)jNOyDatl@-5~6alAz4Cq8`d@J8GcJP7M~ObJ-RwB!j%c!c6&=#kc0d zahB%7@nVy^q40v{!fe3h;0t~x$e&5_XR`dsoVSF)NB z(YaW>>cUg=)`_KO=?vu^-{IuNqx4yCn3|*%&hRfS_nqvtr+nh830T~a@PKa##3ezw z0sSKJF03B)vBefT%{w#O7D^M9K_|+04;Bel@9o)#w8ONbrwN^8(n@vVMy1mHA8_)?)CUoEqZ3c+VM`R$a5Dy8i)QIPh+>G;5niGUD zL&zb_Ab+0_a!m+%mk{!93i%kyYs?mxT3DV?SOhCbxo_zLi|3j^IjLM=qVoK85W>k% zgFJor|Klf+FqR2WF8&JTB5)h?JZ#Ey!BwcqRox}a}) zxy5r4XVx33%Sxk)zwCgv39l%PkEh>@<$Lj*U~xG`Jv2+bseHQJ+n6~ATjb7VD{PLs zI(%~Oqy@i=*oGpzT3nv56qoB*77`)1Pm1U0De?D7y!u$P{HGR6GkQwC6{zqdhcjbw zCWbS0lseO@l&31C>FV5af9iE~PnkQ%f6W19+5tF3DG%CAazzEz1$`#W0xCwB$b3tS zES~ejb?wz!jk@+~7u^Gz3QN%yMP0|Lg+=*FVUeJ?S9{T@Lt&|&awU0FSgKAhRc9Ab zii#fX4XZg3E3#dkSp>I1=T)*0Cu?Z>zj54vBG(U zHlxkLN+9=y@Jdf{L$V^~M06!=X?YB*^@9*FIO0%PwwQ$F_P-(TwF}f~>6d}k-XYUc z(OI?=s@nwh(U;s3#CBT`zoc)9bfe$ki(0TinV+gGN{=$r2&yF!xcs>SeTVx#7_rjx ztW~*kw#o#iDP`T5;zHB(-zmBB{Sy5bp>|+lKrF(Edj_=YOQ$>#J*X**%0AbLWJEbZ0<2q ze7gg8GUM~6jPLywqKks;#)d?=D6y-^^4u3_cMpWwZ(ZSBWOLgk?k^>L45As3Qbqs} z3vQ*NLn+&*mZd6X@T^Q%D=_c2Diye8sf*4Ysgyv3^1}(qtLG?XExd3YEwr8_x0y&j z10-YW9pY;Bj7L`Ak_i@13AXe^r=o=o;y(dnlXm-VE}y%Uf(ao+K`Yk$N2y zbD5aDtQ(2Y9xRXGys
    &t}KE$>O`PX z=xqxcud%`W!bqHsh7Zsa_*6UCSJPo}JhT<>;GomBZ&_w7%xbO9vW~^@6(XloUyJmG zUxmPF1GAd9LTOXJ&USU2fj!77n{#f;vgF!9&SLumR^?FWueqLfN8LlfjMXG|4W`6< zCQ)0Rg%)sZD!2gSV~RR0RlP2q8(U~5yIP#8&P~T)BdnrNLszYX1C?50Qy1HmDg>RQ zIi1s+cHQIL0(U1XZK(2M8%py0G;}6rrXj8l^zIChym_*T?!#Z0=|;2os$r`i704&x zohHCm0Q$DiFl0Z<+k%3NeTh`nldhJ}Q6L_mWD%%Tg7pWh&#gaLo9H`gS$sOWvyiOe zYbZ@J3cpnNEoeYGlE}GC?|1Cy;E&ZrOXk33oo-@p(L2f2h!z`Tv{pm%#kD?<+BBmCMc z+LUsnBT{ZE^zDj9juBWs%~%Q7X0By(uazxYFkp*bp;3bMOnRfO*+6lOh}oW z^TX5V2&jPQL!$!EP(sY}!{?t14T#OBeI>%89O!)=yRV3Dfq&GR1N#x@=|Hmu+a72E zcF`0t8|#?^{ab(&b_Uo={};K5-Jg;MsB8mMQfZ>(j^k2NxIjfb^?b^JB&O^DL_#VF z5CoF(I2LIUG6qt%bu}AaRP=Nf4ma?R#&9T@rhVOw>(4f|N+%3dm)Kbt%mFUjia%K} zB@Nmplo)u(px-d7_9tYD(hMN%f{&Xcm>rwS?B|K>EkJ3O+`kwOCa08Z3@8!uZXTl| z)q(tjVta#YzpU87l5CqN%~zY#=W$F<_6$LXP%UBhXkW{rS{tVK00wzcH` zkdUqgSt-YEyEe#ML@_;YdTY^Ja zBQ5lI2-V{VyYep+su$rrc1l8(d{Wf>eL{6Qi23ITl~42)L=G2wp}J6+2dT2IW5^Q* zf793$PcbS1Y^)fWh9x<|nTMl!ST7lpb6miuG2};R)P+Tm$;p>S2Ho+|JoY%F#-3Y@ zvFBd(gknM`Ij*&#>4xEd=RVzA`EZ(^rG!xuj|2^v!Mb>PVjG)aO4)3F$iHD;!Y zZD?bd>E9L)3IRWkBoso?8*pTamV^XK!c;23F$0R37BSbEC7}%Ks*{q0M`5=7XGy|s zhying0ppYT6^iDkP6Ta*PUk{f zfl`bmwxMW1!l|2Uxd1mBRL-^#IcodS3P}Z4c_#t(G%SYwT0KVZ7G3{Lp?0LJ^Q;rU zR+A^T4ccnfKPrv>_q|mosQ%g{djgp1Jb`bI|s4BQqRTE)%? zcMQ}?0q^n|iH=n(kOG@BOl7cnRJ}osP(M9bJVz}(;Cm4Ei%BXDU1Cj{Z;z}U9~c#A z;aacPWDU4&54d!-jd?t<3W-yk#dDmcJ+OdS0|3s$AH(c&1%PuayLgV^5ob-eJE^4e zyI5-Y%pS@ZTl7VyZ^?YxQHqGgY)5I>jUq9jOq;LESwx)_Q_kzGF*aG@y3U0amMM8j z_h;rMFHXs`dD4T4+;BXAjpxug^4WS7o<{|~&vF_})G8& z`s)$kjR01!!(K%`Zd-P28tk8zTKBelgjl0{564NX_YAN_)Ru}Ax_oAX>nIv1og$wJ z4>goSGaSs7v}BTrFlES}6#2vL1vERgCRA)Ox(RnTD^mS);`^`zjtvQ>-^BE-Vy`p9 zUz7rvRHezewbmuaYwK!n&Cwxl3?xVG?jbmFn?GZSGQT`@79Q+;7!}Aw)izHy)o&NL zCC?DQ5#G?j!XzxZ=|fNnIw1(1PT1aHg~JM2;1P47MP9Dd`2#$z6 z5&2PsDa1ivn95m;MW$N3uoJCh@lK9|2ZqA2yT=Jgl%&`A{L(*$7uq` zUcDA;xZS0ePrw$@kYN4h-6JH%f(dHz0a0G)a<#;+ z&P&Oi+gqEB9gE_g2eP#J=z8kh14iivtb|m6d~UCK=WS*$ou_)>JT)rtUlgK7lOWc= z4_q;7K6j%t^~;S!A-?Jf7I%sXXXi##2R;sBEN~sbPp#Ylko$s;Iz(sY9-w#0j6qck z9B*DTL+oeo?0BgWb`{U0^;fxz)%(kFSgpdOogqWQv^fY(q2{x1@;r-(XtCdYabXC1 zoVa3se&o{+(d#fkw8Ylv)mGGqu#=(xaWBbHe?J+9Nv;AxFEaIAbNcI**}M;qXW!aQ zB>PNkxfe*93&zKp>Z}xGD%WPMnap{=V3IPF4?^ICTACy0QDxyigyE5+Tk2|TbE(tH zajg7Am za9@l{TfNJieHM&PIO{$t@ZT&XeRE`%`SW`y4J)V7$Jv!otM&GlI*NxIDrn&i@V>M z7w^6-FTs6A=Wu)q%mIZ_Tf-&4gT8VfQ_a3p6OjtrMY5xQ18isB+8K7os?~S`YSwcL z;C;2I*JE3K2-q!0KCEO=ZjU{_p(MNWK>+(|7og|Dn1!eEI8QnEL4J!akG_DI99q0m z)8&W!pkkLGRnKi@?p)+1VZ2+Es0@yamWFM7tzl!V3m|2;vV1` zj)mn_gv)EQDmCql;(@O`uVXInUF2o;PL~6*2=f5 z*Q7XGY9}jOW$(*aeXuY)8NKXbGV&Sx0S+#^H0@oMR4C~z%$91;I}Exu&8}XTqEtNZ zY^}W-mljAwxN;?9HM^MWNhl6kZ?c1j>ju}Oq76b2l2EH$&y((i;?SomP*gnQPUP(@ zn{~v3x{L^QItB3!1_gg1Z=9$j+9FS8%7xSAY1rvaQfhYiT`gn+T@X5d2^yMRjnG=x zVGG$0r&oMg!7q>FOH|%KqEfR(4;peaAs!HUH{ilkP@K_iZhfZ zee7+3E4OUnY1z)*98&+H7TeUh7``4u^PZz@GulvQus%to1*m6kD^ z?pzcXF6NSc#aJ6eF{4pTU>ya{tXx;Ujlr+R9`C3-8}!Pa8;2*d5k0pX@FwPV_JZl= z_b$BqYUjhX=d;L{1igo`h18PyB)$$Lg6KgJ9^H%W5HqHq6Zp97N|5z1*tOj5?5RCl z@`@#yd6kCZ|j8^aA2Bgs{sVbprcm71f_U_a_t0dKRUkB zL<`pua9Z4ux}$yv z9y$vFr!ME@GhR$SP%tp5b3!LwYB7c#IsbfwVMn$?JKe}|=vH6ZtHnYnUc-0aat!)) zNkmx;e+9d`D8>1;}V6!YRwP@(KQHDb-I@VAdK_IQxp1kDyugtS8w&ghT;;JTv zMvE_MQEP8l`LwQ9^K(MynLdOo#t-($hx{Dfs{<~CHYn_gRkM6c;0=0?(Bm>_r1WG2 zZX9Immc_>t4tdM5wHvL5CSH7^D ztmvV42NQ`K?G4YJchJe2(a9e9Z@dbIc$ane40o*hCEmg3?jDSJ%TQ;@tQpq=Uh0zSB2dPwZw07JBH3H9ggU1w9XgHp__K7`U=O?wNaVYBm*Smw(6$H{9 zShXKvE`f7jJl#?ePP1Z1c1oZ13FjY$PKt|b(CsbiWr7k*{yFXz{_Bb4{x#H+{r27df9nBndFC*3`l6sm96I#>TklC8I@Gy}!pPXl?e3()&O628 zx1E))K$B>{KpnJiFy`a>Bvu3)_gKnHe{;CpRcwSWE3X3CfGe)D%McE5qc`t8c~Vk! z1$a(!Tf!KzE?U~-pY)!7P%=U^j*Rs9m-e3Ykr5zuy0*BJaF8OvtDsuJxgkD{Gn@9} z_aG5dDG~L3%O{Ezt6C|Vc!JV0zT21Qv$#jfRho*knMGTBhT~6fobxdCsCLmQnk~a| zIenanFe^kOXkE#6Hw4Z=f059ab@ZtJI(X++tn=mln8#V{Kc;iA^~dnFc799E`7>?S zcCc_8Y|iCkepYKb5D!H5PWx&O6rMAE@TzwY3Kry`%l9F$;DcDmq~aBCeW4+0K~8p( zYF(ui9a)YUm)@2Jm&u}iadxkofrpU9vrC^T^8ktVo2{S^1A29q z*nb&FZ61tWV&^9uD?Zg8=?@;OIerWamjV7dltt6R8GIIJ9jEiS#PhoW)ZJ zp(w!!)bHDPi-!jhvhgio*@9Ly+h_jkH(&)$ii{)$;ymmiJjG0g8PaCe?E0HUEiYFp zG*~6>Ds^_Tl4q(_Y3!LJz#O;M$Qg4 z(O+*z&*gB`4Wp7CUrb_^Ny_{KC^s(Gqp>&ra6_E8=5H2HcE}0~$ayGJonM5aMoYey zg0GJXzIr;GdpIEf4F;0PrmAs#rrC7}ila@v$u3q{Th*arTbP{0Q9IaAT!&=#E^o~t z3${YQq36ICt^sDIqI;xAx`$&^<)Mc8<7ML^)|heH#%$n~{Np}Qx_9X~Xs&;NL>e1i zZ40sV#cMu=$~dKD_ET3q-3fEcN6wrB2WO=;MKx`U2Gzy$mHocu*ry(%e4^fnlStTp z{zmt8o|m$0Ol@Lri5;g5MziJ3N5VF~f%*uaXmu9bri5)X&iM%z4d)41Q(tcYEVwL! z@#cZtP`vVqvRoSD<_wuuj-V`1;s$pDV~mMdU+##rzG54?P#j5s)yW2Po?T5)aTZcv znmBd{@8wFFSjeN1%B9LuE6zYh*;jE2Zgz%udUmFIV;-ow5LP%0P&p(zAAbyVJ2$g} zVtV*y420}PYyHQbohE4zwB-d|ZG!LeK0N(;(x7XXOl*-qT){w0d8kGzP%v39Yo!W! zHP&fD)rJb#fYRk>tkIUW^a}T19;o=(QFjI42J8=x`V4%cN#cj(U&$OF2J4a1zSMdv zN-dcql`1?aI0bB+y&j3vH8}b@J6$QUDf8@|A7ZWwl#&VaO-xw$I{G(87$0`y4a(JJ zt-UO73>1*MMn~N<$jNsH$`6xY1oHF6AUX}noz;Lb=T~V06TPLbQqSJ1k$fuaSdYOl zFUh(poYCOPeA&sidTY_wxSQdqJ6%WN2a3+2czH!H40%8Z)%Paa!>&%jNhWl^^OR;e zf#z*!*h$i_gOZA>Jl@!_$A&fRK8_W8>ppPQHL~3*G}^)LPr)*4w6e{t7-yhBxf1Kd zEv(ea=a2-dI?=VAFPhQq9D07m*-*nZ~K(=aI61|_=09f7zQ64x3dae}9HUjl+F(RpFtG}3o3n!9r+J{kDb z8CVBKrhnO*uQ2bwiPiLrcvN=kjDE5|Ldp+U)3t!ZYC2pcNWP@wcH%0Tui}gbPp??T zN)43kLuEVJal(}768XCxn3X6Nb=e{-&vo|AD{nwu`c>ySBB43fTrOj?fj2EZpe!_<`F@Jz+w85Z-o;{?b+);nI-VK`2Sv$w$h0K$~#~FAVQ1%@4 zT%53d%dra^C4WD<`B?I2Zj5;#pmPgl6gcd_;k}C8k{%}uTf|Wc+$4ejaMs4ugl99? zL&#-rLiJ`tEtw_N5~v<8LG}0!R1b42v5DQI`ZwtgXilVp2lS0Df@M3*6>QEtrj82S z%P!(I4RN83XjWHO=dB>gw>{4=w5e&_cnc=-FX*&DXPM%iS_F;J;y%Z_1Y36PaDDQ% z^{wTvcM0a04n2Xt&C|wPnx~DksMk%Z|G?86*+*K|h+W7UuYR`rMiLQ#;Jp^R1(<0d#bh0toA=x(o2znajq@$kKj{CZ|VVih4hf z91iDv`avbI6&j;|;T&ZG&iLtDeCLL)&=2y-Kmtb70M$d_Q>Ptx`_BgRUX|LOXRn+U z#)wkk{{~&%y(ApZuuJYNV%WvbB9uF9F5(osy2ys@z!I|*h696mCLsK%Zwd6ebX~7Y zBk=-(5j3_!M@yWGV3_H4y1KZb&=vBlg<_^@`;1JmsR)cW8ihr2hu(Zr(lG z{|cbR#v2&zUADE?;u$R#b$G?9KT8`8Mv%Anci{IZjMPIN^>j3eZ9Csm>{{QU&X$96 zGsMl*h-lbBRnr`APM;xE%$=Vd+RCkI_r+@Ae94jX2Ih#q>0dZO5u&0T_0_@^;3?ns z9796oY6+%b(KmFH5~m)FV8WzSjw;K3vj8R~oH2LQt-xoUTmKG!s*pSUUB#lpn0kdw zgyzd{u=S7|O9}2e4*2*e@C|4S^tQ{$b+g)7^DBKq(&=4eqW4KNy?R43*hME!_vr(L zFg)4S>J;aZ+FIp(Ik{vsn1Hb)za4uHCPMWIgqT9pP3dBGm|flgiIGAhAfl_$$y$#J z6tEiR9kWdv`ud7HeUJvzQcYjJK8pc`2C3@Xh3!hGaf9g2-@@e3^X)PONU6;XUBxzW zJN5QB9b#rCk3d zmmW^b(4QnNnRpXJJR1P}4bo`bZ3-}b;z)wt8XMP+0u9cx*}R8`Ri)_eEU#EzTD}|( zEh6fW4&k!pVEY{LdLr+z(i`u{^^YRtMfc+Rt3+0V!-ek8yzM^#fsa&1DFRSjIPcE3uVtQls&&t z_WZ(pQXDKS<&VE`Mswi|!-f%ks?})JWA(6;h}8)$hkF>F!%}FlR_75;K!aU^uYz6r zAI1@uOMZEBj$5yA!(bqcUFtMzc6@%=0gLnHIT$gNWGoTbBw8xp5R_biDox6^rlV)6 z@lTC!8okrk6zAJ%QQDq5^Z{Za<64j=<-M8JnbP?l(JZ8ue203PW0Q4AgLSa;J=&bR z)mc`U9?*HQKJ8b&s~wIh1Af>iy1#-G-wTbxM z-5tg%j|7QW7;p^oX_=cdOvrBqa%_00IFJv612!J5*lu8j51xm(Jh;hd;fBB{6sc^> zt_0LZ|FVQQ1y}G4aO;f-tY*F)rfiG9XlO9JUkRh)cg{cD*K9pA)3*(w4>tOXF73l* zf>mdU4Gibe+6l@YwK4#8a5Sz&x}>kbdBi;i;gIlUlyVsRA^5_}k|y?DLx+&7LtQ~v zBPEI+C>5ITi*fYsVtIO_9l?rSUAV#IFDE+0f-rB`FoG%39KY~qWC}Lpcnn5oN(-6t zX%?BXU0K)|;21)t0BZZOnQ}&drtAPyJ~A_91~?sN3a*hNQ(9t}(sE3u@JlRH7(fP0 z*(I2g9>bJB!;qjZY>Z{f-8hIP`Lg@Vy$lbuI0b%77YeiY?vA~c8$vdr9^xtJS_k|V zz_~Vv^I1#c-M2GT`Ud^H*5a`SNMaUbZFk~0{Ke0U+a~ zKUGRlVC;OhX|HR&sJ)ExesH@BTi~{L+-U~<`a<7PhvN|*F9^l&ZS&Qv!`emx4+V~e ze1C9|c)svZ<+^6qTDgf7_)qoYI}hEnuIUH{wsjb5m7U|aDZ85v;}WKc?*#6+{r1}r zea3+F@e>inMTu)vc8_o3?t7mVCXKlrokh@VfC^{nj5L zgKJ$0pqD=`hX$iRd5r#~&yIS3`ga&C47rKKsUI^L+9V(lYnV^DiIeabv1X5;e&$%S z7^S&0r1_A(hLC=1qqu5i4s>LHX*=&_Y)9xyj`LX2VVo~S6gxXYU?P?sv?!$@6&q+u z0fJ;^CW91-K;wR*qAoM8zjxPfApz;xHZ5Th&H=ThkF~_Rr9@##iH$sMcWmNwksBGS1j7DShihc^N0eZ zvng4$27<(rtgtk_Y)o%LjK<{So0K^|v{8Qw3k7rKuZ=1>N@$oNn8@!E0jYx(MMuS_*b6_y zbO@m#e6Gk(p&>R^)OY})A?R8{tl<;d#5YwCE+yvs*Fa+UZjup#uB}QiL zCo!V|8YM9#SCqPzrAA^8>wP>|P%EVcw@6~Zu}j9!c@n|>^m|(6%2Tgqvfw5fJ&LJa zMx(PGzmM5mw1D;mou(JOX${wp3Kpab@hG5G!W%5e zoFB=epQO`%gt-{_MJ3Q~i8y#7=)g$lx4s=7n|)fU zx7up)6w%kmTb*cepSfl=ge8A1|Eg&Z<8OAnn%00{#lA9>vBoRD@~@h$P#n^9KB%*TgMbdQ79ey6@;J01OZZ3`dyw z+`JusKqM=ro%S@OXvZqxj1A3Jp01SQ?z@;EEPADXiX6DDrFs;DXzn1=116+fe+nn> z{891RvqU`7;9e3Y5bx4a2~gY&o|yPpLfG<5-ExT?lQi`PD}IC{!c#>k5BGd}LZ+Ol zIx$0!OUz}G7^^lsikJuUQCzrXOs9e1$88+h#&v?ntLDc~!H1#`kv02qwFzHLdkAse z!;di1@9d1`LU5%4SR-8NzKVpzHlPtxU9aK=%u->K7Kkw-w&rDwtto=&iIxJtWQf=tER4bYh^@CHOEhaJhi9fN%ohfwnm;_%>5*YEUq^<4%$H{ar-dQN@cD zb%wULnKQ8R(F%-@eYMN%%Ll)ShrYM?W@>EZ@Wl5gb}JqY$CL&&IqEip%Frk?fN)(F ze!|*5#Dc+g9Gx*AW^HhG2|q%Spx5Gp)xA>9hr6rwW9)MKi&k>BkN1>2tL?SZ5dn3P z?SZ1mH^tTFtF~LJCu$eLN!wJY>SBS=Im>emqJLak#?Rg6Y(}u2IWz;!@*4jgD^EB^nT=QnZI;o-v=G0ZXY(or@Kc zvNboc2rrHwPC=#Dtm8nOvgUb?$~-^Wt=GIu`N%uadn>P%ogr2spKp5{*#2Oj1;y3ZJu-hkp4c$gVhn=%BM;SM18Te0&3 z*PxZ%9O|AVoO%4rht-TAxXp0V3ja-A&4pHU)NUwdy0TQXvR%w!IJyA)YuQQ;fk_qw z@+sa2a{K0XgwD{akV+s~7Q&RavnC(q0(Pp4HFwm#fvI2HzZrinB``k!`2lP;^Y$%M z;|ONw7<=N0+FZ;mG_ktRU&Gl?&V{<`d>Us*Txb_e)Jg zDb-11Ab?u$+qA_{rXBvBj?09S09h5ZojbI{s4u=PHqMl_# zY})o(R3#n>A|!F5Fe95bqs7uTn8?WjFj$yz!r+tkC+q}kli=Vg78I$%mz~r{zB>?W$=5*Mk)!=9yO_s^dVeyrI+y|oP>1m1${K^;%KN|CRZRI!zB37*Epg&KQF#&5RR;l=xjov zc?piXwfGf>)G@yK-4At{2f@e)SkDdYsEZ)H-?4T#bIL*ABiiLd8*piX$aFG64y(HpU)U zr8X`@HyXp$q3No4oMEA;vztvv57du)$TKWy9OTwg?^nmLP6KC4?U#)s=vpo&z=8X{ z=zoiyD4|(W{cXIX{yUV}FvD;U3HmEp7fj62pS)A2iis>yYdafLUL;1k@;M& z2zSqD~g0u?4Z7p(&6=xDc@RVP|^tOotmfPuDb(eTC;jd;|G&TBRa36ZXHO8 z5HJq}_@=V8Egr10Ng-F+q?xw|FEPH29EgDVC@ELe6q;NY+cKpwqD^jlBue$jO`8L7 z$HOiPojo_PoNo_Zfww?9a&68tW&I_y>hlWPcJC5MQUO{5ZXM9y;K5cJ8C7U7nSzje z+V|kc9oGG@MuG}Uw)>~Uu*wM0V%+ADGEBfPECjMHE3RZAh@rtkZ{5syp%UKmxbQ~I+u8J1@3V~T~R_#;bW z^m60gKmEQ`g!}JNukXco+}FWMsf8kz`VBXujSHcqg|B79a)!%4o|c0n_q+7X_7@1t zj#?nHbijSuyEJ5Rr$SINQFBJz;09nP&#J*GEoT(YO)mn&;RL+^4P*kl4`8A1BZ0!r zd^a)S1`|XX6RtKv5HUr%_a1y1P7Yw4*~O zHf- zp)-&zj3Wn!=;Oj~XUZp3bs4MrjH#;Ms2u+heF@hM;8!%~R&iyzud6z27vRMYwBWsr zRjN|irg+-@IJ$*k%V=aovNVS~5-Ksg4x6D@h>eL>$EMS~M^1Au#Gk5R-Xo*rl`Ne< zAq$SAGabw#Lx5238cx`}&P3uNFIs#~;%hh}7Ibao+=rbhU*}|@ON(9SmpSBqe<_s7 z`HoH7Af!ALfa-|!Su2p9Pu!-&DNM}n4}1>OM{?l+wH=C*!0=}b2(gQ0(MMx_B39{6RUIjmf9H>;m@})d#mVzSf#<8vaAhCuJs4}IPE5W#34XO-G2hdTXFcqO?^7t?!(1j{+qh} zCA4e7ED4<3v*C2yqFPsySGYlf2b@8P@|Bi=W)r^6+nv*_p0h~ic;F(LpTG_!z1snI zIn=EXE<rz=y1mc3c`Cx%vXPh=E{o zPy~iT#hlgdr6T{&O@2U25lc;T#oLJUA)AV|w&1aE0o4vK~XD>PQy!OGTZ+m@*ofGUxiv?8xcu-^<$aG{Y2RG zzS715hVCQ!HwQ(fqQhCy4r4kN8H>@(rbPl8bw$@RM636ojmqyal4AHD=2&$)bVE4> zv||uZ%Qhl#CJQ;NJpo;_b2vV$l^ZEX5Ai*Y@0edmI@~Hyqh>I%^9#tQvhaC$Lnsw5 ztGG?2Y`uEDeY#S)PKiEs++Sp#(M3irTZeJakQx{V9*dEh)dNUP3F0xyV+ztjUHP)k zR}RRe?j0~ztw0$(tIan(V`iyYwY$IAL;X!oG21xQhiIt5qbQ1-_u^^5R9 zdECvv;huOpdg9N-hyIXK%Ox@UyxU z95{|MvywHFT~;SP5GH<$AbzrtaduoO`-inJA%qRD2z~sq3Nm+2r+}d%o%)_X?nc04#uE`2Mlj;U)N+m zhl+O9mEPd`Q;f5(t6NluO3XewV#%myccFYZDo{M{fq^GtLemFcp@+7LdsB97CIW=_ zf_X;y5H4rrEe=uhNw@9?uqoEy3gR49y|{4+Un*MQ0l|#ECD^EY=+}@ZUbzI9gNjBq zZ}l{#qS1TRg^pFL@WHVu8S3AJCiH!ru3@*v{DcnBIS1u#gZ7JJIJ=ka&?+E5D5;az zzafZ@0gp)%HF+KIYP#~Re!7O6DNq(Ta@|SEb_F z{-Bm^QE}%VM>e$Vt%8c&nt-Ej59(7AYK|_oP%o8d^>UGI8uD zHH)*awsK^cYbyZ2*iVLjC65Q`qXV(AdP%5+(68DMbHF)wtYWgk&ttA) zhT-G?wpC0Cxc~on71Mq<8~mTJirFy(i2AQ$el3&DtC;lfqn43XOi;WIyo$LR)cxbD z7~9tWgR2;88Ci3ZtC%lm0$8qMHe&Sn*Q{c0keFjvF|T5y^?%PQ=0B%{Q>U^wQoh{6@lUl{(qZ0q% zD&|tpK&zOe$^X+=F-u|nh}FlAw~E2SUT(0^=ep9aFS5GDCDsXfiSAqT60r$kbUCVK8wfDBK_r2 zzTC?A#wKh}8`wH%W!9Jf*Gg>Ti0#SkX>c9F0y7f0rZ99p;s~6rJ)QwscEfBoJ5`+?KD@;W+=ID2bPe(zg1QNNjfiri zQ+Wt;Qs|<9Z5v3i+(SJhFoF3dneu%CKZnkVU{vI|vQWh{!U0|NMWfaWNbQv~L={D=tdM-nBp?5X zkB&{n7qGk~mxi^s+Dwx6C2rnXoucq7LK398=*+k4&yE;mpX*HMTxeJvYEf~XgPg3WSbA-?= z;8NfQ;=KibjMP~M-Yl)egmlp~;K;9f#4Gtv7TpgQX%K%8e% zppF0!n*f#rAWWw8u2*ptm2gdX0mi=2bi|&W^#(9lv_pUmJVp#pnlR*%=i-)^ z8@Xu&@)Db_z0*Z>A!(YSZe6! zhtaJ99X>v1Sl(Gx_sE@q04U>L3yp9v1zvkL+Tpsu^CWsbiDo+OWB9f=6W=ZmY~VM+ z64SRPemi~Od@taePD8|~B`sPa;F!bPIm~Ke$~2-M_=VSR0X!{<#1& zxMknBVBiT%-VO@PgGDDw&^|v6pt=cf2nGN#Fmv>hS^{EHi(P_s=(Sk2q_7;+4xhO> zWBBK4skj|-L%-ELxQAn|yi_Nd}llJ?$(2(Jff}6h~hL!$9i> zG-e=|u;wng1+dy?fFYiWQPKerfY9|e_|p~;-Yl;V6Fvt3CWi#HW5gdFCo^z6k!-}O zo1+@=T4fCRpj;;SkR~d}`I60otvLt~LZ*vm8JZv6ENcjhv#jQ}xe{JjY#Wo|Ez&S| z77oxb3GiCd-b({Zz>cKO9-}W{vUAz;5F7gjh=J?~Pomy|qF84A@Jx&c(*YE?hMz>2 z&>P*&PZRj*+Spvz^HUl>&EqFCH?QQUBNlwRfuGD{@VWf-M}E4QpUmxRbl$GO+=DYQ6H#dLF}o@4q=f#tENRx!Oe;ERR7kLec$ ze!z6|FgcIuqXIu-y1DvSAw9AQlA-Ow>2p00DK8i>uBs8i9RqhVS9ME5gvku?~{6UFXsY(VFyPKwNT{n*}>9M{~S2A&cU4!$P9=mJMiT%UaRqCnj8gyWfPutH8@qu;?6yP`S z8g#J#xml>$_o*|N*^jYnQ0(N#+G+I0for}x0v zlioE5Tn=ElYp{Htv1`z-`#zcE>>u)d%95C4cMWPTfnb!hs|)`}_&&w5HP-j3>QZp( z6m|`6x(x8M+I8Qj2rK_NzE1@cb>2mG4c^4KCU*_cV}yjA;G? zxId}a_QIQKGqHu8pb)zk3+E^=8aT~pSqU^jZ=)X+gKE=5s$zT4wS{@59~3oRxP1yg zs4dbDYK!oL^5cW_gId6GAZiEU(~D7b^bP{!-=L(p zhp71w6Z5i$m;KlfD!AZ4ZaD%QZS_95--2WExV7tcwLnv^6;8ESX4wEC4RvF|LX%-j zH?66K`seQqg{T$olWQJ5?R;3Bj8GT`Tn4PL&4v5p!iy(gSH$KqAX;eVEx`Si{~*1!8UO19Bmy7(iC(vIsAGga?;K z82F;y330*o^|(SKklKueZ5IBJO@g~}(aGqEqIK5L7$u5XE6h@9G)q-(TipkPTj+># zP+rZgJsr>Z&u;jQBRFfXT829vdJrSI_4Oe(Wq!A^s7tBVlsotNOZO?bH`c${qGIPp zMQhHUJFh}HM?Jgp=9_NZwpzrS5_?Mr6i<&*(~G^OzQkKlBnC)db&=JRsHNQ??rj*M zb;GWRG6(sl5+H8*+2E~>wWqH1{LSK&+7P^I8~)JK*BQi<`hZ>Aj9ic(S2yl1rw@BD zd+IH)1Us7@KiTU1*72jpL9OfK+^M;j-3Fu&Bx@yDuZI$~Gx4L2VcPUVJI~(lJo-SQ zHvhvO-awU1Lj!*apMGA`p@)AtDk9k3cU?RSm$+#6{2+6?qU@&n9@Cyuy zt;Ulzi;3DVi*yNMfD3IZ>baKO^OyH2?jS-33M?5=%l~1^6Qn;N#odcz$k8 z=2Sfx(wcGMr!3Gr&0)>Ow=|vWkA7`O%FS+#*E}bfIkZP2B-Yx5bmZwgtZ- z+Zw*&l4B)}4@S{Oejde(&Cdg+%+Fus-(}?IgUGLMfa<3n={&5CVPV)oy+rv)z0`Ll z0`B8Xlj=~)G(O*YbDCn2G%V&^0uG$)PUl0337}*FJpTnKdhl3j8GM6uX zhQ#&Uv**MXCJx%_IXiR)f;T9Y`}Vpz_PVs) zZ!=v4z4Rn4vEn6;`}W*b6xD%n8j757GRMc1S3p#%qkcI0VxHBpY7Z(ZiE99H>c|y{ zH_&HMlg{IhbE^jmf;G3;>Ztn!fUj6OcjMV8icJ4RL(1@FAQ|hQLG*7NnuA%xt~%8MoM-OFdFHc}qsoVfuX$Lt zz9$4zvA(CwdC%&s?B=y;f2Qo;bhA;Klz!u_ellMlymDsaU=8G`MI^lY ziGojuV@J=xLE1N{DJeY+KiV|$@c0&`=}kr+Ray>x$*UbJw&OHm(~)?k1rT~z(eX`6 z%daMkYigJ=<|E~Ogm_4p9{N3^K_yLZE*kUEh5k86u587vQ$#IJ$%Y+bKrI)zj5}*G zF|r~P1R-dZH-EQd#|{+#m!>ZgL=;mN#~7z$J~s;c6h(ZFh41kKCf_KEn4rf4l*VGL z0I1F*1aifex2O-)e^7n8uV#y-HqqB(S?oY~V%4+d(8s6EO`JBAM1&Le0P@45B`cbzxU6ir8XnHg4hEdgz0uBWIm0 zjQd3YIMB!Jp4+qyGA~IM&C~HtSm7}WLCk?kh)0hP$~Mg#QL($TR6roj+yqz6UJgmNXS&7N>2*Uf5swOGT>D#S`D=;`pfxd zXBtT(8;;9(ne~nn0oY+_Fj`P5sJb?Zg{%wS4dRH?2tGAY+2i}n;n?(} zb*OVgd0$h=dUgHVwSV!ux;Jk$u|X$e5=t>^-}L;!UGTj8c?+O7H=43gh^@4LoE~W5 zH#0hZ(~K&KewxD)a3tD%Cf~IWMo)`(P^;&hKx-^|p3(=Fp94$hgIF_C%fvlIHTx{p z=TQ1BDKG58uU!KQUE$O|xenbJf!RVizQ#D;2XZ|#0Nf@W&ez=M`=~EKREPd@*Czti z`*FMP`Xf{PsiS$7aOFN;1Tg4b&%D@DB}GQr-z83?QE^K-ybtV#1vhf zsc7s#$1$pN1d*RQ-^X|tTb=xAj>u%8_ub2NGR^HY5Ztin>JWt0;qQReG2@7?&i3+t z)#06afzOUnoorSoet_y|5XIQmxr4}K#BLzCt8_TMbqK=h@He(Pb0}&xI zJO_CS>^nwv7GP&8bh(Zrx>fIBzP}tJAFcqvco4qTO6XbPHETd)E=vmrQ@vex7We7P zV!5gf*zj@l3=_n!Vj<=b;%*bf4*{Xuzp!*~(}N!c6WjGC&New^dE*?bE>1KS7u%6P znD{&(IN=5p*M)Pf$CF@V;>+Q*4R{iglDILP7T^;*L*kZjS|gq?ztDUnpK61NE#b5s z;k4Fp+OBXK>6Up(H=b%cpTO!+63Lz&OQa+`nn+1_G?9|yac?s>mhLZykDbu2fl!QlfQW72}lBS9Oe~FZYM-wRtH;BYe)k_?1 zx0r_8%mQ6^%a2kv|u;EV9b7~x;vkM#l+;qAD`6F1lqKSFPb zJ9>mM2-_LjC+gdKF`$crqpDn?qI6zod^M65qSy{ zHs_mCKW1tvQ>#s>zh$bIsoPDdzhvqTrke3S#Z=q7NG-)5qq;t(mNRvkDfJ$v)-m;E zQ|dgXZe*&tv;wB~Fx527CRL&E0yrqrJ^^%ka@OM959iNQNYzK7IO{4pvxiK*pGU1mx>lc{w~Z8W9YnA*ZrGmE}Pz{)@`Q_Xy6M{0O2EtVTu z#!8U8fe2?aA$O6r_H-CKy^}LNBb27%-21JygO%>=cyC@@rn|e@^|_4s_XfKWETae; z253eLtLPx?T!hs^02k#@_7vRpH92QO9>WB&y=E=!O5uH&&L{@#ZjXIqmyUpbOJN@?}xjr=}$qVp1_GkvRjFx)DXtxcZ| z4i#r#>CMZ%M|{mKi~gD#8W*_u_h_jZ_+v=G-dyfH3sbhPGcL}A+rs?P1N_Y4hmP0mSv&hTR z>VU%cZM^4P$7{*A=O)fU6+Ne^eiot(B{izR+_?<9@4j!7JQ>vIlTZMDt#io`Ao)FR zvBu8ra3UHb5iKC1;o99;e#jceb&eJ&hIqyi1#O5#ag&bXVS&P9Z%)j^h#lA2g=M4f zTZiXj0y}izyL8~2CGg1RLzpZoBaG+*92ueES2E%@0e3#( zenSBr;do>}gqW>qkln2#e^elM)bGUiSFe)bBOQ-)fd-sd8i5|Cy^1AngR2d%Bl)^c zyzZ8ush+zqq(OG$TOo4EuioDI3UbOMt4vzd`CK?DNhaOf`EWSN#w6>jp3pLxYp{I3 zCv>-bxAXm$SMLlhkR_&hW`mMcQgXVWWDlzaU0yJF7@#?_;p=Og1lz2ymW9qXgA6A~ zMH@{kk4cdDS0C^my~^VXq~cT56y`=)S$*_VJczm0iVjC}vUVdr1kNFN7XF|(k=l(^ z9EN*2Yp5;nLWFnEAwa1KpvMGom1inqx}&95V2(n_f5x#z3}xOaP|kej3ARz>6IX$Z z!z|S~eGr>R6g0WbQJ06;fR~xpn+j8rN%G9@cw`G#J75&#T`+0`0Wo?!`fGB@QU46S z`^y6U5_{0K0b_+l{h1irDmVHOG>+YpW=@#WI^Z}VCWKQ>u;WN|;LqvmXPYAn^doul%ZDz69LWW>i_ihvn zsk@Jh8k1zbrGLLgeD{nGaItjg1=jyAKdZ@i7+}mS>AWBY$yOlIWiQ>p!|YOV~5lNoOjXW=bn3rBRg;rUv2I1l4fkCaZQrby+mirO`^Nr~(R0 zX$sZPR9jPrwi>qwo|HDDuCBWuc2fPz$k&}z0Zpg6CXMRflbpO;Q5^@Wx18mq`stpp z&U4fi&@`&?fbkE|N!b#We4i4%UP<((Xw`aKqKg3Nsyd!VsxAXZm(jG5>Od3y5UYlX zN)6=RzWZ9O25^i*K0WWFU=HNwC)7Yj?Oo9+y_*7SIQQvM8O4=rqg89{QEYYi0NDFE zkP(Kq`XCp2SbwQuiibOV4|9nYFg|0moQwJ!#VP6ILTX+^QPs23&FE z)X*S(imx=Q*FH=WAUzed&~8_3M1o%b(CFwCAIGviv-*HcRk2#g+1c2p7)@7-a(*Hk z*e|T^Z)K}a$%Y~BifvD1>ss1iE8CeV**KJAkwiAT9j80mffl%8bAe)vKx)bk=JE5; zc_-7>E!VOjh{AJ^%kaR8Xw!vUFbqkQlDljn`C!Y=ZB~YrD#H(rg)B!l)xd(r&lO3k zcS_RAXjQ#E-)+QJ({e1M>_Iy+utqR-apTY9!L8ctP66KF#`AnC}#fBux&+*;2))Fl&j-*ppTXm@aixRDe zk*+H1!&-bwuhJ~(5-{^t5X^{iE2Q9kLf1#9^m5J-Tzyck{6dRMQs!~TSf-t)I4#fb zSU&Q2Q}VcCw;+$PiT$xxVaN*Oe{f)_D4{9)R1@seYR`VFDbGEon(_qT(daE0Y0)V; zO?7keg{`(Yx$Z^+e$7-{GjKj}aTg4=5S@2kRd;iw;Ft8JDpyStKK`;jM@Tdv8^SSD6yzGq~g z=tHaC&w0}^k{+d-$_2xgYY;fN;h%FCGqtO}U{^^zj?>BWIu*_6U`hI9YiXoYkK z4>}HaG4q;q52=2Z^8t_ux1ce87{H z3v%VvJH{Hh+N^bF~{Efj4i0hZ-KjR9+BpR5;Gl?weEKHD?(M*zl!}9=HIjEj`pCm&?J) zzcJT&+85gKXiY0Jhu%zt>w(5^161bnR=xTFpcU?$O4@@vJh* zdf;V)-1tyDYmnz380;I*MVT{-6h-?CpB0=;PtC}wNtgrJqQGj;bxh>IIeKZS*}D-F7=6wn_=Dy0$K&$R<*{H z6U}}PLt$Q)hACnJPXvgCX**O(|BnUdMz$yYUi2!nv^+QDK`^8K#!j-O)xnmkv&j~5 zX8@fUxtGD)L>c*N;G}l0AUxE7 z;P+#9A|?m-ih^&-fss#ug%qPTf!s#tA;a}4Rx97 z(rBL%E9XUZ-dy+UvYxto<2X)7IZavo8^wREAFYI1ZysvEU8d!1I2P6Q!z2whsp}nR zoB94e^s0DQNlb{r2dw(?-i{+?33psCp$G6h)=;B^tvulnjR)TbgP|%m10&60s=)BP z2JBpXKni3A`!TT1TUoB-%}qjhca5U*JSt)2Gh2Zp+c;($E7|yLk7NMyt?wZDIlycm zB2j~rgBrM8)f(|)AePPwJKwJf8#=?`yF&fAYJ-ftt!kSOg>r@ zt>9mwp7bn5{4co4*`ZD*fhR^isW>I-gE#To(g_Sc7+l&VS`kB)NJ@BVdq-d2J?lV7 zfN(Tlh3o>;C$)=4{`qti0112&`qnIEO@Eev>of9ryUUXJEyNf|j4Kqzoc0sS+uFvU zb~o-#Z{|c)P_M{CJUJWh22y$j$+(r&j6WqugFPn4c-zQYaqL$2D`XI0c|{GY2Eh>! zH(FW30esl>-g^V2?lcair#CVEI^*N?^v9V#+4v+q{Q;(rHa<;HU(WRYMtget%}BQf zY>J*iz4N#%T%D+Q?(4n1cpQ7M;l-B}t#bxw#KJ%{dZvTCEcO=D^D@`Mui2{NV)E?= z=4X4+Z;X+JzAI+ZCFVPhqyi?5GMnwBpi)ZbGr6DnL|XD(Bqvp#y2D1rU1qJ9vEId; zIYa%j*1)0MNMmN?qZ2yTg2VJHyrsQ-_cxSY?(sc9BL?n`;HF9FllV;BH@N~gXruW( zN@sc&_9@Q9x-UAZAUF098jS@Ayspp16keQBR?>dQK+HlKRTba~AK7*C?_eDl<4x+i2NtGN^Ci zyIVa)$4etfv#1aQEi%_D>a$6mLpWkzhT$X}@M6g{40lA!yrmgfpA@mrr{cpF<)=@x zL<)uGV+m%=AjTXA#+R>Q@U&wZvwQ!A*O9PdKZf3o#0@%d8;QFIxXG7_e+g`3DG^sX z5Z4j$w?v#to3lvO&BRz0Cbp~e6{bR)y8IK-0H}95i^c= z)H|E>jdc2_60L7amEUFCb`f!}gWe~v0?~XirOMlgxu2K^9GE+a`Mkm`KDFF#-#tV= zL}X|CensS83UZ=-)xb1|v3(S3U)?a#RMtanvW--$91Vw~dAP-8NrVk)0zW7wTphY3 z5$h7*AygQq1HHMT;L0fY&f=du<@jdAk;8xOd>|PYiRpHnMdX)l+YP zAL10CY~Z(zv+=QE8o$lqw;B947axsTv+!xJNs|Zv*g4WX*aHN7&kP|>wD5<~!gVfw z3pLY{MUoQ45UbBlwW%cQaMmQ~o-(|INpzb7;>yl&gsoB=_$o+U;3FzE0jqz{jLyBa zHKU?A)Jf)Su*P0$A`PZGmpLgl4c+N7$E2oFg3ZFzG}>uRuOrQ>HZ|=RXtce;Q7=@P z7c}B6+BN8pXScCa91G?%TG`0xLnKsPz8+qJFmGo@mdtQR`p}-UyFB|nZwRG{FC#6cU zTk*^64}cPtNp))|H{oykik!5W*HKP(*X>+3csqxg-rHK2@9XFUZpmvjO17KdXN3;2 zUFkz$0oD%YKp|rG29_7PO`c$vEa+0-VOW+fYr&@;d&FEM2$8 z6`X56&y3wN^El^ZXu$|<(B=a~D+1{*Jl_vAa}mJ$taWQ_PH`b=X5l0J91H6k^q!Q` z<11F|Sql!>R}E#&IL9m@_0vgxTw3k#1a<3dm|B*zhG<39>(dUj0vGU4>`F4E@fgaD zGXYxWZ>-t7__5vJ9qGXYzW^|aiW)_pIuiJ^MWB`#>quZ)cLd(XYQS7(5y+(;27yT= zaH~b2f&}J}z?|*~JO~2On&xQ8h*oc=!uMNEEFdv7u|hSGpy5p7x*l`EsATdOCI^v> zsidF9koZot-->+;hk{P?Z6=^@+gRb3@nie^?y8eR@LvEXL!=7G6C{BLEdqBCVe(zBEYt=(C?GLY>U8H61bcMR(40Ao&-i&1f<0v@a0h?4zLJ(L5v&{SlbwD_2v+mv)gf#}?>gokr}AFp$h(l){?1AbXWpgEyCp5}kC1nR z^h{&s`DAnGH1q4{fW3{_MjH0_fgK-gHU~R9A3S;z&HOu1?Phve+#D3=u+2j$$+5)= zS>*CC8Np3_&vZon%cK71L{se3S`R;}wd0^Ab8`FxTbs!m9uZ{3j%oc+77N6zko68N zn;E!Ls^zFn0DnfOx~-pBVJf5N1_LW&l_8M3kw36@+jt{Jlw=dI`j$+)#fB0!@nge$ zJ2^p|aHb-3MoPR2v+8T`;^uFXD?rX>S%0Sg)U82WcE^uL`C}G;)V@kHI#|8^1o>^* zf*v^~k=xpDm`}iM06E1C>yi*-To2Leuboczz)))4h@nFmi2lZW=M;AwSVFS<~j;JXaZ+i3N0eAumi zyf6GJzFrI$GeXK7kY59m*oi5A%ak`tnYeLa!DpEU@|HfFX{zCzj9?phy3>o}2dz;L z9NN_}3{U-@w~N=-v94!4wTt*Jxxp*!M`L(+SVIKJs=ZwH?vziD zH}j(9V&8O-Va%j2igOx0-gC5e$7L|7o8PJ%9^nq7=1sf8*dVjHm1Ljp=%ri8NxG<-2zA|qZ zq%NGpskuIP5NEyau=Wqh-JDUoSbyt6G!H!W>v4*LmxpO4OTFQZ^}rYqjNXA4 zs1<_NkTin1-;Pf2EZGO!*uIfpOhhaKv5oD5F)e$l1ldEx7i%~1lPI_4$KNJB(qsvf}_RO)Rp|*u*O6=*<8guys z?U){F$I}v_HkhKn-&sGYZ)XMKngoYWjDJJ~#7Z%FJ`7<@Vq9KwESPy|{A0&!2&jy0 zmZU*V&Q?pyz03L=L3YM!M`zsH2c1!_^eZhcxZ!^#&5c9YAc!OdPdWu0z^k=r#jW6h z+OIlA=r9`Fy$G>*^hvq5Otf@L2dew?Fs#C+5BXxKl>7b+5%^XCgJ?W>FW3r(wvOy5 zgNk5?p834FP;Khdz4|f_UftGf+M~0^;|M>q$JCOBg~M>*xBOzhN8JN_b$0?>Kk1^* zi6vEL@T~H93`#{0m?eP&%Ln41HU;NWJ|~@d8E{0bd!v;M-_-;1tJkz?%evSPx{>8< z%JSvjOSQ`pAx7l6Z&IE`dU7er65;`tnJ)1OAiaAaIe1Z|xPMY=VJ;roLhJ6Xv^?(S zsnIJtOBx{04I^JlW&k%J&#m>>=~Sx&Ycy}0ZOo>eCmgI?X1 zS;07EIG%x!kXxur@zvgBF0j~U8B`N2M->0tz>pXZydh7~S^Ya@$~l0-Gq3bshNJvT zy?Q3Ppfqss_OaUEOGA5?SA!EZ2eq13oOClJ-G1#QoO;*nmv-wlt@WM(80C9|=TD6P zOM8tuiV-=I#qmx}n|=z4P+9g`Sz3_AV%A5PM;vP1ahNM1HJ0KO30Jo*szdbs43q{Bgu9exm3>vnUZ`Qd+7o6dNAW(=tKk=uiF15B zOvUqGbw1{KM^^pt#_x!jdE1*E+R(*WVpi72c-9`#W;h?q)xShQ8*VrkV!sqyF4P*x zA{kCd{~_|mZbo`yj3IF{6A|11MW-N-X8J`6ITw?R#CCZR3o%ZDMJyL#Ym_PYntLz; zch&7&Jj`gJ_TJC>0!xZP5g&uuvCkz7+EWH6d62~`_i&F#c#o-0)Ez|SsW9_)(|k84 zC~5xYrofg&^VKU1+|;4CMWBJ$QgEv&Q$}Q@eT}sEPo+Y5OI`?x&qaApAdC zV0}|y6I>G%U)6IB7U5yt5MD>Z{f$Fx_X!8Rr=U|KZQ z8rYly@BmcgLgJJoda)#Qzhw8;=!I6eEAR-b6=Le9R_$7+2 zopv$P5L-V5aU>J_8^a;%+b2=rts%U)2ODigcoBVy+bz(i+i)W-zrN}z-!qj3^_5TJ z(KWqlvtGFcotp60_`yHL$Yig%HfvQ|^qMV*89d74&+^@K3oPVnge^dUJT9cxtlGwD zWGxzl6W^yKNd?$`1$~PPF)`sCpp-`C8X(0cW1J_LqcTrq<|zewL0W5+ z$E58Kx8hAsCm8-5Kh1CB2W1n}h{fVJAlC_oD#9i<(l*x>i&vqjv|8;3QZ&#F*B`^C zSY$zQo!uX+$1pagQLt}u2=@9+iOs=5YUzS?s(16K4pFJx(ZVXr+fS)a470B|Lnf61 zuD^+)w-7sNHBKzMfO)hW``{CBZZm(0osxMMmc`~RIG;CrU4xHj#`08>xCRe^M5h>K z__iJY69<}3M=J&&6l*0a@#SwNSh*E0FqDWzm@+HRgp(^)i6w6Z`{-^QR`=yO^pzgX ztu&adJXL_ME)lsze_)(b(9m;Vhf||zp*QUCoEF9rV8~1lsvaIYs^=MpAi1f64NM-{ zixQb{g-;&95Skcc7$3WK9UG=$h_*ba1-5Ec+w{PCy=qf&VC&$jZ7O_G-K)!cBPJW7 zvGrK!dCHC0(^ZF_a$z$*z`YM0mbetLmfeh{=kn$B9uH-eyd%>&=I3H$2z0Ehy5Mmn;6cXRT`D!Dbi(hi3# z#jy@xD|QzTtI%52esFgro~^aky<=UZ<+*hCo)dfij4|Ls0WLWCMRDgDx0tZkuRIjl zB}y@ks8>!wM!uQ}n@80a?WN)YT8q2AB(P;+S=~F!Zbw`_l2SGUiAIfQN3>A0ej)br z#rP^~$!6a(`B+M~)aPeUEUn%jEbR>JkH3q6r66&xWlPd4_Dn=KA*zIgH^=HvtV7=4lF3W+?n8CILaIxf|yWT!TS zorBn_h>jiEGvBsaU^i>Dl77K~=QQ9 zc^e4T7oE_36SZFY)rH#3LfBavGZz*{^ZUYwbBI3ae~Pq8zbcx386@<}c<&~fUR+HT zh5RGrw2Go+bqW&6sBB|dzCw|T=d$9BS<*mNVOLJyT-6jhQzX9^3`~A6ye9d5#G>T) zQCpMW$NU4|ZN4)`TCkVuel8dCxIkCdTyR`Y#((hhM0C9INgsGYRCx! zEaN7oYB6t&yPC533Gby$N>dMrik6*XWU=FgTL$6AtPV69SG9-p56r2fV3x$yi$3su zz4ge+&PGW9e1Qe8M|S|84frdM;c9)B=OW4PRex40YPtLcYI_tlVt;_eQe)Oy1z&Gb z+l;?fX$MTgnSj!^S#T>qYx7AZ;YD7X*^7U8`=U^SV5j73(( zZb`yD@S1DPVglehQz;4?U_?QQC<1Ul0vhAb9t*7uKdoZc|Ah5p0vm250iSFjfC9)8S7>(um$UxUX@!z7Yj1>?uWz@orjtxFed;L zcZPknbU!wVppdqYa%iPI__s%Dwz)z-)iM2HHq)yNR0@k>E)UId$PMCp^$xw4291lW z0hI@&5ZK_h0wqz->sYLnl?Jw8%^0cKlHvOuTnBx%h#UuZ=JY~;`wa`-Dur(ATIdTP zl`OPH3dP-V*w~A>fO8Z&x7$J)n8GMaFZ4_l$|Y!*HqKyisxd4TYhX*mUue|>eRLk@ zvTHnA^CiX&Tr&hg3aK@xDXd7`Fw2qQDVZ>=6t1zceORr`47-p3g z*bL!#a%X>Ib~=16;3-;1)SJJHq%riS&ifQRe!v!`I&b9RT_1YfyQ4E<`)$F5hLZ+~ z6V9Uxve?1ao>p@(?;R90ORiuZbfSHLaZ}QS)-)l42@U|XjIK2s)1_u6P0#SH!wQUs zCfJHcB8Z8{{gQsW7ZdJoO~yjAKGmyT=GEaCH`S|OhEI=nyGOqW7gTbz@f2{_LKz^& z>Z`BVS9oa~7K2p40Rqx&;Rx*ee^V__O0_)NWgb>;sz<*JpI+^D@3&X$x^Jr%A4%z2 zEgZnv*Rt#>Njp~D2XT(6VG3wak@!y7%E-{f5lrHD^#6q-w_ynimxF?n;;Y?IT+y}$ zqbpfWOR;gsBb~Yl2T*z?o>*D0Lp_b>Iz6x!n>Ad$>tG{1wAXo{@$6ro;hj~R^y>9| zYUeaexA?2w53RusUSPeTxm$P}Ep!IleD#|3tRWUqXjGO|wJMpB z@>985H0m0NE;S=8E}N7R5W|6`=uV?T-Cfd-Kn^5>U2qLX$lBxx39WW&)sL}h<6$4r zFhYQ4kB~|hlTeB~fi|)cfn|Jk>%lfXuv!|F8CazSR!Z(xJ+v0ba+XRBt>k;%4g$-Q z<+SKEYqc6%57w-NpSBaT3YaC0%Z8%uU0dhHfR61ZS7qCe)y`&^MC>!X*9d)t(C)bV zTSTUe-P5&4aBPbn!F;h^4LWC!Fq$QLgxX(vq~6&hUg;6Y#dr6}FQ|m1M{-DptZo)o z+bTGy6uiH!MymuZu`QATpE;l>d{`> zSry`^>y`PDOWc@>ORn(veoZI-{>F`*N`m;XhfTl3Cus!{!vpF~bG2v#>txr*QNiUH9X!*I4EZ=Q1)VD;80#RBks}Oj$fu@jD^~;%j+Sk zVLVj>qi5wqCmg~S`W={)eHJ(q>VCE--rM<;*Amp-UcOdRXm10=s$tva#oka&%+t)e z-@@T!6TJphRGi=xhp7%9x1OlxrV3C=IK%D6rhgDQZ4-n%27Ap3 z@F95tQpaiz)F#sfumaa`69nO-ZRvV>n5~_MYatkH1NrrV&+%kOe;ywcVBb;%IgM5x zG1ovv#WOLJ`=05c4hwjJOPMnFqdj^i`A4s^k5Kh+&F3y(-6g5O5 z5YknKJ}LwE(kyd0Gkn8=l7jyUW(I}N7b6@6U|-W2dkJYc&~O&;Y$5}8Huh$n1?*;q z2a$$X9LRXo{^3OJS18;v{2}fGz>P1ES0bdPnCpo@3i!q*Fkt&;_9}T`LE5lC&?h?% z0f0T`_p0ilaGDu~S1{a5#;d*F4F%hq{&^+mZ?XdRKx z&YCO()H>l$e>&J=1!Sax zRUp}_NLuqek`>=n2tK<2W|7XLWTAljF$3!J_S)8Ttn`H={%;k$ngR$!VSUwm-zr3J zKMaz%8;$GyRjqZe`fB-zi(F5X8`HV^oUJD!C*7DXlG0?2g~0ES)w0|3F7$BoUm#|< z*_&Q`AO#HYm_vXUu6d77MOCQ99!A}i=h3$f@xHXlQ#z3}PLja8_mGm0tT?Ya$R)hZ z4rSA~grgYsEDg2tav=|w971Fj`v+78a*=c$TG7TmdP2zx({>~dT=BxER=rIp$EpkK zs~^XOYUtEH2xpBosM4v!(I`~!aa1T*7M*tIaD!-$=TzJzp<$dzWC6F3kmvpi<2c5W zg^>?3dDs@})oS<1do{$b-oZn`94^CN=E$43R>SI-eY8n0&z%Z0HLOwJCGTr2dFOh9 zZ$F7U8Wx#VtJ6e&Rd*u4l_xqj*HLh}^bu}0h$9XANv}c)2fhG$GIEAC?>rm7CNHnHUZrrG`Uwm*J376BT;HV&>gorao_N>@mzw z+Pttmk_@Z28TKi;JHV2UR1H#DZ?nv*{Z7(Lm>0leONo3t z*JfZ-pwA1(ml$~*rUe|PiOFFH4=Y}L2pHK+w50IQYcUn#DJzlt?-tk}bCur|A7T`d zc*@KZkTEhJ#8cyf(1V97GK@NJ`1m=#d;TTEZ8xqn?>vb6z;j7y0jp^Z>sLS`_6d-T zMFg#MfVL6z3PGz0+Ts8`NYFNdwh^?)0a`}Tg9PnO&-GsfEhFdyg4!LqrV{jD1a%PP ztj0M6O(m%3yJ?_P2s($LK?IG#huyBD4+3-wLF3aw2M9U}Jz!i;(2b5+|OpsfV$aex*Oq!Y9^9aKfo0)pNZkb@f+5mZIcXX&|y5p)qj zuJ=$@9zN_Qdk7jvPys;=g z#C!$W5Gw@FrhOVoc=RUS(BO*2eN`aWKR7teKN#U)1_n=wJqo_~3xhrVLxMNO7}w0& zV!@Xvf)e3wpwuaT&qBqm)e+r~ZUk7O$ynPOBsHlVYDt9Ory~d7s^hK)KQ{v$pP9P3 zLGl%8x!UmCiqv2!a%LXM%>9j}WR@s-i^aeEHL&el#n!!1c-N`LPVT}OP=T?RRgm4E)$lc|QMGHe-Qn@4hcflq z-f-!_Pzhv#N2b~r=3KPNT&RONSDoOb?0e=^dqVyfR$)L4E5z&Ac*H-=WNpfh0W|pp zAXo-<=%EwV3xcvL$IEAOG=w|LK#hD(=NR<>qVY0oC)1-qvkU8bLg)O3p#d9zZC3-N$0##)lk--R+SXEQeDPcRv+P^8{ zmS@S)Ri9z7^Z*7nPjb0nLl9?idcQ^ZOe|O6LJTgfLVtAS!k_O)cW%~DQ#=?;6EBvY z(hUQE9^1nHQd_pRPw{(g^7jG$UYY#87r*1nE#w#Y<92Q$Ty-zv3IQ&BaLDB&)F7A~ zpKZ0m9yF_nUSZcDZCUs^4*!{(@6V$dO%Sp;R(%q~A_lJ_TTP8XOS-i-(72ZL+?QBt zdY}Ndwn$C8D_E>dY*i+Nf>-rDvR}bD%cO@+u)IyZuzOOkM!xMZlv&$J7@n;A3Cett zkFz7O)$w)q#8V`R%jVBi|E<}wHLt3^6vyf~Qevl^N1;0c);F^Mbi+Eq>G5n4! z$Lai;;Y+eYr-5V{*a6YAc6=U=LVZduGaSvKtYrJWzFMx={oaK+{tVw;^i_%X^!E&w z#TZkEoFqfVTxfp$IQWa8bV4>yI)U$=PbpALmuS~dpx0ugXlGTP(p!*KFVIe=)`dIN zAF|T|tvs2ag(~6W;wXg22`Pn4Lm~PUrR1@vyF%5gse= ztwypjCcXb={{qcW&Q!)H-F5JVL_l1?$|LMK*#)Nh;QgB|Z$#um)z9sE)e-iEV1qGD z*gF_wS*&w%e;?P%!lh^MA%oH)<#^}~|2)GT%Fr(`o9b9=7?@#kQU)w%@wVAE1Cx?@ zF>055Ku_s82)T&C8%Gm-`03#!A66o{D<5W{LKYvk#=7Ifxj?YhmNkm3R$A_d?_zwI ze*soPSthC@(mo|wor7N{tMhLRv97~vS2R(b(@-7rDkt4YTQX9GXbT*$()_NqsKIR6 zx zWQ2>0sMV=Z*@xJ#$7E#7Aip02!Jfq*M{?H=zJpa!gZ#CRfKZw~9DhKBJ23J0z_NIN zwJi3<)sR?1h$!!3kig$eC|#082 za^U4+=7W+Hsa%SZ<5!v;VFiRY!6~F+gR2Q1D-`;huPG#fqoTbD>u)}1WmWl*{uPQZ zsW}iFJ|#8?OP-`cGHE__sNESDk7g0D({GR#rr%Oj%JNU5l4Q~^|ExRCoQqYLH9CHA z2nf^28Rssq4-ppTPXCUDZoK~6s*IV`8YmB7m>O4;_*@6upFmDEd>%1wA<#K4SAPdt z>4*x@G*3nS9802va+bN`&(H|goLTW{cg-JzGAzMZ^&t?t3?Uy8zAJX?>zkoHxsbv1 ziJp86qG&EhrmoY4)Tkg?qbJ(BtI@;vBx-c>gYIfn0|d0mKQ!3Ge_C)*e2noEa?ZJ{ zxE3e~o)=8#XgSmS8;hCll>W1ko|HM!ONmKPTJ;uN^(SB@T4m`mb%fSs^+{DW8u|;; zYfVvm;@vg&iMs{Inxgu!y-Qg+=L#tb9P=EMt>dt6k+-hXR~yA@&N}qKJzF{SkkuFX zZ(#geJ$_}kMPAGzmC}6p{qE{C1PDoHq^xgM7w^TGGS>pDxg(w_b?M{i1?4Xhh2v~a6HgGtbhyl zku=WCgXXYA>ZA#YxjTLMY^sGwISmR48L)O??EmnDEcns7e6@9GhB4_wNV(Hk_eY$F zZeZMA?$RO0t5K49Aqfv*OkV*ZU^luh5BXh~dqrkcdYNpKtnZ>`>Y!$9A(nYMINYKk zK}5}&XkAK`MQ_T*4-Afo*|Rhg2kcmeVK2vRz2|CFnCA^QOqZt>dNpRTId0o^KH(MN zHEv|nRuSErTkFs?+bBJo)FIs$nmQ}XYereBT2Vho0Mz3{HG zaOtTF&-XpwOD-_H_QBDHZE)lcopZFoRo2rL%Ko~cEYv%mAD++?^~qS+FWysqbuY{T zt%ciV-jbWtJe&6LY}yXb=WrlTZlSqj4qtMr@1CJB?qgwz0ea$)x@U%N`SCv?h`eU1 z9S>iU3DeZ|xJ;94-Da5%AR5REK;|$mmz0{hka>QEL~EWs3%{*9P|oEPClD~&Uh>ua zp8GG58$og{Sc#Z-L)D-!_?DI$t|`kg9gd+~hM<fg+qPHBtk6zY~ z-{FU}bQ}!#s-@HZg)^Ksc3_921ABo)%qM38;KcS^eAs>4j+IR82-JX)Pf(!)^g2Or z5j312C&BFmQGpwy2^#On^*e$#5>!Ue3G zCPx`B0~-->w=jLHBmHTnUuPIhch+eg(4m|NhYP{kXiCu9* zcZJ8ppKVv<=N&Fs2f{UZ_|s6-QrjFXFt&kvDU4fFG;JOu4FIyg=q*+&n_D zKMU&I%tVD#S1EoRscZkx<{d!bdsYkk;oZf995=48MNQtgay(slhCE%UPd=fS<-xVT zIM2SbuTMXrUz&SbLn6Q}D}nXD_(g2J6xZC5M@lNrNQMGvoHX8D6j|2c3JvZa?#V8K z-(a^{J=sfffDdWJ`LXTS0s|S!)EVO*4^V-P&e}qq`IE0Xrn1ryw%#2BL&

    x`qk1qp^FU-*V`v9@Td#)YV~u6>XlCRCr5fqpiEjSu zZ)vYsLsyfkwaF?XVXY~AgCcVNMXW<~=$^c`%7?fTy7- zyTIBiFh%vBQ`tEqBZ=jf5{^N0|0G<^leWUFouX7vYiRTgD2l^vwwv^&T}u#k+HG>i z+-{RI&uI#%tF5+oI4UF^a5m&b$)|Gtu_al>c;!(L)Xs~vHatR15mskoQI(9MZj&>M z>_8bI%g-DqJ4$Vf_;*(x$9gG+M8-{gNJ7$`mnJyE5Ko1x9)vT)K&-2QicQt`k+wNv zM}{?4*&18qHDwXKfaujKysVtz&-B&uad<3d>i7_aHg6C7MmZk;(`hoWQ@l2JsL>tb z5*jb}@OtkO>`a^Kg^F20hF}n4zzZO}`YUYx(J?kcaIE35_D(EZx~vB7Mk>8EF@4xm z9UNG}s`Ic(HhV85bZ?44>6OjhOwqb>ZOSRfEG?~cb|jqD8a?bvHa{IODbHPm++F5j zt7+X<4t{@d;MxPnfD|@#!L^t%3+VB){uf*}x)_M*o$Yt9Uuh}qHg`af5M_e`-1MMQ zaD~;NpKhoB<&-E_)+Nujo0e zPDn6EDT5nT7zA_{z?hfcQhfWas^XzxiArR z0J43=N6Br*nLAH*Dl0(xc7V6&#{hHt0tfn{J0Jp!n7YZ4dIM4&CW2OMKFvwDiHX3v zziVt^o@Pg$(aAiEl3v0!650stbRnQStv9dTtynKfY5}x=Bu+ zuxsXu*Su>PI-~;!5S-4j7%k0e1*Wg=b^L_Luy45qmr(J@!}l4@e=m^e8bw?SLYgLF zk`$*c>-RYR{NtkW=VrXJd@Ta)j+!zgQW)phVB57o(DO$5eRTv6X zDvU9V!dV$}Ukxg>o7lsFjb-WaoX~Grf^EP#z?NbNZ}2N2hdS-l&d-C~#(s>i>76HL znfV+Ypblb0(mP~JpJN-{W z^G%OdTP>tINOp;|@bjhYl0KnLq}fOD(en{og<}6+D&wM_EsQ~j#D0!8rABlJPsm4O zT^w}$;x_vO#bJXg#9XOD!RmRmK9zZ3ZxicL$>BSO!WiXy#xuxY6ztQoD$y@K6ZT&!0VYF2wo8XRruJv;JM*r>w_cX_pl|nX2t@- zjsgmkt%%J9%ZQe(b;LHnAOy0~tc%brY#%9WyfuC@hCVQw1Am8IPrn^ZsJ`b?%V;l&>SOvQalWj%s4ZW!Hb9jA? zXO3Bp9G`AK*;x@E119_GCR^<4Z_FWDtplwQXja=|!+?g45KacbNwTmfSg7i>l3BMp zvg*ug*Qq!(T%j36b5{MvWC`)XkUvOhD{-9iRt6kdHCRH|H=2Jxg>IGz-5o#bPT+E# z#TNzr2{9WRf0ptE(OMroGya&WRu^%48CS`y+Q+pDgef`w>jrnw!(Kq78*^CHgAj@P zzJbX29^Z-0GN$o&F#yLU2jFmP02anQ{`KgB6KvIRhy>Ipl!nK=4Mni@y;_I8d{A*9 ztV1ga6{5|P2tp}ga=JGI4U@&~LC81y1ojvEeg@PKb(Cf0fb*$X-lsyhH3r^u=~sJ- z2b633j_yN%qSIa~X$e)=y|X+|_gxA|$xFC(|5E9IMFB^VIOJ}1f{O=~RJDfA!jqS8 z+tGm<5ZYIJMca3xkF+Jx`Lg{;QFUla2gl|0&HwFeVR5t?hBbsJ~3&^6lebe+zXbaLMM&FzAB9Z2ehh#je#ady<1st6zuW*mpl_A)A4`bDi!)KJ+wEy=G^vMp<>?qnP5%eB(f1R zjQ{*lvI$tT_t7d_c&ED(7fxE(Ty(k2IFDhLK@&EiCTv1eWX}vMP9WAj;R!=H*93ov zhQP=LydHkHoYijn1j4!#AGWam!n~wC~FdYw_F+D$?#9xMVbEvG1q>uSt zPbgWSQ3%}aBODnjkwL$2CAuU!xhLL<6(O!XB4Ha7wHQIF&G<0JFu&iCzc*6V^M8e) z5uRWoq|qh8W$Mcv!3F9|Y4B$CkjesIZ5yaR(as~ZSt*CAmGIR!g)IPk#89KDc&4s|(+ z9X!j?!7pz+$@e}u0yc2*nH{>orX|OW7%ZsESQ3fdDMUsYb4X;qgGfDy7(u4iI#O>( zs(v?Rj}+OP(W@YXEh2+~{Sx(b1a&se#nycMZi2BQN^Q zvlzNEz12&fVtAbOF5i8R0`Ub_+9rj+Vo{I6@Q!9%>*{NNVv$-)QrjF1JP)K`*VZR( zKY?3%;T?IIJwYvaxxTVtEePpr8`k5G!3V#NzJKfA`8S%MV{?W(3v4Oe=vC?Z9VGAU z`d6RC+N)-Lu*a0xwOE8~bvu^KRK#<6E^8T&wj#J*SE*|Z7~q;^`GIn;+G!0JUoC9_ z#!D>HsZO4Up%kHtcxBO=uD2jXET)m?^Vqu3xnOY-zL;+VVy^ljGW=!}TYKMTeA?o| zmVGe~O0v>Me-!B99p6_h`kr|;Gp>GD__Xp}^2wR?8D{0f1DCL*1;|W=3XE$@&Ou|hVzB#>kTTc{ks8@E*O~>@2GX9$ zX?a9JvYA8!sie)9=W=Vk9|8L?v%>7oE8Y+wL~z=vwHM>bjy>3MxkrumyB7{YNUOSM6B=F9UK%{g5AcxUB?P&3M*zm*tizfJLKVU*=uU?IiSO}KX zte3=l!?-5Mjet$YGnL_dFTsHa3d0uhCGyfsQbc?>+C&&***=H<*R&9CWAHhxj;4f}H@1TQw~ ziMq*w`X>;u?2Z=62S{=Y@wPhfMuB7$4+m7^$@l$?UKI88VpMT1g6s>w7J-+}hO8yS zCQ6qt{ZBM&W1t>gztYmRIGtK$3x}l^b)?{EAZP3NC*mPfSjq-eCOIgSDaOAa{5e?L{aH}PAZf0Iz-6yDBqAg=dN2XG% zmdt~JbAhVpW3mbg*VJEv*w8igcLb~OSsJ_opVtM;@p%O{W;ONa2QR>9VQ>sqsP(ew z8iwCJg9Gt7GI%OJ|C6@gfJ;_dZH}vee!fsLfk=!ceZPeYLNETa8(=%r?U`ORwc4nQ|0z z-&26ew7X$EFCrBhT-(eZiQu6)uFdk@SFbqj?V$H)OKW#C*am+v{81wKfK@~DOqUDG+pE6C(!Quv)gkN7vD%kX zdU3Y9fu*OgHXn9DRXY5}*nbJXu~ByK(pbD6HBH&;TwV=@xreDoR3kWno983dVJu#S zxyu|d%SvmM{e^1-*ZrbiHu9U+uN|L_SzJ)NHgIF0VEm@_%f%<+UkZ%EtYG}6^&5fD zlz2o|&p1LQY4Z;1IhX1`uy*x0D=1EQir@f>0cGH&ns&O4bMCHZ+jE8wj(pe-0%_-1 zW;f?pl-Iyn9i5GnhIUeIc;IbqI*bZ#sI$wrrZ1OFoCE0>yp=VEhVjt4yP4zn963|ri9 zDiAkLBX*V_T;wu%1JfE^o~Ep+Rtmg0A`Rab;4 z?gnCNO~n(Y;crAf-LNsjnGanj@jZhj#x3mkprhaKdgLTt*JVzW-hm&+Qliv5P;&l& z7?&sYexw_nHURN1Gqc#SQ%mH}!qf5mRp+u2&V;}3%$Ec|&hNexZ?JCyR zDacPCHPN86*q|;b_Ys997K@Cq(cLC6#OPM+O9%pV8^Rc45AM;vMhf>?h#&+&*0n0j9?H`L7SY?7to-4s(Jz z@$sX6+gn&je(C{ z(TdKJ7KTkNXKYm`cW2zg)A@oPWGRMTdGCE{@i$9{~5RE`cRTudbnr6& zX!NHiI3vDLdiiG?m@VoFtHEuLiCKL+qm#;8HWC;4DMptC6Wxqu@(J&FZOv&;)9yrO{wgn^dViC0AK z^xZ?osKcZ~7(@b9xq`XoD0KPOp0PIR#{?5AP&tcqWm*Ew?((M?{;iVa! zy+hvU#0(J+A-$0byi+E<*ww7lx8%$Dj(o$A&pe0Slo6k$dOX$(Y3l3N9`Q@8Z`twl zt#96VvGvUrKh65)jt?+zg*suJRWE9hGRX$#|A9SlSSQY2cLBR z=~P$P70P(hRo`Ms2Q1HB82&fZuZzSN`D!!3ZXDa3>F7vKb?D!n>U+58I z=a-npn(<*z;kU!6_GAWj^`-IC%m$*gq@!FxluV!$7;h5R?#TW=?iEo&Varb*#$fO3 z^=Ab0{TT~;pr*s)xA`-J7x=xw%i?p54wCR5PS)UIkbql$9+FZPJ$EyGvQfzNF%JCy zX8LGjJkzH+(ywBAe`6NY=Q`3aMtWk(U>Gg40Hg0o_xM)&LhR<+BLGQJt*|sPX0ULL z*B#8mf*U>TGHFSA(uGq8>)q7H@Ec7#1;4SjbD8T1cY{YVUhU!#*qNa{v}T^owaeLD z+A+{!RF3(AgU!33?)({{EORlwSWX&01KIipve&xrgIF}OGOnMY{x*fVB;Y?uZVa!1 z#ZPS+8pE`}+ApjnJ-KA=!#VGRaLC2t7ucj6eIHI&nCg9xAJ^V+pY%PB?P)Gf zO)bn!&b?0NCalLL+vG*BYmz}Bq%Rsc zq03zc-!l_AWw;lfOF6now)COCGP7tE?b^&EjTN7J;yK~PpL>Fy#)+S2no}X5^%YpI zTD=ES>RLp2ai=$!k3QlO!Mq*=2YFpvUGW?( z`oK}Hsr>Fx5B$xDFSeurrzvJRdWe7Plt5eu5Cw)wXIUT`Gtt8p06~)qC>KfLnvdy# zd<*4ujYD4VgZ(VtKU{OvA%2@ML9zxcaz?QVCJPAj%95GS;(=+Z=8DGmL8JhFe|$nrlOH zJqv?PNy~CS!$r64I+&e_RcTdw)YAYn(-b{$D7tq1J*bVnw(B8}o!^9p)mL~*LMGp- zMu^yCPHjiSN)*6OPQ*Hv#VJ;_oicLFTns>Ku$>P=iIFQ!v2gg*l|M5?Wgr}3@6|WN zgW%gBV@G=1{sG5JsEVu1sT7^vPx2(_QcQf@J^fPn(t@VBTk6;D;xF@FP`7G;vnON) z{y;N`)F<6I!)8B-3R(}fpp;ZnVDrssz(a;p?fzT>tS4MCPTY-wjr-*Xe3QwSk%|#c8N+o2ZeTBh=N~~q`9tB0K0>vt`8`p7EO>Ri532B;3Bm?P@;X>~bp%=fx zysitej0CZM-4Q!SGGKjm95qeya+VORZ%zz;TPm8uaw5ixKZMQz|3~@VwRw@;wW8&=X+2p zXv{p!P=6Cxr!>?$0X~WTg>Ha$Y1I*ex%waudC=a4J>rd!j&Yvn}L?M&0u z*{G(@M&tKC>E@pBgs?&s!*G~6?SrX<47~9QCKH;MQvBVczjR@6W0>pU%R#*FJ4$;A z?_5oLmMuU$3Y=(ZEyXy$3c-oq)1$uD*NHAKFZp|LBwko$KD=GVT2*PcqUc)<8T@Z$0~W?i-k${lYQ zFFl7Y{CsZ~&yyVDouL+H#Uls%9a%3et=h|XjSp#0sb)Fsy?I*Y30a!;^xbm=ELFR) zHt4Ue%R&iD{x2YPT@Jnlxs-_I#y_a~oYtD>33^;|rGqvSw3?t-(?RtB#g`iU)6?m* z6u;4UBRzdK)2A7&>FH%mA16;*jW*sU^dLU$h3@Hu!XuICPHR;T(rrmy(dNhUNybNb zkr!;@(I+0N^)hI{5%4J=AKMG?VNs1%n&tp3D`Nj<%Zdmco(knt8_Jny6rqk9G4DHs z?qc4tgpNGZjpmD~P z1UYsIBshkkfyQit=HkP_fqno9({zI~8qAE95-fu6JY~D_kqP@MwcQ%d#?e(Pf!|cu z3Q3odz3u?MMWg(kxbbG1w*v|B9x$aFc86r%S&BubhnalO$VwNLVBLnG3kU%~^&Y_D zexSf7S@pA(#zK&0@5yHDOa|E*e9zp)MYBcfRp4U9bdC#2O?53+9rfrT)-JlAHLWsN zd{V$1D3Nw?sUEVMnL$DO5~a`R+|eM*-!962Y9g}b%U7$ z3iS=xd6Y>*8eJLYG{7Pq2uNU=a=1VX`!hy|`qL0JHsr$}_jw`J@sY!J|l)>8Yu7*{zkt|LZ|uhMAD1QWsVV)Ia&EMwqRxG>v%Q+`;@eff)Ia|e=0?{p%46p_B> zk1-3|ocRoUCL=!`b&rGCUSbR;hI2c+D<(DSYYue~+d$MaiRzS=-w3L&mYy}{8L9!; zSo!YZ`!Lon&bNA3WC9JIJgHFMa>OHAeZNt@*S-`QW}Hj%&W-rLKDGqx43w_-BM~(e zW_Zk}AwgI$(cMRu%pWpJR5>X)=Zmipa|05;(3q4Cc}F0@Q`DfnwOmfWv~o}Ua$|Bj z?&ImWW#v8>afcaGiR;{WoM+ehr(9zBP|JkaW+8lz-8okRni$p(y^gwHOG-`&Es;`v zwIjHKZj>GljWVCZ7YyAqjO&Q+(356QRm+~{Lqy5Ih`os@i|~O#BgZMLKe8D5Drq*M zs;c?gUDTUWpA`nbhVkF`iP|uR1 zRI9Hi8u&dl(9C4D+-Sl#A~m5i%rEc-Z5d>Q)7vruRYSiGGwRcuu!r7cC+1PfmUjq@wQSf9N8fZDvKn>) zYs%S-s_qes<(X|BOn431&Oi_GD)h23wL z(n5l75$qh$e*<^H_d&)7ggBM`qXGfRBZL%vofN7|Y?3u3IRcOrvAkW89BPaq#97#E zfnXz;h1zqhTeW{1U#0dX%rVPR)cy}G9-YFX<`C>y@0i)Dj^pfI6)a8MhJQJaWBOK?WIjrZ=NZ6+FyXN{Exy`w<033Oj{`JwmWk17u4^U)`Uv05G~R z?*TjW>j0bczmodbKExllK#nj&yM1*($70pICh_wxTzU?Kf;AqK!W>iVL+A_2-f_y_ zS&~C!uMl6Q_YCH6ico*M0<&1ZCW4*9e5nu&_65HIcbPwh?u@;LiNx4TRA<)=O`?Jk zE^`u5Hxspms7@g}j6%_iqzaYmG6xb>0?NNdR44nIlc*3cm-!hKR_q6)`hI!^)+JHt zQDp8W>RCkn7g3$fx;=?XKxn#=heYRk+R}C=W?*X244lR=r`_r{28}b_%rXs16ded=%-W6f2uD%%_g-1y+{Q9G)h^6 z4cekW!vw_BBjXYl=j`{F>P~i=_ozWyOTPsv5}U5eeFF*?jq0t=o^W$eM4Uu_qAHC)xY8 z1g~~9WP=T+xy@Khu+zujE*rd)U?Uy;Up9CH!TSkzo`_7c!FLgC5}ezSWa9TMaQr4C zAIaOtIbc0)*ky*Fu(=M{r~gzq%9JmGS zNl+VvkQz4SKJlEyccG>jOfM;yl)cx%RM z{sNWOd!NA4V*~NwzJQ&zeyW!5)n{TO>h&OUD*oUXB0u19<(UWq?9J0>;;ATazCN=6 ze+u-Oh4@pb&n&{9B7G(np5Eb!k~({nu&|K^Q5HpR{IeLcpT%G7&!((=ycErEVm2Wn zbCsnwVxkky3{6?Y!rBU?*wA4KQbqU{=_m?jiBqHy6^c?1_TC2KmrDK`Y~x8yF)w;q zPSkTsNi)1!nze?hC9O+8-AG(ba3mYJ6!rXV1dEs;EeQG8q@!oU!H&PEGj zSb9DYmx;sl)gY+)HJbm-t`9QtW`-w+q3kB*NRZP>If%D~n=m-cseic58 z>N-QyQCbm8%VdpqH@W!3HvU8x$i<9dlaopGVc&Qz%sZ_TJb+ZP}}u6QHoxbb(ubbgN|GSvr}i}n_L{eXY)Rh zD?ZqGjEcP3p~xfXcWIa~8Fud#Z9K9;PiS>P=0DU9my@p73nWh>9FZGqJQcSma#4}5 zZUW|eJTAIZ8re{eI|B`ZUyD#pZ-5oyZ*ZZm07!b2WvnRamWx-PMK0=36GiW#WlkU# zm|2m|Ocn9*`bj9Xx>kJjRb9eMJoMCG;-RPh5)VD~mw4!@zr;gN{UsiH>M!w#r+&G| z^3-4Ap{M>54?Xplc>V)VeY{~CY4TXDZ@_s5uSO2H9QF%U3lUixkK$?w*?u(A)mokGNV3Q-8z`Cb-r~4lwafuD8I-RP=1js zp!_0NK>0)$S3vpYKWVH)yh3~b$_(mq!WmXu2XA1SYOsc> z^c6JquiKE6xTK)Hi>4k7HcJq@{tRySj)$hg2?FUJS3cj-zbm0Ue^ zzPiB?rm$gXTw8{7u``3?{b$0bvu|*Wzc2j#vV$YyPx}jkr^g@nj}I35$0Kb_Fh9P* ze}!7D`LFZU_JdxF|H6tpg@_47!Jd(hIao_V@NC8L(r{56fz3szi**mAS?+-}%RP{0 zxd+lL_duHE9!Rs?18G+GK$`7)AkA_Qq*?BPH2((-kJfBqOcl9rJHTSJkLUe?Ezz2- z(a_!mbHDSREu;9sLtu+|2yBIifF9VUA%-fh&Q;{`et1Q`j;ml5cxiBthRLKgHX2M( zeHkek?yLI=^h8r&3mT8hY@2PZ|K$)2=9;Z8ETsvzl42 z{};TfC$CltuT}}KRtvAz2(Q)(uht8%HVLodS)$z>&h2WJm)Gc(0u{&fy03k;8dwrJ zo)PT%L{{W@ChiJ)p2)>xfGyO^?GC*h$C<8V!lPkfEEBeO5Qwn=D`9RFibN)fU7RB> zzYz9~Fp*r_`3btA@73*GRw#j&!rPZ4?V?b2<6ZnRx}+tTSsssVUx6Q5OLSgG!e z$VP%K94k%};c(3YBhseBbr)MhORsDXFBaXsSakPd(cOzhcP|#*z4-rd_deiJRoDLa z1QIepAfN$)qD&D51Q8UJm>>xdKqZ1e6ss5`1V}}o$qWGni4C-wJErBf+UnJ|q~I;R zr4_5y6m13J5>(ov(29zcR;m*x)mW)Sq~!g4_c>?g%rGD-KF|HV^JL|mv;VBU_TFp% zTYK%bP2auD>bnb^zI&PJyO){1d)cY<-F0`-FSp3(p=n@!>;}eiq(wIunUfFPm$f6- zg`KpO(QNuq60y9~a602~&nHO-xFtS{Vn;CB@;>o2VfAQwxDTy??f==5u^UO^;!i4e zfv)w{^Q1rVWBw0En^obR+c8!p@VyP+W zavxinOC!awD;O!J_`8^cA`Ael&!Uc`B1M~$f1lnSkMXNEJTFO*X-YLKnmvBZiE>gX zqtVbsJo>*6Jc0QHO{*H4`MaVPTY0yx!kVaUxG<1ukZr)y-(!T2VDl)<1r4^%@m4y{ zoWEEW%Ev_xI?>|7w3#sevT>2HNhddXI-Tuw0!3J~wbRHq6YuX?2>OqUypx!K72tpD| znSG73*{Nz;sdA?8qSLyK1ZiJQ3vg-}rqDB7q5pwySkra#x;fG7WqDmDuj)jvr{s0E zyw)drJuEL>h85~i(>le^3BKupYiyRVYu+ZTZ!bDFRkW|>$|(U(E;plR0ioNdI(;y6 z=S%iP?TKj9&v@?6c`qMN}jZ$YXd-)#^lPRI$ z{*ICE=X;p`MEaRW&CZlac0;oe4*MiV@C1{P^bHX=sPX9dFAeCSCv}Lle^kz)M6m9~ z{e!gOj3F20T~zfoOY>wo*zWn8Nole5ta%|NQs%t2i+t62Z6BH9yrxFRJFjVx9Otz| zWT^9+9y!l>`r69=`{A!Y2e(Us)WXS;P_6WtJ5$yObzsnT!B7M zUlpm&)>(HM>XJ0;AlF;Rd)^mqzi%b>ux4H8wA3qTsngXAB(d7^Z(8bzqZE$2rGB0L zlcqw2K@Mgp@Y*Z6cSxjRs=~Xuwm{)Eg>G0NFLyJ(Kwd}G2G%5cb(WVAcs`Nn)xth; z({{z$m+18;d71Y1iM+DNfYW$3%geO4KDfrUpC98zdmAZtH|5`w`z;Mq6T>f(`-Fz_ z#PB!BeQ3ifxx3rj7`gXssF%CDy$!(K%mvKaT2icNm)Y2!DUs8IXo;i!YMy4vQ@{3h z)=@py^WVwc7EDdh&I~rqMQzPGXP#;G!?OKBAI$nQb5&0&gcs&#n95$Y0gtA9KU*N?$T*EWQ$kM2k&qL5B;-V% zDIq8FObI!WXG+M~zrB%F8vY&U@bCEUjK0$y`dWK_raU)GP>8)jRkC}cK9(I!Q!Q8* z?*VQVMEGHFH+pvR8eE*}o@3kcnHX2lI$e`&M-X=Uojw(_Bmb#s&a>|Yk?mGvk#(nS zk#$#aHwIZ{Rm3uui{|0k#d~YEq}04D!>?Udzr2)zHMJ`B@stP(j?IsAYb?fCUlM<7 z6Od=>na60d7`XmU(_v2iOSZnrv+DKC)!KDA!Fl)0+AHuR0aoQ5GQW9|LiS}S9<;A| z`LMLnnX5JA6L-+Q;5OF<1CcbBnKzw{-o3RIQA7L8`%zMQIRyo5bCKu=S*j{9c!D!i z%@JxZV%v2Y5-=Av*KF+o=E3PGa)vDv=~z{~BizAs?ez*YxLf-kiV=KqaNi(S0MJ>@ z556dC+jlR*#=k*~D(dAXaH#0uV3hL*wV=eA`D9jly<*m8c`?>_FsCr=A5A(3BYRD$ zqk|hpk@do0V4od3`08NRW&0HyRnb`Nwxa#ltbTpv>sAs{Z8dmzq;``Tfp(iP7m^p# zHuE-QQwMSV^vrW>3D8x@NTK^!NuDy!1)ozb&RlWY{X#;8La96TMLRv8X)PiFbbZ zy`LNLz-|AN;SKvJ@tV=@$KKyl$ zCuf{@MF*s}ZP%xU8`z=?Hm=^X^jgy~x_ec7u2Pr!WL=;CrRov%+8qXY`zr&u_M?NZ zweO+rfjVO|yKP!GOX=jP`f7|`gnF!!>5G@{VJgwK^6>7CTm3y<9_!RO22B?pf9{}W zv^qLvTu)cV=?LgO?q!u9e)f!5b%cM*X1!^f_pI=$LqXVVRzt{o?>W+l!`+=WrQCDm zdES;&)y~F^cBxpxw{wK1V-tm@)+X152)PY*3ulqH=3{T{{GsP(=fc07XF{3VLcGG8 z<`7V`!rQ@lM_kNc6=>BR!)-tc&$9rS` zQ4g|F^B&4SN^Z}`HTG%Bzz*38UQg6ZAC!&;ZdC4sD>&5`_07+gyYsmtKP&o9Nh*mQ zX@(RFwddSlWLSxk`>fb|_C>MxJ|lQHxu7K3vfL;sui3KHTW;D0{UT0eug)<3KbM=a;F6X99x{x$|DTA!P?Kfv+GuZRj#nDti z$f&;}G^WX)CJQRjZS6qH$4Ah_9mpshn!D92e6ESF9Z1Eo$|Bhgq{0SG7!!?5+lCcu zMw=X1JCK2{>@w=xwFBv7cctT3Guq@-JCIgX_YUNKdfxDP1dZQ;6ybI3Kq_Xihlq*o zKt`{F*PmGs!2JSTmt$-5ZWO3J)8LQ=;c76tU@v+4D@zosg>YMu%ng^Kcvy z)2#!RIj{P=hEm|G?wZ72ml{loEn*-pDj9f^xLBpswa9tSuFYaUnQO=lNBal$Fp!DLgaCXK$3od;3wDb>v^F*K9d8r-(^lfI$!2M2BKy$4}VOXnSh zuXsA{3k+d8Qg>ZiY?3BLDNWMevoXH=rZB49UrDK6@ruWf*`jK2xs> z+h`_haL)0VF)PTBV zl^&DSn!Cx&d`h5a=2Pi&bJK>TboB;0h5y=-sm_Gd$gQfqRRmMA^qI@3K-{Ur2@P44 z@n)Z^pu3dFuFC$^Q3xB&aSsBfj>%%VBW@mDvJ~h-u=xDYx2ST|S=Cm`M*p@wuD&fh z)WgJR7n(GL7-lGtTv!V|4vw_FWcT*j^(I)i(6neU6^%3wH0OHR1Uq#K!arriaFHl^Ho2 zo)Bv^xQdRIgH<#}tYLQ%nXCRztm@IG-|^qsutl+Ux?){QtcKlk-Rp9F2*p40KvZ+s zdedt(1S8_CGr{NqZt8B-Egnm|5N!JnhL%WgQkJHLFWv$I@pCa zDg?zgDy*b+a3TB2DIn`*Bm0VIzC8|;WUln%={EH>cc(H&G6Snwn&Am_QTA=0$Ym;) zxy)blrUWj~dzs$baZ^USDh~KiArm@!BHj3(66vIfkyN=PN{6lOv4FEZ=Inx@|D?-7 zv;h{lx?!nU(aqzdQJj^I)URkG4fn`*jf+wHT57eFgeN?K_i$(CaZQ&}ui@+11`5~n z55*p{CZL1UM3c=oW||y;)=ZNY%1pE20pWGG^hQo>Ls5sSJ6!u;8_o*!+mIUQu;JFg zC6O5oKU5@loBJ-2B6$rzO+LBYcr@OGML8Z<$YX@J|WJEN(!FQHqD)#i-V)E7I_zGgKruXdVUh*~t&$HRvZmmc6;6r!i9 z5Skem*Z@h*yCv|vz8|9#i#+Qfh)>pJXht+y?4p|1o~2};A+z>(s=hbIz7LUmV?V&b znuM(T5$QtKGRQJy6pO5E{~3ANDEf5Ac-uDAeNyvA1)gr$q?+EsKZ@P-#!JzU6Y2jz z)q=t?RQ>?B@XeIHJaj0zVW*@sFB*S~RWxXsI{lqidM-tvtkx@_Z~<3d?X| zkyQ#~Pa8EsEO+xoNQna7Ly1dolAgMU7Lj$SE42t8(ans0HOsrv&7elRGBo}hsiBz} zmNy4HJ9;u#?*}!n2z$Qu3!1RZdFd?leuxe+0WtjjZ%V4^JNQOjI;bnxAr45rO~j3c zxKIaX!7zPqJe?9hANQsiu7FuMToattV%eif{gIu7OflrlYSDQ7t`oP36Efz4bSII0 zI1slvA?`90w>d8EFBDgKi)L0id=UpHhpl!FtsQciVldpPELu+ehVrwA@9X%S-8w(!o59+ zY-Za7o!Rz%Y_*5q<)3MXbf6=S?>(Kh=)~}(`>8TUePz_XoZ*KY4pCpQoX)7B4=Kk@ z$wmsj?2AD8(5=X}$I}vOwvVtTxuzM1(RXUAS2jAQDNBLA;d-`=f;$jQ-(u=f=%+J6 zvbkF{F7iS68;r*|dK1mJy%C0~JzWf|(Vv?+P)7?BJha2z31Ev%+V0=;T`Qv=|BQ5Lq^4+!;}`*K3WMW(F>`&i(pUTCd8svE>m-3@7XhA?|trzy$^gm_CDmp*!!^VkHHkn*~_en*-PPW7qi?&aQZK3%vgH$30EeI1^?_$Gopq1sJ2~?ssMB6zF`4?MJ=uq{hTSsFimhQwQw*v z76saHkOdS;j75RAB{(+QbTp>T=x#f+=@8aNDz}9fAGEJAC48t`?$p$(%Y%OoHga6M zuZ+l~{+CF<_Ix@A`XDgdiXTt*!#LEVB#J?ts#G1@{yikPwv|k3%OwWocFus5^|{14 zHFSd)sTJ12YK!)AU#K!+XBH~-#U^eLZMI!3I1pzAwQkxQoIsZL1t*ZD{lN)j=|FHo z_Kw0wxpb~?<|^Hg!%J1y>W|OJT=iXWG~J1ik;}+3SAU(C%qP>Cd`)EX)guobgdAFA zUiZvZ!+ADchkxFv%vCyVhZ=TA=4EFz<;jt=03&!db;74{LKbOwnvUU6cP&Ea)X??n z|JmW^8fhz2&I*l7R4FG(KCh;PsP3kn#1aiyul%hr53A~@^dHlE_o^c>1CdKThw>hx@;&xal-@^B(oj~VIjNI|x5I*%`^ zsM1|UWW-u^mayt+NV5){sP2$sULRL?)mNOCxq25x8Z28I ze1$e1w_B7bMQ3PmS3cRIj0v1pAD3{C=Yye?Z#t1=-c3x+CFVMQ6Qv zE&oW)u+K|ZAxLJ?Je#DeN1a2E4GOZw737x$VJ4CfsS?$}Z!F5aZIiMr>v#F~-mB^P z^0bj9b@jc{3o72dDOFd(zeMYeq;H~A;DtkTT-1^~HmmYI#wrwsLL=7H+?DO|-@rM# zd`Qk6mtB$BIL=HG*f=9Akr&O57iDbi?QA{^5_Ie?^U(?7Rf(I!kKh=5juP168HVCi zaItrjr|AX~Y#Yboy2B8JW>q!T0J@XhG2l##$2vy{=xWgrLD3K6W^rQ-$fQ|MwC?fI zF8Z`+dnh=fjf#)<5eqNvL!2l*&Hgd`OJS4p8Vkj+codI+3JOX~wV?8mGAOltwc*R` z#&M`sNNFT<)j|?zyQUk;0T)9fhZjv0sN&+Cz`nqf!e+Y^~x+}QZ%uVc>0COaBpdxgO7xsKTbJbqT zqUP?bl)#n9GZCLzG8AMcWsGg1LMI)KSKc^i9C(sRF z-z|4~R^``1G`PGqV%-UFUS@R@V|34|zdDK*UD9v$`1jDKaB8$aZJ~wQ$%uC0R$Z}H z#I8P7k9YMI9xP%^Rf;#eQtU;FhU%U+S>&g2LN^iER6(U~N_9<3YMLj-WW;nWrio&F z7y62`s>cS7)ke7Ido~bzY#qEGe-CBx}431ZoOgJEFmTIAWpNZA~+n9X#Id|5AsK z)xDGS_;o8!smIS;brxLdpp{jGnWUhLP^8Ej0UL_*3^19l*6=ZO?^G(<&@0fRn zzpCl`eg?TN@RrjU9LG*9Dnj_uXMes-~+)~Ptt3o;qT@FX^{uRAn0c-^7g z>snTJ4P6xu<#WXZ<9cms_t>%t6O}ENx`ga+_R75>b>;cNJ=%~y#?E<%P;nUbcd2fo zo*7qWUhY4bP4IIg3NEdW-k4{k>de5GD@wQ*tdy zbgh@`RdTKJh9+b)6^&n##jjm1Mgbt$$S7lzJDb={>IPD_qW&O4OV%~kMrOWO`;KD~ z@zDFT3&l0#n-65i#=5a1jiB$TVBx05!Y8z!XqFVCY(by!J*_Q>OcIcQT@E!k@F}e( zefs%qx>tofCOdO=4KF6g5RjF*T6GaCSncdKmExq;i5DMY!c%ow?ea zkC+I}?b(FQr!>Km!bCO<$(xV5=>GeajM32wD-~YdUC9QF#D0GsL9SSk6|V^u-Dd_o zu4JXO!rOY-0u1~%1`F2&i|>Q#z>Rf&~s{aD7IX{*+*1oM`V&*C-teP2k^_48)&ljsspqe;)*PD07kaT<2W2T#0wQ%Ts ze-JjNy-xHpZ0J^t>MPSTS4)wC$n1v@?E-sUZgF#XBPw^AM{6a1Jc?f$6x`?Vh>apY zJEX~fA9vcuqJBbL&2uLr12frTpv)VIY+@w5*T>(zX(q^=Ge?to2jN^d!Vt0>mVy`t zP9!OcR>yRzubi8?TG#tJvq9$12~$BZiG{w87`}Q8D}ujJ(h&6ukN-;p;Yns+r(qN< zgl*DMa6Y!Pe>*dXF;KA=WxW=&(5t>;O5h^KI<|w__0P;pt2);jEvwHm8d7I)WlUEt zeCf0)HPT^In)L8vXu4G&nc_d2e^u$#M+W&bB3ac(Zt-`jJ~B7ZiAuy`5dY!^&}>%c znNOy`5of>=9pH#gk>PeL8)Prr={jlt87$nj2SpPN6%Z%ih-7}!g=TJHG-ItK0L2-h ztG%IVsVJ3AO0{nbkf6cRs3f&td9G+5xJ1cz^moeZSkYZ(45~VlK<>BTf8GYC` zv6f4X6O61O(z|hjQI3gpb6(K>FfK7A*EPn5RZX)?` z6E#KJ_A&TNaZp#j7=roTNQl?A&gMN-b_m$LWj?lz8ZPNog5_6 zL{5Xl`@hD15ZK${!CW)d_+u2kcyD_r$S#5i>nv>eL^>-lvUnphIc@;SwhmBfP*XYR z_HjnOP$7k735}rurc@{Q6DB35K~S@?SVTH$tOX{PV_OWR_$_QkfDt=hddp3FhW{wV z?*vbxQha!ZL2jC#6|c)PY(NFazuFp{@#@hi`?qxwDtrFytv6vHcsg26jcNK4kr>j- zv)=4Xc6cXGSLHjota1EmMk~HYm2X8ouJQ*EG_LYRu1R&B zQcY6%3Sd>f)S>7Qtb(8MK&<6Cm9C&G(oJbn>H3ORr*2b@G1WP{@v|yjZ@Fo^_)n$3 zN($~uw>dC;8}9WAx%EJ5`?O|Cp>9$OXBVcnNZO1Ho`qBarwTHH1qk%*;jpcXVnkU& zvDAT$+b@>TmsO*SRbu?2?On0**TvBl#}bOrm?nPB~ z6EfwIge4SookG;>jm&e@eNB@QIBJZEP}?dgvd3i zu2ZTpmWYkzY#`_)i~?G$!Lc~b1jf})Pt^`pnZq{)zjemY4W!ah;WN(q@> z3DYR(I)$j$o0W4;mf~RZ%}}l*S*LFo-#8f^<@nW%77D{RR@CG8X8*nfz7ahp;dM$l zT;Pl&$MKBCq3IO58pVimjbe#w_Prvm(U(=})%IJIYZNPgT^wC;T%!n$Y4W!ah<1x> zq@>3D+p-I)$j$o9SwNeAz7X$)8~veY;pjpUPz#xio&9 zyi*K~K33G@SmtM-iR)@aj7fE!QawpmqkzYCHA+PT!Dr}dga^LS1HREC$`S6a#_S#6 zcoe>Ic8s|Ck3yYgUL|HM`cLRfB$_9KofKp|U;NfYI$Y`)zU@t8~XeByUD zXumH>V3lU-52{!&hA)isW#WD@2|gqyU+3 zM_~ce78&4jU@uhWH_AwAv!8#|p;?H2Z7{13cUuz+X%AgT0kgC%Ud*BzEge?yp1fZE zk$Jt4wDj~ZYI=yI&<~lK*E@5yGF5#SeA6jZe5n1I#vUlvS)UtRe5fgC{MvZ}XR^dR z)Q&y-EtcJxj?YCXfc6&_V(=#BG|S*gH+UjbZ6uM2H7gEz{9gX2V7~NhqD65G(eZ=m z*SXdkS$$Ypea4m5l^2p#sgkjd=V_|*xm1t2BYSC7j%_4PEF3qYClq8k7}#G|yc?a2 zZd5X=KF%6RD=>35f(>rnnyLl-tlgPU_NqS8%U{Mn^nZ@@%v`mK+&4*stolf{+$k&- zh?G2R0q%AeiTCt9fdE(XN~E44j1$uM{>A=sWTw3fC@O6CSBW0UHwq*%$L(?)e0<=I zayQ0SB?`7NEYi+(!b;KX6HK=5`NG131R_P~X-R(1MskpQ&&D|CGa`HX0n-R%%bh2N2A0 z@D8gEssAC*U5M^kZflSH7vOj{#Zb>a!cO$Vg2mhGZfU8TXsq!f;tLgRADj{@-l=Uc zt(l8H2?|&XDNgVvKRn~$l4w^HG-Pi`;%xrLX=nP$H{?Dpj z!Iwg_Hfc|$F|~%AdUF0C4deGX3gm3etbp4&&WOEaTS|sp!_>k~i5n>WA5i)#&vrTn zG`3m717Sj7fxaU_ksp9;x7@gZ%^>p$gTxsoka`|!C9D%*p|UM5?H!Z~ySqhq!L$Fy(H8%^!bp_1m{tW6976J30^AQ=Kl{2f!+Qc_RiGRirKg#g9 z8m`6rABW$A4Wng8R|01?as#3%yXwdsyOhV%uTjbPN0&^B<3JOO;BqtRZjXk zzehrcyT?fTCv zZ_!18V&%uD9JeS?gvK<5vJi+mUlf(z676zC=`f1|h0itdwI~p_&^Zc`WKp1?>lC71 zZ$>0#2)E=9Z@<9AU*E1pfs@M?$FF9z$)FYmR@CDb1@{ruHKF#_ix`vYI;9$06hJ*Q zE98+15HFH4$tDv?DJb)OJ(%z75v|UsNXm>hU(kwIT2d=s9aJrJFr)gy7j$RO|1jR< z#OJl*)#1ceygHnc6|cc8lB0VO#){VlMYUtK3$(DysdUJzRl4}dwj!RCwVx};K=2(3vk}=(a z&G`)C2Uc#4qzAe)RZze6sF`6%-kDl$J3Wk3V)ch9zHPyl!@Gk=4!_)Sw-VawebFy{AahFtqY%ZH zVP?B>izdd-L|f!1W*Md;3KkwsT0|PJ>k5yG=yzfTtr(gq7q$kAlgCqs$)Pw?a;|u9 z6nfv7)tWRVSBw?07#bWjAX-tNBL5FDBW})-p~7w`Gf%MQbk(q(ef8y0=4p{!`{R9m z4As1&mvY`;Zv}cgi#IJ#!qgKdR-G?ZhCNQ$atBjN=<<4_v;-b7+kT=ijQNGOx+1Pm zvicuQ1Hzp(+jcMWk=`R65Zi@I@Z(+O8=h{x8~2IUJI-7d#k--wVu)zE|K==ku(7`O zJk!F$H$ZCmNBZ|JM5xGR>>~VzJ~+#F_mxJ=tS;jXA#HCqlj;guElTYMTFL-zw(&ya z_nFFmi=;XAhw@ru!@Z;v7y43#USp?@6tgXiy1Y5jxshlNyBXdZ7+vDmj8>n4kc%Aw zn!adhs^ed%hv`+urcTOj7dWS0fij=+I0j@g!fUrN^eINu-}n=tgYT)&t@%lZSc)OZ)ljiHSgh06pb_2Xn00wcDvB5*cIhuhr`%#vp0Q0{@SCV z@oSE1Z_bnRlE15&6^`J{?ETdJHr=t(8VWdik)~Va4krI|$J#dUBaPo2P(t=PSta!t zBY(IUZ{!qaN%>t;5094vzUMMg3SX|sVMT69i0oJ7Y`nL=#TDl5do)x0p=pPlsqRFf z`gp5_YLCJ;^Rc;As64)SItI!6_X-=u!`8AzQk$rF%*GQ^!1co81;uYn`MdJ-S4P$F zYP{Q@W2l*a)WPx_VY%JLQYb992upWiNi3Czgk_8!wl`s;BaOQBVG=V^zYI1O<>N$u0qX$c9SAS?$Aebryf;klOM(uh5m*+ zbYDAkhH$r?1v#Rqklk>jHF7dZ%Y}?np$YJfHsh&l8S^Y(6eELip?#s z|IL|J?^aC}IwSHu%^OKWR2DvLBR1NwR?>k39ICA=+DQT0Nv{bZ;Bk^Je%SO^B<-`4 z4(!BGTg{5y*tPfxvL!?~Qgt`xgqkQSYj(33!a{`)2Mh1DG+9r3@Qs~_2pU0AB_!lo5 zc~uvCG4*E}Z{*Ut!rfBHv*#!+e=@C70KvT^JTwf7r(s$W z8WzN8cx`Vo8Z_&3Xh1gh8H(XN6~lkO6juy?{1?U0*|u!-6ZqZqHX7xp9*=nk=a`ZF z+eQ9Nuz1S}i`=Ajg_Rbk+{}`8Hfc3IDMqmrFmXpRn&x2VMlkzQF^{8z02ms zXZMI`pw4eFP1CHba(>v*_?=>Rxy>XIO(i8_qR)2t;`MK=GPy#wM?{gZU5@;5;v za$kXYZT;*2tzPkzC*YIo&z`rk{W!-7+R}!JKX4sPi;nzQZ(ma;@7J9A2a11n=Bh*B zbCS0EHJf0c2<{jqc$nCh5^^&uVPOW>Djq&={W7tVR*Pw4L+Wm`NfP#y(?Z_UD@o z1D&L7-`i%&_B^&uoT2C%`i02(?&3?MTq2tt7Y$_8Yzxd$vwaQ{K}(7jTS0K*JCK2< zc~#wn6jKAOQFT47ABanHYg_%%-PvX~Lf(DK``H-dv1Bg)2!5iaHkSX*;&y6_y*yfD z$z~{{aAyMB==PUC*#0eiSc?%oHTV zss9SI9c&9xA%F7fsLVCCaI*K1|H!OpGIpI^^jmrUy(p_X8k*9YG-KnxeY9<2t2-}j zTs@d1H|k!eO(H8WR4k#;8VnHNU!T znRWbxZ5P$f(#M$X7w&f!?XjKx-R6Rky%<~2*8WPfwZA*bZX(C83Y%?vw{`)tQ5Z%t z(H4H6l*4-}}!!;fnSBZUu|9Dd;AARple{N*M)f8dIZiIFCXFQ>4@-!Y#GX)1sMr+nVTzu|#I$>xo?y6gm);TSfXg&r2? zqWZB$%BR!oR=b-iO?u|HKBhdZ(Yco9#kk*Y%YpRNo_1Hi9AvE1Rk&X_uj9;dr!wA~ zbR~fkzLy<-ax8p-EBr`>f5Zy!1-}P{Co{D4!GnEz&@a`SwVbeTXdvPn?cZR4$feNV80XdNFjWq#0(B|Xu7Tov zsV)hcX=n>Lonuc=)lBOjwmEe@7@V3YCJE>LD%bmH*ZXkZ!`IPhl-r3=8Xm6?qmcA% z4;@uwp^T}pFx**}I?Y(1ll&&M_)ut4YiQ=tASy_+_M!o(_y>`;S;~Nz>U|jX4)V$b zD_gW3mO3n9eukwxDO2qhxD>%bbvEI10{zoCscBvVW48v5Y-pi;?ft9mQm=e(4DC{pP*y(s+1~r z4%*k4`VES~lk-Pg$7r{XAw`7_+gY7zK+1fQfr+dQL`gJM41QZzWXtioB1PL}b;p*_ zX6`#?T^&gz83h9sT1Dv3aB|Kz3ATgzVeYIg+BtYFRQ62MH0jAWr8-@sd$J;#$UM|O z+PM^QQD{kqin}LqZCQqU@Aj^4%UmVv zTE8=VQnXP=5pUk)EYW|X@bQ#c3-w>9dXHtU`VXQ_h}cKQ!~db+am!IVvAb32MY}_@ z_DVyINh#-7fVrl1p|Qm@!$I7nlfuz5>l@3-EJ?*~K|5xH?6kB} z&y9uaO?F_%;`J_x!@G>&NaxxytLd1R;-73Qz@~FHvqRoF{xh)PVrB12P&P?$%y)=O z%k0je3g?KwVS`%uc2^63%%i1)j(7@9_sIE*<`FCX3n@cntUir;l8xtL;Th7fD-lmQ zcpBc3tHq;P%H`SjNfUiH!LiOWR_HEU}3Bsh(>keEa;NC}#?s145O*E>cN=?H z4E=wqUvFpmCsdS^^mLMT-Y2@=b6xKj^ImV3J}_G$`K>q0H9ki15$*#;`QpP1`O@6g zGz)8@{v<0B2YvWWVj4jJVaL2d%nAD`3-WSzZ%gMw*==O!jdIe)8$>sUf0sgjWfpag zsZu+?4=BAA>dcAmA8S;SYL?d?RT<1z8B|+&HN0K*?|-*h@vXF%oQ~8f{3Et@!t-oF#5|Ue^_%SMPZr&}43skX zS~j*~ul;YffQ`xsb#*^>wWB6*t-W}%VG`Ffd=GRtJdv22Lbzl{+DzEOI=E(SXjP9k zE`f{c8|<`qznQcsUj(TYJtcCUtEdO3O$FuIJ!bIVsZQSF->9AZoBsm; z9^A#hpY5|5)>^koo85J`KiauyW5+D(v~?4=tTXqaB`)intIkY(G>aP5?$OsxwfcN+ zO25w13pBN++a+}4(r{g&Uf7beW95ax4}-4+Umf&8UB*>)8Q)13-8Sw0S`DH?+aUB8 zqSiSxPcIYKO*O)u_EC6 zYC8W3V+XfM0EL0O!0_;seDjjla7=7VucDY|_IJfBA!Y-i+L|6!QKtTS2)>%K2;D59 zYs7Jc%W;yy>F)?btc7FSb~6Tz4Sr%0tr>&;_O`6YC)DIU?g@Nk(PwW&oC$uX5Qy6g zl;L~Gp4knJjF?b!EG6^XcY!=EmM=b5o?>02SOj!0-sn8*WZ3O!2>m5>pVr`B@3Tv2 zfGJgK!T0a;If?7 zCFQ{*tTGR?;fFjSY$6vO3btYmYW4H}^uznOg7h%VlP%tP0J~W!^MZ}q?@kdlWeJY4*#X*70=-}n}+g^ExiUG!~{Pc)QV!lp1*O~ zHafcp_Jo5Ucf@jJ^PaK;a?vK=IrU%;|)FGmTMj55Y9wQ;LME!O6-_D47g-%MS0u?y7l zso6eCHEQBhgZpb*`m!F)T)obO->(BMMSD#p?z1b=-<@=zWpLs4-Y;-=N5Z5cm?U%6 zB2|YD#mK>s>JX8_eQ`}w<-KA%b>GFRdn$Z8MZuXD4qliX3okEC9)boxa%x@&W0XJ2 z68C8B{}N}aa+j%ooev4@9mGNrq1EnC;da9ayQyX_qbnieV6XUrJ-@ws%Jv;D+n&p!6UL~@wD^HLVZ{&r4ue;0KRbZpcv!o!cUn|vg$nvX zt-b%L_~OD{6pqqo50NawkA(-DFjf^~BAb7*Xq}dpq*ToV;tLuk40|Z>6&mJ^YM9V< zFe>QdunHPJ!B$nA&0lJRhpOJD1`khsHO= zgH}U?Zw~l2bLKaH1@|8Q zNR>`M=WanT2bIx$Tnn3Z-MH%{Ewua z)$Vp83@+YvHUcUd;0v5QBPFG2I0WXmn*ju>87wo+!0`X@kC<8a371i0_iXc>nc@k* zvEXo9U5!`e@;&{hqZ*{ErE_*vUK)Hw9YNhQI!NVFb1@^LYnIWL^(**xLh#6-RuiRy zF{_W6@B}|1Jvg{e|7~^;&NpeNK0RHne2%eoBn1ryy>28 zHD{!FriLdhKHPTWP0w!=1@S*EN>e;qvL^pk`sd*9@fi+AYIiz_Q;Up%+GqNLJa zILJTb zm;2oco}5d|XIy0axgQsjLFH!QoYIOpI;h_Uh&Bqwtcy6wN`0<$;_%Lom8bc=|7q@V zafO3uPMm5b<9zF>Z-IW!)B1}07Eb*fJSK?cWV=zFs#hlub4wRgmU;XY0ZMxP`CYvK z1KhS~(Sowlg`S=SYv5ZPu!-k@VFNq^h7a)U=6$cimHSPY19q5wJQoHQcq$jo_f-0q zdddWg{GPIfU-y*GzTINya$ppY16%>*0(rn_;7VW&kPj39 zV}WtNc%TrN089iX0apQ61J?kPfg<2qUGOb2EF#lZEz4Zuv`M&PT!O~B2- zEZ`QP1h^F_1#Sao19N~fU@kBZm=BZ#UjuFj765ku3xP$zV&LmQ1yBk2fdH@sr~;M( z%YZw9yMX1u3gGSmo;g(O?BSP;(!U)3T{=wvhU?!Y`gf`RjnKc5`gfWBU9NwMaj9aA zP>d0ZF+wp$D8>lI7@-&=6k~*9j8KdbiZN0#Mk>Zg#Tcm=BNbz$VvJObk%}==F-GQi z2CRkFdf+F(I$%BU2=L#)Pk{}<&w&2{ehzE|egXUvcof(KJO=y0W<m@1Q-U407e0MKt3=Ym;_7)rUKJ}8-SaD5@0qk z54asz1XKc5z+J#fpa%FB5CXmfd=K~m@DT80U>)#N;OD@jz~jJEz|+99z&4-}coFy` zum^YrcpZ2Xcnf$3hyd>c9|DJgPk=U{{eUjsbf7bk37iS^0?r2d0_On(fWg4Uz@@Zx_#?0fcm;SJcoTRFcn638Ex^BkBS0IFIfe`Q=;CsLi zfQNt|1M7gF0zU^H1s(^U0-gq*1-1c=z>B~ifjz)0!0W)9z+1pOKm>Rn_z*Y@d;+uq z?FUi6KxZHmI1}gvoDK8^&I1MjgMo{IOM%OQTwn|^4wwjB155#?12+IS0VTj}U>=| z3h+AcCh!*U4iEv}2R;N21D^nGK>G{HKQMbflfv2lvI@F|UVv{X{Q#32AASoL`O7?2 zr4^iz>_g zv2Ac3554MFo_u;Ndem-t0GkwqDeF6Dqa#AYBSUAr= zUr6P@3P1T*<4--!DY;|O9GDFjDzjco7cVYbXgd>rJz;+d{05j?zM!mR5#A-YmoJ=S z@!DS8Rb)GP8m~pnTm4jUWr@YP3rp`PvtN~z{pvYH_@h8a)-hQ?47U{FvDf)JPTgad4UOciCSP$$1nt=@Bh)2XrieC-*q2)f{ zATS=>H{1Bzk=6qH{UB>S;pZAvPqpplq?h<)`DguUWvIp6#ad7;STwJEcFFMJmyH;@ zB9FA@{tP?*Oyc8qC*H<=zU_W1?g0h1-K%Z)`L??vs4YBT zyDyHTL$%}ah`v@p>E{D8fyF>Auoe(*@x~_meG>hm-1Kh?Zl6~FCATe_vnz~W(6v7;b-*&L`XYy{7-Ja|KvAmyB z7$=sgWT(x>wNDhh79E%q<=8d^5)~+V=?hbSw z{&R4f3XB+GwNsqvi)}>y(%TR-7`_&73tz2`PqqAj8=oCkIG@0MEszJ!>-g5MqO5Y! zf`Gq#(ZUitq{q`4_x*&sm2lg6A~=eA%FlCo7w;C^Z&5|m%f#!0pKqiUZ>h^u@kZfS zZTm4Vibj;*4E$cgZ!zgvrA4E+L#Tc0r@ZbbOf_MZ=fynLmQ_D%cu$O{Ja54LKA@R+ zPCZA%-5Djp^dST{X&fT#LE5Ss3{z&QE%)6CNd|ajD$M064k1L(oODM}lC8n2DS+2#uKmHBS6Z5;%)Xy{cU4);H zr|oCDSH;_h+hzFG^3-@?(O~tVc%Sg6IuoC?02!n?5Eu{K3Wx@!C7c_9oxnjr$ml0L zhwOLBKjqd1@a6Che`%9l-=!7v0(X=x^jG>8&Gju}j=W$|>724Tz5y`i03S1zic;o^ zzS4>^A8e&S{`qCTN+v75=!8k-S^(&0p5T9x_b(IwUp@{0!c)(H=pPH{XP(giKJO=` z{|n-$S3NoYMHQ!1{GvS{&@W&Apq&i`gIk{`tluwy|AJG&zwi_jfJWt^K*aJhPx5fN zoyH02|AP3h{xtk_u%}c3&_mtm|73%bCTK=f_hg^1j=#??q z7mc6s$yYk&ThHG4H9McbV_3;v+x=tv*)-<;oFm7^4t;w}&*EP{{n+j8@{fIEaM{Ej zhsSjN`vpDjdhzu!yK+~~{n6Tw#{Awq-yZX|_n-LB)|-xw$@$^5pGax2kGEdTrP-;~UsHGtwjfq#SBp8>99(cBWE8~?rdZ%N`me3<2b z2>+c4{+9@WT_#!i%;^&RhYzy?DE$%m?{oWCe!aqP(>?>g1Brga4QYn9#rTI4{jH)i z{%i1War@6Ho2N-ZMd=*lzX|_Vw?7{8Cz$cyjlYNdX+0g~K4{jj8}7q^Nx&Rn6|f%I z4jcqhiQ69-58Mh=18adTzyUxwG?uj3@6P&4CT=|Jd0szh>Q&>fnpQY&hHrLR`2y2d zSyCDfPY}fAKX<{RMHT7`OkDfv@~>DFSUBe-{&VjrU3yadlI3m)(_cc*>UhLmkCX)zkef~whz~VWj{xaXh!Wkvg3a%YrQdBV0SH94vv=_5AY_tMQ z`3$w=>M6XB@YGywrZ3MoOi`v^H*LninS&DZs<2W}w8D-iEF9&#(U-^TP!n*` zk<3%^bn;B`+&`1&D30SP5+0u&!FeXqBelsh0C1^L$jjs@6O)vm&{%o`@3)B_Rfe-3 zlV7sm*n;VWP64xyu#&I}TZzbfh;QZ~Q?Jezpq}n@hLKKUzMZtD1k9p@zF}UOPg){( zl(AXBTV*Ay7`Uon`c>BwSmkiO9Z65oUx=ghJ5Kidbo}F{Ob0h?ee|-*1HEP0oFTr7GByEt^9>s^%ueSbJF=e2$G1tx>9ZZY&hwP$pJdT* z6kLg@r|{OF1n;TipHXma68!Fdmyz0(-wDPAW)c>CUF}5mbj4S{cCz@T>bO-uC%|v2 zK>kh{>gmR>j`w8#>Ub0VL1BK!_pb|CZ&x7QMhf7PYdYbD$Nkgy>_v;0Rg}-0?`H*G zKD*4!Df(ZjqJD-rjXApwi+>5Ru;GFio+%DWT7+4Gt2@?Xrmiz?3uzGnb_ zKsYtOsI}jn`9*u&@561JLz{1SPR>Z*RfUCxLwyAc7WfRom9TGRS;dmFIqIuL%OF5M z=Xuidu}2_#2f)M^4(F$L_jfWmqC2d4CxR8vi7m}B>*sz+4C6>X;i3{}H`DlKT*JH&ckR*G`c_e4 zm*jPhd~zV+6s8?CjN&~ptZ0~ldp8mX%kjSz|2aI}{IDChqd+$9 z@~Z_1Ze&ak*zfCY{z$`pJ#M1K{WE0?j$h!YFypVfeu%GV%J?BZMulmGMZVjX`R**M zkbMwOwjEK=WO$OfdBFW^!fUeO{%L@&SXjEiSEl`8jct-&%_(0}UWr`RSGr){BKGv= z-=TB|+7b0UQ5yH-;ZEb);-bQ7SB)!~K4bjQei!$gzsmFMB>3ziiax#w z{-Iwo{(>(Nf3i9_RX3IGgEnn(<;TV^^;5KHPGCWxGFCg{&Hi?YnsUhRNAMR5ZWKnc@Vk{z6k}Br)%ow8D*D=c~U0-uyNYX<`GxE z!q5D$bV=!g0G+_ea3j_*Kl22)C-wNYr2xm_{{r-D1K-`ZB*p(Z>F<>UcT)Ucfc|rn zq;XvNd`|i=PJ;V%(|=i#G)@=&6O-UR-Sl6ZB#qNWe@PPDr7xJ9B)CsE{ZA%I<8;yAm<0FfrvDE~(l}l8 zznKL0>8AhfBx#&3`VS|;eY)vCmL!eSMSl+#J&9xc@$`>A^$v*0ngits2|x2>o^nn? zI`Q-i|0#4p;1lkVLd?%R!96SixBQOBe~J?b;wGbiR6-iZ%& z{*naTUk3ei6Vf=H^j9U|{xaylJ0XqJN&j~eaDN%}e?K9O(@Fm?5^x_!|CL|7|M_)7 z8gcX+{GY%5?o7b_WzfGnA&t{X|C*K_=P)B{&Q;* z+^3uV`AO1P5<3V(l}l8ePlcaIF=>KUF+^3uVUnWW8 zbkYB865OYo{vAouI9>F=kp%Z~^j~~x9ng$v#YyGQe@~J|9Q_9W$vYqicVhq3ngsXh zre6!x#5L;aqCYbU?$b?w&m?J_F8T)~!F{^vADSeM(?$Q7B)CsE{S%U;ak}WgAqno& zP5&)P(l}l84`#<4^vC_&_-9OU4jElPJ&y>p9ufwp?_YIG!pO^UpxJ(iPsj6zrtr7lJ;Ts#@@xZ%H7dh zF;B{*CJ9cv*vumV{|T|HP6yZ#%@f>HJ0|Cu6X8b(0j0?q<0hSieaz-52$Wu;eDC@s z>AC55;h#KUa^bZTXH4>4JlZ$Ses^@$;`V6sY+}umJbf)8jT7KEi?C$ue=_0gzQ#tHC$F8co?0r!_d|Bn*VIGyybPr&_U(7z=i4LAMtpTmZqg!iv4C^me5 zu?XX5p77-B2{;GrNKm9oTar$kj{9WuXTgr)0qxpAJ*{q>P|CGk)=#IGTa#b%t z15{Kx2yJHi8X{=`pZt6>}x^`;u48GMDQ3d9wr~IZA&oG|yb98i_rxnure}eLjJ2oyH zsD_xIp87Tf+E0B8^mE?b{%g?}k)IUGAE~fxAn04a^Q?!luP_HcCmoq{keA}@!+i_j z;M~aj0YLt;wNVmSh?O*t$0vtMtF8{=Z~TO)vc$h^aar^nt?JB={}96Jd}|+`8GvZd zUR#$g|}fbji2-aAK-hv(o?#IeL0hho5Ixs zYXODTxqwafyX@@AjV(1#gY72z5`T$qN>6SAy*uk6;n7b|_ZWb<(ERjt;>p2z*Hb^| z+pSZdPo56or+FDRU1r48j?lu^X;+t_6~&hw5&iU3TxpIv=^KwE|B~V@MaR3`?^D$Z zug{LBr@r&`&-HZpUgcr^`sZ8E*tr77T~Vv8kLc4zXS-UDL^tJUD4m4z6ScX6_HOAM zU(}|K;>g~getIg-bUO}qW#U3BtXrR28B-sG(ZD$}P%~GDiTG{_pvMfznn{_(=BCf` zF0pk;c`BWCv2<(;7;(v&a#LTYpLxP4%FAsFN*CVlSy1Ai%fE_J{$YG@K}i`$c|5m* zdoFN0uowsciFB;NO?Z~`oZOV|J>$J}@6|2o-f#Rf-TRY6>4vsehc?S5VjN*Ahb%xp z^CYbL2&WvRm+hHTKCj$g>1ibmPZj9_HXSA}*?cQb22bG;PWMmcb2R}(r*k01U316L zV9OGc(J-fMcKIFHd-QNxYSBXUSW66r(XZiA56T33Rslg^4e%iFQ{Y#CoBn-#tBpOw zQ*-~AE*ZcbpUT^zOUhf;7E$ETy^*WH=HTJIjAF=bVgPm~| z0Ai&lTQvIVsc)61e&$KT%HTa|d0?CJ_%gYp6f2|AGKni8kD7Lg#dhX(xaD$*^{|ZD zn550WdzaED0}ldgf%U*IfTw}yftP_dfP+8;NaW99%jo-siKoh;7{1r}h3d>!-svm-t`xFy)({?e>!gRA8?KZw-RPk&lv3J z<@L({=RIPec!Kxwb3YyTmwJ1>d(QHD|9ZC9lxrs%m)e)c%unMlmF*xqyk(CoK8E=3 zOh7+9=T`a_GvILYr_y&vr4O@Moc)mgGH~(^4Z7Nq2fp9KMTrlv#skc zEt^yFwNlLNS})eQIf7Q(;IzN^ZyKo6IMq)(KhY|1ekc15SV?Ls2pz#Kqv zbRNoYzt6PoS*ahbw%ruQ`F(o(w3jNF!gkZ8_?k~=thCaU&1wf{Hf{&_o`r)m$8!7< zpT$?u_f*a=U0imBZ!D9!IRVDU#f#`wd;^OyVOQb1P3+9c*?|`gA7q`wH0xpz>8W(? z=c#n2S%?M}58@DsVoA~?*7OZDeT3{F>Zj)*Gl4F@WATDAnU^V>^A)Qf(K%E7^c;7q z*DLtwt6pziiP!s!n_|z0ZuXiy{+@6r%cDcnbZGjN{0$>}hEAPD(@#(3?<~sMoj>6^ z9r;^(kJr1U+UuQO<@G-D4X^jcrS@}~*Zc8uD}UdjL7pssbW~P%czpJ*)z}~dlRhTj zl{));g8UsO4Igq|rH)a#T@0F=aVFZlUdA+#X8C3_anZK_@6aT zgNf(P)90ms`2WY=yTHd?mHESGCTST+3PlPQx%ewBG=-*3(^5*Hv}rPFL(?SWQVIo! z$z*b&X%aG%URYeJBA^yUK}A7C1w|HI6hu^%s))FYii+qeC|=e@1wmz%RW9%M`b`i2vT7q*AW~@O#*gwRsTV=K#!`FBrdV-1ON^ z2i=2dxj3BHhkHd)Z578@{`g&}Z)9@#TkS;Ug@r>nL|Vh#T@+6r8QWPS%A^u>eQw71 zzfQuZUWh+_7Y67t;s5_Uek|LEF!$md1VjoIF(bJ6O9zWBVzCvHqv#KAj`i z3N!9Yuzc38*?zd@AIN?2-D})@@!p2;atG}P(+a#;kR2^Rw!;xj&zLFf#uEX%3&pV! z$kf&#*z+#OoydS4fJ*`XhbR1U)D57~|Gi-z6c6KjC-D3--}V`^%{S)tqb1zY4fF2> zy)6&{eTVGdKzvPsq#+t$D?B#YQ!1ko5(>PKc>NAo$hl30J?Dbu5Gi8Wy%N0|2BEp^MzJ-clK@1dx}0R*e3B#l4X>*}-{ zKV68ve~dT7K(m#0%Xv1sNzuzP^R0g{%Fm|L;w7AA^~+bByz-P)hzIE`bN=|H-MX>n zu-&g8s&oBnT-Vf`Zdn8OZ12{s-wd>i4~OZuLnQ>Y(Dv*&_<7$l``@SDs&(r0_j#E8 zJoAC8ejDl|@Hf51=t6O)b^tt##SLfa=$&l>*0BxXAch7Lni{WEfMc^+0 z+zr2MzRDdH=B7&e$M9|d&wb#z4BtXV6qgywe$=NP2e=P-hV>A544ovQJq{YzE*=4` z=yz-KQzk&%?F)W5# z1dVZExR=H7G0Yo)zY?$te%bnN!gT#(cn^SQ19)!7m+tsuzj_&PwyxzeL-}1M_vq$D z@Lmi0FYvW}6wCE=0Q38H0OQB_G9CQ@`u`{(b(QX?IDX7EX1;C2aOt;WaJ2h>=Z&6t zqI0&sL%+enz>(>Mx~bTfEfhENlr(T-6SyeCDU3riJTT1JMt=7gW{e|XaaT;v8-=IL zw^rjhzwjAT6bILliwANueS>q{@rC2g8zrxQErz@?Kk?JA*Joctw*>z9eH}vQw}J@# z?3d;e>1&)AY;bxUSe117E zE?r<@+Qf^-LSYhG!9fQv@bFrr@rkiqKHuNqfQNp~1MtT$>m_jnn%TFq4)90&vbr9Z zP8|7qa1kHB4uC%g5Vl)9zw=_~|*6p}S#oLu`n{He`2RENYKJeQcQ!d>xxXu3!9LvgI?^Kd){rOZ1@eGjzLmbL;k>L2|y zkVRiix1FF<*W%H!iZm!opyKy9=xkqMy5Enh!NdN_ps_Cx(2Qf!9|7Gl z^r0+cj{8?JQzGp-&=!D3oil0U!{d2P)%5CXXQht!(GjYU>2@(_Cm0&%YE(tSD*kQ& zZ6VB@i}`ifbk`3WtBYfIje*`wKrjxY3GN-q8q$^oyf42PoAsd;yax&Yc*&`Q4R{FfB;ZBB9E4lPH~|>W z9OT;;m|2hZ;EPp;;W4DR3ibFGuruHIjtp1em}KH#1fF@s^fEsW25!!EUf$TeC%y*w zwP0o5`}32uwV*W{+5%kK2BY}di4XIP`LoO9Gx>|)zW})N@b&YL0LMZa0_@J{JSP9m z;JXC4z4-deg|z#C+XEWo#dms0&yVW&BuM`O=$9F~4U2W+YT&K}>;>e;@&g0D_|1MF z$^`fq;C9zA*7o7gV&Luuj=H_wP-76c7Pxy24!84T*@Y{odfwFo8s}YeP^R*J5GeCN z8wdUZKqo6Lelt;Sm%)A?%=Z0L;;$snGMY5ctuZ{e12>8EhU?uyh}*+H{zp;H=u=t5 zu7A&iJ{x@gFkb|20O>shaXR|_x?b%94$pw9S-{l+R|y{&e?0xE9N1SFKBl7?X6q*_ zB~WSua0AFM`Z;cR#ZTbq=VicoerCw3iojiIcKk6({>-vF#9+F@{Q`vuVG_PGF$R;*UvpwmuW z+|kBtb#aW}VuORx{rTby2+oG&+JLt@3&uvh) zdKmOMF?7ElPlG3RJca+WKTu{o1${B-j`2S*o`Ti}+5*r@$yP(4my)fn1TA(vg}*n0 z7CWATwhy!#gjq_qdK~mcpi{Q8efsRg4D}-Li-C8?Q{d*@7&D#%UjzIK@J7Z{(AI($ z8Bc*f5BRlk6B$qOP*@SP4InY>e$&^_2L5W`+l-rVzeY5Fdr)>a0PX`k4p2zP(SXwd zTL8NN*8=VYJPddmPzitM0_x~LpdYXYa2`<4{U*-wexN4 zz#IV$YRd34!|>v*6Jg7ye#tlP155cH=( zKhj61&zv04-|CyNHg9Ome^dS z?*Q-CLEx?fj%|oIzpNoLAZV=Xq*ujWM zLZ+MjAy1y!W$PyJi-BjI)nVweq72v!e5b*?eJt%Ie*MV*%K$e4_5mITya<@fxB@x> z-H9azLz+W zcoJ@&1F$ZqK8!v>W~$!mrQdxKJR^W{pL+*x>Hu`V0bjq2c>(N~0nf1AyfL+kW7;mz zJCSzQDStTEg0>fMHFMnzfgMSLMDscM!7XepT6 z@O5Q9C@aQcuLk~3eDRTA5oYWS!`_RG6de^17XY`*@Ei#Lu7$apX}Vdv2TI)xoRR+u zT!(;uL5b`KJmoO*K7w-f$8iXF8%G5?Bk`Q^$Bv>0!SgvLoHpYJw$jZ6fm}dKK&__U@W9Wgt8??QkmF&AgzZLY@z8kcMK#T3WLHh-0v3)ma z>Z4`)ZqSbgJ<@k$d_Ns{2hQET8@L|e78qQh?*?rMv>HQm`)=Sb1AZ~^x?eSYH}E$A zzrx_%z8m7#*v3iu6f7#?1IZ2$Uhdf^~1*868c{n10OadJhb}bx=lWB z{q`wEXM;v=`tQJO<1-gHBtz8!SIYn0x~fSSBPNU`I z7Pz>+l5WDkhf%gKuzZo09>56TGQh2X9{^UtuNzEw>?`jz=Bwd`3F3V8N#N#lGkop3 z*7nA(b81^!+tRgoF5{rVT6tJ=Nw&XFslhze4Zq?9b~ri5U0XP+oR^ zKsQ2B(#NMIOXeTXTJ~ekJTbOgJR`0epgnHw(D%seygnFsNWs4Q(FSDEwdVx%Z`rnRYhWXvQEdEVIB>L@<^hjoVg|{uTgU`FpHg>qqStmJ0axJ z;j{nMFIE?F*^%sooaBNQfc~>h^Ndg?ND>;upM9 zSgsK>p#uK7q;6ZKF73V4g3?akI7f%kp!uEPtY5I8kromMU%{@6^oK{!lNp zC`{+0OK{J8U|qs_2L!z%@7PmKd~pshg6(9IEN)n0=RTgm-Q#G55}(=dqd_vaLHuL~ z(traLV_2cKc@KNAv4Dp(rqd119{LB4Kc1h=V6$X8v%KCjuUz4o8=ITEG;iF0b{m($>1J3q6U4=xl7-*tk9&LCBsc51Vf9Y3=bjYwT*;(AtC7)q1=9Zo4{~ z(%s#jvvqA9O&dLHYfEN*x;@?1*yD55($N)zZEf$y13FDUzNQXA_4vH&p;sMU9%gf6 zS8L-8tE=bX-TW?j9Fk*R_r8SCKxgzAMC4%XUxay4XG&TiGNn+I4)z#=L zV8P+}ybgbg1sTl2?%s8R?QUvpYxI?b#fQ8NpfjC4F)n)BrKGzWTX7#rriA-&%v^ut zlGfSP!K#|}m0h|my(v&~Y*$|9y5*SZ!INy=jZHnR9qn=CvwB<8vF=cN1NAW7)z#r| zt_hr0e66ZeEow97@~_7{`$Ot8>g(!9>KXNlIwWyS;-tjsiH(VK6WbGe67NiWIB|F4 z!Nd;|zfQcEI5;^!c}lV^nMv+UzCHQz*jP6%V zZfE9e>~3mTuTvMQ9cqtyi@HYLp#DkS zqrRfPt^Un2$9(Bu!p%lFlG{WFSv6k8l9BGD>SdbJ{9#fTygB8FN2F$k$-x>os4Bj}PuDyaU9JjcB za^F1XyA(1R;A+L4&Vv@YQA5<_htj@DQk60LNZM{E;#yRo|iZA z;k+1|?HnCRJq}ZLE#xtl$E4C0)*=R z;R3{yQS6k%b*!B6Z`W^XJ!=gXa`?JN*-oWw;o}I4%NA<;J*>xblT4*^3ra|=&S9A? z&pncOkY*&y`6lDc<<_uUe+H3HjvPYcNnuB45XbmlsQT4(?!^Ag2CJI-W_*p%8gY32)@ zbNSQ3dYqxSuTvnCN#>&i&<{>(aa(d2XX@OFP;?}1+*9nIr_e2bkuY>^^@XC-c3g;8 zA1Y?8({#=+7t$?@&dA=QW40!vU`-|VH$cW=sm~o%Al&5(cdQl2D;*h%{ZZ#wNbb*I z*K9GvW>8bF&x=xi4^fsc;uQ%Q?Ipvcem#bZlRU=dL%pQ|XaU{2z_=z>kblRw^_2cn=0_I@Y)`2)yudhnQL3=Cu zst|na%&JrZ@F3tZ-}jd=6TY)C3Uvm@K6o^bT8Imwwqd3?F)=xA-<9Ls&82f9Ngjh> zzH`oN>O8zCFj-PJsk?YrXI09=a~)MF3!j5|HfRKk3xCfCjX?Ky4y&~r85w;kp0FCf%*k_*?gv)^^ z?icu;mZ?e|16U4N3S8Xx0^mOb_%&eZ`5NwcT~+FPfCG$My3_GCl^9(p4(gi`8O6wp z3M|QQMta`XSC#sZfm(bCvkbK2OR#kR_dJ8&h3{ytD%AxT0(=4XxbI`Y&j9@x!$%&= zx5kHidax=L2h~GpJAk9j_i%hG46sbtU+_!a1y&NFopBmzy8fgOU4H##Ggs5hpMEF! zl~-N@N8ArGb5A!lldVW0>EhlBAoS~Y=uR+L3!eQ=2+wX- zXso9m4Y$?o$fG@nG4(zSH~x6-9kt&^!eQQ0HgvXXI(28~1BfS(mr6y5Ie4$ujXVN_ z1X*C(*f6z18AmLOye!D&a&pX=0+NrGTg*DS-8t$c3&YzdwHgn(G=|Fu`uXZ-Z7nUe z!l}dNxL1~!L7RBa!xtyo`_X@BO{T$9HviAdt5V+u`~vW0K+P3ZshI$NUk$+AUeHW~ce zVE!6l&h?nfeNe;qZuGu1U-1DAwJ_febDyDG{@)n8{SxmtTfV>Lm;PJ8ylEV(>}dPD zid0Lm-c$mtj)e9ZfVBXc35y;5WqXw)SQ$+2MvJSpS<73iDeta64KmM;)pSEWHEs@= zC>BnmoTrCr;7DUXdzvFMnDA0>>o|_kDrjCP!?M^ZOE?SlX#K65t5Ws1RHf`UY^MEh z4Rhh=lL+@kz!K=_MJ94iYSaTG1t07>=$nMpj~zi6B;}uut|Y=IX&Q+_rZE(&v3w^V zI1$lK{orF&sXqV?z7;wKKr(k8*)epehHp88Qhm( zehF~qT~(>J&uDm!?@RO7KdoWxo~qOzVZIq(%gb+_;kREu&d>L^G&3vdM<&{d9IqTPQoqC zr>phqER|K;)lT&$tc+jhOUB05_GY8Kgc8ng!-7O>H&zDxxOKhMYF@CfDzy!;1MmjG zUcgI$`Co#32q*yF17JO69}qqdO}z9ISbC(HeU`(kuwbuk9Ua&XH5>8lqb3Wuf}t>g zu~}9+2Pd$iMEweyWo{ejSRxF4_6Z6CwcG1;7m88!Xc(LprqL4$xyL0uBv zVj^)dZnGI1L#xYca+gz_DV%N72HF(DK_E5X6ig5pU+Nbz?&tE@WFfU1m5g}mKj5d%b2e-J(^*bCs(`P` zX8U(!(S>L^e7SZj-rB_lI2X5i$U^neC4~8bp8X&!&2MH<=*fiNPN+t47cf*+oKrZQ zRoFQb<4PT;&M#c^<^AX$3S$SEQY&>8g@V~kaX4rCU)Ifj2t?59x@os*7M+$a%{JbG z*WuCsTDxZ8rq8S)>>T3$8WRO}(8dGCca`7$Fy_#>yc!Xg^lCOoP~=?@C>B zCj2z_?L-T}WE+Y>27}DSwiH+CON=hlbuoU4YRUNJcfx=e{$lM$YpQjANZ4au0EXr( zQCn!pdHQj>_QPtfY`?cNTSPfpEY)DTLo_*sGSxqgMPtP6c{eKZ^?{wGSHdMScW-8mso3oE(WV! z^f>6)RD#8r$x)*sr620lr6ADZN~i6&ShL#`!)q=DKnc4VRTBG`V!}2I{s5&6xW?b&oy3uPIC_h$&S1Ye241ZGYPzdKXMJNQm4OmziR`bU zC!$6YKd2KF{Srf4Lf`tb(CElr{#+YmUJ%;3%c|grS?1U$X*}iU=7}9n%`#5q7dhmm zOqL!PaB+r?3Fjim;KjV23v`b5hx7k#-4WtKPDkd#AW3+X`-t?-jU^nG5%FfCEPglU zio88k+%ex69)!B$Fix8~urq!vL&j;DJK@#*%un+B@U5fV^|nLPIiKjDPE|14uLF%= zdVP()x}kAnqJ+n}$05JP{P*dq)Qy180v-k2{tWa(fQ6vF6W<+xXMsNm-{S#m0b2n- z0sIMo8G7v*j#B47i@7n}#KEtCC-`Z-;I~i(Gl6!euU_IOI+XmX{POx?{HN<5+8NXEPM~ z*4Cch(qqloRMWdDy%RkaBg3>Xo(?Y6&QExI5-}Uu4f)-T+q(J&C%p==yuJYng9a!I z8lWg>XqPKCIcP%)Wc@bdruCa`-_IjEOk|osX`8G45LURdZ^B}~=Q_MTjf!do9Ub%;FUIFP$>Cn%qLI#4~4K8h!@aS{N6o@v!!1%q39@pGje;|lqT5!LfTuey15skgbY?RWwQTweNp z%Nod94=?5FEqQ>(Jm9{9_C5$|1CA(bZT({#GVhA0I%J>u6JLcV(R?i-Xs2?%Huw|bf#mY zYwX_GiXEE<-;I66;A5V0Y~~!CW(y*-1lO4;2#63!9@gb!q@`kPmJHaDgYHN4o`UfvIANKfYx^^2o1Zw)pJsLURDF))04-i7d@oH|9ZExI^M(gXJ zgg~LY4lM;!KOx5#Ha9gpgBK5vFJwJIC^}7N&~G`j(YUz{QkV7H!__bH%*%b|6+ZLH zi?Tbgy2o4_)fWWOAId2mP1UJ)17K7)tkd7qvuMM+w~tL0&X9bioZ|rKhTzJ3V$e&D zW-EfwIWF|guTCWZ^?>gkSDiXyL3QdHnEAaA-9Y6)E({{gb=z7qUpHtmudI#&}ebp#L%QI zxo!+iuBg{>;+`YVE!sL}35+ZIV-HU))iBq#(R@8D6;R}*?#083bUmE&5T@tz5bS_4 z36@J2=>D*Pdv_0)=fFkjJtcI*dK$+7`3eJ4Jk2K)OL@FD;0L?AVwRDj|6H5*{72d` zVHlh6FuK}%_8r-YVTSBsWGzbk;<(`9*&aL_6?)V}c^FwB_N>DL?tF#ulK#gnPycMj zbHWKprmsGP$gc_`mWNr!SFQ;0K*$YYVfV*p}Q{Mvo8t^{ApMZN6z8e6wfPVzM7Ptlg{m8*S4)fapGnQ1R9KdOSivXls z*bMs%fW3ex0EdBg65wMne;Hu;?6(QDt$@ej??(Y&0xWi#SFh>Dv9S66j!g2C!^Qmi zW$3>QtihMiRt8>09;e39d;D~HQ}+Mea`Z_C5-ZRz0xtK#p)j8WI2J(jrQl8DOK1=k zpxyz&`oX#CX^zvd8v5x1!oolI9{UQ=h>+Uk#^dxe=#KNqMY0V|uPU(`IBV93FS_zL zYaH+lV+&BX$+|g>* zv=+mS{fXZ_UFo!J@%L;zm*m+vN%Pro^x^ksRi{4Ot;f_^Fw;M0s~JyxYfjEqJ%-r5 zM=UF6E60!X70XWaAzRImaK5uudOPEuo;q6*^;)Z;(Qep(I$MVaT(qO>BgdTq=za6X zJ?DoI|7ex4INmy2bx)0;WW9tZz!?vY)z};$X4W;?U7+_Gn2iT(ghpPtmChVrI}n^t zyvPz;Z4Z9FYE4(C2yblGFoACv?g8!$!?&!&mwu3T`FaiK!A#f*co*Ofz(atS0Y3+f z8@?^(dsd5fH)6i@XD#4WfIkEGGr*?+{{nbF;DXwdY8~ei=f|zpDZ;56(O%C)IQTN1 z{25g+m$OzgBUiHsS2OLaMWGp^Q)EXZ>t8X-Ovzi$Jy@45-~aSFSxCNa+%YshoJmhi zj7`jw_;GAv`Y8(y=kqv4+>h4=#|E(=5k*0rJ1+r zL|k@GT3RbJEa*1IcItKP1wLN$J{@{XJR`_eOwm5*xNu%z{e(O-EQ{%Qx(9p9Fly>^ zvW&OoVYyICY13ixc8@P%TdKt%;13C@Im*+>OY6+Bn zQ$8=_H>2dy^@$eu2(7;ytsic=xUsbBhx!>ohDrTV#g^*Sbl@oPm4d@Si-S`9e`|ad z!jA(aFZRc@$3ZM}43ciGF3Or|FZKKJ5M;JtJrDlfp#I7eNltfji=F{CjKk`9eJQERx~Xd~Ay`d|2z!XS^*l{bU`>5j@F2Jo_y6XRW+3A>ZE)8L+@jJ3Q7B z#*?3NGVvLx#`OHx%;Oq_y;}?SIxZad$lHUoY{Ib+x~Gl+D{x$5GY(}<*loj--G;%O zB+KcY4%*L?;hue!-?7m{@F)rt3p#xc8VBsgHZblOCNMpZ?K7wMQtlMF2 z4q0T^RrUI#^pW5rKLM*_cvMG6kbOOIoWC0h$02TspGg|Nl>TB#n->L#yEv?V>NNOa z(xGJsY+T^|2VQ7mmSq{%4Zh1^(=89VZ6<3oPm(da>y{xWqLI;Q;NA!<{`C*6hEJoG3nO^Uj>y`;>S)F|9aAE=O z&oxM6tMi3`T+Y;ImhofG`(}FEH@0`2-R?)NYi#zp@f&+OHfE6JT{r{|Q+RR%IT3XXxv~{)jZd#{}%|2u6W)hn_dc>PH@lEzI)1K~V@rUU*^Q=X0x6UDB zZfwJX5T+MG(7V(c+l;jZ%SCdA18z__rsm82DXecYvs=jeCG8zwnhB&r_Q^ZOF7ph` z7rB9OWK7Fn?2{VM*^-}Q1p60vNM<{-K^Q-%Q_7>09MAjMs0r6c0i<809MU-feO)04 z3D~dn;rIE>Vcz|<({H+Yp@g3&g0{l&`29WtxN5-qX@V2uhxP9a(EcaDh8O<+PlU}d zs|ao=x;;_fDKrkwF0F3avbws9&t10c;&VGj$CwF>6X)4bW2=YuRHtqO z{PzH8Xcz4Y1 zVqsf;XK@^Va@%-uG$-5)pLznUD~|MQ;aiXWc`G{T^iYOd@P_KtOu%;l&j8i|E&$vB z_zWQRM(FJDl`)Is8QVHC&UOn7i}DrhrZ3ihQ*LWcbCWsOt~X_Ntw_vVha9&A20OWr-{O&IFX3wCi#O7mtBcNa2smgZQq-aW;>3epI>BM_*jY)ZGa z5qK?${kjDu^@6&7d%ukRdK}bo7#RxNjkKhb36wU|>qy!#a&t)(0*C9K!+2+JTX%YW zTgSS_HrEP%*Nn{TcS3ak1PQzhV-cWn9j?&8g)*(}ORZ?Qtmvh7}mvaqC2LdUI3#8E}8Wi#9 zQy%NNX0q)H3a-J5927G|gwbM)l`@zI2p^*??sw_Y>7>k#Jq*pQEiH8Ak-4mlP3nzp zjt*7|TOvSFUYfg9cD4-3)6p@ETeyi#60sXw-%LVuI42++49RZfSvy<{Xv{yZ5xKR- zc2>Ue(ybdYos^YF{c<>??7BfF+qn$|{-WL z*r3!xcY{a6B^=5Fh6QJuvFU_b2FymFFmV|fAL=jo<%Gd~L(e)idJE+fj{g;z@9AWA?iFiixB>0-N%vh<+mi*>shs<1I;O4JR!m0c(x!cY25JywX% z7WDQOQIKms*1doJP<5*1rs~u=fFj@>fZG6H1)Ks}2jEh`djW%hlYk!{&d_^z#*C-@ zc#-V{uElC_c1}PF^~sU7cBOnL4hWhZtR|j~_?Gqyo0+ER*Bu|O#$C1=w&Ap8;N@AYa2l~fwmDO`PxRv!*GLm?JZa<`v}%5 zZ$@7V*bKM`uov(#!2N({0SAEZ`}lqjyz~=c$({L`V`>U0%dlSCoCidg#12p;?QN~LKPi)1} zPNg0~y(C}GAsClEfCWZpNSS;A-Qi0b<#ET+X3n1%7=NsZy^%ul(4!*z@ zS~ZTcvV&d11LjNz=MI~5{Y(6dEp*Gd(vA0Gp9^5*v!$WSMH4?dLRgw6*b? zwvKjTjZ#D+pnHUVRyBj*9?w(COnxVTJyLfR3y>`R9HQkVKt!I1F1|eX+)V2=SdKyc2+GT>GugmWx zZ?N?FNUIw^S~xlK9Anmixm;s6Cv*Yq+1L_@TRe3lwSPWuz#Ftd*VeenkJ{XVJ0B&s zm^p)RlIoTfIAVeHZ+sgXXO z-cA1eNkh?xd|j_A5N(0NPH$m3nWE;r*!75(U^0mbIBsd{Xv8GQdM?%=11>f-m!(Q- zki%^q9i7&kMk%yt3v!QT?poYvmyv7Gwy+-+J1zfqYf;re2x^ZV`Ab*Kyqoyd-yCBn>WEZXE zM6^%DwXdCSmY6$Wy`E2qp$yCMR6~|T7SFEk* zs>oK1RP2U-_}h zdn>ffN)Vf{H)VPv9Qvzu;Ar*@@RCY7?sxEs3p(aoj|G zRpQ3PCldE19!~rOcTxW-F*7+Qd0cX7@{HtJ=tCxw|CoGh@;%89qZj#H@+--QlaD8V zmHZ=ar#`6SsEU)guwj1EV%M?8H(BvPP;&dTnA{;>Y^F_HGqaOsv}h5lteIJ5%(kVA zl?`1>rnEM}69fqpZtPgcZQ9s^ znwuuV%DLLCgVU|eCZL%s*>pn|DOWw3iB+0xBV#6s^`uy#+K^ef1YuH25xr4TMtR$& zG9U$#T`uaeIU*KRX%bpDZPLwCEFutU6FN8(1jnmxY+ul+Y)iMelr{*<$RbGeost7> z8@jC{&b%aAqKUv_kMWGng#lOrPt1P#P7qqWqtWdNT#NMy6y%YhJwZ;am~OOg(I(t{ z({+x`eiWW3hEc-MJU*n&zpnI|CDCYF+4?te;wnve{;3BXI{g$wt_SNgCZ^lF#^CZ)k?p>{_WlLfHPe z+8&AcUI^``p7wS^7We81ZlAZFz-YoX?LUDP+hcJH#VXZ|{^vZkO`kw<5yb1rr#Hoqa#My}<^gtIUE>FBSadYC%#1|4@gBiLv>=X-ze%AuMgKOr@&a+@<5^&Z6giGb^ zH0bigKb-qbdlYooruMtcKyhNhR^#EQs|(mWI)fg$tQ}r#5hU_oLZt|7)?UTVf)ppF zSlkcg%cHRSa)nB(F5HhlB0GORqCO4z^6TnRyv6rBmp9HJBCKqL>DcI*p^@yuf+F)% zXxMnv+?Mw2?U;RVCcw8D(#;;;%E8_R{;n5#9MD~$Hv8Wu(HPzH_d<4u0HsmVJ2zvA zSzFmieMHn}tVe4S>%BIa8muic9yB7F(zs>R$83qw!pJO-kXSzRN{F^fX&IxW$~a;{ zbZa~-lr~A@mK^pb@^Ps z*^K(rHr&_7(;(RqZm;f?^5I^t>%WWhf{#rN<@o+(ntp`C@%#DaGJaG)8jatRK7PMH z;V|~c9_P>gg!4&XoEWa(Z8#o(1n=5^t4^H`SOus9tN<(qNIT-eW86iQ(d|j@fa3nT zKmQQtqNaeCr=XW}A9fqImvd`r`|G9@e;6OO+wi9Q{qMLh=a#f`^iuK5{HQuL_E*AC z$ld0UeLDW`Z}_FcX!$F`E*HO2;goY@Y31B9z5APH`pfj;Hrvh&rF1cDfapvS_Z;=n zKUAl#{7>BF@LxEe`081yHAl`0?%UGs*S#Q~eKPmAZF>smF9GKQRsn7VTw=ag;Tt;d z_cy;EzVo-$DL-udU3Dr97l7xb=QRE_n0Epmc$VkKdAX3{z5p5m8v{!33m~gr-De)0 z0yyM_>eSJIMS$gi)d14Cw(sAEz?FNt=K4J8T)RIT_CjD~UemZY7#khjb4yfRJ0tl4 zY@8Ff+$Zf!3=a+gLBC{gz))TzcpkC=2Ly{t7+hhAJS@YVrP^Ce&EkG=C8qAZ$S1inwuTuv=YK#{JD?z zpJ&WU-39mz;PZg{0bc>kKJ-l!55@OPpIPdXSMdrpcwllVo|LSu)9(avUt&p~ zWs6FY$f#sYXyDF79s^YX7eA%Bp`KOm(X~wtnzg~WYWqaDNHuh{uop^bOj7kmQ{k|CeU6T41_pzS4ZZiZACK zPraiu#j)<%`TDK#E8kF=ngRROZ>dbllHz5RDP|PcBsf=OzsbEv{80hutUNfyBs~Pr znLq67SYMpCSEguI__Duu0PLIDm%seVD`VqVRi^MZ&lvr94&VFsR+6;eztc}X*mZZr z)s?9e04o74fX#pbzz)FWfcF4C3b+UGAmA~;F9Cl9%zS5M>IlFIfR%t2z-GVzU6I85bzk_mw-P4X1)vV0Ve=f0$Ko@0Rw;?fXe~z0elp258y$-V}M@*{s@?P z4cr4x0IUSG05$^#06PGe1KtBDl|d_f`M`2!neb=L%x7z6-L^mC2>zetvu;>!{PBDA z?XyyQPVw?w2>f@5N+c^PXVj_L&e}vGG3!X~;x@lT^%3(D2eTPSJw^GyLh~MgKQ6>E z>^%TKUgB8oENSil!TiE;w)n_5ap``x<0Jk|fw1wh-znI`6I)@ zhZv+jG3%HU5%IXV|Kj*rseOPw_oME~%|`mNdAbbzj$hut^IqGQhsGar3}oz zlVwG}*w4~$x+4#1#D{+l5V83fW`zBrZC+m5tkkOo7^70Nk6BQ+x-)U`k%Q9iv6 zrag7=DHY~U<`L>hZTj5A!E@)=ov}%~iTlsAm1<}EgQws7>z6-1bn5{8X(G=5v-atJ zqqS41TeiLFicjKP(02g40B-}_2=IqP^VQhje!s#0=z8qqy%xHscUPzKz?}}-4KUXL zpTIegyRip;4e(ulf7UlOH8?fcx3b7tzGTIcl`!MnN!2ABp9u~6aLp`2`lBvPJLb7$#o~!uW)K`jCcZ9 z=i#cLMRMf^b^`S{>pR&M?csrz4tpL*4}|9{xq|6e=1lr?Oa0CdLlNH#wzVUy|}{I3*@^YTHdQ>d6SKTZEJv}u~YrK&1* z4;5PhdbMNevk$FGOLWAbf?%(wV zOTTvvZ*<$k`mX21HMN^P)?@zw4x ze3zwP3wm$F{hM#I^r!I#)p?QpJK%0h-|#%%!(v4=Kkfg2J!a{16z-h2M0_><>Srwd zKG5Y6#enNqM^%}>+&ikAL#H}=!$4njCIz2-7YZ`+LhqLK1j{#Hw0aW3v1 zi1?rVgr)Dg5cl|n#^90^j;6Z)R&EF6m?4Xqc!L&pMg3bTT(I^-i%SOA9*??li{u0xSKY=WmMImrk3U#AIF6b z;5x4y7q;_GcnEkjM5AJgD z@+FBDP%>YP9E3pUlw-pUXBk|HyB&NTQ}LMy{v%dk{K3llRuON}NjYK{j($Hmuda(@ zWLf)o9*E=dJi|UEJYartUOgShCw{psr=Y`(#7hS^+Rv{#3wMe{IK05PTSDCw$0NQ7 z`MEf9&Wl$A~)BeZ`D(O8U`v2E%%A-pcNjNUEtQi#YKtPSZ9 ztO5Je#Xt;cQ;5XW7BZ$o(;qxFfOns8g&i7PW@`3fTsb+M9Rc%>=`fov3GCNQ$quGl z$}yq)-IixGKU0oN-m3)DPs%ajnrpE9t}IJ-7g#DVD){p@kb%0Mg6r_ITMt0XLKOXsaK=1}x7rR?p3{ju?`l<- zMk%VuLeP{t_4+8O-yLn#y-_O1A_?xTwr>_saeZq(Q^1pqSfSXhZV1rKL(Cre69KZc zJ&(9AKr|0Gd*tr~$WoZ5$Z)+=c5(E$08N6Pkel=ZY$?$?~KZvgnLC>X<9VnHI z)4L87^|xRXr;;4XHCf&>uRE6CKxzySO&o{Rk&u_;D7j3gUac=hRIe{Z$z+x*%HVN+ zj-nUJsTWI7^XfF)PHYl%$>h{<2?7Iqe@R-sx-XuVSHF%WsJXT|+6WBeF(uU!#bV~?hl{4m0U1!Pp?VLXl9r~b1Xb(uQAwqzSEeN(OU5qOkOD#JZe z8MZD|Y9F@zjoP77o~+hg4vZQ79+HeuneExaHudIdFv=T0@0|vtc|1vdd>Xv^xh3`a zX|VFCrf*DxPo8m7KbaP%`dxW8?kLtdRAI;D_^cGh(J^)SG}!DtiE80AnEN2hom!r6 zC|k(r$7Yo)IfP;<8|!)WX(Yc(r^gi}%5bWq?N}FL;$75Id)n2fO0eK*N_pV#n`P+s z@?fdCpM^#wsi=jzc|@r#*nBO0hpwvV$6&C+jGcw3Yszwo7^dzk#}k~Hsc)9!<-ANi zS&kz(D^tHO&x>bWj=Cn;25aqsj9C$pKRPv#d1t`E~ajqic2DP+%e&( z^FHM4puE81O`z45Dfo0D{j5A!sFvo;XFP*KgDiW`M>dU+nnm9FwU zz5?4Z6{jw;E6cOFg?211pe~bK@<{~OMfhaqQ&9f^`61}RaKVlf^70*?X8uTohcEEr zJ!jmytosAwLOl@WPW@;`_1JM?x(Hgv8%|GD_55-y+w&86 zw1Gjjm*q3T;;DqOkxAansUD8-Yk7GzzcW+7lh?Vt`cs5OVuyN`!;=e{Y=3`79)zDz zx#Po;G;>4|;g2~XLWNTyT@@kuGk_tOxO}xNBa0tT?BRLaQCyy_4uE(N%yvv!CNYn^ zXc8A^cSoplUdtrq!3dRgzz|QZ34831uAC~#KuYFgYPm(_Soui1LHVSxSC^6WfjWQz{m#kz8y`-=h0`{J2{S&(0) zW-lw}Df^HNxLV6{d07C~HdS@iZxf8i^JTgHSpep>%VWI`Wx;Y(gLp=N zHOPbQ>t)$|nE>A8irBD?m!Vt$|E=Zu{WXD6DV|);`#?T`dtW?vFeC7ewW?ZK&ReMr zWNR+V=4AwVUtg9tm=WZkk0ZL%>^sQ*Y*}`HMv(ioRk5CjGGgTl^^SN(e~lOh+rwqq zd>H}W15b?&JGMs9@4L$L`)dT*--PE8OXpi4Bf$OLc1LLV-$B2K<{;*>_c=vwrbNu-B{_vxBnbk7==(9I!jqneQOcsWW z`YJPm_e0d{BRrhvXa$$%_(+69W+>A2@$CuKyFMH(Jea%9D#cI%wtaLUEg}w9llvHQ7tG7pZOh>B8w?xRJV#B&7E6>yT2NaeM4f3F-4+K%vV-mFz6g`Az_CQEzFC$byGuP;j=^kW_-_wAk;uhKO9;Vba2N`y}(>}<(Wukr(3&;E)l_6t{pI=ql zHK)dJE<@)Se*3|t-H&4oKHF}{iHY4f-2c)piN(-4hV!=sVI&o|{AQur`Y>+0k?b)8 zD3ffAwyU-a71$W@#5B0=wz@;{hU*kQ2iFGR|NN=lm@RfEPtEBL0(R@(`suil?RMLy z=43-cjIWuR(_1+J|7WJdFY5cHyY*Ga&-_)6O`?Ak&z`gR=81K1AW?PKAO<->+&S)%LorQX$lq0-uUL1!I?#9J)v*fj6IxwSiqEEGXBI+BI63!C%M}|8=e^t^^X&9oOybpVh+W6o z1y;A(8(}37E4^iQa9X_F%cR~pEmj-lZ%oB43NUq$U2ctuYY}=$)M(6G@)N3MYDRQU zxM}nCQ!`3`@r9}Rpnw=wUtSQcFj(BfMi{ds%!O~&zc9)LrSRm4Y@JYFsfm)!oc)AF zQ4%Lfe5XB|$?b+vT2QM>Fd6chG2}jU_S+!GyK(qY43kX*Dt|HGu9ln_jf-W`(^Mn+ z`S%>JovtI(V_?WTd-_hy%oUD`({u#Z%co{__aa|6HLu-~d|M1_`5`_uw@1|O`z!tM zGVhyzwGUoi{^qaq1Mz=pzg@aHeaK1C+EqULY{tJB<1$n)^@i|+?HazJ#!Ona%eHW5 zYDRZ+c>OeZ&5Rov)EvWIK9xG^oA=+Hq-1En-MI<7c>kSx=~VdrAi)_U4}o%d>?kWl zOZTYt0NkrQhMp)lWR8wl&B85qNDDHH&8KMPPUVYi4;*B*{syqyv*Y%R%8jdh$b3N9qQXcB+pCrfe=Yt`RFXFGo+|yot{v&=<~id*TjJvvQbpH zeq1DXRd1DIhJbBjsx^!oQCq{PNpHS5+^^mgB1`8%AKTT#A(BqgSLG77YrXGwVO$zC3^c7O}0aq(mz}0W#NRvYP6ne9;D|O_7 zQDi0qwQ4MWx%x;L&mIv+B=YKOVG5IyIa$3Ni(jcuJSZ;YQ&fK#Z$sdSxFbwtAQJq| zaTMIQp24869IIpwWEix=o8t(`WVJVrz>Pa!iz6U|RkAuJJ=8E?8b?4{8fL{fKy6bO z#Sx@te>_Yv!`2a~O5vi_)o6X^@|AUU8I1S4m=h4wYU6mNUV-{Iyl3JtG>Ksh2$BLBXVI7F-4%lqIBaB24PF}0 zf#-SJG^w`y7b5@r#igv)rTE$DiaiWgioq2w;Hy`mmJ5HqWvz{uq8 zul{I+i-U=>0)ZKP;24@)p1-};HVW5QbpKd*!i4&x5mI(yFsHsAhu)!n6hTY34R6&m z5t4{JQjuPX(6C;PVcy7b>QLL7-1up_JG)TxBOF$slHRhQPA}p zvuN3HTX`l~G*z#UFmV}Gj*S=8J0e80ee6RKf<20frnDnJqV9?^@Su?7@K@t$dZ77! z3=v8=WIvAQ|Gor~O;{Lst&X%6w{Rpi*scJ{QJoZ_%Gx8;iRO&cx(I_fw_K_xLZ?iP z!lF9CjsiYsxY+^65VprqI5*%MVK~!*y<)ssK+Uk-y3Yf$*%NFWQMak{W4JJ50Q-X2Qy;nkfHqCR!a9 zgU9gU9;%~wtU8V`IqY+6#vr}lMLih9A$L(c8$-|=d6~dFBmul7>Wvuc=GX+tC|^%e z1dAOVVXR%n_AUf5&Tdd{ds=-I973L?O+hhTOzNPo`Kg^ z{r)(mzHT!QPKuN{WdFFm4u&VXUgZnX@e2cCU=3>m7P(LoCtTjd*S>U9U>1 zkq{B9G8nU5P5c@2OmUlJNvVrj^@T`2g-j0wwxr^XUGGJiPufPwW4oe?$)F};ndXWZ zf}U}!_r;K?WkJ7)qQyx5l^BL>acn!<5jw>@Zl;(w$3)#1tjmGJ{4r#99qhpD^ zdP@v1g~~ABS7P|${QI}*@!=^l^=t`NlmXTN)eM}nmk!UDNXE>NYh%ca5W5Y{qnct^ z=!1`?-8NibAmOB6Ff|X8GZDjP;(A#O$rlOs5vXyfSG?)%E9d~9u+swJ5>bjw1*v?z z?(JF(%6n|ryTd%?mEmxx&75$l0o!%NGGI2i!M1FVLDXhDqj*k!)HkAdecIByK*96L zoWsQAa;t5KQQ~s-gDBCA!LzN7z;k9VEmFlO4YP0cxhR?m;%xm_QIZaa#Cf(?^n#Mv z9!Ot}l5l82mU#bMl0-kGGU%McmYqpXbQdF$)*{!8j6ZxOs7UDLz1z(lIRk=_xE2^0tHB?#0nsatH` z__>(E{OII%bI2ucLk;ujq4Ny^na>0yy|kw9v%BfS&d0OGA+2D4C?HrFFIZ77wtcMM zEhJhVb)ZhXfNN&j+2j<|{b-oHBJr1yA5XF}B!>M-x!lfG2^)+!I$a#`-oy<^#8$WJ z<@zu7l*sBo+(H(-FUMDid)}+qhN1XT*xdemWLu_~!!1`n9Orli*cIM&XJmQb;%c=0 zTGNZ@PJ}+l*z}m`H#{^(CTuh1Z&W2-k_5!NB434yvpNt^Q96kL`?#?4>c|IC=C8HoF7?GIRSVdtiX}B|13|qZjw?!NIq!lJe5X~iGYcqVp?TBD8^~0JjlU4N zlBSg!hX?SuNJpbr1<>1z+okB+RYw3%zd%zH0c^e>w2630XAcEJb5Z8KrMw}JiBR+L z;RwSqH3#Z@Cxj{JFV#C1hOxNaaa4Wo#4wtjD`YoyF8V3mhHZ}MH(1sEOTz>@(S6_3 z7^Q-aC>3bhhWap#?nEzmX@q238t=@iS{`;Nvea1Lg}mwF)Cg6g!#7UlPOp&&U8f_{ zw;K%o`CaPP2*>tZe@5?!dn}eFqd+AF$6#9NOfK=PkC5E-6m}Pi1M0jOhV8gWjLCg# zgtkL3M60V-`a`r{s+$66(*sr5L*=%f;YvsxamA)kb$FO0J?+9URuXw?7(0MP1EFjT zQ&^G^EOWyJPQ}j;leJi)#=>|WBYQ&_iF-^SyIm7T+q2A?d`poZ}Jyj!hl zUk}r`jNFH*p88Rk0#y~70;;ciCQKU36%FZ?FbUn5AsxEPUtlPSq5LjGnja?V%T^iI z$zc+bP5k;Wo_!Aq=Y$Ce0~$7xwuMPM&}POYNv{u+;7XograSlY09$=nx+Huk>**?@xV0n)mOI(&gNMIwR8WZE z?cy)5Q>yFLHdg2^v8IXZoC|8gmCK0SfqzlS;*OF$RBi&vNC6v^VWQgkzr=StB7lEoFJxvXUIzEUhc$>Py+JSIZlT;wkw8BB52D#z2E z!#EH9Q@7A1XM7~t7Bz?g=EGC>g5l0m3~qz|aw!hmpbtRv(G5CO zD|LfDvLsm=^hu@2Zi8N3k|Wrlwep$I0bJ3m)R(P#GrMDmvZ86y7awIJYtXDooNZHi zTvY391N2eHF$m){rDj;<1f7fDTE-olQ0;cmHO_@967Aa6L3f&gfy+9V$Sz0QisW}q z77T&vg{Ghf;5?{TM4Qx;QW45km|*r^ZGxx zm!evIU9z(jhh3gK=&T@zB#(n8mP0c-nFVz~cMOv!%73vZNS3u5lSTg#qDcy5;|dg6 zvr%270{b$a=^jVI@Y@2wJ}^8ZF$XHC=d8AdWoFe5%xq7u)?&4LVHS7NFXc_YFFA~U z^9hP;p<;T>PKS0v)ds(@v@JU!qodBDH73d>IPKW8raWI{1UjoczZr*e<+3!w7%s}v^@?3%O>EEZ~wWHLZ$}{@Ls(L#P#b>;4E__>?;!J?Vx1 z_sKF`wh#}r(_tH?=ToEr`HH#JhvAk58Qwn9? z;%Ft1l$n&DQi>iZkgcV;Y;kNa#o{ZBTg&m72syRE2y^b{J|W>#<83a>XN%;m<+vin zazi<8Q#79_#}g@@edW2Oh<;Iy$K=YN%kcz?>R9N;{jENbf8Luob>-N6MYe4!J`=&8 z$MS{S(2-U(XWE&LoaVAcwyrc!q`-Pg^P1usD9sTmtX<`JrKoNw&0+H4Q>8fq#q?M? zKHH|AD$V38qWN`kB`%ptE)%gkP7ZR}^GI5)1HC-F6OT%BdfRU1CP8 zx0GYE<@u>HOpyY8pbWDq(Z|ZLM2hsOvdmJZ)mVe{HyD3fP2L?>h9yv{EoB*Pv2H2D zPr+s)_XrjS{qc9Fvp)|J%!GE|K#)HqSw<(L-B>9Kp7rkR6NM+oB4 z-12PhB-Op7%#P(j$=Oa-PY-+NNm9`)XrGGNOa28@vwBH?{S?ed_B%?mxJmv{X&#&0 zyJA?Ri-;!ntL0g}q<()YMlYeymt{pVXAXrb0g6N7=O%J)DGr;&4IzfW$QMoKxl^-y zNgbIEvzOerOv#QUUtf;NP4*q-xNOqzk7X)RzTcjT*-Q4%r)KpMt%id|=o{Q6_mSjR zm1c1hyr49XP3~tyEdDM#TG0PGCAXL0C#J#crTEWNaU;pq7Y1|1A6GZc$ChETiM}Mn z6Y96MhVAWBFo~Y+rt(a#w(V0>@Oe772g00QXR71%SQ!S1(^I7x-1z*t438I=>TSUc zhssR%BswO?mLy9&>PnH_Sgb3_;l-gR#1rU>bUX&ivPfKZm1A+^^VYIlUYu@-<&!=_ z$LJGf7$iRXN;9~z`A!)gFD}0barqmCj?5p+aY$@ZBf)a^`{73CHRYJR_)z}_SsVH{ zKJoh71C{#E1C$yW%l2;`AKoN8*wksjauv?3b<@eG#0gE63I1P-rGTZy?c+;%`7jj4 zOR<<I*3v8m)C=?Ar!)w_{7$%Gu6p0BF+AYYP+X3&%KD-l0>bYSI|@xQVFF~QLzKD|{0EBn$r-43ER_lx z{vY<l>fhd!L+=!^ue?g(QR$YUsU&A|!-0xr zBZ}n;Vy|GuuGe~1#C|PTyqd_{nzN4h#&K!K&jeZ@Ll4RTA<;V?UFOBo$(6$ip?l5*kjc(I&1tm0@mO{_7L z^_2Av8Vh$hDw}}gv)+M-a>)ZgezG68T`^C<@kN^AoH;I~01$c-2{Wu!lno|9pdxip1H0xWlm;CVMkYX#-Qjb9t|b}7 zctSq}J}ncMdAGqzZMX1$4i75-%|1qIy#Vua zj*2{mcDDOWCaVeaOk&iZ{5ZUI7|A01LKh)nhIA(EoVx%{#Sa=J-t1Ch7&?qMyL6xA z7;lsibc&HWpCGxNVPN->c(eNuO(w>h-NzN7>SW-S$kixfyq!SHc(eOZti&6xIH)|( z2SvQYw<17(aIkDx#U7(~oQtrD+FirGG2rdShNYxWnd@$H zj*kys+dY1fvOswFbO`Bb8Y&DeYau1Vr%3HFzW@w6@{n*(w6LEQA>jBUli5>Gt4|C; z$8Sa8;SLFky3DIqKsfxQJwNK~ID>tdW0X_j+NB&mZgmc7fuiuv#`uo>;9kIp+p-b1 z&af581|300QMC=o+616*BYOPqM7}Qb@-<1TCkXg{4VSVm^J*UuP6z?~9h@K51>xU) zmePfkKo@1BL^oj9V8@T37wDpq(u9HV=cu!8XmUXnX^TQ%mqIYO-8+LA{7Gk}Ad7=_ zHxigp+nEiRUp^1`=19-*&Ee<(y)yKAIrNMvAo9&Q1LUFANSJ*J7P{eoCs32X2r&}= zzB$Cue1^Yo&b^XjtWZMGDMjjhjKt4Y0~3c^-yEXJ#PE-cP<0~cVqRF3al$oF?HY&|2fRPE13HHEWDmUy7k0F|D=Jr`!UA*H;73w)j&6eyZkq?5-iUbnn)RA zsKcA!w+TA_`ur%o{s0L79@0EwWW7$a?k1g%!OGo~^$yG4mGb&!~4`+99>CznGX^H2x>DRT)-s(=K6+siLbu^9K5^ZpB_o zlI;l%x)qBxyvaGS;Y-Lo3Hx*>(i}>n>m+oseCgAjNT)}uJg+yazXDSRa}qCia?5HU%SU zBIkiISh$I5%w$uS7_|n7NFK<8jjm%EK}=1K*)IK1J=3pHBlnuOo0sJIJ zq{Zv6*V7QYcHheU$uwdEsqNakSLW~r5`FOkWOa2jhi$w0Ok}JWLZ2gHT>^R;QCVon z9RQl^dyz&Ks}5~j`qW~DH(7PKEH}7>ybq#8kF#z>Xio%pCIM|fLG~Y@_;~=i7cwBW z5VUH?H=V8YR+;N+Z&}$?!mpOGrpM*-B|G|(wWuIWyPi#Z^#^3yhJ+8@*Cn9;hNQ*2 z$o>q!*Rj(B*e}vobJ9m&X!$r0Z{gQs44Ittz-p4!K=PA^L}Y zCb^kKY>Z6sg}aXR=vW0`TPn7ieQ6zs{ zjFh5+{&;LV-IB$1OBUD7h$|6sTD$UEcV_^eflj0AXm(=aDR5AdP&2f;Hg-xD+DU}Q zRO|C7W-_X-b94<36hjd!lf?8$wyj69m>#Z}Hg8hQ)vR4ZeG?93uNz2IueT9l9MoI5 z#+e#5)-s}0w?)7<(Htn+F2V_YvF7Na+VrE$we){yU5f*S?n)Be#}&+nsGL%vj^z)Z zjz;gxIMOkrrMs)81X_BC79A5kJ&m3`E{)slrm}0;P!;+X9H^*SFj0&C$;t*KD?2G! z+3+M~BV1*wbulZ^izEC*JqQObvMGFDl7g~iH(M1# zuIp)928!zTQz7YQ{7Nu*)EHz{%UM8Niyx|YGcCA=!{aiYiK`DL~x*7?yJj&pue9CTtN;|$TBY3DU{l{l_=pG4lS&PPS@?A_9V#2V| zDR418h=Bs-$jqpHb{}FkQ%*ydrav(cqBWgHE@luhIp{r3V;55aOynid*nN5O8d=W@ z4CMJ}L{9wVtS-V6FI~U|Zx_C{&(}@Xc|LnM<#mOnzV2t>c0O1U1166fSzX?R(|kQR z5(7PkYR-exd`q}W@A3%}-%^4o98W1ffXBCTBvN1|5mQQwgLHunj$+o1-W+WvQ+5Iy7n;(bEyrpP{F%C<@c z;wE`pWeW3#B15)S#xt;i0dwbN37?m9iyVT_3dwW?RPu<%~2S)bxnga;+M8ds2(z%-((*dUL z?GeL$3bVIYBROtvP(sk5sm|p9Q}_0WCX?CQb492+Pk``*y*-cC?Cnu(d~c7&1x38` zHNgLIZ|@fnggCHrZ;v(d_V&60m%6t{46QSJdpjh@Dp7<}jcn@P9x)(S4k_niR!i*d zu^B1J?CqJHx3_mt%DlZj(=^=M>kTRH-rgMmgAR?B&8qzX+-0q7BOgLO^a&Dg8@aBm ztFbe*5)%rlc~3TW(d;$h4a2atxRw|iqjAx~UPocrMf1&AFi+X*O)da!6dLJ{$L#Hk zTY~{xr$m^&?}0$LaT`tE`|d-@4`V(#g#-iwj#Y%gdp`37kY9{}`CR4+1e{2J7-u)z zLJUDr9L9lfE_Cad$-J(6Eil&akns?J&`U^|S%}_Z&I{@)=NBL|D8n9Zwr5AMcgCA= zq{%rddmJZ<0N8c?C{m93=i`U9&ucK+$&>O}?&3u=;+dQ)X0c=vIb(VHR?H5%@KL7q zNo^9ADwWSMAfGK+z)kphaH1}z{Hb-QBX|B{Y)KTe$f}*1E9a|Czd}xr%Xxz~HTzzQ z>gD3HmPH#DAZ$s%3d;OuaEU<-Z?nA}W&$s+`qyh(t`*Z8S?E?4pyMEPvr ze70vc=UTm#o*l9ZDNVc5m`8)00x>8i1~~+- zN|sQRETPDg@F^v1rw!wFA|?0h5orcSs?%D^t8*BrPMc#Sj^!LXie_jl%}~|g4{+pw zqXCn41elZ)U@{XwmCtz3XUJyfa=E*TE?%?_DRt##h`uKImU5bz##Py}^|zXByKEy; z(wt-H#IELISIpSe!q}y(v1sP8P+$`X_^cM-oW(qWfG=_*`%=U65)?(moQ-_Le<0C6 zQs3&|kXUqzqT;>LmJ1pm%b8(ePZ-wqhII-VrHjNq1%vZCBG8 zjTeygM!NUThnbo_!IrO23T5oPnH#ddy(*glaNy47Ll4O=WpFjC(P5;RQ{L4 zc$m~kgv0o3iuS{O`jHHz96ZR%^&9%vQswj{g*a^KLgbA5qV(D0;xl(E@CkD2Np#th z0!~!=}5TR=kd7JzPsM$gyOEZcMvp}_!ytX4N(oJ zk@OOuy%5XQV!pb|Y3yRoB<5|jmD9w+45|q5j=mRD z;6?S)15tQfR?AEAa*hA8TF&KaIro28%kba-16S4Msv3HF@>27Yduj3zpx2$-N$#!A)%IG_I(D(neqER9)(*EY8Pu&j4mGbn8JRd_0MG5R0(a zn?+~HiNZ=Cl1~)2FmFy2$K zzy!>B_(A5ACgf+CHxqJ3dyv_kK1y&jAm$z9i}cT|`VuO+Toe^F!?346rP0fYx!

      ayVG++PR|);GwvYJp(B)y36RG|9CuWFGp=zt%yD{FBK;1fmB83Qgu=6=oKg(lA9h_hw906`c>!uI-TZlI?egt=@kC^zkfQ7T!n_#BYPlp zYytfla{(_$m;|(6M|q1Nj$a}Kak?AjJ%aJ9qpZ8SVtq|s0@{~xGvJyohBuS<0)qH{ z;J};74IE^-ABueel|?*x&CXBIA#c#>hctupns!tU}GSTmdR~T8;$qIs-d% zS^|?zj5-;J$T$eFGtW&bBSxJCM9$dO5Ia&|3OMLoDe1LHb3a7l=*sXvPRDuo=uC`} z+(>v5_j&26IT$4@+<_>Up2x6NtYRyCGMzitl-almup5>B9b#M)vx!k(0ugBgQag(} zBRgq#R((!Gtd!%=CPrle5&0Ij*_k|T@XCl$?SODmo{VUDq|T>E4xxD*U0?1~ z()Ed^3~6^yqN+o`4TUmk_Ty=#(d$#Jh3__`^?+BOZpt>V?+>>?J^ia&vB`%aY%Kq> z_NaotrZHXA0*>_g--Msi{FgKbp?@Iw0{#md!9xG92$7Kgo(W^RZjt?*;GX_(R~z_2;6pdH%!b zh4uZ-TVg}OzY$yo{%@eY(4P%E8~A5}vdDi6ENtix!jeY*-RPf<{Xe4qP5e`VDfWMg zhHvV>q6yBh{L5fTbN_14x9~p$OIrHhgvM6>Z=tKie*iYL_D_N2HvVrx-`2ku+S@6M zFT&%rY7?-07SHA@nKw7aM7~0g)WaBtE=8VT)Sokea%z#tU3>^_-o>XY8SQ8}vq|kV zy_$^fO`?YZAAzp}dZLN3i7W-Ni7_{a7`qiFzmB5NQ6$W;Be{FUnV8~kMCBpG#M?w- z;_)^yS907~rG%iv8zY=@Am^7bz$Tgin@Ds#z&sJE&LR*N!i5rG$J0uHO{7@f2xpap zZUyLZf`Qbz8p(E72P>>6x;;om+M{vx#G647+K+@;)~LR$8&qUoGZasH8YLJHk>-C( z5TWMi$ps5$;|`E%bX4IH4p}oeN~s8o^<=&>*U3gdH*GN4w1J@622NiTWg<2My2g0C zCdK1!4j$(z6kp65nu5eTpK6depOVc5r)CaHgANI;V+fyR@2trekFv}WwZ8QY^N1rxFM3Kn(0Lc&p zbD^Fa-c*3Xd2Zx~%HufS0g;kt~^AfBz`?SC)qn8_XD^k>*lcMfiPu;mKA>=$)opR2m5DX&q^co{% zZHka}DMHqJLd50`p3SG9gBo0Ha#7_RfXEBr(Wu^SL|&I7@_JXKsoV{wasgAh8%^cH z2=jE@O@rD;_3cK;9VtTY^z6bXT9m%a6SANXmh54Zz?aJ5<=0IR643VUdB7E- zoH7uyzmQPItox{6`pX6YM_bX5hmDMbDKZ}MYO`b!R6lB*5D2eFyXeP^yI=^vymAu; z?|S+LBjm*tAuoACKE?fp`ejc@4g>5JQ@3!K-w@ER8VAA4ePQld2#7rWjuH88ipcjo zkz&_hNzGv6l_veZYghQQ<`DUT$wkABTO;?O$<;&mV9lKsV2mR0!}_RE^F@l9W1bq` ztggRwEmzKqVEYq8ay|XMVf%Xu+YcVwbL?V2dKF%aIZFTJRrm~aX#KOvp~CerfOZ0T zRR3;7{wqb~AD+l17cLK~mhJ@LGv%6q=C*|DGAcEcYO!~)hG+;g>CW z;&71+t4JR-xRXy!jR`7EE36{KSx4Y(0@@#0(iV%KUIU3C2uw@z70@o1rZF+<&#}N* z%@FGgSwsN0T>gO*T3`PQh#?5fL99=l2CR!qlTD1;Ms8ljyNe}BSMv@spL8|vMdlZ$ z(OHo$u+eGEYTE>X31i50?)^J3L5HqwQj&q?4JOcl4(Q^aVS-NA^j>j$%*D8YjqWQx zm$86CnWV{8|Fbs&|rZvObD3!Ib#~PJEt%>$x_$@p*gQorpu6fQ-z}!QxdkdyM)2->l(2EyrO*s!P2Kysb?>KX zH|rjB2xTmalXP`Sx@z*0Cws{mpj z=T>aewB%`9i`!s@zSKqE26T%j+W@o8#oSIz2{mkYF?SGCNz7#~=1yYv(-oJyn7fGC zO*vP%m_5XN$(X*%#oSFygk!)C7qgd`7|sdw)h^~9Vj5HOP8V}8G4J4fNMGw>_5l+q zrR1Bdv*%|F znS{~ACF@>7GL}Uwl09)q$T&ks1|^#OWodGjMOsmRrhvQSt=7VVNd3H9hx?@F?SVPu zV(w?H?q@w;e3mU*&{!8h%-Oah-55_ zJRx=ocr%75m-#}RyXdcX3G*OoK9Yzgn{u*P7P$zk1^vr2LdH2b@+SRa46F~c?JSn% z@P(jwYV=#7gAlJq>5<(%9ZbiHJFihRQ6%i@TX zvk$e=9c1{4yntr5vpDpWTn5+UZrE#acn;jK>;Nol&F)-s1QpZ6^m{mbYRVpEne^|x zPH`L8h!VjrV>`*&XN1dgJy*sJE}8Xm83nlT)oY|rbHS>2OK5Z1sc)C?<>FDxS}?*j zpnh1wkSjU;0+&Y-uE6v=5(Hc&>7&x5f5P$lducYVSoH5~nHx;q__XxEaO~mA{_TXJ7>h$7_|Fd+H{||pLkuJ` zHm7X^@UIBOTRQ&l{}{D$pEmyg11otVc_(<1pGe-vym?S7@kH{SK*|%zhX7z=W|mJN zf0RTVeJ!N=K@sYWgij<>M>;dgdm?!*GEbuf4>`+O zr=^L3NZE<9^cj-l^hZHK=Udvb3t;LK$wZThTTgKjs?K2&LORbn<4+`ev^?vyG{wfB zNPb;(P`o^m{5JsJ6UirIs^FH(e|jQW+!uc$nGVN^r29lN9n7`8c_P{5yeE>WBk@GC zDXXU(UbNwBT?2NZYy#MY$*%Tt?!N9u5WD-j4mWL|GmPR;yYLV&o_93Cmb4o8kPc4N9p#yIVR_*=tHMN_8i{K5^9Tt*$(J3Cc^3xoN5mZbJ=ab z_!PP&-Lzpk6uo3}fpGamO zwF9}&Os-3K1vPwOay`Nu`XKkU59caYaUUPo>h||n;NqTD+&{c;E6RT68J1N%DEuIE z|EMFB6~4vF{^vD9HyklTw>VRvt}`l=cr2J0FYbJEW=W1?9$gu9K7+B&HXy6f2#Lpn ziS`1`H^&vB>O2aqbj}c}iOO z4voKwc-Fo4aVLeCYaclu0zPYl z;mzZPFA#I@7Ou>bJD1Zn-;2TvUlHQT>y44*#SJG&b6NzH8dU~gP!}(J;m87tk$air zQdRwG(0&1xY?6ONF1W`}VZ@B`7`aeAf&Eao|wn+E??J`~kiH_n`kil5DMErAR zV}atI2(GBVd^`4>Rl#?gpvm2mv z8S+Fls;=tt(da^ZW;lO1B+cS@&KP}kAab)!&Ixy{1D;b&E)YH$pRKZMp2u>R+pD+2 z9{V)Y%eluzWjPli8Hg_K*t2zBfymNN11A~@FphByg?8l6i?qeT+KMubffVa$rW>6-GG z6_K+d1HmlP$6&A#KoMW$GV8a(IYqN=zH3Sb~WI zag8P^dqQ+SD(CC+JF@QFlSK^vRcSnJ+0xJQ| zC*>G__KOlon1g~XX92*tMcaIH;^T`0!M-_5KoDAogjwn{9n;}gxZg0UWhVE{AqJ}5 z7cD#>IgY555OnGwbv{GV;S{6Iyl8=FGO_>0MW{MiVW2VWvDM-usz+-^REm`mwH@eu zbNG-k#%&_I&%t1itn0P_^YWsFHb6QjBbi)DSInm?=Eq&J1O*fN(YX1>6^Wtt$V#Y~ zzX}AQE08cd07n^W&5L6)9>FqRE~EPY_cH2#xs3WOT$Owo^)2SjWz;Ayn)-)*pP*>u zUPk4nY?L=)_(ujX>$~@3IAZ|wlosQ%+%w=G%?4sb@ty&H6(xE14EV>8)4ONDKh~7l zD#{%-|M)2=3_2M|qr5Je)>QUy3F1{Md|qf3ijud;w=yqhX+C)%BdzGx1VvWz7Ws7) z%8l)`-CSrj=A+oM&z-ir3HG_uZYTqy3HG_uZdxr6Hn-Dmd4eGKxzlc=;3nMXPP^j+ zV!6+qc2_Z`QdQgw2-)XO%hzfDd7nGV&F!>&YHDisxoL&$b58)^?qNr{xgF>=ml(6p z9p$ceS^@2HX_}gS?sLh`?d>aAWcInE+}sZIzl|8P&mHBic3K10#ihxVeeMH5M0pJ$ zts!gVu1K<(x4@&^_fBg}kGNalP8s0zr7*{C=i`T% z>~`(~ST*Yow6fdE<=kqJg-%Dp%eg$IOzPE9-X5D)!zD}5A)#{>lE?c4u)Bo$w5;7l zUh0KGzVVYN`WzD_ikfhi=~4njld6t@Xi5`IA6-@gP|bfsde@ciM9{@Y;67c;r5@C8^t zfzp(zIwTt7olG`2Qd@dbPhMyg|^mKdo4Bek`W8V(=f%+-bUw~D!dprt`a@{KBR zwHjHQ0M3P$V@6Ng{7M3oMGXFAQhOeFr#@Q#=qxOq>|Wu{SZvw7y}CTI2Dv^a=Y)69 zK+Q@iN~VF+Q4hO+Q!wLwJCsue@UK`@1ndFkq;!BeT`-fQ?dGst-C2vL*FYRvfP@*c zyVKkiL|r06%n9oNV(3^|xDL2Ra-8NUA?TDKbzVR+|8xNM0CR>qfM_zwGSw5I>ii1y zH(0mG;^cT*S)&f1Sk})f1f5lvIw;;L2ADSA=-?P-4~S3PpK|pvpdAQ8e8huU)~JP? z7^rCF7!;p0LPU|s>IWxJ0?=|U5{?h82&fXSI?*7Ar{Eu$>V9olglZV=laDwFRfV5W#@AI`}ZJll)oMq3I1oWWVifFR-w-R zMK~XD{^wHV$dg08DC6XYL0R9vPIC4_PhD_536Oh#vnwr zKMO9j{I89HT>qiItX7j5Skd_Hfe0dhlO-VZuL6C*-wI(H^k0FcV#t4BEze?VKoj;4 z=*hE~|3hRdXD-}v_#}j{y*oStYdZT%x9^Ad;cf`~Dn>sy3)62z?izEN6$s0T)oz|n z@lJ_$x1CDw=(8cKDPiSf12{X8Z*nqY@}{ty7~SNZ7dcO(Xd?U@w(m4U}d&Ib^j+jyQ&=^iSd#Fq`-wX-OPz&iHd-5m*m7^4@6+t&p z5OX5yHp)T{Q<5i+IZq;BF=A+mOmwlelH){23D_h+ z>fDdyyvtatm>Hg9M3YG-I!}bE^D)qo)7*wXo>qqE7{$s&w;Xg|A`=wxP8gN$guNK* zkcke@0gDc-+Zi#jTo8m>BVm>`awj^c9JnVgC+8_X*-$yf+fQ+(p=cC>%dw}Jb;K02 zjzH|t$!mH_ku2k;P&E6|6v|VLZ$|q1S}B*6+a#8w%Ip|I0$4>a7zleV`3s8NeZ4GV z@F(k>dw_R-K=My03Z!ihe+18`T}E;`?-}+@H;0V?-pi48?;j`(I$Xj=e_sYLGXrNW zxF^sL#0R4QX0-sq-O0}+Ml}K=+U-IT4@@c}M)hIYlNj@ZSrpW9GZNi-1zb6TJJr0V zwhTW#wv&0EAItG*XJ@|8FEmo9t5ga1th+ow*2=BGPbSOd!q#;ohEd;MQ>IGj`EJ_U z0-_ocTqi``^u2IE=nUo#xtOQX%R}cd_oZOE@Y1s`uL5>GF-`JlRp2wTMeuZcYy~DDf zq`b?GEE&8B*iVURRG$`fH81g#vZ}7;C4N%d(W-=Yba|0nH*^QrPvjVGxWp~Hge#_^ z6;s(bZ-X-EaC;$IHkmE*JrG_?5~Gd*5v|4?63ndAAW=pPPOeb44WnW(i-J0iM_!M> zS|Bunn@7~UOmzQGE!pKFa?QtT0gVXi-;%7|D`izy^O;I*1(_<@fV79hos*s)1LTzA z+baW@Z?C%tCOyu#*Yr3?rdHoxGqpN0ZTj|_Y10XF=g+ryBm{Hd@1_I8U_}ir@a5Cf z-SqHtfH{M?b}nW)I!x#s=0*ypOCOBw`l{1`T~EwKf;~P;D$oZ*H_gqW|Y6fvJq0=<#Fm;i5WTcDKYN~){O}%t9E1J84^}m+xuWe0#KDu zy?C%^QA5{v`;G7Rr}%DvitqNP_-=oS@AiAX>v9q#>X%}$>L*&{FO*0%F(+0rzSqn~ z1TERuAU*IjetK;5%OMz!GN~>)bq&C*Ga$x`KVsAzAfgRH7S7@t#<>=GxtBUz&$m>C z>$zuW%34^B#{p5;>o5{Ik4Q=c7f)0Pr>S;F(L?m=w7-Hr=#VwKWhKq|37}^KG3pzZ zt-u)XWRcjquoQdWji9Osi8*Cy_jV?DAmFk)11mW{rE!blvw z2a|RrtQ|hVyhII-JgXOB~oq-Z$7tdOruFni-&J&2^Vb^$v;2R|Mb3Xare#ZYe2uEAF$wDaY+tJB*I0r=o}w8b<*}|e zpgZZ4-UhK%+rKMUa(dwV$l0}ztnA9`3VIOL>Tz9pSwWXcCe~M8h*v?uy1Fx0&w2>G z#TOo0*Q`qTYA(L>#C)0(>?dMFp?f&LtI z!d##0p(c#OvLx3-&63=aCAl7ImgE7f|6$%d3`h=a<5Er!^%f*0*P*C~!&>)01W@0y z4v8MX8z$}T#0-!{@^-pbmGIvA9uAj?UBbmAtUz)Hn`g2#kqN6i%oN&*TUh!IHj($N zX77>Y3YQ_dHxDVfE)q@?M_aU+kNU`^)2(h)oz$cTb-$m1sCr*V358RUJlYZ|xmz@0 zc$CWSN)O94bg5k0>FMT-^j==s5X}5`Z;Sofs>Pe#`GEHAkn6pLnonv!p2%m)liT}& z=<*%4UrPI5rPf-}Y-;_gm|msq4e+qz@BML8Q2mpQ^tFE@o@@c><;7y?`R77a6HDl; zqa@egQt-esvOIPLlJAcqWsvArl%odDV$oQ-`^R&TnxfBvH06Uf06b$BihrRb+C_z2 z3jxK7Vx7>rfY$uMkkPTer_IDA2CgCXxUxRv3}|u44~T#VAuW@D`U;RW0K@1H0Lp)c z%q&!5Fm6H(Xoj@L+NXpnOK6h&JW$23W_)}i(_ApZ(cPfS;|3kF?haiZ&lr$3F&r2o zA)cw@F&@s92+GuE7qlKO&|@9s__E$u56j$zDOC*(H-{zlh9W7{x4^!FK~qD~}t@AYY^<%B#!jqDA#m$s7f zT7voE1xQwDZrM^@ujbOkGMBDOR(XM^a%L46))|#|o&t4{l1V^OUU^*zXp0|Jt~*}k z(4nosJOzV=zD85k*Dd4z28K1nYkW$_^aa7S;&8mZr&Rj*E=^vmc2enC+flmPEsc$8 z#n`@Hx|rKKgJ&)}3yXeZV(suzr?Q1^)Eru@+KSklFf+Xc-e`(n*|(>o>@n%DDyE^K zFR;7u8^!ZK{j!wkaigSPzhZKuRk;JZuf}gw=qgY}EE#}Ystl8>ElF0EuYp!2pCj!dTlf`aB^>#x zExA;VW6H=^ZKaHS)glQy2xjD~wvHe9sx5Ei8?g&=^%pCUOt*f*fi>(=60fCwxe32m zsa)c@LJR%qQn?~>rM{8eqszqp*+y$SoRQxKv?}4gQ3(yJuv+s$q#D=wnpER!QjM=k zHNGav_&nMGF=j)mo*Ho>G4lZ?O0HNMZHS#y-V!weqg%^}i4_SFXE zHkwp%XG#^XNvYyl#Q-!NYQ>hOR%~f%#g?8>v89QM&2ED_{csVI zRo0(4uu?l(CtBrNcTh03*kx*AMn%(5yHjd$om&eNgBQ6mILO4{nxq(9CpO|7?FeF? zMyQH|NHM>meLiy=H9^RlLD_}Z%i^?jW|ea&sc=y4(nVT zXz3kE*52$|YwWm7M2(Vl#~zX6E>x|JSRGK7s_?g?Y5QE$_NAJ(FV(btsiy5qHf?Bs z2-3?gL2|&NNl%GcX1+RL=GjU!L>(|gl>6$O%8SYPI|uG3tia`F!;s9)+Da?%M998d zlM1_Cr3=cD-7BYDI#w#TRNdp|R0%JYjd+goT5Lt~veg*}%9$v#%rbeO+Z#(o@;+B` z7;Av`;HiQ-{kk;;2Qt+rG2Z7gN-gaB5{xl2{xKiPJ67m)EKk8StX(38?l+9%4C4bX z<6_fDe>G11;tZuIM^)T{v``;)TjXeJiyTdDk)x?Cax|$$%;NHBVu&s500SG$L-M`V z3I|&FYLb-?dexIr>MzM*Z47_NHN2kb?)wde8MI7Yem3T`ilGM3rYg=vTBv_@>+)-A zU4Bii%de?*`Spal{Fe&S2%Vd1wEF_KXmvA7{t_}%rJZBi) z_(c*(y7W)fr9W2y7jf38uxoK(Jr*R@MKKC$!npM4J_Mg@KRq1owRV zFb=e^Z|6k(z3){|;_rhKhdV$>K11rskJ-fz{b-T_pZK@tVrS-``T>FTESY%%6tjDtj3Y zj6cdcWaLTweIYBic>EnpiN7zs_!}{ZqAur9db52!4ixdDh%piLwQH6My{}!N2)%R3 zIE>pFciQ7{AX9@biO~Bdr9R&z7!Q&0mu*PywVmy_(HKn63Zn_VZw;dxdf&N>Zs^@_ zJf4qOryNyLj2(kQ{g~TakEJ%(W2w#cSZZ@Uc0zMKmT0caAy;3GQAs~<-+}`ztmv8u zz3;v1N$CCk#L)Y}HQWuoA5RRumy9_dPEv~6RK>Samsj1oyqa2B5F zgx>F(RPMsnEdTzM5`KSp;a9@j7DpVW%!e4x-`P*&Kv`djJQIV;-SaUqsH`OEYDBOn z_*SuUKieB|AY)}D~1DtIlnP=_2d6^ERZsW{}MOvNE5WuGzR96uF@72OQCwMxKO~s;=vd z#DP|}@1BT9$E&8qqtEOgnDx4;d73dkX_vwF8>-~xV4g8)^Ag;01&ylWLZpSdz^zX~ zYJCb)>r;?gpMn$WQ;?|75!R=K3-Ds68xE|?%%u7Ry!uE?29ul3#APVCimI}xH$)xW zilmM6JPwRY%Dc(Pl(@{WNEIIvqu%DboRVa^IaN{|MNCejy!~e*>FGR!1LeFRvP?|Y zb?q}TS=W_}adA5t|6GHlpOd~;DKh<-#8@w-V)YV?pOEo(c7-zM0UXG5WsgJ)XB);U z)0{ajqdP8E7}r1A2iJ=rM^*F&RH&=mcB@Klx2n{3t4eLRsuS9+D$#CxAXo3iu&pOK zx8gtxgFO>g=6cnWILu3KBx87e*Kl`S%s(*(rx|nZSdA}nK^snZu|ZR)XS#KnnOc{b zsdbr|T9=t8)MaL(E>)1LpS%RgJm+N`SdYF*bt&-bA~9I#HI<3K2FX=ZLkqa)dC!GN zmN=AQ^`cJ(%SP?5m#v(N!!n0AE?6r^;1xnJU^D@>0}w@2X(_B-SUwIye#4I& zvCAAjtEk77PXgjw{K{^hgZxTIE{{BmW_T0)nFMqbNGV_H(hZ(ND!D3BRemmzpW|mX z4bK-x>B=!%fO;4|Sb_6&^SGtAH$RQF`qvgDmpei9D%Ps2)U1?OGVH#_L!-^!d_UJ; z*bOJ&SurH{O5MrRzqdq*?3?d%c=gVzT`ZgPdY>cPoz<5*<1Tdu%LUN~jL)j9qnKnU zZp=!^*p8p7$nD2?c+riA7gOWm#ngCsF*P1uJRu%ljK@ReP{`H&cOdzzGaLuD8m+Do z%T4&6l+x^#=aS{^Q;>Y(e2N2ENWL|RWl##sSRG`PeBor{Kys2kB;+F=r?lnVxc=5z zg9Fj;8A)^-++%S zxB^tdE3_l}P~Ia0kYxJ~;XpZSMV1-vs^glslk%BOND6#MaG)4cjxD8TLp@Zey$x=A zsBu7Y^A;KPRo0=4@g_TnR25$%Ez~W1X69_+OPM)a_)=!h7QU33vxV>YnX`q@JBb}R zoVDu26-x&nZw{lOD~z#xTfcp#S^ZR%-MtDlU47C4Umt`C5R91w6h)Lz1J7do*de?6 zq(dUW-40WEKDAtiE}~0)*WtiEM=e{7CTYG2aVPE}b$hno+-zE%K3jTtCrw zj4PK#KDiP;TCRla#cs}AOFYwOu7Z})%!fW!UV`{0;dBg55wL{ z{N(zVY30$e!6<10WNZAaV`z;fK&aScq(pTgx;+AAC(&b=9f}{WVIGJ4x?@0O_%H&WlKtB_pp+lT{oeUPNDLyEqR zDf&8jGDTnK6n$O1GSS!7(^vTs^)=p%WRI^c4%{iGzWn})f#y#4%*9+X-0S0IP>gAn z4a#sVLPP0Cd?h%Lmwc0wcppjOea!HVR+SUT+iob5L%v=(aEFk5*Cg@2n!@{HoOe5U zXDmhXmTv(L+}$DH2T8o2rtrQS=Y55|^M@e$)VB-=4tV5iG$2vmUs8CF#(C?MgYAt4 zNdE5o7zdtKk#A-aZ@TMe=VxhT&tIq+Ohp3Y;CG)g1=#|b^UL7I#Lqt(cf+>&Uw3Q4Op z4(>OdlpeTvAU$E`uhxRa6l0XN5%IYAT&=-4jiJ*njgrZS9wFmhyEGZ^#;MpK5M@AG zKm5vYPY^cp(qt|5`&u{vg_#62jVRA?>A04vOfzdKKJf+gT>QNI7>2F@vA*e2Bumq1 z>FfBp6QW*X>Q$+#U#q~^pQeLoOBxA!mWg?C+t-#f7RIYoD?F&uD1HZ2Um~il+M2TS z>A*{ky}M6S>Im&6pkoLd>+A`*6O=&ZM5XQr(C*76!tgfW!Dr3FEhpR3z6OlDY^o^v z3L|RFS$F^(24oV@zks0Z4Tj{6X@3%4&9T?O*3!=X%^wmgkdoM~L ze-0_`M*)S%TN-d=vqOlyr6Hc>jr>I*c2~>wHvs+`+U1@*D31i-;|0fzG$U@gRKsjthc6Z^BRtJeTBq25{Tbp%~JNUIK z`8#ku9J0A~meBX93;pVWaB{_J=zBViAvw~7C7;XzhJ`vd81DvtR_+SLJYT};YUoxL zG-CIEF^w#nh0QD%)|;WK$}B$DYoQ%IZWeC9dnHXC$@sMvOFu|ZCA=G^;xNFlK9XkE ze@D{Xhd9hFSw{>@v6IKOEU3uBCmpJP0b3Rq;2)$>eR{d{I(!!CgESW5iu5Ez(Z56w zZ@C^n7E3{Cp$}YDAEddr49goMz{hb5_cO{nB9LWdF)QBqAkCeq2h!5D8jc6C1P<|T(CYo8 z@T!m+$jS55kavb92CdJG#p8@EpQX9BSnIKvBAfLj`sgPFb|6WQ0VqVZIs=G3J_3u# z!Rdh^LvX$+qg%{RKiai7tQ?GcSS$T9IaHOcy8yb!`ekMIW&*Yfr{MiRur-^&M2IYF zj+{QlrA)xqLo@Ia1yT~2PRhzsP|h-xO*oht*m@35R4^=?z-hGi8 zg5^r}BTxq`*i#9dbw17|2xMT9_5grU61dy^vNEnN8&BU|ZoCtO5iV>kLm(9)nzIRf z0KT%#*h$h?8Ok3Lu(ckcR6$AtpHbD*-7)f!MNb0DHHPKN1Z+JD_7!9ykUbi1y#~3+ zP<&V!KUVH?Q@KhNdk`hvft}!%TxCkCRP0rhECIIGExE?yvA#l+7ecJ5>+@b+dvfM` z!I;wx;o-toEzY?@2-<7{gTPnz(NvVaY$#V<7>BJZF>ZDtC4pg}w6;#frVUvhm<+Pl z49g#j;;>Z-D^Dd0f#sl#Z9uLRJ!=Aftm_M&-LV@`G6UGvZpq7DUCVa?bHK&E=FzJP z_P2oU?Kh)jZ-2_r)mwTMN23aM$AIqZ()CTH>zklsZw=^jm##dOt~^1GS81QSFq#ZCSI3rp+{#1;)ODRNaffs1A2)|x5T3} zYN5YPu*@`E0^al*m>q=aD}&_`UZBOaGga^!d=)wg2#-)TL%%!hu?IK4+E zW}OdZ3e?qo_{KB+k)Nd8!{RH?^vCY}I4{-;tB&CC^uRp)IHBl(OemuVFPMkhHLU>I zbXD0^n{dbq$ezxFD=_iH&P)R8E)bOW^dz8DW(C}Fy)Tf{@I%MF8(Q80c-jbz;MPLO zY7>w-*qV*e0EL+Z^nH+3wgm&Q?ii4nZ1BoBY}M>g>MW3E6F30M*p}=qFgEGhI50=-~-gv1?IA z_6Be@{ngj_3;Q<%!Pze$lLJl&FlXpNrV@2vuM1mCFU5ln5Rpybc>raPU=6AV8_MS} z<+!l*%_Z19Bqf1Y0L0cIc?zn(!jIG2Ag^NOKYIoNJJ`djF|@HWeyT)X5tyH(W4~H?-B(#^(*_K53u(dFGu>uVe1>j@gYdbCNKcX z%DcGo=;3?gzAUGTOQ=TL`61KJF{5U`+h<_vZ{x9{1G3(zX1f`^py>HP1;majJPGh2 zfpIT)yWU(dJQw&JMeRPt^agms$*9cho3VJ$BFD*#Q0q&kVTFK<)~$F@qbeDnFG;K5 z9`M0@92V~nV_pizAPgZ`VqR&A`^@^#356c{xT`m(nP{21Vge+A31 zRmiJJ@+S3<0#i?c|1l#+KRT19P}s@;0@Z%}n1LxgsKGL>9Cb|@UiKtb0QzgwhM#Oz zs_{6qApw0d)-Pq}!@v3m2_5STgjatS6VTIG{J=awIw%oP3B^-TJeq)Rj(TUqrm|5p zkqa4;)6c;B`bk1Sw+BffNxo(rMS?QaHNF^6=1>U%U5sMuevB+7q*K7_0zMV$yx(Z489WJWhPUQ9?b02<)sa0Tk72t}|MvV?i_(RRr zDA@sQvno>(k`g}gree>bYyj|!+_H$_sw^J~#9aKW_fgHmPz4pAfOr>hFS^79hPYal zzYR<)1T%-hra?2Z^YU6TS}nR*1^;Z@(x(=y_7=d)3_5a_>OkySs=ZbnfRt9P9b^Ez z_P|PIPeV93K6lv3ITH=Y&JsXxG20E#1ug`RXYaDz@Lb?N$>Ieq#53N#tp@Vuu=KV; z6!2WYY&AS59)|$4)!=2h)v%r%?0L=6@yPLCREB;7Ejw&NZT+_B0;|C;C%}*(TNKX) zC^}_};<*6rMjdKQqGu&#iy~fU*hrNQ`1zK{ zTA9*h6Y9$Vskns_VV_`(Op})zaVk(H1aroqpbypujy_R{H2s$Wl29jJ`Uc4BAEuk+ zTnN-O^wxk@K{lESdX1K|3q?^BIY1hR;^;cG{!1u~+Yh{WLj~!*xcw?fDzX0)05$lD z{W=rTrgAb63dZyk`NebUvYr<+sCxOM|SpuR5`Gy)-CG*Q&C{T(WHs%6ZCz8}XbhO(dYnUH%^U{&dxC zH?0Ko-E-jTeIR*^i<6x}3STb@%%#?Af{Z;Kll@(NjZs%!_8DW~I-{;=F1FwxA(Mcj ztmzjZ;UB$mou{s>|0Q6$%`p9ZI&OfR3MK+-KcE?TF2ijegJ+*>=7h!5FmaB9jQb?Q zY38_b318eN#^JQlT%LX)$lC>QRaheZLDMN}7nD88cznoM@#cBB6%|r5324eMtJ@vW zQ>M6CAB-m~CZLxCicLjw6BHLhF<0FW8Dp!}j1Dv(n5X`O`PDsfj_?gzsTq>z74)k#q^PZ zt)Kc~Mj$1D{-BICL9!6KH?jt3pI6*or^;^t=75WR)59JYlht>D{T8ln-wUz^&y7zs zzV$X+LsyOI0Hz7}sp@9f%jKm*T^ypMfm0~0^!;tv$1e`a(!N%l+$_Yo z7AJRRq-`FOk#?MMO^c9;)G@tI#zLLHiEywz5syUUXJTS(h|>kj=oLB}3AyA(^K}&zuSb>~DZ(>x|!VvF;AT733|{_k_%P;GR%Q zEZ!61#2Syqd!#Mnv3O7D_*lFrE^nMd(qwG+}MhyOKeq-shEnlW8fDX4oR~CWJ5yP!BR-<65V5It?KVhmp56e&shIc^y9!$dg=UiJ7JNRLlm;AZ}hd zEk0{TqJPXwPwF41r?Y?PYEz*FZiU8NJRSRA_{Hi&&Km%H5MTo9u5_8_V`T@qJFz!i zdcc$H4F{q8Kw8GHdYjT7T$8Al9GFLGo%kE&c^R z&)2WHrjgx#08s9E|5qDAM0$+2vfa6Ox*_+=?&yrC}E*JH8k>&8}r zfVW8g&{SZ$hqxN_+3x{U@)4X-a~*bCd_5W)^oK<6qmQ0P3;LGu#cnlyt^l}{AQ=Bf zQK!QZzLhc%`|P8{JPV_JJ6&~O0Tb;CiS|6kX7qH-*!J1nWNpW@N37|2CR9@&f#B=L zeFn(=j#A#c5E#$IABkCWCNQ3LzfkTO*q!n%;d{zzI$#m&TS^cDekXbJ)xda$sUEG)Joo2=d+`%-^mkzX~VbZLF?aO zc}-`m8$#_}Og+*(jQ9(6b}>guQ-G-;E+>yP9m zpp=vFwB7PPS@U*so>$gfiXz>DFA0KSjmZ8dJfU045bd*@67$dnz_gO_%V)O)=Crlz zf!QvftpHmaqV}8*)D<4815ux&$LXs*R2QNapyl;$d50z#e}r+T`G~sBLpl9`n$7c@ ze|o5Tg5t2b*xaDyvwJ|+sO!%FYPxKa!cY*+>4=!oV}j4E!-$5!(0VRk<}{CYkJXtI zZA{FZYBXkAk=}|L&oMNd^5&hg9W*iND|-GfP!?%08_m4Qknjy$^K+mtQgHnM5363P zivdba&fwU`Pi)@5AU!Z1-zk%Clx^LC+qckv{)car<>A$#IRu~k6IXUDDqfGB)sPKs6pB=jsNasr=gHSnq zBTQZ?YH4C%j{Dg$lf&kLQDyN1-e0H z@|Ok5nSTee@bTRV>3};-Nl;`EgTGa%>dNuJr>#e_4Pvz2!v8s@59PlZMsmbaU3 zBd@vW29)SoYr{4l!DF#w@| zAz_Ae?nlj=BRds8XfQ95EhWZlXS>uaJK4^Z5Oj7RbtZ!3b_|h@-N(F0whz%>JKKF+ z5vtBw5U$3L?R)|)+u80zvC_`BfNm>(K@sol1vm*kk2>fLyN?^w_#!9VWtScRLFi>9 z%(6zAjAk(W3f!CE4A^DinP9TZiJ^7;bhJHq3dV14rQwTiz&rWKJ{!i+Z}$%m!OmdLp< z$R5M*mIWOeoplXB`3{7gukHW*9SHf}v7LV_sO6IoxJMme+PkQ;e80r`-|v_Fm+zPS zjnOg~&1vB+?+Dr-nI{nNMfkN6XILF{LYJbh`~8wMpd$Q!i8Hb(O9^Vfvk3zS%8EeXHd^orOV#lvQVbEz!lA?U2HUMxx*x`P> znx9Ti{&=-ra9@H(KJ%geyo>DomdA4}G9UGDKVJPVF-aeT_!^kP2g;~qnqPx`*K-FOl)=KI$2z43X> zCw&xq~5a&Wm)X+ zk$bNu*%wJ<#Hf!+Hku-`WFX*_=;!EZ=Ej^wfYU&z8*&lQZw}9Pa%DHKA&d05+{Jj7 zM>jkh8C*Bc3qq7`b`Eosc4D&^Ks^HLd_eV|hK$ef%f}g6GY(+75|7_;7%0fbXjPD; z+1U$*%=YwfjSTiqP4Zyxe!ig;%ez>e&C;FFoICO)?FEt^iw6(9)RfrMGs&K=w36EOF&@C78S z>q7Xn0SA8bVJ9aG<1D{^8+C3E^W)~u9n!^MK3^2?+(}^={C&K1;M`>#90)JKX9k=- zdz%H z?%WlP{#>I`6>!FAScKr#ofx70OOaB>kt8|wljYPWaa>M)PYws2hO;QAi1i)Z3Mpm$ zmL#VjSx$iv8wdCcJTV-6oQoiaXE07+n7l(hFl;TF53!{hen$-!HH@r-l+s7cjrTo& zVX}roA&yyFuqt~Td{F{A{U?CdhhY94fN^b%Af9B%;~U%mKlZ*mzN%ttd*+7kkJ0 zJr878r$QP=VKvH?YLuj` zjzGTJmJM-~X^5k$HAELeL%h8nPPafD9tMX1OVFKIEdlD5Tw!7w-zZ|@jc?TX06G=aw&Wg6coqT`LvW1*7Y13D+qZG1=5O5+Y|+xYV40LNFKQ>=PAUm91gc3W4zw5~kuHm?F{ zUisQ>U-@rfxnLD&GB6E{X%rqPL~`}@`S6Dwf`cF@0hb8I86_pXJ~96XG=_f?&|U zvC;UJ%6~H(O(Q()<-e8HzR@JS=H=hSs@sSUd-?Am=SF($_ZN15P88=$c6zH>HU{Rgfo^ynHNgQ>48 z*nJL#Y|Ho+5!s_%MmlAupSl;{FuUbDcM*QjinShy{oaxky6kR{XNYp86Boy}(8 z&H^k7Q4AR@eOg4sJI!k(VWvPi$)HHO4CYm3)0;hz@g#P=^D&LmPcXYPpM%R{T0Enw zsPYnfv^>+JnNrF#eWtG_dbN$gam@t0Hps9%d5EBbDp*$6lE*)xjHBCW|8?&*FHQ zPznlGRVK`w%6<=SvBik>QZZ@Oew3SD5rxa5;7*S_xeL@uERH%tJi4R}rb)UF`07=s z!DTzw%^9YAOHqY7AvlE|UArbXk*0&D4m_rCE~OVuC<_*$mr>_>SQc)Zy@b zT*{c02HdnHYd)-ruaG20XH8m&NLR|_5TCJRA!IcHJuquLcI*a#nZNR;CBC1)VHbs< zN5xt)!4FVUuMLuM8#poQM(2-a6W!SzADJ!(3*(kHW%__ zzN!kOw%179a`9C=3gE0ZYK{WNAgX&5&|)bPjGCi>xj=_k!6C@MQqHRCDBva3d4DIF z!>@wi{_dQoNBOp&e+nygv=7!x)>O{cqSHAPjOMr!<-05Xze*oJrU;5quc6p2-2w4B zUx2&okxkjs%X{okxAf|BORs)0WahBwtcK@Tu+csp|DU+G_s{s1?EkSy68HZSxAa~` z3Y<(Yxtr-ejodvCPsm~%+5dYV9#`kV`2L@4JJFn}`u?A5;Nk^u?#o6o}IoG74E=fP=LG-s<~*M0?X0pLSWOm4J#;g3iK7S5jdayV(%hmIVG0RmSFVMfCiXtW# z>R$zfFSj>L{TMEjeV?n~ufFf| zCQ5@9+wA+0Q`No?V^;0^n6UW1&jtjBta7;SO!Pi@(|?2G&O|e0Cdy6C44H|}5}(XO zH`8loqKCyRGtpwy{tPn{oei(5(Ewrp{MI5r4+Io)f2etyHUf5F;C1!`Jk*n zn{v4{HO&*VQ-P7)sO1c*wi|UdG1YdXm=~8OCc9Ca7@OPcI~hWcW&7B@?IkSzobB#b zG4n2kJmu>(5pMO#UXu+yBZHA3ed|2N{L*24WL(8H+%(|k^5!> z+H0WP$kbkdULAk}@D((Q&_K`GXQ0Lr-fQK&akIp05~=qIpaX+AW)?KH`N@fMkmcwr zXcploKF$Xw1I;5Hu?lfMGEnQt*-YUR1GSG_SPJN~`WUKw1*JCkuAHxC3DhO>z~u=0 z-l(WYWGkT`=1W*_dyaB`z7s>Dub>}#wV6}~HN*q;9A{#LZxK0@I2uwJy#3BO%|KS9 zMKTmM*+9X_DKS7(_6yrczG^YZ4De_F>ZL%rj655@!O| z*>L2oP{+I#>fB|dQ}Py(bN4HfW>6*5<2};sG?JIXoJL8q7lTU&a5m>OX7|PV#it^i zCT>i5fz)YgxSB_ro!09l9yP%9Ed@rIIPZ*O z?#-jyPFJ@ll!b!_xsPt20^;xtIBP4hONqZ`#bDhG@82h3YtS(-fIBCcDyZ#q%9kyPFG@(RXLq-y1pt9R~Sqf>kPP-FN&nmk}ao9Hb|W^ zq8W*&6Hb}SLM0c2(0i-<7+S6{oHDYdB=S}_S3x0RZ;gQ0nPJl4NavJ!l_|I^SI0c<>XcVgrwh4HyV8O)ybTVYc4a^8s`C&~^0cc{ZuC-4 zOk6MJhXtZu$RT7=5GyN&Esd)wvw5!7DJMFv7mo$*a{;0EwCgdnqL*@GS_-}JY1flM z9}@P~EO_NUWj$ZnBfbU2uk$i^BH7b zh;=GVJwuAk5F{_eIu+6`E6AU%v4Z?mI)_eqA=atj3$e~B>%m{Oe8P?6S z#7+hE!D=6}K8MfZC@(K7TjphD>ujz~7+JRT&oORqUEStnN!#fVY88U2QvU|I}M{tP$;bW|a0ZS>M@=*bo>0s^1R!L{y!GxAm- zgDd3_DY!CmPsW4L7u$_GL0r$^h?A^0!5O(IJB53c+c7-o~Fw!xJ@31q4IL^Go4 zH$oCIWSs|$)fn4q@9%^sxKg^w;7X#&gWY7Dqe>nM!daWmP;?9}yMy3L%EOJA)TN+Z zbU$Pat_* z%t(#L0Bt!B68H*oRRem0!KLzMZty&}50bVPTyBWiJ5%839?EvsYIsAERqH``#fUSw zOpG{#%SeZ8sOY?{=ssKT2Iy`Gr4WOEGG1>7-qJPjr5}_Y3{R6v6`scZBgB^R+Jn#p z9tBZ&S_I_bdTqkCC2XXMg{KiiU9yUWrwtH@nIMOd^#;>k1aCvsOACDY znPhkx(Tv186=$K6ZwFz<-KI_*L(4j41Y;i*?FG8?KvEK-Q^wCDgIJ@pBYv~Erkv&$VMh7-*t zje)c#!}$<`RcSe~>4v8n2wJ{Lq@NA)@cD2EGGSNC_rQDJJ&9T-rb^2X2t+NDL&)j` z*ZKfXTU5m=EfZa(WtW9Yj@7~h2i!S5j%(SYHCiTH(Q*k|Yj|1~VuU0CUjYNqL!CEfNZ9*vRmhaM9yrJ__%OVhG_u^xCa6CnSb3u zDy#00s74Qh8rP!((H$NJd3X;Tf*ieFHGT)wHxCONsjRvKF`gQAho1$a8p$Cf@>or< z%kl>MBHckMtL{KCJvGKzsN`WFynUBZ<1w^UqY+Hh_%i5phjEAzk_0T8AOFg}L3jK^ z(V|b>jL|vuMv%L^!ZBjh^*}_k(bYuK*hNHt$CwmJeKvuN7_}3KhQGtv!eK#A)^+Yd zf$C}6o#WKmpRMt+i$<9sif5*5pbtBNAPa^iQ9XJI5 z*oYh3wWr;O@OO1@2`4(5g|0n0b)+EJ_M*elD3jC91j5S>F=`r#E4GmMl7ui~)CCN) zk?G_#GHUz=9Q`C}N3=hCJf6-R!cPxv!W%onI~k7q^PBPk`{)3n9;^x}U^AVCsQ039 zqo*=T_gRcqbTQ_e;rk>Egbrwmtq9ygb`T}{#0Nn?g|q{NzC=$zpBO!p&;l3p5|kZ1 zhtM^GX?8kO>W7g%x{8=Rf^GU}6o?B&q;l0<_uUTgR%U|XuL(`GCj^Z(zZmh|x9poe zL|&Vris)w2oP8#xZpwGdqxX_dmqW^-=#-;xG3*)%Z}t;IK1Q)e4-ungOI~SC6n;d) z1{d)y`|zW`lW>?Sq#Tm_W{t9e*@uZw^gBjtW}=FkHb~TR6@49ANltAA%8Ol`ncGp}Snn4hS7RhtM9uG;5Os z_RY{hqN@ZmN3?%bNuJE)Z>7*0;YmW%Y$jtCqJNBTCgyGv^Qdy0kL*X^V%W1L*8Pmt zj>f4GJI2VHTUE0+NG#ToCG3UzGOSp_o9hFp zRk|FRQ^d3vY~xew0NDi%P7h@Wv2!G(g%~pqCsGe?+3~OVGm`beHwdF?C&Y@;qZz+d zf5e!9UkjWMkK|NC4?@i_$5qXB{x%@Skr6pB67H?D>!Ptgf`HSA7&=d~z)6`tjnid( zDP1HNYfdJlhZphHbUlT!TvL@I&cyW8TwwIzB2LouwE6&il{2HSp;|>!KcJBGswTik zyF($7G|vCpBm-XjD5k08tqWQJR82Ws)Ms$E$Ogi>U?Hb@g#!@i*78EKY`X&FdJBib zOP+*F*{?M6bGtCuStKqO@q=AlfZ_+cGA15*FXA#b*v;fKL&@Z|?K|XZGf&r~!zIU8 z61a9xj7US$o*FwwH8|%X*v)Fu5vxs?OBE#N^4Et1Lcv76<5;B~@ zs&ePqaLKHH0>gfZ4ErZC98itn$sWVjUxVRJ=J-MK*=2Z19e6N-m)?@V3tvG)Pi_^6 ze(^ZV`FXI3(W}TX`sNc}Ik#JnTH%)Q5d>A0Bcrr!m5Ze3V}Q`lFNe$YzfZ`|zyukB zgAAbBPGO{LF%s&%x58zF#tW*nIyf=X5HHf@jPxy=!JEFv(DxxiUy0O&cUuHUNO-v_ z(CcvTrNc-@U^CV~%!JE@ zFNu8%nfn%V=C)M&2$O=rNXKQQy@GYmr#Ijai3)|VXc6KD&lCc1CYO%eNIe~j(P4cS z{*ZFIP#gV>r+zTXpTG~@BbqZu)$t#Uv~D|`bbS~8Fv2dA1UCtS6G`AbuU*I`T4|kp zQ2)wau#Qf8$XrUyC^i4WEXcjUx}Fv)%ndlz>NuHE_ORrN^jr8t(((lI5<_0ziJ~}@ z>7Dq)hzCsMnd7Ia;9OIc%U-}7Lod)m4jplJ*l`i#-bNj*&=2AdDMk`QgaL>tsul3b%nt_mN5i#=W@TcZ$Be`a^IL5HAl#(gv) z{sP8Fexu1dxCmjKHV)!cAPWT0@$-)|dAdasK;5;9L6f*pArWW9T^>b14eIx9&FaLo zo;iov>?A|wX2Ck9a5@j=*!H;QaP0d80?b0>uJq`|@R3zF6IeO1`$9<32}9@OT2?-l zW4m8Y%q+glzEkhaMWn%|P&twLOej-)qL0v{zty}BHRyM^6Xo{#fz@}9kv{7;lYI?rcD>0sH=Ye7`to6NOE z<&?7B-2fK)&^-X0*!j%u0NeV=&DR+H_dXraSlo>F}U%rvg`YBXAQ$YD)ZzNL{wz5U`U3tIIo2 zlp^%WOehHpf!>H0qeqiNt96KTKLvnTi+wT`8jOU^RH#d%hG^30f%SF5jtTTRPgFk_ z&$wUjW3_U-ER*aFCfVVgm$R_8_@p{Tci{mdB-WK4{Q`XC>s6;&t=gWO6zsUn$gss# z&Gc4fz&0jURP%^Yja#iAmC}?xY@3hWs~*%R9kisc(wj8`$@E6&5KJwOtVWhoONilW znMahV%}*7GOKjGJkW~Wsqxufshk-N5gz>+8r`y@8)pT&&k; zq8vo~$qCsd5LOk^+psqR%za(QGT}}Zc#?!YL&ze#zTE7Nr`*U*xl#3$8~I5kDObW% zmGX^Dx#45LnM99`FNrqtlf)!SPW|;>R>*07s&t~LwYs4t?_6*VEx!T1YiK!ODN=I{ zEyInmFsuiMhL-$$GV@<$Xj#4m19-3j%MM?0H^QgaxaQbpa6V1CA-r+o6h^}jaX~|L^CPaA|gENp80?~m(;O#aw2ydII@J^?3K$KS$ zI16|{uB|6e9_k-}+}z~$WG}z&4hXdJGoT?*SA0QU_#FJv zJdFOqb6Lfs_iTiB4VV4Vo9>5Kc37?AChndHHk!F563REb!Wgx8pbrVRl{K;L?+upa zJ8uW3-5^9kBK?@i`_Mr79`ya;_UyTUE(bcg5LZ zh17H>L$Q*Gv8WWfv!S@0h#zkOqMJdiCSvKWKy){VYl)c8-m#ZK+yF%Fd@`M-IqpXv zLtrG0-rC&a!mbtfrOMi}bNO1vDcj!zb+2p{_H6Vw+K93NY|3sV=3AGhH*4%|D5R*_ zU$Xt1KvTXLDvCC9>v?O^3;^e7iHo_5G>uT=(N->|J!vjQCgXhWCCvr*CGaVgw2+B7 zp9e_Okg+^IT|hI?M&?4pxVq7L5brJUn|llHY(~sr4h;jlqV}eBmsX|+?u81{2D<=n zG)QxAG#K&-s#w~rcQ@g@-9)B7ht@?E@)uxyBfo*OF;PqFVqy>7bTfkTWd5Rc^rRi= z+KbqkM<=6<(`&MqAGi$O)Yilzb~n_Nv@$pC!Kfr@W0(d)9>hSEb_%7{T2-EazDjMV zi8imVLPLM)VZ6ErBWp3RuD1sxXBY%$fVdd3{q#gEi)?8uo}vq2>Y)o5#vboK2G%K1 zgl8QsXE6V34XmSS{{N9ig)#G4Ssh59G7XMv%$qu%pOvizB2|oe-xi-3^JZH>8e?8Q zK$B`dD_cXaG3Gr8FOIwr~z5My56q~IFr#%RH7b=*aaG3JdK zV_wST(xe$<-u;YD8{RJ&WQ=)ZV!_+R2fY7-d5am6V9eWz z@LR~3Wy^=={<_S(OOcWI>A9F8@O$wyNs#d2__>4|W?*EuV>I3M*Q3&03i)vSO2A^w z%j>ohjd`~bPB7-(L)aMe#`vkaKaWaJH0J%BurcP18Drjn9mmul1`{e(vn!ncjxlfa z5=7{|3Z1Ea7XJUSx$Yl_Dlz621M6{vM6Wd6wJ#9^YlF#1H0Gt9b&U2q{=(c$W`y&GxqgeYB0~w=O`?JHs#TdofU$w<(=PNKqvG(^y zMaC%B{-IRDXcTMzd}fGrG>R>tGN>UjinWbVtUc*!Op2)t8pYbD8ORvL+LH}rjAHF6 z*9%)?6l+g4%AiSTbMVY`jbizQW12CFqgdM*#oA|j zqHz1zp6!YvMzQu>lejU8wdWa#MzKu5Dgi4oinWbVtbLb}&KSkocb_k5!YGy=&nVV5 zMzMCIS42g|DAsOl9^o=Zv33(TrWnQAO$}FL6l=Gh$hk!UHNf;^{LIETl~TK#`PS3$ zivVWj_8PdJnXD~lvUU-PsTQIHrAjad}5_lhtX$Qj-J`D~5{&h_s*24Su zNtip^#?&pnc2{CpA86iVcikfpw{w^< z>;Rd^pWzkDTH9FG+GRvD689(UGM9x)ZWyVutUZR7yD)Yc*-{d*tZfc@+!6*9F3rJY ze+H{anOKn8am(5mM-IE|Xb^;F!68URh|LKiTnC(3*4oCh)-JDB0xslQ*4{`i55lph zn6F%1bshvtENg9JS!QBB0+zM4Ceh>HzVe>s;j9>pbec!L5sONqU_!dwxegxrOJd%zein4MF@ zG4y9eaKxb5IW?6A&CWR1%q*S+I}x{ zZ5uOb`|&ow#Lc8RO%^k0dq;obk1>ZOo+Ykt_#lox9xjDQ2Q)%%trK>Vs_+x27PT#d)8YNjt_& z+Busg$;dR5cFr+loiUSk7O`d^vY1Ibi&^rCAS_x=i_xmz+&t>v=#BnXO9YAiZot^@1`5pV%GmD)3QgWI_vr8O z03r8Z1NmZ)jpB*rKZ~(y;0O?eXTc%37F8}`(6(*^{-WnG5(bCZyfi5|lo({no-uBr z3J&8Y6;>zq^hsx^pxCyUvLjRLH8@x9M;iVkVuO(c_%+JA%?mK8^8|B?9uaYUj}A?t2Nx&_FqK7_~rt&B+iZ;56kj@15d zT^9Hh4TS5!ohG8k&~ijFd8MXeJ3#0E_HD!nNdhtE)c-!EtjT;H@4`xp*&YW;g8r@M ze#D2@`i&%VKjI?>(&m1|M?aIy_@s>d+e{IlVo+gSo+Fbd43q8Lj9_+z$qoa#Om
      `?-BHbOyhKTW5`O--_P7q z+TZIq<(AR`-Xb;j^+7bm^7#_88(eEAoR;~hrp_-$x?ihF_nRl(JWgAFH$@!Gd7&{N zrHw%Ne)&31P<;AD;d>6;d{X8!Gx_Z4tlxkWbBXw6Z4XE%i*P@-y$US$)rHOB)n|W* z-WrWo>-y~4{Tqp`&+nA|8{5FE@)?@X-5K|&K1{poQ_$+!(KnFQSw!WZh;;KQp}Q%S zPkrSx>n@_a@<8T|E%Iea$)PdZ@w>_&3dIRtfA<`3Iy58)xAmOIQm zBcftHR^eUOOA3AA#$JYfN>UmTv6|wgDr4VbXiZ9e7Fc($B%K(w69|j@pYu^EGM%@K z90#h&@pd&i-XS~Aa9CNLgRUHrj~YOXcMX&h$>S{fJp*N^*lJFL|JE7F!0w!a?S__< z(uj!NhJGq3bv(SDV8p0V44eA`I<4)Yn=s~h*hA9#m#W1i00he-Gv zuN%)IaP?D(b)zNJf|3Bfz+zO7&5v<5D_k}!s@S9;57pT`BW!8_Utlq6(*}@Er@Ra2 zo6B%P+2yo|Xht*9P%{R>aH$y&_(Mf+A_Ka-*#?k?ikmW4d9%)>D`_rt6U3Y}e82Pr zl@p6N(F{MpRtKw^;?I!o?Z|C-oWADbq#)DMLreJOes~Kx`zs$<(!A%(Aef-Z!H+Aa zS}@Q064+H-niOm~XRZp*)+?Fy%Da}d91n1=9Ig5*H!W#(%4?#)eJp1x^9STGogQ@w zV)&>8YOVR+142jr@)`2hkD-1KLK1WFYct06z$jC*b!Ol;D~B&41{8fI@+M*ns&D`# zIv;rusg}D^U2LSfz?EvHE7b}em+BHkHB#;Kq+%f$sa9wfm%s9t#UjBRX3YevHzm)N zb4z&XXZS5fb_QK(4aQkVaVeVZ3MQ{LnVqtV3_FZ`4;Y_jKh6T~D0RcHC57P~B?U`M z66GBw30w54%UjM@;eeJDz<$V;)(Ih$-EeRogJ0==aK6FMcjYtK@j%jP^yo-O5c$}r zcZH`VL{8T9@uI-8(|FfB#}Awce~KvEUxaLRH6`77p-B7KTY{lJan>I$(CmF%&Qjq*Ny%3^r1|L)t-|%Sbefgrt#Tk| zxP^&!$sSy=1xeEB(PP25^k+!33DUGg8)_lk^l->~B?ghv`w_E~rmQs z&b zVqC46HMKXAb(#Xr>L<~zxSY`cxFRX&T**pdMxzECja-BK_MI@9x&H$c`B|i`04d2` z(r}KDn!cd(`01ys@Hy0m9@v=%vf;(Tzr1J2EUP^VD60X%YspK*hT%l-^$!7##<%uSp0!hcnWIn8s<4j*=m!i_KZ1q&I z9xfsbLn`C&Yr*TJcfj)reqGnH$7#bPREwri)#pG?u7u&C1ax8m8(i0Z<3ZP%m8I(^ z`{C^+E%}?5P)dlEPLF13lr}8y%*-VN&5^?y36I%l^iP-+mh&>vCL=}{j*^*-v7TJvUA)Ng!NmAMAyzxcH& za6R6bar{{oRhR*Z`a)lSGOH4)+*uWc`5-P;69^zuu@Jmj6^koAtD24^D)DQx!1Yu~ zb-Y>C^^oR1{8YQkA>TzD8n?DUuM}O)5;gNzZ&q~yC{BG36pygqBGpl|s?UM45K*=N z5TyDkkjkuz%zRf>G5ptNRaZ1by?YuwaqB0T%U`GRR^34@GD&a=VAPO z2T=zmBIz`GbYuqW1)Kd`c+9MdzGG%p-O!9zu>-EFDe1~Cu-WozfkU<_t)4)U4_gP`&>QVs_G$b>+2`_rEc#x)=#~vnqCS*DzIj z)K$zK`#APye=@6LcNm{l{S9(hkfY6Kt_QQKGtlp>c^gUf(G-!Lf+yy`FsoXEvBH~G zeg6uK)4@HR9{skc3MmXl3dfsOJͯvhBz4I&+X8s&DjoyIjKM@TIL^S$fw87zLs z9r)WdQR>GxAe9XK^+85*Z#e$H8u&Yd(MkBVxdhHl_^B?N*qUYFXAjQQyp;am4E#Ar zr6GPTo<%lSz_S^@Y6E{ERP_LmMeF`>;7>&vxdZ>(sCX7)rPHHX7^R=P45|1O>B0uNm|zXO(!%Obrb)WN z$H3@eGB45%kDh-WMEp#a!t03Bm5lG)D9p1jB7#BOqA2_TP&c!@ zZN{BE-JLsmzRCri=PKQk=TUla>3&3CkLYa*;G94Yoq_ma^d?Qao564BlOP_$Waiz> zq)O!B?^7A1hnbX4HS4}v%?6@|=u?{`L-?MyYX_`Q^i?uie)K#ZBS4IFderUkmF9ul z6#SreeU;3&2DfPdcpQF6pQoN~i->JUZj;iuht%#zME#k3H&U8=@k1Rvn<8#>H(@@a z3^$Ta4{DZ<-c8>miYQn4zXDlc`HR4w8!_$L!}kwr@*Xm3eTy*TM_T$G2I+w&ulJM@ z7^L!fzLw9k#MpGml9Wbo`!xvch1tE{&h|Y6E!|b z7Hy^?!n^pX?%SBsVN7lH+vHO7R*KY3K4d#c_SnwAg5x#j_bUeeA_PVOUnMHwYtnfN z_{Nk^N-XC^h@EO7D4kx_8NS#V7$uX^sP7)dfIr065dp1x_5!Fn&r$j(K@2t;boco3 z$)?u|IIEupbyQP6%Cq7&3f)1nAJqx@?cs02_Y}s}X*%#Jsw}@_0#46- z22Nv5M%#p0nP{M?B%ykLNSe3z!fB})-sN^FIM(w>9SKBP^DsHKb`ET;TK^1s*Ip=t z82l6Kpl^Y<+LS2uN(b!ZC!0%olBdzU2+LZr4)P!zFK#RcuU1qlaae}v4Ou_U*0 zS*YZ{13hM@ITk#ImS-$RFgX@n0lMT?-yjBFOM~lM-W%TLacu+%^MG-Q4@j#eobN_b zh8YotB+u|RU}NnsAXo;1@K87enPWNR6$UECXHb*pjYVk4B4O`ZEl@&Vya#8fW)ao7 zlf~3h>iq~UHELL^Cs_WcXwv##!4z-hhU~%j)L@WK53UkGf3p=dU*p#jZSXH^t47Ul;`8VinaklT=QPj6D55Xc94xW-)x13v zsV~v&OYx0raY-v=_649W)3vr@QxHG&M>0rUrcEc=K}Lzo^;wWumv@k1qEb303|!6c z=J2`NR8c&n-Jw0E0+?m#FCM@e?m-duUpW#OT@$zMU;^RKAbe|#jc=@qFKG8{|UB5FE4>N!*aA8QEfg12~Ot%)yQ2i%_& zoP}STk*>#^nje4h%8GFkBsv#)_>;w}NaZeGDa?krRH+a^q+-?b7O$*?@x|+nNMbjB zZSHnGRZ<;q@%jp+`4~Udu0K@0n5y1-I@)uOyQ(zpEnd5W;!SiNI1&H_sg7E_HbkT{ z{8ammAXWQ7DvMV#YkzkY!+&k@dNTG)Ct*&3#VeT&yN3+D#Vh-yf5+l=FgTCIuk>y> zU*P9^6dhe2l1`&XM~1LournJ4k6FCZcg*7TcSLy{-4zzEl=Sh*M!Q-v7?xm2ur80e0O( zz%QL1bq;gKo|}F2pDbS4$;TJ3nUJ9)er*a|4;HUY(d}$Ow}ZtiMP#SoiTN)qUYBFe z=q+Byf@=ue)9KN>L{&)PBBXG<#jAxbuQq&k6!-_v~XF~{`e3+H{-%wW?hKMpxk1 zW`2#w%TdePt=0CkpTmU5UDp1v3m1GKRysYJ<8WznL?(mk%i0W-0yFHK}_Qd!tyWNeSLB;qjyFH!X^u+iryS+dmZ!vz$Za3trH^y(- z?VkMVBxc?%;<-?)05gily6%U--*Vf$Xvl8l`EyQ0@ToaI7%nPC#noRhdE37Y z-xT-f7sP>K4RV3j{X4yfL)YE|kVycg*J8%JkTYg{lsgPKyn2*{X_W4niMKPMvigtU zfw)%f+ZGR2B~xb3m{c-(>KT(~PM=sZaq678C6gyiC~95YqPRs7)>U%|mdu|rak@Hj zz|h>TgL7LJw`g13Lg}T;kP)Byhj3mC&PyIk3N`}g9v>m$ijR>Wsyi2}Cu=`s@ruHK z$=?wk^oKq{Xuux?wH5GRMx^7v^bnA?HT8_SutxTG1e2ic_k$!D@HGXAf0c0Ri~zg? zQiMPL%2TR%`_92jQ~oQ@BIau0Xm5jmX`r4{AISyk65`Qf0AsM~iC+)}tm-M>AtW5& zMLx<`gycef(FU;K01sGw!qG`gMn!6ARA*o8t;vXqT4tW?C;*SQxd`+AchiLNHkJ_fR!rx@j=+MwhT z%-$?f1{=QR)%Xr{`I;z$;!%D>lnmb(6J|c9dtd zfl`!R0}ElxH^JFXqVdc+6>E0{I_R6`yhQYrv)sI_p!8GSyr|gaAe!qtJ-H1E&{s+* z`A5=sF9e(96%?W`HJ4H`d#>^grhbwuNic@_PM$(ZCNMwATghP>Wl@0*aG8XZX^u)g z1b7u0}*?`H|ybVR8f% z!CdU`sN|c#D45?A0XSQPYpO{Sy-89VZ~-%-hAhTST?pq^#JD(^ZPAjJt z{yMGQQgOaO4jni5mh&^ReXNjhmN zHP3>T4>*SHVNO%XW)EM=$f&YC7-!3a^@PqM0gL&BLx9d^sX<%L zIn?Ai6a=3!I$ttuk*N^Voi_+ArlkIYPjO3$Rf}XhDBco!Qy+k{4j}HFb-u)3UFsG6 zMnu(}>WktnRinbe2L_NrPt@$IM?T8&w5A_v>j_fsmBE^O(V6QBQk@6angzRhJ%QYG zdFG{LJ&AO-e=J6&On%U!Pm|DLnX)rCnJM5t$IKU)@DvfFa(ZSLrZ80qhiC2~n`r_J z&O8sQ(x+2EJ*@U`1g1{{3uN*lo9jX99y%o$pChho~PkMI}))j9hwXUD*u$kw`qwj9edaC7gH|n4bg~ zhQj#>ZM%UEpkbuKp)#ae*($X+;FZYe4dMFEUWgZN!qnI>ejwCT6kL$$jE0P1x3%Y> z0fJ+=XfPrNCcq(A;fR6hLiqLT2-gj@rkLd-YAy|BbOTL>FeJ-+l4Kp3^I|PXl5srN zL-YTET|``G_Z&#D|4|^BEb(F%iYH`|LH(0L*bJ%90Tz}c!yNz(43IgSrPr7$wEYuN z?tw_q44(}+eEuF#nf{co9tGzUxTgmK8W?`~+ty6k*--S-iF15s0~%Q=|3^G@5knShy#_+CR?U-1@T zoIdFI_X1q)D-P5JAAdx$iMkTlK`>RX0~vaWz_$d`Tre2myUhM{7mNhf63lSHl)zF4(1Z%orX5d}2s^x+?fesAKbiv%fodmO7urP25IcK|Iqrg;xIWE{NaDc>h z^(q;^ng?Da=Ujc6fUN_c5;O(pD`+3MiNvP1;vuQP2!f6DS(3pnfu01LX)|i{2v|(0 zNcWS_UV;5&RjlP{#DWt8du{{RQr{v8^$tAS8}q#rG;1Nc=)io&?W(Cr;tLM>y{H66IsbN3MZGY+oRf9!G+*p_->dWUub;*9*;QwV(Z;NvgRN4Vk{l!+I8Hpd}#9651^&|v$eoGdAvDKsHp^;CMZT!X7O`s16dwH?-A%NbCtwkul zKYFoM)K{P*!$Rarg`;zf_>s8J?UaI%W(kn@Vk^_Ada>2*7_k;f!bTdBbPK|Lp|v+L zygI@P#FoRai=kPaK|)p~Rw>lgWEdb;OWJp zx&Kt~|KBV4H|Q)_8|Be~0VwnsE1^oc2^Ga(qZ}b2i{ZYSKvck!n!@Yf{54OPAYv?5 z$=48^;m?em@GvTUHsi4$NVWmhB`I6sI)2`jXP{u@AkNhMg$9a5_7(tYXrL68vYp8{ zc?l6i)_%BYXTq`k7#K!=ie5@*M8-UdCRd9TOo$(0>r93tA;fu$OV(~U#e{%_QV|Ab)j79NkreG4Q{fs4- z`Y~4E3HCL$X3miOudRcRx|8g39tP!V;y1Y zJ$06->_lc>WgkYsL->*IWueV^lC*=5(|e|vE!`mcK)3g-vy|1@Z0XhmI@}r#LH?~< zz3)t6E%s-!uBFVPBsC~*y)!9lwn%RKpTVYTy{8$N<6`yzlfr6g>Q@SHO4LP^y&kVe z)UBlqZU4)RSw^}xE@mHNvKnfsPpUDxYoB@{7d1{7<>0&XUFf>eeM{F}@AE(Hx@)oP zuJxa;8~XcSFgK}-Wh}d9_v*bU@8t7$l(~tyo=-iddiD7{-J;6Zq+^^y9 z{&!;N#a8`eIJfwbFg-!bCztD?-6Yx}yq{LJa#&C85{7=m<(iuQBg>t-(0K0+F?gb|G9Nzy}R8KLi*pE`UFQR(|GB5wqjiyeJM{-d^OQ}D`VxrfG%1L5YzKN_ z#9*r)Lid7m?f2BcFGh90R8yS`L3K3>a8VCg(1T;LCGab@LH&zS-7l8{6Ib0Yd{Lg0 zoeZKG(Ni5GhAf_1TD#y>Kuilfoky zTEBWWRrgE$|NoSi;Qyz{scIhn3L5t7aZq-e_-&Svyn?O+dLhx~@<%~$Lp#+;`ZA*F zcfx|^^QO9nz7=TisnaXaK^ zGf7@UUUlx9Br#)Oj2N|-VZ13p=Y7sFdNJxn;kUzp&8QY5tbQXcZz9o!Sq!7s3Row> zeVZ8_ziR9LY@ZO0+vk*y? zRmKd(mF2Ne$te+~mV>(}>u6e0RvFpKX4ods)dqb?*jpXp9gVCq4XGPthoL~Ep`tCQ z#Il|s2#wGxR;FqGiMEc;b?#hA@R;w@>)7>uzGGtAI zYdrzyb%X|WPq}SI_aY-^jTd<66G_VP!+HxIvrO)3mdQP@HiTHZqyEZ`HQL-*qx*B( z7Uwa*K;TgqgoZ~y!=oR$ieQT%gC5ct1R;xzt>N%G7;A!hgnSdON3zL+)?RoP4v`E1 zp0ndTM;M+XN`N6x>w0*u!;~PX$CwH;h7)G87}~8lK0GlHD$FLN!^i5w55XZo7H)-k z58h-<&A`M|m@&kFiJ6;>`A8sE7;?aqt#GXxQJCDzWMqt~Fk^^jB$vVX_F!EavO!~Aj@e1=DrgeJEd=P{$ghP-yax09l zJ0==yfcJKw3Cry9N+5loeWuiXjQT7b0<%yL6K9z3U?k8B_8~N6kxEmJ+^vo9<;c`(nW+WKTs@gu;6kVc-(fVm1H@rIl1_lp-CFPw zP>&lXrWPzCCSD7ceJT)Z0Xe`p1Fn^ghB;UI*kz^`EF(Hz3p^Go`9u)@0`5`^j;57b zu#9Y_78GEFC$ZP!&&gx0DciNxh6ESFOTsUJNUvQ9@-VNeCdf&HTe?q@ja0t1rgYa5 z6EEGh&k4lRB?mlq1lKwOClf8p(rZoWt|dBNx*iLaTt5vqhF`d)do-<-t_a3KA^INZ z^xEc#5t0O~3V2VFNx?dk!*$hi=t9Wh<1ET`(?A~P1Be7U0djMAD^O9HGORN>Tt`ei zhwJz#J)0;-1^BQn4A(jUXAU%F>2)TD>xho$&|{&J1L;Z~`qIte(X^675lnK}6sJLY zT^eHG$}6TqTgQFSV^FU*Ib2^Yhc1L1{*}Gj`hFk}SHL02nVOr!l|WsJMhiA3hwF)n z=WzX{0x^f=5VA7iT93iGLsmZPO%B%+9nYc1LM49!^k#6E7J4+Tvz5(fAM{<^ zpvdO^koq3ZD^-+?^v0jS-I@WureT=dHw_xnE9-s)$pwtsT)?OwW}3{HOt>B~khwci zKWZji<^o2&&8Qy@?}a%3t)}5^Ws1T-4ShtH=a?mPH>2LpoW%L>Fp$fCXEpx2;{1!i z#K`}I;r|3v6#lajB-b`-b8VyEP4&e2KVu+w!uYH^VKf8BbA~@Aj1PgybFXq9WUg)0 zFH*5_CNCMtW%6=0Ca=Vq`~oI&ZKF2VHtPK>k~ovs3}kLx)UO*R=GsR6hGBwh8(X1& zlxrKcxwa9XU?xiPj)7bz2VEvAYbm?cL+EDo`%-ZZQU6kLKBlHj#rcG4G!^GC)t1eR zMfGRQys0=}FbgV5M*4k9V)23bEBCYX%)O`jh>_Ht7`YIdT+6o*=g1Qv5ATITkbg~+ z3rV&tT}zp(O7#)b@Qx5e1@W6ieIy_d8y@+^`eS~O6k_nQ>LM4v} z;kwt{hIcfrG&~Vc8Xm7I)kkI^20AdfIqTtc{)YLC={o&5=Zm=q=&FuP0X@)CInRT3 z_Vnh?C*Hw&*DF@t~v`nQ|e2W|+dR@s`Of!INBx`Z5 zsva-FdI;i4r*bU0*kyt>t!pvSXf@8OW6Hdk0t zUPh_QKLHvCbeO+KKSgXijfiL`=tG}s*Jc z1(O&ymDfrkslPL+SrEVAI*#S1yXa4VE~sFSd)W*__$djwZ<%o(5G*E>F-H{~Liy@7 zR~fo5NjDq*XrwLBf4v3Xkj0KQdKUQEX+%V6kFURFrH`H=Qqx;F3}phloXe5B4-B`Z zo#2HMY;6TUAVf7a%HDwp%&!=P0M;K%4L<7 zWm1&Wb}h5;C}-bVCezXTNqd1z8+#erS;S7gQDzf^$YBS zqUroPkwk#;+PAb21Rq4S`3l!_18zel-@g#HXIkXJtPThh^LM z!1xIVW^!2e5hDG^kS7Hi`i~(GpL>z}%H^<(>w@^vksOwp4NAGeoaPMfjpi|~J(Mi} zxy?75AqfXz%Lt^N9?u9?+y(*d* zF=F8(CvD#_B;lmZkG{h_X_Ip*f4v-H63(e=0G30zVg{IvNI8VFx_2SQ9Ky+Fr9XFM z6^+@f9K_f>mz&Ozgaf*B2q!#)bunRcKqs4<{=9X>xSN|ie!2&6_-Q!aSyUQFk%Y4- z|CCn{8nQ?zCu{G)lX$Y`Z+WB&BPVNLla!khY3Rj|*`!DUQZ^|X!xQcb$J?YxNZOhP zyzEK%&7Oq6+Ma~}EQXr}57{`Y;2iHJ^XS9BAvY7QN3gdeObq_XLUuLq(H6gh6c7(ZogC@ zSuDX9va;Y>kHNVVeXoT`GPAjzXhxEWjmH9uC7?%vyUc5jrj=RE?G#LQK|jFu@Yeva zRDx^qbnIbhh-om>+RL5tJ@PB2R|pQbfJ1=!$&fiqOx4%`q+ZJy94GRgq~%OaF@2pR zLFKjZ-twedNHyGdF=9`KH=Q1xbO*dX8{Yfi$&@{-sr33PM`X^zR|?#T(t|VSW7ffn zpa-hj>`ZD)tuO}`;io}Q7IC3;lB&@bor@mGDnNnGOAzY3DxuCJ6)qz1ZGb9%1)Fqw zbkYe#*FfZM@EEC9(2H9MDAmdpaj90Z?oleKgRVfsLCVPjI7|D?0gz-JBO9P%e7lfxuR5|YVx zlbN8Le3C&|*(kWW^zA*sFnzsCxnADd4I01zXI`fIfZRt zgk_JOwVS+pvc)wcpG6703XCKw>j-J0Os@sQpAs6AL=%R&g+bP>s`QZ6gwxhJjMkn} z{$`>fUrkNEg3MP($yXMiHqoz8A)QH=zgukPBp1b!i(w`gT_qQTnN&APDn~zsdZ>Fd zMq7!MwVu2-6WgDdp$WW-80OwyYDz2XcT)Fd%0o!`tWZmzONCdv+H^ypwMqW^(>^TaDtK9abbUVaoOpJ3cW zN%Uaf6wrLdc=YICE70VghSXN#mx;TG?mf)5HxSv7>8#sbk&N7{szlJME?LtNrthOJ z9-`P^C5YZyL?2jd;#BlQtw{*c(KDd3W$~0rzsnr&V3bF(;Bp60ry--^j_8_vW5{VJ z=TVhoRc%h&a`bnM^A_p3NYg|AORM)ckiv1cA-(`QY@wUuHU$5gAw6#M9_4Y9e*x!f z`AJmn#6}>(YB7VWMKtl>`x``ad6wD9qY+LO1^#3^EVj?;2#%bKEs%>Lz1E?>7`N z!m`Fp(X&yTbd3j41=&XaCha6ef66MEH3VVASg3yZutZmqHuq(O5yMLP2W{#Z^v`aa zN?nTN+^xNLfewEQhi!^~Wo18f zUt7OcORC@$!uVny7@r^BE8z)mVmJVfb*aMKhQ%U~JUP-y!fDFuZ)u|`xG~a*`3)3SJ0P#Yw_QPNsw}lFegMl<#B#uc zu+*kKt8BZ_qit&zBGy84K}18eZ>Iwa+<7$! zl+_4>>_U9j6SVS7hV!ar*oBbc_5rP0fH>R(4gnUjySFd{sMie>lleSi;+fBzBM|o% z$RT7=ChJCcA3!E7E6?OMkLY-AJr*kYMG*c9?vmT1X(hLLWNS<%@csJhk_OpZKf-y> zO@pQqmX|vfyBS%q^88rkg|p!hWR9dVGby|d%m+aW5$3%Nx&qAYc4fqvnv_ONTfo*i za9BH2^rQC7({VAqTR9_7pgY!&Fb-`f__T_ClrtEbw`FVuS|=lA-I9IoHGA3f*WldI zn#(YJxvy%IsyGleoOx5HXHS+?*+(yPPQgSk_|9TbU7a8oX>azNx?dTUT zBBuOG3l|e-Gr5CnQdR)QauZ;!yKHAi3y#)x4;Yt>&u|t(spA(`PE(EQo5ZsPbD> z>>;*i{aZv-{+rv0sWACa_ta_w8B17{swTZPxxLcR3c#&N7T)rkil81C$BaMzcvz3) zgdMy7ajzm92V!@w)@Ui1xmS@b1Uh^P9M0AFR}!h3t2Iu=S)-LDwbu5x#$2s&U9>B! z9tTp)-mb-IVr&!ywDNZ$cF1Bc))>_v-$)VxlJ<=BJjaqoZloI!sd2YQ!MKb~1~jFl znY|5|E-t2wn66uZ>F#1W5%VTF_i{0viRttnXnMPtF2uA!W3u|Vn6AWhq<|;6m~O;; zPd@!!Om||&Tm?Sz@gwBvLCoIUfEn!4^d#n89M4+A++6e~=D~-7IfdglVwDp!_%UF{ zuu1?k0+=SH?Dfa;Zj;a01Ka-5z&0gClRl^p)&$;k;s%W+ixw1avYYTkVA7i=nUUI* zj$bwY2(8(gS_U-uO#(^HEchGu>4n6naZCn!D$q?HxfhsO?{305g-Lumv8S@-*Zu%% zS!!5pK#??MHkw?_z9Y*Yjt6Z*P?Nb3NoQ|Hm>c0ZOLrv+kY?+qJ{EXd6AEEFsn>{pk{-20wGGQH-L&;Qya182Qa-@z=SMPMsIr_yX2{Jt0KuGk!l9Rc%8qUMq=k) zw56vDQB9rNfe7lO3M_97DA2bx>Q>+{Fr)JarsRQlpkZ4?3cQX5@Bd-%J)o>AvbNz< z_td%P-sbl0oO7UQ8fa1zB?^j)LPL`Tr6o5?Fo2n$jyWRcFp3c!6~`PH1DJCTV;FTr zbTH0fKxg!So?Ufrz?pHr^?z%9>z!8?x4QPOUAwAwg;P~~S5??Qw*iFyD8!5SC!qaC z{T-DUp#9s*F~Rk(?FQ3W|Li_63HQ5zChl)XtSo;MxMlkX0H5RM_rQAF9}D_C{{pn( zeE)J7XcYK^d*RFCXCPLQUsQ#el>ZExd5Pc9i0wE348$t)KS%22egX1X;m-wSrN16I ztn#DCNwvSOujADC+k0a!;U54@oxcU^je7s0TF2?^ABCJW_`d;t7yohOq|tvJDR%Y0 zKw3@yM&zNJ-ww{*{Vzb@!~Z=}Z+1dski~l;Dwm#+C-dAV33I|5@#1{%K0Nk=BthB*t}^^C2dsaz|~XWq`zs;n=&}HH*eaLb@EMnvP!;bZ^B$h zuL6^oQB9G=3&m_AU?NMg@C*ZCWx_{^PXTcTm2(7`6T33u$?|IvoAxDmb9>Kt~;RI{&R6Y0yz+YF7 zR+xCPn3clp%k%WlGaQQ%`(iO!BZKzEVk6X;eX;msq0B~}nP3#(T-5(v=uF{Pb_jx5 z(2ba}i)mrvN%hoXZt0<*F60?FM-7KJd;y$)X2uZWdGad|n0lVvAN+e_%z1J-Gv}7^ia1MC z$WwIAPn&@e6PI@xlw#uIkNA?9l*8t3MHICZ7(qOMamon+A&1S&8IodS)15HtJZWRI zTauzE_0-)kvf$=TI|)*Dah4J`Yj0~Mb4rq;n5VgqV^o^AT*819JC_>?r`WmNNBA(v zKccOj%QM6nI~UCsC&tu?*X${GHUfG6{XPQ)ui3AVu;4ZOpuKChRhrEuU$d9%_yQ&m z8z^|qK8?xd1QWJ$F^f*TW>1MHa`J?Mj778iq+t@gW^b6lESmj8%%T&o*;DihCeItl zGI=45$%_dl>{((Kop{Zj!cQ=H%|O9x_J&FDn!RBHv*2k@fry(^&9|h4$*Jb+fvEfo95s%Mp+bt5YnI3H zQ&0;U7<3(P2gdT$AzSj(rV_1>dNj7G(YPc?bzBZsnes;HZDFzAtA{S_;C(oI!eNAs-sguf!W)!iVqsw*7$8Bs=4abn-?a~R53pPG$`Ol1X z+X#DLbr*Zwrel!SJ%5q(B8a2+u-$g!q{GJ$T7=)fK3elvro?N>wBKhnSX%vi6q{ff zoL+KImw)?mhdH^YE0^@R9TZu75qs!<{KCpv6L&kCS)9`wGh1olBM*8Cn=f`0mtpU) z!O7*9J`dxsE3-6(>z@Li@n%&8H24NxRdc@c25UfG> zM(OyI-MQ_VzqmX1tAd}ca}y-_zrf}tJPDsU*+FxE-9h_>9kl%+s?;5{#e`FK(A=@S zQQ1;t*&Q@$|78cw9d|iH%?_IW1b*2tb0@^UT>?X$iM$w>%NtH|+%|FwHq6{fj2Ud0 zxsy$pi-8EEsXJ{u0&y_~T)WlkVF0j02Q~iP zNl}&i8;l>S>?XKW_$!sibaP+js9iB6fz6*rvd&kJbexMx=DDjersXlG`HwKDasF9} zpx+=UUlBXt$y2auH4#o>1eOGw2OQ7V<3pm==@`$>OC8TfW6=EtgQaq68_Ju(iHpMU z0(gGC@L7okMo4j(W2@snXX2>YfAxjW`bcy%F@SN60gM}%h{!f`09gZ=<3OCj6JRue zxdeaB-enfIVevi-L-dny#2Ch{ku7Jph8RkfTh4Bcx#O0*1muPr`xuGFN5&YY!x+PK z5FJ#7?yxMJ%qDc2gfYy{v|e zbg;9k$+^5r+bfdriMhN=+be1#@q|3}DCw(Tpc_98ZaC*_@XDvxnFgBpn?&X^nSv_7 zhXN#^RADAgT_(2j`%DgO$$oo0u+gCZ@b^4~3` zSE+L9{oN{N5&&d}E0#@Zog%1U@xo~jj)Pxf9Q@=PTk>xPQf|qA8lI?T9JwX`{S@NFE%~x% z%*TUAV||V*?Zr?ngclSL$*O|_DE*fFMo?tz0*ANcGY#{ma&SxjK?q5|C7&3ul%5(= zhX}-;N=8xr1vuy{;Z0Z363s|v(6lU^%x6f5bg3Ll+>#&AvZsa=*~*bP56i7rB@MEd zTk=1IC%7elI_m%5-I6cjOWcxAfm6R@Zpo*Bxhylc|Z^<`dI9$uSJ?9`v zdykLY?BkxxOJpr3>-bUNioFsPZPjw%vwifMFD^tY)t!{TsJ8u=d3{z{@rL^ zuHX4I$j_g!A9|nPaVk24f8;?_y`DJ&)#|Um2r~A!9E&RRt4=~)`5#_D)ob>6s$Rz| zLTB<1oKMy348+RzcZcmrj+4WOE#$sV_dmR^leek3>qa43?m2J>M%;CIR5@L<8HhZp zoURL@lje!aY5hogMdftk3i09$ihI*T^oq*q7EVc={Cg1hKUd>0r2?bIVJ<{l^Ey1K z+8S>#=Y{Fo8s^K=6c}yI4~$MFO(BC)v^Cxcj)Upi8kWV<6pFTHFc6}xnZ%G3Z4C#` zbZrd_Zz-};wKa#61(h@xk|0G}b3NfSZ4HHHDT=7A;kYQ;nwJ=mqOJLWaEi9(uY?c7 zGC85Gq0j?uO$+>Tuas-$Z#Ykji}_pHv2p5RgBdc9iO(l&C<^7+ zIFHj7p9e=>jjw^~%g@-Y@+m9f`{Usv37hDYGTE|+K{%FlgGlpDl1>d`P;eTtly~RK z@#yE_Nk1OVy#b3UqHXf~B;^?TJp;^OTCV0Ykx@)w!KeJL77u`c)F;I5L(J6AiLKy* zB3v$EtxoBgl+3J&jA7jF;~b!$iS6|!HgujF#deG; zJ8d?iJa3>#Z1)*}UNBI0>sgK$H2-D9#@{b!TSUa`TKg7PB+wZx8L z3ZEEgVC=LZfIcfJV7wt7wMY7^xdM%d-Ej`Wz8N4qN5}3V^zDHXwucAf-XC7V)(&1S z!Z(FNs`?nh_+%!C^c+?5Ss|n`NA1EXcpY%`OkIeHfu0*H-5ZE`Y_F8mL!$uAH;|6? z#+pelFi<2m9j!ojNE54z#cntVlnafd@{uYNtm1@c6vd?HtC}+5rLGQArRSzLG<&@? z#<#@uAwjCt-RMJYs@`FTV%vS0NhcC}1v6Z|+(0xNU=mf2F&%sWl;W_bp0XBaEBTRo^|8ty8%9@^L((m z4NZj~TOg~+X`*mKDmB8aU6>IRezS!iL18&hSOTn0a0TF09S6pH9LI47Tz6-J#4xDg zR(PJ-)27*~YS_Kz%qe2Qz3__UdmRr50Jg~w+YI5f)2$1M62Ok z1?gEXPQ$Teux~8z!R?{rm%g@E^xlKjbf8jnTPnRhdS}E`-A9A zc3?Z4Wf6maGI-?!Z%xeDAMG}G{x|T;UDfX2mHYSqF}FYKU7(zJ1|PL-y)L%Ta1{Jv zGs-xzJIc}gE}?dolfO>a0{X2Pt0FNOQ`VUwCFV44L6u;+N?u)fSG4P^Huww7z0t!U z8cn@p?R0qbbuk$mu1gFJS0QM|FzU5$j?tuC-(&_BCsuemBHa8P!r4kP>6wI@l}_1c znnhzDOo`cWdAX$S$~gtI%LiX{lZ|P(b~9XKG3iJxk4iiaUQAzi!3a9yH1^BeV;^#S zx~+$dsZOlVAV9a<@yTf%j_D@KO8TzuK(q?IA$J9UJx9W;H#GeSVd@QR4o#C--VHOs zzUfSqPj8?Q^4fZ1EZOiQy%-uc@F1?!jRSaRNKT5jp@vK#L~>!-gwZu*L`ZnuNM3-v zBs)R@NBA90#q8OW&^z=7EY9=>!VJhPLfP-x+opDYY}R}bpU-MSXl!?6LvLV_ILv6u z*TH~=vc(ujZwLmNoCyf(iXf%S{oZH-j=yF!AphMdi0kM@2<~(wMcORa@9O4JuE{{x z0YE#thdvu5n?{g%OYHu>_}g+mFwA44-2x#+F6(ORC?U(^NZi7dAxQX`2<6za3?8T3 z4{&d}*p{rtBXJKBgC!*8=$@n}5JX{GvXh~+FjSVqVZvMhb>~9Q?quu+{5!K)l#%9C z(@5J(%rPztVM55455|Ew^$7&`tOZF-R_YT72LK$sqh3pG|42JJZU@K9uEQPD16Nn+f`;u-B{L z4KFrnh;8oBpfSZchUk%}fgt0za0pTmJy;6}c^tUz9V}9-se#tC8n6&*zyr|>K$HtPL^U&_M*_JL-w>@^ja*uZPRJ!-;bblbVSJ&L z%g(eSmsYYBxf~6;!$FVR!Qtu);q<}!mT8DwS`%^!vpcq41%iyb;1FbqtXy*5!3;?h zERkOoEWe;&`3Ry)Rj_d4GInpj0!khJV!++O#gmRR zUZ%(GX3%Iig9ge`ji8hGt<&u?$hMO|ht_uTb8@-9dG%xomvMDJhJz`GQX!E9ZU@z< z!OYago`d!P^#gN&Q7){)9Sp{Qz_hLB*Db(5d<^kQ3tr~$J-=BE{3B}x@224A?GF4C zzY}~YiN{sbKpk-~0(HCjh_weFu}jFRo#CK|)cHBnTwC3L7Dv;4&E#QU)&mI4bYZ$# zducO4Xs0~bSMfLue40x!v3iLZtCz?ztVu?u6?EiS^WoBBCKp-3mVwAITD?S8vgUa} zGpeh=1v3s*w%!cyVduev%*#~2J($Y$TnTKunabF_wFl$AOpw}x3DWVqk&>KDF=bLS z0Mp(#fwHsL2x0k-y#%Co3Na#2K(747m=ySngXM=VL%_bA0s4z$Tu%6l6JyZJs|YrL zAY&LDf?L5W=I^Z?NbK?j7{r$jyYK85U|p*irBl z(xZ5>YoDbcoD0IfFey2j+W~4ypJl*J2d+;iIBoc~aQdj$TpfYihKA{srtC8m|Aon( z#Z<0glEv7?#+C)w>)~1n!~OH>2n@_$h^P)yZ8aWf>sR?06}pc+Wk0yw|EiThunBK_(Hd(8cs^n)FzM{fOv#K=s^kDs?00j0Mlqh%4} z+yF%AyFBGQ#SohmVTV^gglcn?^I=K|VR`*o7om@5?Qs3~gW|lTB4l4A{sdT$Rrih?7lnfT1!H(QDy7Hy7V< zMB<)_DkqweI0;X%a55hR;g#UdN%+rbIoUKBqc$l183)+%rz9075V{R1ya$gJa}MD* z0c(xr^Ia&0R<$uARqZwuh`l!S0l-WIXH>%>kW$onK#c{8(cbSs+Bm2#(abvx2}qt{ zt-Tr4EYYKoxT?L~Ku#vnKY@vqsM7GMPUB-Cv$|I`hEK#>JZ~}hFmIu{EC`ah!L|_G z_#3EhFPDV+9XK=r*B&4G^YTq>z`RYkAIcn4ons4;zG|>Ru@$V}E(X%xvZc5(vC(8G z;^dCzuzWj<&_W!?!*Asql7|i1atUqCKdg_V`tJ!!r+~NPL?su6r!eYo7|-7c(Dw zl82gFl7XhJ_F}12TS2Fw%r`n92A#NIRT691*hUbr`jQ`}boYXrh(s@+kf|@o#|$=PZOji(cm`_~K1y znBm-&MAGZL2w%hHaGnPV(TM&A{-9N&ZLeoROv}E3sjIfe9)If;2_u7nCa!>ZJK$O6 zTmjQepUp8TJDd9+fp#|6bv5(J>03zUU^0}!YuE|$ZxdynG`;AyoQ<+r1md~Zz$hfX z2w7H5%wl|uNJYE{(VHXQB6wAmh>atls^$LN7U948jx zEKFu#Pa)I4V5C;Y8CY3j28LBfFa!J5I72?i|9g!y)oO4yzaq`kwA!pVag17UZN zI`Kb|jZu!v!1GNK&K70)7eMH)n4N3{E7;weIoTY$I5l%J3t{_@*Jt$saquqeZ1`iP z64A`U<{SbHb0*hR&pARM?c@;6h-RxWsu?i~^B*LB9h`|}oZieald?HPlZQ;o0*+4R zOF%D&+C;v2JJZUfY!2CSQkLtYU%yig;ix(O+$u=e--ejVAArn;{O2G{*T02Y4F4Py z6&IFuM}+mLijZ1hM6iI#As0pj7DD(*AnFI=j6L8GxB?QiJD`UE^&LMruQ5Rlow}2f7qFm-6pSE9GB6w$v+xhJfxZ z08wGD{|@i2C@9kqu`EdJK70-7s0BWT&x~?71X-dyyNb>q4&>3O9@U#e;zIc-6+8j< zsyBmFt5e9)xJWZr@zL;pL%9ziNb0L3MhRXc8^Ay{u>@BG4>*lp+*q|rqMiu1kP!qf zeh^?5nG7e64BkpG8O}h%WcVZWS|$=Re?BH0GnuzBj4|bFenAW5lJPMNQmy7%t1$-= zm=G$56gcTA6;JeFctb}4cLY3T^A|6}wC)UeJ@*EDXv+77SN)Dr#%`orL6#M3=#ZZ{ zPT67eaP`$Vc0x6!Y%x0Ic=5M6h3tEU1OkIa@@8_>hlspY)G1`zh3x(LkHEK`h1r({ z*^*M2eWfsMCCK2uqzZ&kiK{d~e>`a$zmcgD=URVc6`xMT1A;7>vjj0uXAqA}HnW+X zNm29as6w{;N;QimynysCNt{YGjveSyLLXVo_Z*9^B=o(-%ww%xODO&=ldn{d5OX7; zT8ml1+-x8;NHAj0bTTJIDfUbk5*ACs;Dv`n-Qx$GpiMzZ`o(UdvfYOcpWtCtrk+;uz>U&9NstPNbP*uXVmj#Mi)a0|uP z7lv``*VAik;3&3QzEtMk^dYgv2CfmaE2pjsi2vLMjwzKI8#v}dY~Y3gmudqS9^6Vy z+KmOwm!&B+HgL0n5gRx@LY8U+7anmoF=;mzuq>7)TWsLgF*fbi?q^7f0o&7r(+t>H zVoOm^1GaYE1GYlKX$EYRSn#X{FRmO&IOX|yx6gzmrk++{d@Z={ zIynEAEGNVaYy%UqW?;sW;)x_C&646_;O%zKha@rEIdxY(k&@iDt;x6 zB?S+nCoL&{z*Ynm1jdqL5;nECkn2pfC#(y|OOqtsq>UYn42?;ffdZ2@0|h2+tm;r* zu{CKk(0^jmW=uK)leWjPZJab|V?8EK+DriglQshdCT#`^Oxi9%yH1+4Z4oFiX)_`U zOxm_dm@#SVB`Rc^v~8y_D50qfQ?1tc1)?w>8inBb1`4d!3=~+c?S)NsNY`4e8DY@y zLxE?5wO5%Bf2pxo*@klJGXSUCtGoyd(u2JqJn5!vK~{_@o6U+fWiyEfrfdeHDH{{O z9^%fXFD7?^>B|&^QwNnv&(BO>&awJ=WBS5zG->)`V_MS}!!O~7Hsv2 zaMDd*PM2f@(-&JFr?WMEA$=EX`cm^20Bicv_~WkNwt@Y((U`s*f-*K5)0fxbtu?kP z`yom#l!hDDz~gjfMJG*P#C`^*FXY17HKs3QM97%FkQX3p`a*Vu0*>(G>@=9Bn!XTb zK<09IerEc@8b_!#ePNNr^o8>M=cX^Y8xZtwOkbWtaJuP>?Yd5v!1U!akZc-(tR_rf z{ss*5*x8!CkfMflWldjd#q@hJWp1W^Z`Ytz%5953FMh6j;YF8TKW;oSe>u1{7D1 z@RdeAk{C!smV|obF#>T7#DsB}gfut8n{FLLG$U~hsE1k>PUdSM{F!x3Kr2=tL&=so z5$l*gNg8CY9enryt#wQ%5M)%r;b($^5DhG1?g3o7bxc|fv?gkR1~C)JWiA{79ICB2 z&jc#nI)<2pTw2!(M7fXyblGtACOGNVF+?Zi(rQ^anV$pwGwYauR^-x3wjvi=$9xL_ z=cM7vJG=kZI;JiUB^m&Sxw(_OY0ba7TaPYtz-N-{IVG97=PMU66(+3 z>OPouh;@u_tYiF%tXsAzTF3Zp%t&Az<4yv7veq#&4!4s(N8fhxb80wMO0$k(II=9(F(iQ>Lp3Hi z);gxySjT*bAY&cV6L-);G|k33hL2qu>zJNctRscyZ&riBBl+N<6s=llVJS9nAlUp&oeTDo-%>j4DTI>t=n0_zycgMBrs=OCWutWKzH7+W2|G$ zY$vde3C4Y69TUuWkrgy)W~yIK~h!X&N-}B!bs~AY&sOf-JGjAcO(l zbcGqTxBPL0;vNCGayrOs`4hZ$p_q0$=ndd?Nr^ojln_4Gl}X_nNISiP(?Pw5BSvsK zsE<7z6m;y~`yntm5YuE2#F#agb?+X}s9{L=PCp6tQ3t3AZ zHtG8g0)xXQEu5WoC}zB$J#11-zddZi?DeyUO_-Y&3>_VcNjv@fm!=&y=|fHvg%b+g zWDlE=89{s4g!~BF!zN@2uup<30H^l^Fb)oz^pV3R#4u>UYIsr(n>5+OCJ)OZ0@jP> zun7yusc>)JKN}o2Y1-+qNrOFXasy~Gcu6c_mdVa5w!kZgO}qnbvnK|*u+4s(Ky3Ep z5Y=Cz0rajYOCC09;-)jC#Q;QWk{MTrvRs@2dxJLRu*uHkGP%IP9!VzRG}yx?(-14F znNIK1;F!ZEsAQ2uhe}9ds-#U43JxlK%7iv`R{~`laMH%^Vj%V7aKy&Wqm7-nIFP#j z00ClShmJ%krgS74)p?6Q13`vYZfxvs0U#a8PQ__s=Pl1hC_a=3%imgoZCP$s-ocH^ zK|gRqv+8EWZV$wC^K`H!TNNC?^{q z=Fn1XoBkf2_$@`C-uM!{RnKvU{SWlIYc5(9Iv0Ght3VqD{`c_2FJeX>dXui>paklxKXH7K{c z`nAl+z{kn?wL&05eUM%`1dvUSQwG$ace%F=BNPT7fDG=!V0u&+pa#DWA$^bEE-Qie zzUvfe$FB^whOcpCR}+S01D-}4#}D-ehYvN;adx>1^b2=%ium6f`tP|-;;z}Ya`3^x z{tZ88a13F!`0es2hSE2AZWfiuniMhEFoe`bqb1sC8?w<7SxBJ;bp>VS zDRAl`Q_ zF7>DslFRNl)e_Q=GPWX!&5I>4s+=5@A5G?E)K^43Xv+U!9WaUVKR8h!mLDEA!L;%N zr%AB{O+KU^H06KLY-yRVwz80vAC#G=!0{kQDgT3}NDp=eGOhd%N=ujWBgjXtH8LpW z7veqhpg}Go+LRCx z`#lGPM0Ol6$W^Y-=#gEkbKB%(?xDAr~PhM{<&<)CgJ+dq?s^1>mkbG2?AubpSYm zK%)UhE^9~qF9@**C^d2oK1F)Ig`Bm>R>*k~0@vz?dQ7EJ2l@Dk#Y?#E7cE|PdRp;3 zRLrl}k^Fic33k1$vT`2!Qr2y7tgj@@8soesrpV@BB$y*^9iTvJ1O*3eP@5d zY5LCbNlXFtowSE3JQdFWi8?&zRYVX4sdu#U{{I~<7X|6N%vFkl)I0OrBql%gsQH(` zTLozzJ_S}mn)4F;{}UCYMfiYK83n2Lf`N>J)O(R_BT$ffFB!-vNWGWG zp)ff;&IFw~8@44iu!`yR64RLF)b46u>A*y^joJ6r|oK1~Lj# z@3U>f#oYPfebpa5D^zC`q~141L`FgCeLFMbG|;I8U<-7s!iVySQMn5 zIneK2=a}@M$ACu^q@KC!!#gC%3KgW@p*Aa`AoZ4+#EpW~TW%mKNST1{30879fM@Oo z@NP1>GYV4g<`X4NC`joE6r`TH8^CLPQAA|!2JpIa_zD!HUXzU}3R16|;c675Udvoe z*^Gje>05h8<~p!N1q0!qB8Y(TY$HLFat90f+tX!dgitO?|ilago?@( zSrA%mno{DTGWE=D0bb&^fWj{kBq~$ypWYVG2{IRzsb_8r@S1IBc1lEL>h;jgAlWnm zS@q0q0bWasR1|Fctjd%WS*$%#nR+eR*h=$Sm@)(j9}}S*Tk_y>$}WK$s7yV%Ex_wR zV#h(dXY%JgakWZVxYP?=WjqA-i)*U;Q|_6WiP11h6JeJ6>@CkFrI>-ie+ zx(HM6cV@9cnF|KIk#=k}o6Q!oD%5Har>js0B{BJ_7Yy_PUR0=U@MO$~Llr9j+P%5U z;T09CXD%4_A(w!KlR2C#v4wVre`i{e zODoxmT&P0b1N2d0uNT5ADpaH)a!J2nz-wIwf{at(P=(48S-BK$z(P+h82I%Kv|oAy z?H-6KRfYNl;S?2WcSv}y03N<`4+q~hzmRV}v zaN(E6s8GYx29i(@gR4(~BP!IeQK5z>vToU?s6q|5F(ZKrH9Uz42P)L?WE18(g_nUz z1A4jgcDi8TZUl%5)iW0ic>9|P4HBj;il|UMbHRYuZUzmM z<${44qe89zW;O7S%o99Sr~#fTRPTuuf~N}A;vIbpP@+ObX?RPH*B*TLE+MOShBH^V zLIs}<&54|-P(5?OfVVH}0R*B#^`@JNo>8HC?UV=mYE<8Wc$)LR^k+3#lZ;FiYWP_5 zturdr@CvpJL>3ilcqMDzs8GKGtEgsg*5`wvs8Er4DmA?JU_L|@s@HDjLpE>i!MINq zs@EROvZzA!+R4cjliybT2*7j|D!*;a>EoP5k z(6-y~fC5059_@#6)&rTFfb$4DKY*Zc0I(}Sr2JF-S2h6a@Af-Fk8MH>{~z}uj_+Iz zCb$w1qf9|Y2| zOHu9qwT4MVuI2OBGe0yay!1AN{cao!Q(6B9b~fPCe6!O5QYsuLhHdf4tn{;h$hTnKUNXpJxr$aSg&%5sxDDzogsB2B*6ev4@(^91c4i?g?N?9@B+SR2owk8Y`$?Xvu0c@k>n_ z3+Fn~MhR+d4>-QDiB8e+4%+gAgfaSt5sZu4(%nMNgcw`KR)8_TMb-Dhtq$3FY& z4@WxLefB1BK`Xn@-mYB!%kHzch-+EdefEyvT2gkOy)GP~WcS(IjjJuY`^;f6{>($@ zP)AeH@v}Cejz`cQvYIfo}B<`7oiQUwq5N;Qd@gwiZsCx&B%P9YUxA=M3x?5I(+8W9UQOoY^~Kxa&aLy&(Z-#FapcJa^< zykfo%?#k=nOA)G62}@eK|M}o%UUgTcd{^CFAh}Vcd?nsBuf(fTJ`nGk2jW#J--dVh zv1FsM`KyfplyeT3NY2ODr_n0XfUTH}Sfo2jDqXk`SE&C&7cOKME^J1re(l1j@$|dv zHyN?WivGW%3sWH?T{uNEvO5}Ox@M%E7(s&N)tZv zk*YMghH#qF{NAsP0*i zOw2-PRFhEe4e#ks^J`V&9kvV)O-^PYTDZ4(){%HT%rM95W8MpzN$FL?eq8elJKgI-Mitq*pyXPxG5L6#A_$OO)MZoL5g4pUs zb3w<8iP&c~F!p|oZM0t5#7t(a)&DY9UL0ec+6T#ykK)ktgbcL#l)HM7!S+qTd{`*F zDBDnL<`&3xB$9SP9n*ca7=)qu5XWmsE0-Qs0aSb?#xV6Nk3JXTaPMp6hhwvaxV`3e zNpVWy;V^DunbicRh@*B9fue25j{Q<;#-81oRvE9xg!8Km<$#ybh9D-vnl3i?jf8o_ z{RtGMdd)9KG*~-)50vT*zof|$Ugz?2@-IqB^3a+CQcHOOOJqv99=tb#B9|WZ6MXT7 zB7+*ts{UyyLu)2UFc>sA% zAiop5L>YBwhK1G~Y?yX_S)fH^+9ph=6ygB>B*VYrK7_U)@^t(vhgpwPMerD++N}qz zmJ%-F_)^WKf*M2tPd^z2Wa4MxXN9aACA`%s@<3OnX>V5~6~nvVm8J;WNq=8TobD1f zF<(YKTNNhBID22XdII9Q^x|f+vB*id>_B47NR~^CGY5#0TbagI=4}D_e`3<$xqsbL z!dgwk>3Js!Cr~U4$s1;aMH~wy(@!9meS=w-nzepp~d|fG-die3M2=6 zQtCkVn4>5Vl2@ff87ARKpb&IrvV&E`cqI=p-oq5gO49$BjH6ac*p&Rm3o$gUWNo3P z7E(NFwbb2I(`=6uptbySayec`=`{zJU(J?r0`r2WOHGsh4I$N5aTC(K014fRU*)CN z<5UrRlcR&!{&s+CGtFdb=`az^}5C^*B`o zcO$CFdTimUpJHNTD7riOVPs-6@Iy33sHXFfoxOq=iEn*A!8z$1=GBk-#%upXz1;Gsl~u^wcQjiqD-)BGDV_&C$rj2|*5 z&3Uvm=ZPk#qlK`o2F>|NHfIyP`f)~I&*+~s%Z&b^urQe%E8;iL`{EO*#|nLGIlq8r z@}$s>Ip?Y_CZngb$2s?7(;?*C zy$izB=q|8<&5lL(Mh0X}@&J0xFRV#^yEX&(aKi)q?vYS z$z)7a(E4QHWjgOpl9{qQnV4WY@1{-X-Kp$4MiW7%Vj!p2@o--D7C2%cr`P4cKn~}3 z&|Gt1Ag8b6`aOpRa(ev*^wL01-$;wp9Ny-kZz{mlD~ASh`j&m+b#gNiCI)i4ROwRx zwXQ(=^D5DUQ~geSNCWDzlqu!W>nP?z4CJ~4muevA4IW0!@*d<7r#YN1W4jSu9Py7|5N?*j(Fj36g3cC)RE$26DQRg|`$1 zsRnXSlLc1@pOU~V6+&F%{he^iS`YU_LsFKakZZj-U@?&E!hn&BwYXjVFJN{53kPA(fv8foxK|QR)8gKnq$sjl+}nV%THF^H zYP7hz92JwUhCKk4f^KNlu;i3f!!l-44Qs;eJG|j(UBD`;UndD~OY09XeF?n>F)2&v z_9R8VETN|Xp|6A^OK5kx85s6U8yM1-&~9=G{UoBjeJzzyMy=-8F*z1w@c}rJThH9d zoe6)1XL}P)FhnZl;6bEvn+z`I{6zpkH^__HegJWBQCm0ku+H5iqL@xZDhC6@6lhWs zsT?7Yc8ZB+MDtW?R5M~!GlP05yx(=jS2a>8mK2dnqRE3>$_b86=A|GUkHj!o{`50i zT2e$R$(9$jg}D}a_7w~;kxIYjJq}ql_=aP+!M13~*k|hcM?qxmGfTF^uU-dtbqV($ z`5m7wlZjHkG_Nj^@K&dcGSjulSWZtQ814{xg*(U!Sr)^e0D`>!f*r?hAkG*Dhrnq3 zH8LpY#tUwZVTe8q&ZUN-$T8eOOd!W_$58@NZAflWy#vYV_3++<3ejQn1Z=p2=s<7@ z7Eb0XAbcC#DY&1}QgGo8vgOAlR9y#~CP{F#YGb-Q^ zWa%p8W=*rn#G5uVc$rhM$&~uFI|2A5$bNSCcd;|e!0RUIC#ZK(o!?AmXr11Y*@rse zTa17sv8Av&4R2svqdI5$@h55!{rBg=3waW;8~8j(P*_OI^hZU12Jf3x0LA zgtb=j**0~xso^T>A=TA87^}6q3M*uFE%`WQe}h}2`Ry)aW^@TAi?TuGnjJznxkJd^ zidqB*8#5E(f4M)~%M8QLpoP@2GNN&60pECO+c4JjM7GSrj<4_gKVXZ><&7G zB1VP1u7&q}n})QJ8QUN)q~XMS;u{~H(E|h-BjFHaiEJCGJsr3hVrGY{RGqYeYGoTi zoiu_PWm`eLw1QgubYP_JjnQZZb&3p3J75}}->OG)ofYll@J0*V`143HnoC6Irp^eA zsQch=_!JJ|2oPPq!K5PGNpT*~r6+O|&Q$!McUjQ~{w(z^Xq|Wr)u(T#KdL#&svU@R z!p)$_4(Hpv7o_LCFvxqIyiZUhDN}x(?}TV@quyw6i0XfUrJe_`X-j5b*iGyUH}c*b zHNHFA@6C#h_s|$uN>$u;jP#bkDWyyx(&ueZ+C9k9=Qt?$l_uR5auNIYNFk3N6?-3a zp;s{6e+*Aotn%(u^o7=RG|hL^UFu}kUN(Bn7RI4RRsSQ1qp>y2IFBg$+%@;C>WcpI zsA6+h6S@rpojL-%)e~wh{s_8z2}rwF(h*-Bd`@T%7>@yY9zDu!1Tr)cQF_ADqmm=> z^NMf%dhU}@{YoJYC%Gxao+M`>TH#@a-ct10LcDDXaUnS0$T;+vA1V4+ z2$p=SL^2({jCE|gZw3p`q__juEc5kPB8&w}536>{_?a!E7|UcjXErZ0SQr*C$;Nfc zSlS>R<}aOBGM(do7FOUiz5=A`%Szp@*e>ppwjoRUNPh`zHEm;nv<{|8SZ+p zo2l;93zLY1$o_YkY}F=-NQi-|trv~uR5U~pW5cQ! z+qB9ENs1GCu+6Jj=xxbO-)HeB4j$w23tbArbwK3NgZ2(@Xario$MCS)b3*jlrji?C zML8{JBj&aEIc3an88aEw%Rhi%{A9(&u<_Cjy=`VB8zVqBIM&uL$JqLDc<*Oy{n!>9 zeF;eR#1K**KFECR7Nvdc76%`@MN8*6;U(mXks@~9J{aYenrT`r#@pe;2a`3QYo3cw zXZR2U<;T8+sKSSu;jq|=AJYtQ*|p4^^y?3 z0k>9Ts(O=*j{Q_U>p9$CnM^o!lBEHv7f3jDtfl7^p&hR3cv2udLRf)y-Rmm=jC^Gb3fM|qOhs`_K zi41!{0&ibcdLTMqWcX$QZ(G%M_M(Fv)fl4S)zls=o$4B5@!U1*SM}W+Wc$Wrk-7Nw z;2X1QK!{?8MyEgL%j?lndOXgdYPgMb<*GhHH$v!oG_u2t46$&k&FOn1;@p@Oi_Ag3 zd%Vne^Fu6{YU?3gXF-UK4=Vqb4p6XkwsA8@Wd|d*vT<-4<5-ZY2g&=$5UIG4Wp@T6 zyV_xdWr^%cDcGI39x@yp9b(7k$nh^X-MWFh-E* zYCGMDT<8=ZjbN@G42kOuJc@Nvc?Qt1@p%-Vhq8t6i*b?eV7rL#iE0inmAX5#if|qJCXSeLFUB2v zQIaCd?#`?MN_J=5aT^$FcW3?tziet~v#Fu$SSei5a8pCq*UMfFY=!BOZ5-EF)4LOg zTS8jXyKPJ|*v4@uF^OOs$DM4#TzoT_oZbzruY$?pTNJjKL|8^{AJ+N*MAymwfN_t6#e{YZ{_s& zUj?55{yU%?=#NJp2KimVXRtpNa@)lZp)5oE3d9}ie+oGd^Y2IKaQ{AF9&-FDuzuL_ ze~Vmia{SQ{-DbzX5@C-x{yiXn6t~eK#m5|f3n(8)7^L`wJlEk>e|5Vyojn z4xS%7{@Eb;1lxY7slPb>36R7#+zLcgX}49n|~jefIsMz{~RLWXB`OA>qu>UG3 zeSZO}G~!2qiTcwaj0}Ho7o)V9{&^^D++TxQ$nqDX;bi-pQJNgT82oen z=Mb9bZ$hr~{pm=nz<(4R3jHDAS>*2ue6ha+vMBLOk>67P2H?y53s6(#ek-_D_#vcH z>7N07mA@BqSnU@=k~RLjh+FGlfd*CQmw~e0FG9MV{pTUJ2LD7*cJW_9{u}-7@OSm+ zLu5_9LMq+-W5J=jKON%k;g5vd?7sp`Pk%AW)yp3Vp1u9m$U`6hCeZiwy93|i_eU!I zd<~xc{dbU`0seQ$!$ALd&<`?umEro^Aa1)?neAfaoQl9~??#n#C@k^4>lMc#41&3x zDeU!%w|2a!x@%*oydoN|%TZ0}Z;I{-D|-K^|zn!8~sz+03Z zPje51e7y|`PJ2SQh;%L(a05ouBa?O4+$HE9!;zE2GFO=Hv2S4d#oatEaNHFo0-1v_ z?n;vcU)p4TvhRfRDA;T7PL;EC_JI!mnsgBO5&|nwb=td6<#KBle@%P@eu2O?G*j(u zRJlLSLEuKUD>f#O4M)>6q%RC+-IHVq=AN9E!&B07cxsSCu6NwiYz|{w;JBw7h{v6o zVBYI!e~x#*%D)yVJjx~yprEaPUn1{CMHCK#h~a0w6@E&=-LEd9e>4gLKMP#Y)~AJj zmahP3r|wsKfSXekhotHeh5K?q<_O#Cge|LEINv0k2@3N&ggHUsf3NTdn3IwO!9*$m z%zD?bzHFFWwlwmom;&C)&DfBv(D+i(0Da#?3YZ32i zWmxE3UV8`8Fs9iHWX9w=p{?))d$18KIoF~mYyT2&&TPlO`rlw~z>ag5DGggUI z{j(U4S>294>7RWR_aD%7*%bYAYOxu_wK~QpW3}-U=C`J*P6MX@kbx5q-Z}#w_Yx5;0NnF;2fDVjq+Ha0g27dE43Y-~z20@=- z7%KNK^A4SdYgsQ_0StqRKZB)LiwR9L zX%HP}^$ZzV#n+(&`FpaMQQZhPlh+EJjbvFH{)Mp}7zq3e0}<7Mr+*of=XQWz3fimL zJ@HU2waO?8fY_+jtxiC^d}i868nKoaxyby+WIQ^GTH7n z*g?XdALHh!KR@8M2?Fr@Q+}+WsD28>x-%BPH=rU}3L#IF;w2`2I>SvV7_nAuK#Nr6 zTpn|otS0}<)&6uu{3j+hhX9>%5*)7f`FCd%n=mvs?lg|9a^A>Y%@IEyX$JO8j@+`g z4|lLN#ZN;!@K2^FZ`qya8WP|7c3Z;ihZISuz4;R_hy~ge$-< zNKUZI-{aR+zUYz?OLWoOh7{%>wzd2K8UC*^($P~eNEhRaA8~hxqR!p14dv&UFnQNr zP5|NhV5;mx3wi#>ZU@Ad?2dWw!oz^cI0+6x23zIb26!iq5ym2LcLyk z#E41)p}Y6S1QuWh5Bd;bwo?_g`vZR?@~(ApY?r<8xA+)fI67p~Gt?&R&5N}|bY2IU zF*K?fGxQOnoCc3e4^9lfI~Ke1NjRIZa|sao6*!kt`gj|6E&i%x|o;9Y#}lDw;Ii4l?S|7Kl^1pNx~M5$D76axeh2$su_ew&*bPsHBE2A6V~d9YjyEoS=j3HfeEe2FU7%#1}5*6@m)3} zp)zJvbYn&D0XYI~LUkka=TZ`=u?gVGvl>!i^?wPv-tQ*$j~pRJObGeLSs?GC;^=9s1#WaXUkA+p+nGc zZUyTqdX!tp<=hT*#tL{UXF>*QL?3uP_jBxaSAPo1ee!VP7{8hc*5g#;K)plMW}?rr z9;fyypx*`b5q^$TK%m(oOQu30nmz-SB$LdX1E>3`#vVZJEyIu6dlSgmTsfquy-7l2 zo1DYoA&0s+N(Q-J26)IQG^d|M8lcG_bxx1#yiD_tUnGNsj z@OEj;Ks+>?7XfsYjwXtW`kxrH5dGT5)WyUgCZ5bKW=vSfBW72rVvW(y8HvIU(X_nP z#e`)LXn`j=2n=zWK4I0ivr3PaYK=dHUK?&|1zl86fm?PuYONcdhXvgt(wt@JE(Ic* zy9yLRn<2(I5{US*NIIHxX-XI|&Urv|9|kHnL;W89sOI>q--Gu{8G^>jm&hBN`Xve= ze2E5d%pJQ8ivM6 zh#YA|IvyGyZ!FP_#QICHz(u?uYyfwDcYa38Mq)B1-PTg8nyV&P=i_U&4&crB z)zEVteol2ipo!XuUo$;-;#Wh@ZTMlavNs4A_z3azJWPD`9H5_u?{%W-c|p*(0lgi* zu}HM~WDESAG{o)@n%@HLAv_bm8hSGDbDB%xwh&ciJxKgXkdjp!@$|If=TyH3^mO=U z6HQOMpcM)}AHL=IHPf>MzZ!ZD!VgQXWAW!?;^?fUht3uB(D@xbbnd2y&SrY(JdfYM z)@#m0!gi(8b2Td7>NS@GopBl*u5|c!r{mJ`-l#P90JbRoD1u)_7l=fLOYe*fe*>7H zcSeTC?V>G%=pQjCag;JWJ1UX24~p->5FBKfhzutN9Av^8KzI??v@}c*m;eDohep_d z2!S$&Z8*|j+7@R{ks(Yl&XglVnAyygBu0AdRgobwIz)z$XSnV=pv=|dhF0#Cz8>^D zz)7bO2SZ6@h%GM`axBD<+dv-Gqskua4D&czd+sT3Wk%w92WqCfe0|SC7(e^HK4ac$I1f-N-W#QN=l920 z6xAG7;@#P2_hjF55CQARKkUk{+8$kTezq_c`4sJA^hb#L0`ek{0m)s>GgpEW)y?$zx2AGl|FGL$)YA3m^rHW~& z)=smRWByZpHnWCDU}KsoIfFQ*a}FOxSvpPlJ{QL#(~yQ}-a`|9aZRo{>DSFa8dNQ9Jm1w3D(WwYb{?CuU(A}TKRIiCx8*q>PsdMrj6-9uNv zW~bxQgLlKZ2px$YQw%;|z#o#Qj@YNWAc2tLmzavxDIgCi^ZnB?SHgZPVUbw(6et#( zhDk<9F%4Qag)wmmDMN{ypI_8yNguH_hF^#)hYh6+4Mt7Q`gA;y{vQz}G%9N(+K!5R z)tW$jMT+S4a4p5%=qw@!#Hv&Oi3vm@5wWZ!#X;neS&^i;h&?HEYZb|a^l!%-klKB`@T(!Y(2L9!F27f2w&SOD9|1gp|+Qyv=|L)e0*L$2nmS#WTUV7NXT@Ier zFB^X&{14$rJ|pp0CS1@;jzhD~RnIZ@k~iS8fpS#)XB(w?=C+k620=T0$X|`(Q9l zZ6QZ~R6J&(AG3hHzt|Q+{S6d}Jh{H zLytI4E+v?}3B}zFO2fk(cQ+$E1kD4foH|gaNsu}%2+F$*LEoS>s(`}f_%cg|v;2A_ zs0tWt_xuWQi$K9Tz_2sTr7&~Jq_6-(*8-GMRWjn!r5p=Qgx1Vu)+R8YYDy9AW0^<^tEraNpFlr~ z;+aD>Ys-_#&tZ^dH78(&BF{^*nxDq17SpR|$Z8qcY)N6Yj6q>@%K>w?OiBaMIO=fW z)@pMz4|Jch0#-2kfQn>pRxl`q#R|&;8CsRfBJXdYJB}<)BAP6ou1>N!iNUmME|{|z z*VLT+oq*S@Dv+}PrwG$2%;Kr^x@)dP#iIS0MyA?|k0s|b*k)C0@o6mVnM{Tcl@-lF z?ONzOTf4cu7$vIN*h?m3@KQ0xf0|L4t9|epv@OitmEm^(RWj#}V&+sUa^sGcj7^Zd zn7#m0YH7G7ca!ZSWcvo$lI2?|Y{xL1waD_idyplXgcR4^lidzi;S`~~Z!>aGz;{dm zO$z@~Yx*WQ+sQ!bY7CurFX2m|GkEg}Cj)W=O8R7={7q!m?Ik7h+`nUIxcnRl((P?A z&R{$##8K7l%i%4)2o2pGMnO93>ycjv3n@$^F6;(#i&3%2$0)2!Bkr2{i_?fAuEC0$ z!3jg$uWPXX@(a~y;lpV}#yB{Exlf#p(U|*WnH$6QMQBu$P>wryz+;a)XBma*(Zm={ zliV1#CP|Sk$DMg~V0aV0B4Sysf3>Xs1bD3R%WAQs)??+3o-yd7Auq>T zR#RP?MRRIBt`ml>z_NNO{9-Vzjlr~@$jKXLFf^FfZR8XfOzTOE85m6K$tKKovS`Pl zr_DxSROiCgYv72zwrA|My*f4ma$S4?cGv1jDoWj(;E~x#xJFE^!qt}0$>OO}xBhMr zSQALS75=raV$&?4sAnj+T1CBqw3F2bGhBE3UlEw$;Ui3NBL140UM{_A3$`-c_w#U5 zhP&lljJSDxN@^?BM|tv;)Fw)D7;&W|EV{5r23sKUghDI_6Bu< zxz*!G#12med>-VZ+%EoB_#OXxps_buiBmT-fv{J3WbuvJyPEFDj z5aaxGJTP+I$K?z%*L`I1jt_st24c*0A6dNI!>xECNs}$teLT$ATw1)vkd(E}Ho{!w zXiwH0Zlwm5r6}aO1pj0$!>^)T_fbiLlPjN4BES9TOIKfnLKEiJVaS1m^^GC%Vbj;lg$YxY~_D^AFB%YF~j6>N<6{j z2?J@9lP3+6h{?%Qh6yZ!**~7bzDc(GtYPvTMW0~uyn!r}7t)x#m|()5brtHb*nPz? zd6mLXFnP^D5tEbG4U=q>lQ#^Le4N(6M&uUcB;S3@FnOC|PcV7MK$gk7mI>~jMKn3} zfsu=PX|Gl+J1~^$X*Ni!-Z439*DDyS^l=E1v;Nwg_17~@KFr7zK=!OZpXjWY?#Bk&{p4%6kUi|r zCig?lo^K7vQbwVu)%?0Fz_z+f@Wt|?i(agPGgVX3xeb~$xsY(JwAnp zv-L#A(1N8^|7a9^sDXkH#}%9h^F895Z%qMM_cIQzr6k(SuLH#p z71oSX-w3ZP%0nobcDPj2v@?Sb3hMj&Y3R6FBk+jW&@_q~J0skTRwyB?_cP|nK+3~2V3LMrD$((V z#us5FtOKF{@XW7hrJiq#E+3pnEuq17L5HaK!2h?|5)VQN;!SetjpQM zkU4u8YB3BL<{8f(hO$NrWX>Ljatvh79)|J_WX>Lj3JjEl{THwdL3@+QEp_P2D6+zO z6#lea2}d15x>a+oDwO7ObtYThbZIVO)m9EwPc$#}(8RfKfM@5aV96)>FvB7zKU*6RqAcfGjh$Ix0YZ%grDtpcpHMlgb=gB8Qoq$d~Y(&Bs8O+y~=5@5`|=+`pMa zDjDwI!f}xq?r-Dh#tip&aEy||hw+@99BG*0{v8}ISc!ZQ#<{x^BEy=}6Bj&>MVg{< zf?z|O_{g6SmP|yVdHI6Gtq#DEM{jgX)r^nc=xpWXX*22Ga+H^;CrA;^RbClw#z${- zUR@W$=Wg%>?u!!Rxs2w;HjI&o=6v2phty~A7i3{HAkWRI-V$WHVlU(M=^HR^;aQaDdcIO@V~4X3VYmU5}*E z$k;YC%W`CFdA^hf$=p)O+)*ZT+e+rvWY-&1)h1>4LKm#s%g23cXXm~NaYZaA9a%;w zPL0gN!eU2L7ObLC$3R}jgsAG`2lJw#CWx+>P6>Wi4hwDTms9ZA3YA(yrKr%BR&`1( zp;CD7Hv5kle5$3?3M+rv@}k4}WW`!v_Q5w1w(M1bMrYsjETH9Y3N#{{SAf(C(P&g2 zZw{H^jjAz;S!oheQdD^c=q_XqtLl7b6!ck5COiE!Wo?73Bzn}l@Rb~Zj!U6q8@yJv z+He%V2;5xYP}n&*%^8h(SPuIoZ=#&LKh?6{83PelGkN!%P?yB3>sP94NQdXQO$x7N z3cYt8vVZ?Hbi3{e39mBRZ!p?t-xT`!>LM}arU=69+JSAvUNh=|H-qlQHXM48 zO17>!9G3ZO0+hc7F>19b%9zzAw25ruF!hHFs=)bvJ6S_r1Y#?P-W-ks+iP-nD1}$; z`!gKXkwbpxI5C}!UG>HA|D4TX=~t#L{#%2#`0svO{B$mAz%j2aj;`te=xbAlqtUr& zjr2DLLa%-itMIqA5FFMW;kF)(`Q#@o2DdQz%&$Ke)aBVNUa>Tl~<5;N>}W90lEjB>Z+-mnR{01LrM^r$NMN@7r9KYlEE zyQSpS6sG{b7e5$~V^}W}5?{ji&DCo0sQr9f^3~lEg1ZyV9~L5>Jnn4|=;3LI=QO zif$_QF@h|-u0>z{;``Qk5r6ISE;zXSHj~kH1w^s@eo}}hj$5Pre(iZIQRqXX&}BxU zkBvgBJ%v7rE3`YV&@^A6OY13gVO$~j>MQig7E$PjWo@9)rzWSnrT|Bk(u$&??)VjF zdmbxa+Rd+}1IS?p`4x+)uS99l>a8g4qTc!xl}9QTlS~8ERjdwB*2C~c*^dBrlkf~h zqF05m8y7HvVIaTPlf&i8veVHK+H4x9Dw64Tl-aF`!7xzObpM&qbS0$i(SY;-x(7Wf z9lj~}mAnt$AMq0yyz*Py^^ zsFy^K)e*juOCaKX{FsS{Wx$1@!|#DOf**2|`g!Y#KjR zjB7`yy4241vdqLV-^5@xhbyELop17Cn90+>nLHh3awTRn!8XI487BUYwxrN}xWiPWPPSB?+Ns@tVhXw% z{s++8T!dJ9(4*SH$2dz~Mr=Re$4uyIn-Naj?1?AK*p~TOwm1_bZDwe>P3>OoA{xr$ zTje$b)hMG;g=mDan$f1Gr_I=&&%Ftv-ZsZf-cES$^TC%3X>IW9GYh~^@GOPs?lMLj zFA8hlawX&9b8OSQM@^C!c}bpQlDt@wtg3p- zi26K}hsl;o>SKAYzRO*HGhXsohJ zA!Q7kfSYVeI4DxORWcitqUg;k$5JG zM>v_LE1Qj(?P_Yd%cksayHU$-eCz=j24YX%SYr3D)x6Uy0H^o7B?5-K#T<6+*q%!o z0o-G(Gpgq^(zY1uRQ2r0EWcNt2}FY?CFed{7trN9{7R-kp_lRNE=hjM zX5vt(xo}hVKGYk;a{G}@z3=NTy01n$fngxZt=Q&c&oKBV~VE%u@*nX$_cSQGTV$5!EmzFpSQ9t>o!XM&ZZ8L3dw2d1irKD zw^`qNg=wl$>j%$#lgl}P`pFomrq2|JtLzaC)#BIvT;_cvhnr+yltG0{j(LKZ*gQv?hf&4HfjkW9 z9G{uCX{?{(vPn4@P_wA?cbLScJ?oO$-;v(RYbFLbX6)=G^CU-l|ElhbSg(f~rIta# zZV;G6k44cX^C9#QepG0vQK-6jF%Zw;7dL#_ZqT-3`5)s@h3)m!7~{ym*Xtq1iW=U$ z%UFDzr;1h9I2XG^oYl;5C}DZ8y2Q+I80hyiGk+~*mM5h+0bH%{E2dLH51nfKtQ_fU zwn9*Vx~_B>!?nHZVp-{!>4w+XU*OryYg#XqC{UHkImfuzF_Vn$%UP2yHx~RE2T_(l zeiA*3F_k!wzYafI@N#3pn&J=;7vmSVV4``mk&RU1Tr?BmWLB!gzZcLe6)O>wya~*# z4GvY_*jLn+aZDRqMm3&^OB=S1ZB0F^u@X0-MGhzDK#qR}ix{gp5M^h;S<5>2u0zQ~ zaa2Z)>?uv*Uz}fdA=^N4H-1*XbznQ2ZO7LRR~*Q;URW#Smgv_G3A|HuR!$m9)rqID zv|5^EcMECaBcEfyS9BLB!+I~=oG(zN`>PK~7}F%;$(?_8&N$JWGyWV*-qE4~E1*Uq z&l1^6=VMyj3=Tp5JxQj;@pHzBeO>|IF^)(Q`Ie%d#=KGyWuyHl7a0d)F)3yz8|Pm=w+oym!4~ z+-eKt6Ya0tY=vLWGdSivgENMqNWD2}38Tgowx6SwoP+POnJ2>V% zgENL0--OPXF9qUx21*F)rEqmi?8C@;1~74((HTQDndDHEFTzUT8x0vK?Q$sUm$Y&y zY7E87HY3k7i~xOD#OsCd%6SIF!L&Q^^9=Is0%yz$5Jawm!}APGQL6NlSQbQH@T^kg z9ytDyNV%-zy?~aFO%>TMcg%jdGo!(Kb2Ax^tyS|P-YjMi_X_2`x!H^e`;hYFw=>5W z-0YV-a}8wn%bj^eB8AV2QJJu&zViIHv!Dlp!kX&o>F~-?7AyeB&P0)yiP3T#!c)a2 zKD^)cM-VoAqJ(cT(B|fe68TOZu3?xbN(|&bQDPwfi4p@PSxqQ_;~)8GDHLK9>0x~k zf0{MNATOU~wsjwX?9=<4$k9x5nnAT@uo~68PGeQoyiQ>(>$G4RW1Jnj$@J=KaL5{& zW7f!=dm9-2KF{b@jB8}h{XB{q)9IPiIzsH#fKHQBWm>-`Y;ta`{oWheuKz#2( zc%)&|8$f;{5me_$1fSAmyh3uqpON&VAp8P9tJO1L>kpPrgMGGR!ZymVeQns*Ezgm) zzHev^Rg?1#4fPKi%Bj6>rxPgF+#BGErdUbS>;SC|C!0@)z^tis#jemVq9veMN;v3g*Gmr~`M0Jzrh>B@aSr27CC{@C}SM$iW)j~=p`)2KWRk;mSE;XYmRVt~; zl8qOs%uEB*RlhP104`6H%^TLlxSH%HGf8a~CbsQqr&AScR>H8l+I0`}28$Y|cHLu| zxhhk+?jav`s|&}0X?ImLRPcA&^>kzGgHZ25#Fs&j3X*gmEK~%KG4|=IC;Z&gG&w&} zGSR!WBxUIu$h`?a&q#jaDFS<0XfIAzr6T?Gy2Mi^o{Ij(Z@B6Sb!Q`!#bXtMJ>0QIR5a`Ht zaJW{&znvSdmBi{Eugp2jGSG^n_<$4U^()?t2~1^=ARnS|#us6LU8((~JwD)3Z0_m_*^39YgG?0$ho=r-=1 zs0gK&&1Db1SXqDlVmL`_QTSh~;3A3lrHV}q^}bZ`G5ifbK;b{%$>Ru4H6{7? zshkny^zTzSBTbn19Z_dA&ntxW&2W=WK$mqkYPiz9mHXCI&iaQ<1L%Hy7H9o~fpOeB zrlWtbf-TWj$j2%4Zy%@l?c)^xdp=I#tpT&A^>%ZD8!*_A&sFH(K3DNS{<(@k{?@v& zUE^=ym(Nw`9V(fhtI)Tq_Q)CxJyQ6&3cXE{9BX08{9J|J?t!5cey##cCNyd_?u|*0 ze6B+8Rw?{kg}z;x`Lvb7&sFF<6kAG2O5x`!^scxhey##c7eRo$6hcqK)gCsk(8&8- z#W74qnr4Dz`O08RK^3H;rOjA+V_O2E&2YsxQ5z<((?oAPrK@H4?p_$>+enZ71N>FWV$ zRyx-({LfVYnJi*&5wXl}k-SqR6BOZlL^wf_f4|5Fm|QOkg7H`Y_{-W%cC)r{yk+g? zW?7pBMs7qolUO{=Vr?17B2{qw#o7#x;=RS%bAgvz%0Y8WIhf~_E4ihN=a)^fLKy;K z!|z(KLxxJ;cP$tJp_Tp7_ADbc)x|esVV+Fpng3l2y;-I3%pd-G5>hx1(_8Rr9+`9s zziR;-lGEHtVG6Rcu;_3rx_Z@=1OCVePH0+A;c2X<4C3*|?C+p$(lvmdBcU!*?xQkL zm;+b2r($qmyZbR{aNK?oe7$# zy91#K?jEds#9WKB4R12 zn$kdx{~8Y*?*&eX2WIiJ4nq;M%4T{ejAWW~F5n<2n?Y(+?qf`7?s@>2k>^h38JoPP z0dXxXmvO09j0)d54S=#ALh|TQNwS!8J#3*dPs`=~3uFhpTtmuzj%zywt5AY)IA4}M z3t13UO{?3X$0^Xm%KklMouKbU*62In?Fp?iR4(UNxkNH?nwkV)Kdo}*n;t6nQpx*o_fM5PAOOr@9? zs*$;3szD5*b^0Oq)ZiB-k-l|K@vO51F-}BC9z80_;XLze&`01g))_)?oppwab*frz zMr=8V&C+|oK1)(Gh$$KrPZ49xqNUX!lcGU>iu6YadI?%*sKMkJ9Ot0|ufwET4K_T3 zeIDNmEkQvI>sz5v1)0VvOg^W^|6TJQi=|3xeZX!$Yq#=kT;G}}XaaZ)<;IrvQP@Kss{DWa4Hmv?z^7H} zKW`vUxnU6;&l|`iYfjdLI*JC5tc?afb}EXY({5!w5@PUAUO-p^d~he6fA+M4>_Z1xsg)A z{h-L-;Sgks8q1QQr86*E_!Fvi$mwscoev;}+R3%^lU54EBvFK}0QeNT#w47SI~jkS zKE#0B(xf~aYl2BmXY;B-7iKIa$#W514dlJAPRzRVohZx7Yx3oc2%U z2tZ~0fy_0jb7mtblQFC6RD9VXi!HVqmdY$N1^E)31=yOR+9xle+A$3qk(P#r#*gFlS_dfc4{>A zG=5EQhVvADR?{ewl8c{}PBWx4Q_{ssY-({J#Ij#UKJ$>Cw^qzk4qnI6Yz4x-j^j0; zBYbm(9S8q5myC~h9I+RZz}J)VV{3S*p&#?nD#}L;R!$Z2Rh4$MtcBCDR|R#XE0}uW zzwHWs`xr6H?xV2e|AMX{Sc&SP+U;F4vJT!H~1JdqA?2rvq1M@bP}0&FjmJ8AAqOPR{E4ltb{AuK>ArPBM!F1F00- zSxyg}lQ{r(@>YbR1#2mX$~t)$Vj%njd`}r8nBHqBF=UjNpoZG0_@?(_++j^i>h?gs zkJM;9OCpD!Dv2hO^j?*o2rFS62tS8(>AikQE4`N_iHDw&d&3M)B~L1cB?7y{xys_# zZ2XKRtZbfLvwK{itSjJ&@R%6^+QMY4ZP~AZ@V6V$qm}i($iD?4ZJ_QAwUn`3Ag+qW;-eBQuc+-|i z{KnkFh>4qf*j$0wvr+;Y3o3mhyh#gTZr##6Wzmvo-`u*TC&Eg24uoAGo#y@(EzPZ4 zQmmXY8wI*oBo2yCZnp^5ANB#fk?-LUq}s-&QOoX%_#2^@@iT+4ifUkVFE|$RAmj`; zHXYu;rXB>FzKfzi5X6x&a0qag;2GvZppubK5Mm57oS3*_hF>BO4MPcdViT^uA5IH2 zEgDQx4u=!%8^-ZPSPAa~eHvFf1)nGcMPWvj>|bZ5}s6WBQ62y1jV zQtq5?D(Ph^`Z<~^XOaQesp#HykUE*=-O0O3MO#zsS^h1x?7Vd>#Rs&tL8tCRRQ&{-`fVHUw{5)tJ==J} zWifBlF7(@`-T&mKU9zm`Lrbv!f zuqij~Lfbtsl+H~%FqzP()g&LQr?P1m+O5*LX&1U(dCh4$H|;`qD6c(D=cZj~S6mV| z?Z7k*0%X&U9@(@Dnit@LOW1OP35@tJzhKr+>Sumv?LrT#bZ*+=Z!?JsjW|8B zX%{r_z6Dn`&~SAF4cGV@a?>t&iKn4#+66B)5I5}@VKdpZ3++?Qmm&t)v;)wByKDH% zXVx;fwFW=)Era`N@XrQk1~=8qS8@9t!{~nY(ns@l1AB3i3)e?SkW5a?>t2kp)KHeF{!u z@i3cq86b;vg5z)6$&)?arX5$mWG^mgzA+zM#!eJ5$zEJ=nb(2JUR-b)si_5Smq3AB zW`(~O7uu}Sxfh4Oo`iJn#f7#gBSNQhFAk<5r`e06V)_L*H)Bwkp)$E`kvZ3kLVpa; zgBa{;m1(vuGQDv-j+tT6=WUEoGgLNtvg16N2w1=ox5_p=**;HRErMh#FZ6$HD^K5s zIAxfsx^kGRx()FMu#d+>hD*rsc*qfiOu+0VL+xkU_Q%t9908-S2BFn{leYbS+U)rY zFbT)4P=EGASVe7MbOoF(7?Fq60h#@%10I*GBKQzyKj(vJ0Ei=}!Xdyhx;Oh-2~-c} ztvVpHA9a8j781_F)q&LlarQ$AVVw$B-v?(nW(pcioc*W+M3afL@VE#o;XR=q- zenrdKk2*lHGA-N-y3YXME1PhW=cDaY2Y!S%l8l#A2vTi-_M@i&DOYjA=Ec5niv_?? z2VTVqXDt!PT*V3J7|2}33FjNgT*V0&7%0igrvPSFt28W^Ko3T7LRg=NKTU3cBU`tj z$*L(AZt<7;u*wt^q+taHiy*2M*|{*8JBCZYh2OtOB!g8|q1ip{0Khw`TiB621zmx` zErixDZ~?ifoY3{gXIrZv`CmvFOfCmVrrtQtTrXUmTH!( zHcUesR+=^}6<+btl&}@6S6UTCMRt*2(jt_|NaldNZ4BHv`@U4u)nfB z7)Etys10MK*hxtn&R}e48*2^!0|iwVie-iy%cP2BO#4)Ok}=GPdWIQ!vq%^%hWP^G z6~v2SzVQIqM9e|!=s$w`ajckTsF5_s$hbLPL%?7(J6er2<{0T0y0RarRTA2JHI=#t z$BF*K8ev7Usf3|WD?Ce8s<{MGRt&E?ndFN}I%a$wdAfwv81in5Nmz{1tS+K$Ncc!S z;${rTS&%}$A{%IaJ|OR%o8r2a3RWn_ElCVc$GO-NEGVkbb?zLjm0Ip1)=jq?B-rk= z=$RaM9#XH}DOlwTxUZp>1ziWpcHKRo3Axu`sU_@gg;Ejsn}s|sG69&Vdk9&W;J%3V zKjzL|#p5DDEcGP0I}lrAHxK?~SD`?sxChbZrn>8ZPje5Ud^K_JMYGt{O@hpH_aV5= z+^?WRb9W=?Tew$&H^V)K)!aDh>t=)&9d69c5Vkvf;p${){Z$R4HxEa8dx@SYHw(dr7 zwR7_zt-X6Ta;t-T1uW3ft$|HCx$lFkvwH}dcX7V}eOLF7utS;qDYWY5PDF+3?%s@8 zdbo`dW4W6R-74JGNL^329qif5ZHrVqV!4-sXusv|0o9|Hdm5BHV7Y$)|6`VW6iPjA zxeBRx!gAk)37*870m7cL+?Fu-(^wCOHqTh@V*Gg)lpuKy&C@F6vuV3(yyj_Cym{&t z=7UwOp}AVmV#Oj=aC%)C%#iRJQ-)+o3s1NF41x9pT+YLuPK;}=o?$RAxV1Zro089t0*HoIUbT8|tc2aTyxq)+*jIdhqJSHhOXK;{ zTtH}LO8BnH%UdOAo7c!5^x6^#JY;&P)=wk<)Eg9NUykbY7W6HrM=gTyb)YN4aM*tK zg@z;W6H}b*0ait!7tEkD{opYkVD;Py-zcQ3WE!Gj+SRBYcLG-l9BOhUxJ&hLxNX>; zmzh`aH?uFTX+%%i!%S&0n?3BH>;y+sKz3&0VN+z;I(VACIp+);loQG!yOB4g`+N!?Tpf5FpzS_#ZQ+zQ3J|XCt07)gFL6k=IWS=$)lL z6L|IVe(aO*45Q>qbwx4I%z=#%cL#ow16w@6su<)2Gw2aN_#O|iDyDhC3_9osKj{Hh zkB{Ix^~`9f$1XSzL0PNGHQ?BfHaG(sH-%lNDBrM6sPPaq^BTx>P8adlH*J#_5qKE_ zGmtd$omt1nl&yqF4W!{avyRWr#?(`$jb{npS#^B*2zO&+daw?+@2>h|` zIQSO_(DO!eWPTLM@l=!fkq=>hROaHVjv$Vl3x@zFzux@lCZPUggvk6Tl0yuq8Jr(Q za<&P?`4J_Abtky`PjL2xp=KmU=0}knqRGVhQCtKL_T=E=GNf~U^ebAW7!gOp;0ic< z(Pt`Wrn?x%$M6PSwsLPm=W1KMe@5`1(A}yviY55SR4K(W`M6Bc=%@u}OhGALYoOtM zrS4p=7_q88@fkFWYJ;K}yAPsy1)d^$l+MLCI}h?+#jh`#g$X7vkwd`UQsbz~i_@gK%3a9aiUj^$NEy2g(CGKoql#n>PL8ON$$U2|Tr>uhVLcIU z8_qFLQfcgpUQ{G%Due?+L7%%@K6PE}&Tln*;2EpVYw4a6h=O z2Uyb86Ftih8t(zH&aV#CB%6n-T+E%k12reFu+XOP1dXk-fR1#8Ly&)Ef^5YP)Fkur zWpFgt%aVBnGq{4wgvp^&c-L}0E}1tl^;G6l@p%}Bsmy!e4LBd25epSBW42{;xhCM~ zNk9bAB&%F@JOL*Yhct_ilVU&DJOWNODO!=@F?OUte3B3<{wq6}#|`3iAo``TV6BqO z3piO2lFUc4!fBj-C-af4a1&0+`z=95S5GNsPrz9R&Oy&QD7A%B+|-~(AprR-!gvU) z@hXhJXH68q+Jz+B*0<<|VBCA9Fq(q{d2;l} z>l&~_j&K?@Ml=~sml77nuzV+89|HOxm!PL`^2|AcJbw#c&a?Out%RRJ_!){Wdx~Gt z$~l5O>SO0cti&gr_yH%Jar$o_bNcTbk^1lOT1l5)fjZswWhACCy~?2tl7j1i?fxOL z^y)CNx&@9XEV_(&G1Fw?%=&%3<3Y$ozFs9SHPE91dIT6>HjE|{XHEjf@86x7(*!~$ z5=}-w6Ui9Xe}f+ST6kZsWhTxvnK+YZzq@yQiB`g6Ap9JWNhbc1Rx)uW#mehd@4@q5 zcgQ-5Lm1ax&IG5K1gAAfum@oezB33DelLV3foUfK6Hj2;Ac2rTqU$G+jA2bR^ttd3 zMHXl$%_K05=y(EsiBjtK% zFc3`98-$f>gwU9xVkj_iQ&fx;2&N#qzA4BU)>K&YY|!&kVJnO&Du|Ao!k1_z>;_?1 zWRRHRm$YJv3W^m|ya>;KePB^e0lotgZ(y73odSG~>^%5)44z2Dtvdyn5<^>#?6Oi% z1ojul^GHp7|LO5OW}rEqHxr!y$r;5YIUhK5F~}qQ@(V%g;*FnqNU7l|KVsrGANqhm z96wV+SW{vBF&uNsZ>TZyP@>~T9_op(64Ed@jGyxRC9N1)6yx|gNly6<%?3wUB9Oy+ zT>yG!ZEOzfwFO2`hw~pF)|*cm^}dLB0bz4kFUcI%+gL}DM$CG^a#-&Ucq04Z@UR}K zJga>IZ^OfS#Kf&O>`Q@YHA)EUK5%tQjPV*C)+5@tnr`Wdz=Log{MBJSpO#kBEh$!J z9XzZz0`zzgj^fQ>y(#cU&VxgcYB!Mr=N;C&1OdKH&0)O@fYA@Z`Hv6lJqhB-8*qMc zSkJ*Ix8Y$uV&aAw9u|m(p@gtr4_B7~+3>I)(Y|4v;hqR9VKNARby&}*mEts(Qr|@(L(E4GTBvVRYw#WFqt%aAdbFkQ!KQ1ycQsqIPez z^Lz=*Zwd)3mHHk~_6zKI;EAL~EsFqmvP@H`Qq83eUIF!3Wy!6Sa1y3B+D$UY3wsk| zju*;nbffAhn#v+v6%g|F=X8dcw=eVt_7IIAp*l`d!{XtObf z;bWQ0@YixzFn`?b$Q0XkfpJ`${hqrI{(yT65)pLsFXi?|gyRsm1S*By!*C;3I`4X> zu&Y%OyIE!5b{77AitK=v%|_M-wUzz`Xz%c7o1aUyBKF6?fwsA9LPzW`1cX_LuWuIe zhBcK>&%r$QN(`!*OVCRZXhyw^Ku-Fta=XtiqqG@Gq`k-b;)2sBA8DKo{RiZeX9vQ!s!86o6@63 z6Ezy4yq=j|PIdcU4zH@V-$Q;C!rPc0KDX>=`qettZHy_H>F+RaR2rX4Jqlo+mrK+HIACR_Y&|2AxBO9}SZ% zz%5<{!D>`N0x13f{C@ljw|X9{HNhi99q>HR;AD`lLHSp!DCqK8)SzhQe5~KCV!88P zF|_i#vvgg-@SQ@Fzl25W8Uj6Mld1SBv;gW(YCyzLL1u1)_<1Z__pYg&?n<)&KJji6%q$3jz( z0PJdbx8YZKndh-u6MUSg9i9iPeZOM{#uOtV^O*UJq;vuV%%h1%%i=7X(QM*Nq--taTgjBb55GY?E z<>x|4s*4PzWCyU!@?lqMe6ORO==6nH20E3@0dFnZX7!^Y&x69(o`)5HVW1d1|->4e2p$Q(dOGtC~dJ?Akra-|#~e?ZCEHk;RXL3+=*B=1na(X2hIUHwM0 zcB)Y@&!(~L+C?Qv5OW)2ZDljI9TH>PnG0qTLzR$FXG+us5IKD0=q zhhHjdJqwa|;MWd|=WC>wRW+8C6G2#>=8!Ol)zfQx+iXVnrD{bjs`QDdRXPpCe`mn zW)3s{8;Oea#pjc!G!;{$W9+CJIm{|zyDY1dmf$ecageGH0*2w&`cH6*L1BtaYlrqt(VG@epFey#PX%F0U;ipJQ`R)pAL0>=x?7=8O zW5Ab85Bhmh+H;U{exRg-oVOV#A1iTcKU!pRa=asEuRXe`q zFjbULH3darIR$j*;8%E>=doH7ypyO4JrAVM18JD~JlCOQS^*DDO3u%9m`AFr{gdoG z<~q#)*|kxt9b2-sVl-9NaT5c#Ix;BfhC+1}1U98db%wPHgTIT0^6@LA)0ZAPr_)1c z89j71(nIGydgvUahtB8p&neQD2S28;mo_Q1x^zeImlSph zvu%VCR>Y>o`0WbFXbz$@dgj2>dj4wca^puqBYZ(t=MYBzU50=l8=kIZaIDT%a0`20 zj=F$f;S4w%@k5B;rg)|+yBmD!T$b~~0P7Deut}^SgH~rw{fm|taw!ONofXpPb?e!thkssg?ofbTkovXUXhoWDF!rCYzu622n{w8JqM422n-CAtGKgv5X+%D4WjL z4PrD9Ne_L82$LC$wW$ZvWF?G3`cz7HOayL^hW4W9$d=t5H~rf!yUslD(YX|oI7|;- z1<#K$9l(OnQFt7Bw5w0UXt56_L+Oz71^l)Q zOBrVYBCwU1FHc2lKyE7<9Fyg!BVjZ!SE)+sLDA@FNg(5}^OB-L(Z*1E>pqhZjb}>l z@xz70n3-8@;4P?fjW4gmBobq-qHercu^FBSFU%64c1bk6xn&_Q80o2xAvCN>sE@+A zvKPh(fenF4XIOy^<{1`Dx9Q0UTold1L7Bki)QO2c))Ub0FNDpIO!>A!VBK9PEKKJ0 z_aUq{or%TgF8C?&z!fz@nIs>o2wZ8Tq(;vvLD*GHm7T}WT~LeUA+WOCjKou?2irks zHy69S%H0IN?H-4cj=LApYqz!y*xfnZxu|oX3m0`x?8rr(>kt}tdzEr+@d)S}xeMWs zy32u2a5uE&nbj}*^33Y|emt}KA-aslZsV>zvpTjn&#c}Ke5(5+lAPwQgx#9BUm>)q zdwXY|S$!XFGxr^YHg`+G+rsSx$r-Lf?3wOIpwDtYsoOV$RKeeFM*dIU zjFe}ubpE3-w|6r#B?bM4+>8wFP^r8b8N5}o9YRx=#+#ABZHnY*>r#0$GPvCXLutGj z2__R7wNl1GlH808?pA5M85z7CUwbu@cr!A1hq{TKRGv=b&B)-cxFp_;1k>jd8nraZ za#$`9h;{-+|!T(WeR8EtvVavOM3lF+}&CClJFDwUTk@ziRSh&;-9W=NzJ|PH z>0aV#D3>hVOAW+JmW;58T(S(}0wfmr%_U0!>AVezzfU7ioAD|n{44^^cn=c(zthi4 zknl6X>AV36Khu{!l)f$SSao-&u3Vv$SQzFwc;?t?u|t-feX!vdU-i`$q00R&Yyq1&O>c5i&1Kgz~(KFE31l z@=eLak&am)lsm4jx#Q|C8;L;{GFtAqy2}_Bp_Tn1d>N@(2*R30xaC~{{X4F~%_@z{ zn)vHUNaG#X;1*>>=rrDOMad*5@3`t`!Mzy`T86s}lMi><0#CU90G_EB%V_9C@$NEj zY>&AO#&sWKFp?427?_8T$_F-52db2ji=a}pfI6@->miJ^0vn%!DKdw`LxEOyB?y8T zxN!s?*ccU>>qrCkfKNtIdLby2Fhqi==y9}+fsOuH^K!JJfsG6|W?-ZVx5D{7loG)M z4aYS;M;>AfY$P38H7mBc55SW-JPqq5L@q|tz8@Zk9<4P`lODuaG$}C5NE+@-x}L1n z2GY@97~lm)7$_9|9z(gnNXnsUV_#t87#PK2Z&*JCr0xdq7BnI{Ff+hqv%pN#iXmtO zf>J?`p>uQ({DIkCgqEHS@Ei%68|{wKKwz#Pl(QdWN-HoYV<$*%=s@l{S`~fDj zx-)!?G_$%3e2jxRF^3YZY|evr_y(I36}}ndV@{BD7Fh-Gxe53JXnNfYqxkK}8$=w< zDrUrBPapm&1SHBAR}KJLM$k<=!=% zHtW?B;@wlP1Et%0AkFaXSX2v3ZwCVxL6PzD+Kwp?ERV@gA*l85z#YkO+he`Pa%)ed ztRpp$WyL<4fw^+QArOW2>u?j=Lg^7B&B8&XP~M`76jDB$u?l-%f}S%8Yj z>(6~7#lyhPxi4GaNT){y!leE)tc8{VaOepIVr}t9cObEcDI{hPV7(Adqs5?#lm@sn z5GiHZW?FK(0&PXw=xagpXm8L)Iz{(&WJG@RlED~1>?c8))$I^+8W5S)?ct+fvkNE!l zB!V+iQ&AQGrt3dTi}C(EAf(0k@ILXenfUkzdZoqqly}=R=dhXh{9<~g#rT33$gSiy zAiD}RPU!;oLzHdHy)^*H(iDnmg%xd766LU=Q5%1F&<6`QjY@59OLz~THEK&spg>9H zH)_Yk^ZbscJ`<0!jPI2PV)gxOb6`PvAXYzMAQhNAZJwp~F=2R|D!@%T{h&94u{2ZC z`xy#(*a&%q4NzRjegk@Ja2@&;1?afcdK9YDw#>nOAUm)92Y{n--JdjT^}|=USW$A*W^_Lg^Z9t z86inVlh=%pR6OAU>%R|8QuUig$XjfS;zHgwkSFAbCj`Zo1<0O`BGniI9D49%{m&y{)8etn?lTbYHPxfKNTpu z3Pt@wcp@9%5a1GD5xPZESoTdBC_Le{w`gb$PT6*vSMu(ry<#@E0#kP|r% z|J_|9S%y=m1K~b-HQ3#SE1;4)?;2?QuR|?+;&3Phc@8}=%-3BI?b?2Im;z$(PYhEI ze5)v$z^msWHvI$syMt>H>W-Mn=#$Y<+3w*HjQ&~l0@}@;gqGiR(9{Lp+=U=?SAag` zww{G1#l7}-h|PU)73!Kh6*N(|Pd7B~{}VDTJq&t3*B3=OvN?K6FGPHuDO*-_PX=1Z z4cww*^=`Bk&<&HD5eh{=ZvtrZ9|ek9#qWRDMlVs;$3m?pUP8LxkFL+%*^pZ0m z{zU_Yq665;ykwxH=w;Ucdf7Cx>Cro913GA+?C7)sfDR3TLG8T4=>1m$I&7fUQJ$cR zyf#kCd{MOJ$AI4a8LgC^R~(o%Wq}nr!d$cSN}@M>gs}Ha0@_8pUk~U519gfnVGJJ| zs4RL(IiSxE;@YI0S03QE79wAnwSwN!J?jwmjWN-Q@?>M=AFm1Jz`%Sf@_j`Ma#f;+ zjf3GdEi`Hx+Um&UX!A<2PVpPhN070RGYzDp?Gs?nvkVl9o|Xt`>Jbqejcz|1l+%nc zQXzOcWR~nWi{(hY2>%K6V|aPLko(50kmS_vca7%ZLO3)lwnx382Xl^32qo1Ih zMdtdd@Lh(;JWrLt{CSh`6CE|thLY~va2`fFi5}6nRC}GzP@L1W*j8-s?j1qRGQ3z~C zDQqA`(9IM?NM!AxEI=4T_~Hop65+RW4TSz4bvZS%3scd^F2W2*SP9Qw*uUgE0O@utN{po|VW(eZ|9dm;z$( zPuiZn!0Y31-kwM^_mK^*NFT2bo6ENzgyuCH<4zm51s!@I`@D@q6;bI8aM>l=y>LQ1gH;<5M!4rV&ZnGdO{%Dg%ZM= zis-N5EJOdMBUN$=Gg3u#+%CQdDwwC7bqV(%d!0+!wywZY~jnmR^RsjE4 zrQn@<_$ll`o|-IpyAE&Z^*}9}V^Skc!UVrb*g#Pe7!G=vnvH{Iue0xRR;g3X6y;Q! z6$EBda+>Ltw3(t!pgovjVSPRL!kYP@-E7PH9!3i3_0d10IO(g|cu>TXYydq-TPYnt zI1E#hLiLQDb`Y(ide-JN0Hmpt@R9WA?4vdzEE1h_Beozrod^bRtXMz{{z)TL0lZ!Y z=OWBhLJ8BQ3M5SD&=Rtw5%M7{YmEa@!t^yDk8FfPkScqX;Bk1%G021%sRRkriJ|sv z91^BKD-bIIC4}`zxcWOd0Vt%wv{J~3CKDTnxCkrZgdDsyf(Tg&enrblU=*WGW3Pyw z?ZFY22<%pvpq&KJGeL+jB`xm_q@DvO7o$?0Ff+=KgqiV5as;E;gqce~5V;Z#L8e%C zwnc!YKLB1{Sc{n#)?zKb28Jo%3v02g9|STlti^H+WL{W{LHit1y>KOl}2)w^5%+jFkmMtjF~v?o%&}7^^$O z79*vJ$rRN7GB_#+TuG;}pj6gIL+9d$L#DG9&a@I9WjK#v9tk4pLxj58%I6YUr+dgc zbO%_+ljS{O>wH-l`EjR&f$#y)bkUE%&8P9Ys!z9oeky7ID)e2|x0tOY%_Y?I3P#*j zJ%Ukd(o#ZQ1=Fb|s+u|srIXeWGefW)_r;*nC8AQ5Ri>)Rbqf>0@N1>2MmhtJ+LiZ!oN{gm=1wA=hDQpY%R4_X)Q1 zwf&IR2PCYf^W?Pv_T5cFB%FFk>N~wf%s;S*kn}a#-ZQLXrW=K|%8Kzwd~)`Op!811 z$9NV#xrLQqm$h;_{y0eFUQP-_%)K1Bg~RWEcyOZJ!pQ@o+Y~q(U~$!-(H37N87rqM z`!mRU(W^V2Z8?dNTlp+?v4t>fa^6x(G?T#sV(?GejfE7v7tSlFyQ-2x2O7aR;9JQ6 zl$Y)}#Xf`*to%)IdVIMZwAG{=E41CdLD=t5Ak}ChmKXt|*=PpE&(~9-@`6_0%X-1y z|L$eIloLTKrxSx?R2pBh3yxLaQz@jc;vEF46ckytA`>nrzl?h0dK#uPHxUDyr9jnm zkj;n9!Z50*9K~Bna#alg4>?^RJGQm+JIZ5u7cvHX8}544(4&Z>*UNDBK=OC^+0O!d z>Is(B`&Ky50P`Mx25N_xYw)x3DZEcJ5U`a~H^|n2y1`q(<}n#{16QLl5S4uqb%WVW z!LYO%Omom9=zqm!ML)k5$-aTa!Mq<3M?#JJXvk?B`!GK8-`2DVCu3^y6FRWhW?O6d;9Q7GBb;A7sl)ME{|r5^LQrL2^ZpuG``C8SLq zV8QiwqEhA|sP85ui(zw-vyH1!6GCGR3ZG(Qm%%ahmqkK>L6xJ>Y#5jP5qunOQ_XB^HkJ9-(Y>8 zMv(V(<4MeWY!wo9lDBPm82*7){tNiiMT%ZNHxf@~BIE%_F28!ECM0XIR-YnhCKcix zQ#{}Cizh3@I}IwtJMps06wgHU*6Lqyc@^TF`W2$_8gOQ-<0h`-eq2%&j>pB*T5n)= zO#hP5RE6VyRT%V!NDHbo7Jl5s@#Nvm2dY-kD})%*(emZ!AT*G_piPrn8&tl`zFEwr zWymwnP>o86vGViacG1k$@=fr{W52=wYmfb=Jb*Z5Sur?S$ydAZcMtSplQ4KlF?8OK z1ga+LS^VMF0qe<|rmjdWzg=p1wW;N|OD(S%@D+-gYNlF4xEfX|w?CSTSXFgODjSVb zMcMWa3_bJVNu)lW^+uistN58o%NlzySNB7>^#^#tU!*@#p2n^5(#PBOb%Mi z+y;BTz@?Dl11M-iNUB`dU8uO*3L&X-UDpS38dNU>vA4zA@)P*KgG8}E6yQt;GDs54 z`-%N<8mBNoNjmZzD~0K}jJ-7#u18OWIW+>>(;so&2SF)J?SmLiX>!m!`0KaIks%ZZ zt1wN&d%$#7$f~{$o7Q_}Af#9w#o#xxxDVqwE44zAKvkRW;sWU|a3Rsu!3*UWnHnx# z#zV-e$MGBSCZd@N>8E_ljkB%l1_-bRp_D&_fJAz%EkN-VXsZ%YY&BA_xY;WU_$hzD zr91pinac6%ZHB!TqJAVhJ=PA8^`Gj|QN(R=5hG4T7))lJ(vA7Q*Ra2d1ePNpksj+# z_(tybV&5BQ?f(QMe#n?-vj9G1ST!PCL{@sNz3}ya+M{F455?I{e^&p1pLfo$;h&nu z?O@OCYy_WDck>Ud{o-b6VD3L3gN6G{o7Y*6FyANCp7oFV))#xf48GU!v+{Xf6U}|w<&nfmbxO_-DV(? zJC!YY5BqgOqf7y=FiRx0qfG(sX>*~^E5HgeLiml?2!^LvgywKmH_Mg+JRe!L907^+ zSV!O+`L0)lW*I3cz$3pU+eR9FfnmD=I^Ih*daU=!mV|1?qO%~*<`o^*zlMcnaK8>v zuO-#E&~ELGE}7Qytx{lCV!j^uv+0CFojW3mz+a@q4DZ|vwI}c%`R&@I&M!ixz)^Nx zcs||A=Xs%;<&^y@b=_;fi$9dPPULoA)er3R<;v0eeWFUWHTWpm=CM_J)n1A}?DNRh z>sC?eIvf!SJj_!ws@immui5NXRE^yN4HLP0y#eQ}ThLtKHyTggzHf8a(i);6qB(xn zphg|hIH_Z{>1&SJ{)maa)G?9Ah4{hUK&G~$QN=#|F8m=G^%!n+IfPL_;7KnT*5I>9 z-3DEy3OQZzht#B;VyJPT)(SjJBI%B}yD@khS)PZL@dfKY;SUo_^2PNcc+t1hT(q}= z7mbml*5FskdyK76bLS`gVRYoXRCqhgoHW@A95&P;Yq0JF>c(ubbDb9WLuyjqP>=ex zI5kd&;*vLI7dan#vPpTTP^nAyEhCFZe^MhmG8c^XFTEkNrds zzJ!!#vP^V$=HL&tAmu?rEpy?|eS_BQC-n%LzppbMe@OMNp*(Zu0xR&9C%41IIdK5X zk%gPlQ=Rb~n7teO)n%PA&_c(p#+uutkn!ktQ={kL`PZ=y3A~3YD=}ss@5pekc1Ev! z1QdaEI(|bscpj@i!OcX?@jPghxPs7f2I%82A53vfuR6u~0>zKLs`S8998&Rq&Z$e` zVRtDj;<%%+4X}Cr;Mcs;BTsQi0#WFZDdn`Mn5@|jlk+ZqYUFAAv3{kNI)qAg5L5Lv z2#Z*w);YwSA=uF}ro6&o7FboMbg``aISStFFu2!kWHcmOgyfXPEIYS3cOYu}z4dr) z92|-CSmf>h0JuWn;_&x2hl{(s`s^)+RxJWaYmNf$cPM&HJ@NaD1~I+^8Y@}}!mwTq zH=m24W7M;3oSt^bFXztlOdCyW(n$=ZNxhBI*MZrt<4WP6x7#PnwanB!p<5Yq|v3*>s3#l)P2 zxkDh&!z?AH5u1z?Jj@DWnxYE}6nK~miCK+)B~a*LRuj{QHNUloxr`W%wk}ZQVb&4z zEV3d{>|w4VraRl~QV(-2F{i?q0kaeva5fUNl=^h=Xl@iPblZWB9_D6ZO0mci=;UFx z5pxyO)!D=BB&Ij2XP}FR*-gwO6vIGQ53`4u%h&*xd6>P#e87};^Dqw*vkS#J(A~p4 zLd;mEy@!W+jF|q^r`*FlMa(y}e1(U3j+lqg{sww`n3sr2!=NkB&%+!h<_J@IqKA2n zn0FXge-HB(F@?;X0UqXEU}BfB16su{Cw2^(;3SKeZ@apqZ^EEC#(AYyY?t*W310B81Ee8;hh0rvNESB z9*PM#D{xhFKmmuXQ)FHR%vr!}VZ}OA@$^f;xe=JyxhJ8359Y8cmU9`rqqs2?J7XNY z!+0JcHf#jEeR+B#)_EGdGk6psHfuS&i+B_uR=OJA{@jlr(3Z{heKt4oA^vPccnSwT zk4rZhaE`(#18(Ca`3Vp65iy^#Q+vw8dsC4_f$9 zhs{#Jx$N77(6~d;BFV3jNsQ?M4WQ+zp2ygS~y*x8NOqk_eW4 zTjw}25G?z)&hftp#C=;z2+PG}-571`d;PK4U{8~MTYDPsE0c*sA$yu9!b+$BVF(d& z>El z@NWfDv;1}7b#skc580t$FUgi*FA78)k}W=jY&if$g5|A1?$C>)_&-7MV0l+yB7@)% zWU!Yl^WlBvWDzXc66{3`EzI?*V6SrpVzy91Sbs%rw!wRxDGruPwgk(GCKIzISni3i z5)OmVf!fTLU(qsKjAHT%*j~^D%iob$7=iu?P9Nk(c_1C_RUn-(t=c#divdhRvSd-Y z72C-qcFzIYGjWI*#=5*Y7Y+u(dFxIr+p@-kXO>QDp1G8JSs? zRYi4GFU8h0(9l44v(w$s$Re9;BG~K-2!epfqJW}~3!tNe$jFEb3L=UNIt+>k@do5tIYcv|zeLD{*xP`o+Xgf}AErrZf7PKPqWx+}bF{K}(RQs(x*Cq6Wi^C~ z$d=WRcMWJ|KYHlDvmf1k6v-}mgoXF}`%#M3RolFB3~&kZ#f`wKNEIxV=*(aIVI!Zyf^_IDJm2;Q7*MR5Aql^yk= zf3u_Bd!HV0Q%~a|JLqgX85Z?>Elic=?AwU0a{QVJY$o(9&c-z8Bn&FQ2Sah*t~{={S)*YWC2sHUl{kL!#EMvm*8%czXwI+5;I5R-9S$E&}pnx>8% z*ICZgJcF~5F&W2owi4b29bk)LlN=0?8@y9ZkxdN#N$2+lS@4w3cO=L-uH!++na6d! zhK0mvin=_mQx~ut*C}H}#&MmVgfouo3?ZCxT*qrPkr;hk$7Q|B$plZIOz<9NP0-f3 zmEU_rL;6sG_o&12nv)6MW2^+(&Pj`qlL?+anczJ^U8k8msUgGUsQ{BLX(qI#UGHQ3 z=IN6O-ZpAH&1AcV^vMM8SsXM=+6-37$Tg;O(Z`(@fsckYTdN zFwrw3@9Qx7VeO^b9gLuyKMCpcC!tn+eUlH*pM+YI6qO*mbw%$| z>~+vl70?w&^loK(`g(N55&f$HBL#HDfkb}qo8K1$HgUxfy-yX;6-V?QWxBiqy5fl5 ztK^_;ky}7l9MN@YPISeAL~n9F#8dMm6IUED?TRBdWGDvx>^iref)C(BSL6{=`Vh^q z4FYLb9I@d#j;=UZ9+y1D6-P|F;)q>HG+FUWLF}S?QiQZCj@ZRd3oGr4BQ{r;maaIi zL7My@@DNuV(Z8#D{7!_wy2yyEjlqGq;)p(?3b>07e|369@*u9b;)p(`3h0Uhe-{9U zVpuK%;))}tU2((~1WI^Cpo9zk64Dh%>`GHYam5i^q#>SmVTSd^6-V?@)!;Kga^E?C zhV+?%zieNHbeMrKO`wq8G7x?TLKf0h2Er7$A^l_^O!*p~$k0^?S&djBzAFwOy6j|HU@)fY+P?#50tpxhz(-H$#lID8%yg-eTs*;-iVE@N!J^(@oeHnJVP5hjSX5m zJo^GGX zeA!D}ge8J_P6J{LH8ECgAetVFbWTiFARKk68M$-&Am{e(0GX${12X5SK7@soN-pvY zI1?#jm*7E=%Q|M+WDQU?kPX<#EY=-B3>C;_6L-LU0&&@d9HMR~Jl%Kk7=jYHNOY-? z5zRzgHc7LvvT9)Z(hS@=Z9R&X(^g$DSo3v2LVbX<|Jz+R$>4bsQR5ok_+)5c!b4eMX@A(Ka?S58yqiTiXj_mtdOG(p`jXb z<1Y~!#sny7drN9cvJ?Dz~qBL@kWRD4@MKqqlM4DR#dUC8BR&9fkW z3zwZnQ3$)J5F)dziJ@37i|6owuWtgx;AMfhGmvdOm)RzIk?)N?5RAIyo|uPh?9KG16s z+DJ45>jix*&<`QB4Zl(bp1`k!flc^fKjcpQ`3G@)>}7zDFBstCXZ&zn2VA(#GJ>9k z8*FPdHeG}zhXNKLI`dG#%4)cd916Gr2=`??)T3x7sw93bDngZTDV3J;Q^>YdDO1S= z`7;DQ!17TSRl;u*C4@m{<@|_1^$J}V%T3`k)qw|iC`nTi7RsgwR8y9q^8~-vK*GZp zxxHpUy9WwHe4-7$l&BUA+I!b3YZL+w16Y-)y%ACU&#uN~6N7)UDlwg@pT^2tR>jf` z5@LLkzX0#jU+x8ehxq9uPs{_QHAkK_gwAFNh_a@>jmX%)@E{mR_iQ?w+V}?dl4c{F zP1aOms6~C`slGt$Y{((%-i4=o0+6>MQT350qM3-DO_~M1o`J9~6v_sjKJw(#va`_z zlg_3G=(48%5h{cC*uUc2XD<-Pcr2Fy-;hSn^MJauP?(6GW21@j^&A_0xj@u2IpE^~p6*6G zW;912Hd;FM*l41CJ*Qb%S?>W|&`7lN%Tct{b8Ix(QqOiD(Cq^d74~inCrPh2dC2+7 z(dMNE8*asfH9-(7#e*OvYQd#(6zU@2RyW~c!|A6}~?kbihhL;m444f%)HG?Z<%Bm=%LTJg&*%D^mIN8Q@^leir% zJ)TpFVAQ3BCB{D_{X7u<`+*p%6NxXP<>j1`5l4(Qf^m(og)^Q@Ms4oKL){7UPYz_0 z{{?+y%X|5bXsZveF&;ai+VSvOa*$9DwaWOZpxMhzdf;9p9m^z>Bw4vWye4rVd;>HU z?ruEG*bLgMq79&*LfV-^-(G!oKQOZhEi;%E_W*Mdp@#+2tTTp=Y8OOHE+pn(f^Emc zYso96NL5w`^)2I9QwYW%5*j(Ymfdy?(woC;%@&Z?napz?X>MOfVcYTWTJk>9;qY2} zwUbiqV%%1VZ?=OmSE7SW?jZv|Jxvdy#}AtTL8Eq;GbJnByqYH%!)9 zC)J17B&j*PmQ(1U*=8PI%c;lnxqj8k;kBATRL;g@FjoIn+YMm$m1day1lhD?6fP%_ zQ(!GG24LL6<#_@=pUdt(3hA8trC_D4? z+BLve9>k+3>`_%R|D5%r4=F<{QwAJmYeg#TPSv@$(z$0d_hZQ1D!Unv%4UU@H5X=~ zjwPG&3|6g$)li+hwN8#*aJ;`Lr=TN}`MQxCjoJZm%warQ;eDk}U@IcCIvd5D<=*BK z7;SdLb;54AL7L}8dkelIU5dEc3@FEGgmQ;brWgY4#=_dwi4749IhSFxLpzbPiZ56- zqTQb`j#GoFJlu3&{0}hs*ZuKG>kSxnd}#t!@j;-8nn-jz6RI#wA=lU0RBdLQ0+>6_K~&q2n1hyAS@PZECn$vG7Pa*%ElFO-FV^(MR{ z6Y}M$#xovlU=d`|Wdk0nKdVM{D*PCeya(5;0HLotX1nMw#u_ zB|{N07C)`D%F_^a60Px%OmUY^1q1w}Ho!>9tWr^q0XL^av7PO zpc$SEkP$eNaoT!i{e=?d{5$MtFt1y6>gK%vIRAe*JFXP4V3<5giI~cT= zoZ1P+y^~``HJFD|C1@`h(+OudSF<$i?_@}6%JVjokyCYfB3APg@wS#DRnh;?j#TAO zN1jqG(TS=a&pzRAx?;8?@<#R)8>yWB59nTkCpR`S3RTksI=unG+6<`quOevQis9Za z1ln==Pd&h(v*gg+cD(3RJ;?W>8f=xl0Ca_WRw~_r#y$szX{&WI-|F6vqw%Mh_34s* zHM6WwOYxyEwn-1#9uExK zHv5CNIkVC6KH(4A78YYf_M~37MCWgVWo%1pu!_2S5Kg>=kyu_X5yzZ^$78hS!~7h^ zl02COUHKflO&``ck zT4j}Sn3%Vs1pVhPQy z_{i#Q1Wm-d;SX4L^6tDCQhVRdq5u1Fz{I^*&%s>6d+`$bzn`@L0|+mCA$Hk$Ymi%x zSA=k`htpp0fB(un`oF&#_?q6Um(&0K1833yeKvU3@gB#suJ;AXkngPkeLe3wq%H8i zKA-;Ye?+)}R}1)t-a_P6=sgc98hKrSZ|sfvBmLjUE~Wqbp};rw<|40V-hRkZ>|KRY zm3Ym8FZCWr$(wtNkV^}%?q%3T?X86Dt-JzYT6@z_sy5yVq-yIGfm=Io+Ig@`?;2>J z+#3O%RCs%ls=fCrO5VZy9Q2jmCg`D~w;!cC#v6a8vO0NpAeYWw4sz_`6{2iiy(=Ky zv0hu~vzyljQaoXKi$L_Gq${9~9{>|G6I#~ZZ(^qz)NR^mENaz1E^Y@#kp zlGs*AvnL{P&I_38HRobr;)yqjWze02s3Zar?}Yfo{V>ac{t_y)^#*AOlk_k5AhK${ zus(tOYDtS?Art@np8Ocsd?y|!-A_ATq`dbw(9k>ooreAex_a9?2Ys32jmI3r^`6CI zL&)lT52kkN5{!IRnPO{tol(W}Xa_*0=a0m32geygSd zY%kwP`babEpj+P1Ug9yJQq+$I-I-Z*ly61OlE>!tpM><^;MV|ow#Bb=Q|Pj(0j%P= zh2HX8JaifXiqZ$Lx{$SOZ#l#VDJ0>o4z=U_}RNl_hm1+$Ycdk|?V;3W4(uv4+a5? zl)TP|_UgMCw0~ACKSmgx?*+v>NcRzbC3if6yZG=c;o~(1_&9{0E=?C6)-?yIWq25B zNsQJ>{-+4)<}%temoe$)k{@d6M~*d-S0Zw=yaW}?U$BWX4B}@mocm)WEM@EI zfOe?c0b$hLYsv_K&#AWoI!hj!r|si;V;}wJ0L>b>0^FA4C-(3c16cj9GtrD%>qoCL zfK~GNWAR8$ltBxf|2U{SJj7bwA+@}tx|W&!HB!qvOfBz7*K+>1hK#Y3q0{oo-++M6P=n;zev~qEfWc8zZua%_zKG`@kq;HU}1%yOwd^&cK@y z(}!k|vYFuYbfT2aD2#1BKyy7C!P*R1k-DwHD!N`-JIV7W1m*$LbP&y>mVFz-Rv9<* znXm(@RlNm+A9K(E$-QsO!l|;952} za)C)bISK58XbkQrNMUw(H5rP8S0f?U^jH9XZNOiWn3KQ-G6Sk*iyTFcl}|bDLVc+t z=viQy^rXv=yb3{_Piaqq{kcp*_294HSYr<&l3GcR zU%M`Y;({`zT~MZW9s~xGiVMoriyG1{C{r(KNV}j+z05CG{47Bil&M!Vq+L*^0xl?1 z0T-01x4O1tI_-io_4YFz327IUsXeSGOQ7nG@e8qzK(QwNqE zLrU#}GWCW2My_2@roPo`(Jm-c-`ygVbU~T=v1xmzq6)8nRm4yk zw9{18g#vNalj?-4E7X*`21xNLm(riIQUi!)BHBu7fMH=}y#YestK3nvw87K>vXxa& zdX;+@^ig3izR$f?)P9P}6W{0FD%p2=2V1Y~yIjrIR&x?JTi(qLaC+b68czFa()YQy zmYdP^zRP>LrOe7Z6U@W`xA$Ljz+LMRBep255k37eIhH^jO6VsTK_8gm9W}2#aj!i8;hNq-)ET}wXQ`>x&q%Ql#eg_VO=)MT zsabwe=qxog+Z08drKZl&nQLdMsW}?rN;)%ezrjPCrQ!q+=b)*zx^z~Y&QeqN45-k} zBZ~pwd3#DbZ%>t6E{)j|=k2LdvwKr~0j8Rpl$vV`%~d;ZPgTV6v4jUc;K7lFxB$Gx z5o=02VolvYU$V8t5o>CLk;gjGIASGzl{jKetxLTGpnnf=Nv$iQ57pE53T z2Kyp9Pfe|R9>JRQoSIrU7)ffLh`^r^um-bB@*T0J))kNm>VsU^r3j-t$cT{eT0>rd z#1X4zN66=hu;m^LrhgfRj8k;Pnp#Jg5m{3ac<2QEB_^dEv8JwPjU!eZv8L8hB>6B& z{aTlZY~qMDm3G9McL$OLi|?o+KuOns2P4e1H^ zNvH$yB0B&nGrh=q*G#O&WM7Ilg@5wF^AzCSm3X`}p08f*MK;wV@ai=XUcH6=Fq9xC z28w7Xq;Zc+iV1|C-NoO)9Y*G6_f6Qre4bs^nTz`B4%6*SuVe8pMXEilW>lP)x6;a}6H8oDGa~%28CdZMVmE!P5{H&(N z(a&mX4C9Rr3JGn{Ek~a$epXYD4WXaa)Z-t5O#4|KYPoz*522sc)RR9FFMd{s;$sAI z81n6W;J4<1gHrUf>f-^=^$}lK$J%V` zYH0D3$a~!5@yJd1^?RGM&tdixAhU18V1ET7hcRH0>}jA&&jQ_*`1Qeh@i4;#n`e}y zSu(RY2SnucCi$&-6#PbMeh;Fs|0F*KERsD>et!eqGlt)&qxelP9uJ}(5bi?!`aQ*| z-7L-TbWAwAAaWQ37Rg>EzrmoJfgj5^>nMIxir0gPyf%>Ev5$e@`I_H_`1tZ?@?*dv z*)H;11iHHnzw?jcH&IXe%c#ttAC@3A;;Ams_9o2W)a7z9JL_xA6Rb165>zP!L&{m< zp^n=?Z5(Xs>RPCCt}331n4gfg3DWkP!s+pHUHlhO>H&xx#(+h#=kY7GKu21tW4UHB zIHS5oJ_Mo?SV+G|xWctY^E!w*`3>a7fJKs5@jIzI=*VZyQGBNBPriEhAG<);GxEFN zAf^67G)R9T8nhA3oyI@#xUQJgGTR4js$w&KxD5V!tgxjJQ=0)*lSKA6u%iJ8^pWpE z58Di5`J>5vPAT0=kBks(m^^?r1*Db?<*=92m z+)n0F$uo$33qM&ZdBFgf8$Sk`eXza)&~uGzo1I?c`Uj%^hUG68NWF@&Ej?`>I2Hq? z8xX19v6<;Zl5xLUTtEEK=2vigHR{U+RUHN_()U|@FQPxy(TmYqiWtp+H3^~OzIY4; zqto&0gBJgx&3#9hQJ2mJX1&3F>SHalm&g1W_-7<B zFvDwp1E_G>GM;7Y3gDDPo%slo{9=>*Ye~{KyE}3{rV41sA*we{tz(bfhe#89DjunY zUkL+A{H$WP8>T)8HN~%#fd=@MFi;Oah*b{+jBG_b1I>vqE(5v(q3%R8aEzcY0s0h# zHsV)2!T^&1ln^@sKdX2K&}SlaF3}8}O?2rW@w}O+D@*{H-w0B&dW?7m9>&iqUI+9R zgq|asf$f5R3FsFQ+Jj#y18?G2!oX|zp+)V*pM%8l@e>1lM4+G&K2i+uQOE!vEg9gW zBYsC**v?Pv34LLEE2!LfKN&qACT+Z*90zplWIX8ognz~Gu@vnThtL>9iILbC87iEH zn5fI|&tnes1)>oVaBWaPHwo=P;+)D2oCzL&4%H!D&Kgkg(57bSS!3G53`0ea>4aU7 zuxuH^Ij;ohY-`LA7=5VuN1E<9(mjcAf(N^BuB!%v^-$=O_!Ub0YsBVry+izK#IEAr ze!2YFo5B%vqFrwkZgPtrEI&80CR(D1Zh!6qZHEI8mTJa9M9Aq&Nw`5#m2i*Xm=xN4 zRtMQ_5^^RYa?IIyn`KpA1Wpiq3d{9AQjR$dX|g(UR|L@0$>k8*Xx1F=6&f>6Ya%dn%boD1MwybmTj!|kXHGfL2S-{r29qQ27al=o?x3tELQ%anUqy}&R zDNaXHBRNVErz5Gs9EFI}kyKAk{Ke@=YC5O%;&dc+9;eiDV_B-0Vaxp@Z-5+`k|^^)*Q-^GB!QN??42It}j-2%~JG znNZh9R1!vAis`1CrB_XkWi+j#kz$Ku<*}so$e$sb8ld%VQVCtneZ9 zuX0w^`TeZw?`Kv2@0?Y28===|`#f9Ze%+M!2b!{hup9h%5H5T{2zArle=;!Xrn`Tf zKxn!|XEt3XjJj-K?qUR=c#%zaziztwiB30NpCc}10O38zOq%YIw9<6qD6E)`>-QUkQ{>J&nNl=wJ%_zQ#<`CAtijq9t=nhz1 zO_6QRJ1zh!xg4V^chH@TWl(u8H;l^x#gIOr7%F0=uo>}yVyHO9Q_cTgr*%f$mZvZm(93BKXxT(!?oAxZ_X4k;RmSTJ(bM>)l_d-fQ^>E*$dlBPN zs?hYaPP5#LnJtGu7ndMzu2vlnSTc(woesM58zDi|Wp+8U5R`M`&V4G6=fs_Rlu>>j z&xt$tDx>{8o)dT0rG@4>aU>!yeuT?ejDVcTcK)t%c_JHsbtJO+8zSXIw)2R}tBkHn)$3XSpd#&g%&D zyqT|5uwiNNcR!m6%IO|PWEFXO{x9C(n)5f*^T#jKQk$z>?#jYnW2?E`m6ZnJ#EffH@mDl$9=CxZ z@?-pgspWBA4)C7>!d{8bv{$B$y0ogC23X%3^c3y2xys{aF8pN#*@(raxmxuHf_4_N z6q7xgT#UB4ai|fq8axSdId1@#-cwWXYVu~{sl1b?a=Yr2IC1HCk4{70UT3WJguD*Z zxi7l}G@f@Qo)ND;Vx!&?(8s*lc-HV{fF|y(L2Q<{aWeO1TcAmLSAj#em2&`jI@_p~ z?nZ;%gBtWfOv~vn?_1Jq$9XxWkiPE|I<3}dcg4%+(;Drrjuj9ZC7x;hnK{!&T}qrY z6Tyw!snPC6qumuF(i%;3wd&sj+83}AAR0ZITr}EUkvZ2t8a#)9oLdF!-#E9L^C@U$ z_op*L<#D&JGg2`-6vN61<@u4LP2`yB$j0f&u_kg{b!0aa={gftEP746WAoY_%G=w6+LXYo)wvD0HdR(Ob1zcK>i`3TwLXX5} zS}oH?UCNo$tR@bWqdYFM)cwFB#fY>X(_F3k!$CU;S&G#jO)h#|q{v*Xb^*v`+d5eP zm$t2oTfVE2D$_0Bt%QrgGZISD317J3!_^cGiMbzep(+@RYT2aD-WrcA#ZL`)4+DSg z>qr>Zj%UN)>oK=p67?b1N|x;c+pnWw6)V7l;2HR<+jxpW@z5B4pF0J^d(XtWK6eU+ zKiME5>=X>|JH#M8G=}$gMWYiBjo|~AGDr`N;m@}r2&FRv_eMM_-;k2YfFt}pF;KY- zIKtnr6o@OUEEGllf!RtRlApEtAFv4FG%|z_4!(ST~R@V0*T=|AxSv`uDm850m z?t&c*(InG%WD0n3 z0NI`d84e(O6V7k|Ih?R|0GXuM$8e+5i7^f!X*S{jGOQgyh99Q#Sd(-B8Gb}V+IM64 z(V-G&huGo876xS6O8{+ zL*nYe)vg}g(VC;~D0~Pb2YPpC3*uNWJP2?Ksk;exI#72OqD{M_rA@n|iDBLxmARv5 z3&b`}4pAwqy9z;Z^?*d;zh^W>U?R5ZGz%+>P6rAa={9{7E!(s^nrzvo?LMG;L-HVd z_d7hUZ;k-c$hnVG4O_fr`r<`8C$4p z<8lz_I)7y0o|2B*s-vFvqjD}tN1dd{73$>lxT4t;h*bOW(p0tCZEu&ZyO`IAI43HJ z99psgAC&+-2T~kqx9j4y`VzxAcn4pDubWos(*T>hoEDZ20^EXFzNJ*YIO$aRW@;Pf zv{dDrSt;%!#X;J9y=)VYbJ<4a>#ENVan;6$QgJTY_)wiVmp)X!UipZ}x$>d%&1yoN z3m-mZD$aEem9JMe>V)KWG6TiqT-or`#p80yCSR{I#I2SOLW20O7vFN5;UjMU4zLV& znw))erw7(TW(3wk&J3)DoTbYfkKZ^66+6>N9iP}9&@9uS;s?3#G@Ay1^9fe+!qx!K zX@^X4a~sN+><@#9ScfG~%T5fb$0150hv<47lCH3VFzpj2L=uDrrP0`$RfuFTnsd0bD}{x**VQ7#J_YuMPJ2v}0nNH^&A%3=T?Z z6s1J@+pNYS0sDqXsCT@>9&9M+tt$#9vl&rxMAOwrG~KrYX1d#$X`H8z-FI>eX>R(6 zrn^TQZCs9My6Pz3f-mjad@N3E{K^hI@K|3=MU@T@U)tO1{_gkUH-u*sG)O7$oC zNZp-{R)YwQ(9Hms5V2V;Ny&w}j-G}&OV-V^7h|q56qI&fw2z|32)vBh!CnSV#RQ}$ z=5ZAzi0`^B9=Ucq4ySvlE*B>v?PZv0(BWdc#}RcoqT29`{F<`X9iBpNK$vv8j1{5%3Ut2X#6^sU>&J3rBxxRpMC; zwXv<}FH5abwnXWOPKLT;Ln!FYxKr^HFB?Jg!&IN12u5Y`uE!gDJgw z?t^voBJ?P;2p!jp(4)*^akgHB_K8z@vIsrOtTWfq%g#O+*9*;l+PGf!9c7k%<5mk+ zfb>e;bg$Gc&?|Kd^h(_Vy;3)6c17luVj$Bi8OZcX-2%N*w?MCyPA9!mw?MCCAk!7|2LqAS1zyfCMuF5~S0K z1Tz8>7|2Lq(isV6_!6{aLoZOjT6{fp`R^CQDlI}MSjvvp@9^0_G)6z+s(Eqt9BQ6F zu8gslU>Cxvb4M9Wvcs}U87!TJ$mT9nw<^R$Z!;Da)ivx)*Pjbn^!bmy7fnnOc%t?5eJSC2{6kWSwqhx16hlsz<=tKr9-4UnCl zs*ztSsk#F)d4G6 z9k7zs0V^?(u@VCrD_I?|lGOn#Nv9JlSskzv0~sqZ>5P@EPFqQTd>kxLzgm24CI9_m zSjov47DjS8L`>2*La6yT4{@y)330V!wcT-_Beg#tZezQW!u*4}d*E_y_##5SHrK0d4QW`*>D! z#*arlX9NqBd&}T0UCK_q?jhwBSnBl zVi_r>K|NATr`01xfWFY3*>vMT$Y*u@HMN!}YY%B*tV*_Qkvm~X6G75MQ0_!f?nF>- zA2f3NppiQflsgfW+b1@1CxUYOppn~8YvfK;%gt^nu6|1xtCGEz$X(CKT`wqiy`bFn zf^ydj%I$+jZXYyq*9*#BFDSQ9Y~-#Nl-mc5+bHcE2?eNpGf8rJ zFp^6XOKvMgMoVUxs#MJ< z!C;wT0@82CI`+qSXIzdL`zE|^hPOo^49uSy_ykL6W3XOsKZAGLwG4cYS?6hGm|n{A zR2Rik9m~06SH;mEUXPdKt+pH#_6HccO)W>@Sq!sQF|Y|!(ODG;e1lim-3+uv2Ipf@ z$-W0K)pZiU{B|A|t*lZuzEZYrJ!53a#4cJJyJ#J>i`GHAXdSeR)NkavMZq*vtCH0rYA7>mC=05gEU1RE zpc=}8YVbj$1|KwPC=05gET{&b*r=f_s0JT2YVgwl(UY%)G+3-W9yTkt| zjHn^a)T*QniW)kYlpTU<=nzyxhoBld1l8b!Mh!k_)X*WQh7LhB_{2sH9fE4`L8Asg ztx-dVYBjLMWUJp4M%0jIYE`m*i5hwuHS`Rsp=VGHJ%eiK8B~K08a4Q!QA5w58hQrR z;1e4)^bD%O2aOv1v_=g*tJT16B3u2IFtQi}D*bwnTb1loL=An68u|p)&?l&dK0!6~ z397*djT(H=sG(0#4Sj-Y@QIBY`UKVBgGLR0TBC+O)oNhhn5}+G7_Ejh7psyzsioK|wY6pizSl8Z`_Gs$o!24L-3^!=RuVe9)-DPixdLs9FttA!MuH z5=N^b&BdzZ>qFEq#He9NPz^(ZY8Vn!!;qjFe9)-D2aOtr1l2Gks0N?ds9{J@4L)ep z;HNce7*eeUy0(a`-x9{^c3dTnlXBr!Z|ULSpw&(e5K3ghWTYa28lgu6C#n8`;F7dN zmP|&P;Xt+?9h?+ce>Pv_RMoLEc^<7~jy&|((=d4+BO8XKp8qJlg#P zsy9#~y9we}6O~c^N-`AlT5HT}ZP2{d2F+`2(7e_L&C3UkdHJ9*ueCw*S{pPkpV*k! z+Ms#)pfN8$tue2)Y4fV2@FLH8BhUJvJnMt|NFI7as& z1o%PE?7R2~sGBqsz3*ZQG3k95Q$7=j`!2{K>Qaer-7fGdfp?GVPSN`=rVyRpcj2?J zvU-DXH@MT>j-r))7gNYq_FWX>`^q5DM}@t67J}`t6u>-W-^G;u=w^_Im3#@`lH4g5 zfFQOQ4}z4)?7ML3>*7ql8Qs6>&-!ZvpEK_+bIQj}XLdRd~8>y2AAl*4VOL?Frg_JivRi|EW~I#Xh0OUy(RHLAy_yZ?RUA zo}k?=oxlp$d4X%sMF^_%_z~bmMGoxkJH8@QSH3lzDM~1Y*!|F7Uk&1R3B=aLPxsaD z>b|ca_B0+tSR=8_P=%q1a!nM*=xP+NK$)Rqn~b4dtb=8{mFSX(;4 z%q5{Ts4YF6R$Dqie-2bSlP{Q>{Q5x~FekW6sVNgq(idTPm3SiC1>watVOU%fhVS5h zFxhapnwz@BHDUN}Zq3pg4%cvlmAEDhujMu=z2Wd)Zg#Sgbng@1uoo=hcLC2NopwiZ zS$A$uH~q=pjcVWd(E$sLg}U@-aVd;9+g+ti@V0=N-0qu+>=(JiH$mAia;N@=j+0GY zG39aZ8V^>u*#=MdYCNujVMpA*YpxFjxISpOTFJgNu!nDwl&9mFZ2T;k3|@<1Y%3lF zsng7ZPd@^GVlj5vMn{F{r6oFs7__(0jPd7N(Q#TfSA4)kCuoTNmB`dB=}tuHjfC&9UMc zP_BO!?&a~*eMci(2CG$8MQ^Aw{u*wM!B5Av({UrpUo8diGMlYe4J|*+omb^HTe_+$ zANe)@RM>1ID9$+;B&NWqF#{^T8ydC`VBPFPs(Qkl$(CwwGfZ#CU7x=SG#zZ(3cdj$ z)ho#QbNtFr7>Ag#HjN+O8Y>ndF8lR(q%VHDXlI&YA3OaF-05+aO=AaTyAwb$9OhM? zQvwe2ZJImtDu4cM5L{xj<8zi=Jr8{e&t>SPGg=5O!>M#sCgv@G7~dU#V%kRNcb@OZv~^LmtC4OS zes&%T z?F|pwo(~$^^Fd>K!-KXrJZO79v9Z13LEG~|V|#vDV|&BXwpYpOpgiz0rk5<&*nuxN zYorPCV6SW+U1MjCJ&-7K?2!h|DBF)UqwF_)o%%7Rk9(7+&hijJA-oX49dMTDEH2w+&*aJ_CX`} z&Y;{ogL3=CM(&+KxqZ;c?WZ+z@2r-aEjU~KrZBRalV)mFvb~EMb{jS94ys{yPz}3- zYSs=)`18vL|I4ZEw=z|JaL{gyC#X)(>ks@#QS zqK1P;4F`j2I2csJ!Jrxr2G!t$Mh!k_)NnAUhJ!&h_{2sH2ZL(xL8Asgtx?0lv>JM5 z4Zu6f=4kO7o9E#8cKcbs;bgRWg%XM?+rfJ_7sO^n@d1L=gL8%H)vpNl>Q@AN^(%tC z`W3-m-3PTEz*6^-S`Pp-dqIGiyj7Y32IhlW59zd84*>mMuxHH^poeF;txP%W z&Z&dQKjcj>dRU=^qRPGiV}yJV8$Eo6py*+R(ZhS0At4?eNc!-}9De9-8@PiyqBqFN922SN`!xP}~dc%F|sI4(mE*D0YGVi#f9-WbG2 z4__iEdbrN$;kuw6t_$knx}YAe3+llKjUIf^=;6Ac9(x4ue2KBHssE4IN zJ@}x}gAW=#EDh>mX;2S7vC+fQpdNhC=)q5G^suyA53Npw9`51HtA)d6NF6+vp@$ol zPz<)aVa!+tVxtGU%IM)nqlX)VdblyDhZ}=>xG|^)A2fRKL8FHogL=3zs0W|e=;6ko z9(>T~!B1=SaAUO|+Cv`o4hGk%lfx+%b?{+^9+oSi7-CZybBUF;`I#zJyuni7h^C8ud<0_lg^XJa;UI)e81m^xGr!FlVNNYny9ttUNIV1zWD zX+~Mog36i}RMxbhvZe)<<%339K4_FREvT$%L1p>GMp@H>%JM;@EI+ML*0i*;Dm|=m z{4bKH=NXVkRk1S|>~K2Fia%2-UoUN~RGOlgcj`DR)tR6-_j1~Iz-G<{td~=UIkKEG zv|M%(4VNw!s~dXS$VJM^Uc-#;RvKGa8MK9!L0ecEw1t&HTkt_+3qELUVP()3Rt9as zCpNaQGH44vXl%hxYiwa<+7|5XVeBJEgR%dSg(X<5FC?|Y+*2W^ahTg@KH`(~kZY^+ zfR6nc4}$zFYZ6x4VQ!MnY2B0fYD#7$KsJSoqsNJln^oEY4*loQ3s2wCtI#mFs+Yk9 z?qTnno`{svzfR&4Ab9NGXWcgot<>qRe$a#q;kvc-4TKZf!!rrPR^JQI5#rQ-5%A#n z7ZUygLbn$X`jA)SI4?{KHP-9!C}fY|J$_bAt@JXrj{!40b%bT?A9B!MsJaq^9JCjzt}O-P zhfH#ax;NqJjt25?7_PWZ7wvYc3(-u(dUm=P7FN~*5MG9#ysnO<70(@A$X49#(gpX` z_(g@iyB@(YXqwDJ6w_rt1Y#3Qvah|^mx!gTr& z!_x60OsDTSmk>oF3pXF&_Bi?hr+d6V{yIH~VMZ<~r=cs$cG|~7!;rQEE0&z-GQp|T zkoGa)bet)1k@yJ{z~mTRQT!zO3vx+Zi~>2sW`ZFu<^UpmGfK_FU+Q;1j<`nlF?7u> zym6)QJm!7g7-x07_2^Ms<2WknVKwWU0Xrmq93LR8{WvDHAIBG~DRPY;$L&BRv>(Th z8EgDFmf?jNbkBIMuI>0%7>7HQoT}Y3GG(=UMjhv97w+y!UBN2q9$-G&P3IsWjGIoo z*SA>LCv2Q-6PC|RV}Y~}9Kah5f!K9;5a9QLJo!GrZo+am0l)enZTNioGU)tafwq46 z$mm?acx}UEli2ema=K(Ef>HN1JX7SG;P=YV;ExcD{e*}A`7$$~a?gCe4C&98p)th3 z!sYX2DDe3*l=1nJOcT>y#}VF~0Z3q^u1Sn_91w~6cyWev*?|ijL%`q{E z1UXk^BqqkXgo*!!RUu90J_A_%ZhG49rdLEQvkA^P6`qfpuo9>Un|gkc+_b_I^q}H2 z_*D4g;fBP^3X~`v@%up4T8GZ+S!Al3@O{5}H|HC*<=9^nMqzVU9oh8WbR(d!{yJGl z?g4N1u*6r@d6LPC9~Y=j-D&u%20=zuI+4%(EkNkUc7&{Y?0{5DYDHBQ$b~em767k? z)|2mUZCFjXlB3?(pMh-4D0|5X^zTP~C}X8j#8|1%@GNx6zflkL+-eUCe&VNiQtsW=vPWuDc2y;!N9vFm?l0=_s9K~h z<*}D!ixMLFR04+ADb_)w8_4wsW_*$huH?v(l+kFUAd_qT0M`Zqt_=;>qldQUE{KiD z$P8^8&xdH{E{NxVj=hHmhqnA%B(H5$XvcslGxop2odBIjpCQjkW*gg^iEn`6Qj922%kj|r~>%byd_kFC=GGkx^` zSHhO~@xK|IGX3~(By75vSCIqXwDa!4U-9Gr90It^gdqL)zmI@Voc7}{;}%|b8ua6D zEi9E<&{P=%_fbYkD6kgjsV8Q>% zkH4rd?Z=-AM}K4d_*2338qpFeu$6{u!(ZV@ZRf3vtv z1|yzt7MB4TGC10!vomD6A>@$38OkjEA%ioFS@=T+XSj}|M`vc|&c;J#vdELYv)lMX zA;*k#8u}f%4I%XVZ3w^LhVXyqHiYDB7)31UiE%^d_qzoCC+`xF<%MvQccE_IoqSsi zlf<2T$heaa-KE$Mp%av2&Y`;%$a za_Bj9uQL6q9C{9|OLO8b6C~OU2HZjHG9aGh9qmcpxsW|4yJe2Nor^-4qN70KN#41* zPYpuale{xmXCd2=!6oMdJjC65$hdpQU!4yke?g?Udk-0R@A#|JBeDQvNO8p;GOpP1 z_blL049jIee8D@~7re6|P{Jz$C0yv2kiOuZD@_T-7re7bL-hN^3{&FcJ@lxm`3fNM z@eZICow4KZ$Eb+f^u&%Z>#a83up|65!}P(9Fa@qf2kZz_zFH?TGzZ+QI-Q{@-^V+U z;^RHETG+C>h4WhBOi-9_6y^kl|HHx`p!j$Db}DgkFK#jeYNsoX5!jLko5 zGWN2Kr@_?Y%>vG8G!K2Vz-*AkuEc{k3vjqqz>%c6S>Q?FwafUq;*Y?Y%asY8y~t|X%^aDJj7y3y_uZ_lk3~V zt7?H$-P7+07fL{F@Dr!auc7pJUiILglF_3h!c*D@$hS?_%l zL94+cr1&p5I!$zGhB-|>b85(-rC18_XSxOf2Wp5S4_@BB=IfO5qJf zqfCFM{mEiDmh7jJfPqNJrmx)#2y3Ui3GH;3N;4FViTN{=(gW(9jL2|>`gg(^u27#Q ztX-idv@299-MB(cCNW&!aye8PUhYlmi^6;N4*}$L!)9FDJ9!x>z3%X(>in^ol%(@Q`|Mv5UzWqE>LjK?; zx1UE!sW{Fto@xN6%*~mWT^ujejkI`0AbtCJq@q`naVg9GC$`-`j3|eJNGQ<;f5K%X zHkii5JO|kQ77w}4JEHINjoTbJqCXA4FI~Xi7FcJJF5r`y5)!}6e`iqpW&VM| znd|}%bc5mQF5vUa5JbtCfqOk3LBGtzpySEh8ENjto*r*yErVp(Q zCkCALp_LJ4kwc$J8L1&2S|L+A8(MAxa)$xevyZ`_&ed=sVXK1twuEeJIAinzRYStc z9Ry6`;8z&%e=rTf*nB()vXD*X#gEn8Ed!LbkVzT9XSMr2$42n_w^d^r5rcoSntK!Q z?ruDe`w~5d`cQ_7>LaqJP&3bh1Gc?PEc5yA5RlFsgq(z{4>xE+D>3l^yyjO#@ht;TL?{mv**jA0Hqd^`!6AyySRCg-w z4M2_gS=h)&xEfQ5VNG+btj5%v1!50C4pEoyNcVX>PKHL^8dK#XT#czjGZA}$Gz%;1 z5YShGJ3qo5Mav#Q7fgD9hd@_js#BA>FavwcXUeJz(ANiH8JXn*nMfW6`HV6IW5?q` zkYZ(w-i%1|NF-|Q1-o*2*W5D{PSB9lVE_j3(>JV{+p95+i17_z1@P`W zcwC;eGb)1&XaM|JT4Sn)P#L2^RAcI=h>ZP+2SMg(Dx(R;8D6%qF_l3~b!9Xch?PMO zQFkMr?#Vzp;mpb)y1Ft93oGk#5Y~9-h|2J3b!CvPRK_}#qQ=y#ks>M?*cY8H)%@wNB?@b-iJvWZiE4g*m9 z9rzP(Q&5d*M2w$=PWRo}cB zoU@Q3DjC@QZQEJ^&?rAbSSolvkcqrQtl(P_j6H-0L5h`8!8soR{}rqvuHI02J6oWw zzUj|u^9I)d_?AE0u@ZNDOpSkw6vmz!5#ww8bKu>!@C$$9kC__(4^65FL^Y;%26=1{ z9t2rLqw({AdUtnb|3*x;#xE9#8YhRS>*49H#bblY)Hu=A8aFJgthaz}e`J&LX|=}5 zRy2MRI_nx!KLm&)m_)XOvc5;aZ&HLs<6i=qINd`9&B)D%Sk3VuNU<_Bo_KdZwb%u* zrqUV_<7=@!@b0;Iyyj$fO#i`d*MO+T)Js4fyABV68Fsq~sPS&5-4au+#VrC+i{ub> z2jb~|iASGL(UQ|WKhf1%G%T#F2H5$v2;2j9>(gp2lC5a*IJ~ZFOf5x){kGK& zpl`Q?MT;GQOyvIn@);)~7@LU)!6WVVCgAx_j;oq>-k<*oLrvKqI#STwGbUQVnr_3& z*#^=N!6Kp(j$B)Xzvitg*H)!L3?q2g5}o$@mo7Qj9QGpZ8ANh@4S4_ueaJOdOe>&k z6%)_2+J>Vp(_;S%FgeE~`06iED%tP`1^i_M+3@9C&DE;^2hb*Ab=2#>A*W`6CUbtQ zYIZFG@1R@2E#!_jt`^ovytCheI;;loBBtL$P)9Dne{bDz*qE1^3WT?9DN=iL=0i|# z_6?}@Uyrry@k4MPAN(8!(8+((0duRXRQ)uj5i$5TAElo611KBpK;+Wd$SwR6{(A$K zAl4f;gW2aUWA?8NWA@Ks3hjE0Ps6m?b9!O+;5D8DLT^6kBVOs5(4lwZC9nkVu?5hr zHw83tug5W%8UIi4wA>^Xo1X89NkL>)d?5DwMV9FSwiVx407F<_6Y+dG)wmPT%Ek=| zMdAl)0a|sTKyj;N??}iQ6<#h$)(*g~smSy3~EL7{e0N&Mk!0llW7()idAptttOz`uFC;XXib zZ)!ry7NIjIonuAzu-5FNmhqLJBJM*iK-+kyn*e>Rp^Es0%weB~I>xW;0_eciO_{Ds zh^IayU+8tw?(vORBko(RqT}KZ5&CYaQ1%O*ZAE_kv5=`wKuf3x#kthb$TQF*MkdC2 zekC%A%X;iyo28)htFnL-f-NuLkk-o_3Xd!N0-PHj4_n<86>K%rKM%J;7)f)!! zBI|BMIqK1MLS)@x1hK+`^^Bclw%k-B%lZr2aw@V8yBH$t2s0w9I|2`(jwQG2!8kmNgO44g=_WE=4tluerDy(})=SlfLI%;N1uD zcxODgM0&_HE7HTXVHw%`5c>PVez@$KoEQM_3oZxm#s8?rG$O|5{R;5*&FGlELLe4y zjEOP;{x##4t_XfQiFVK_UXB`!boLjVHvb7w7Y(`bRj0wgx-uKS9^J|0bd3~O2AGi^ z#869|&P94m7lm<^ZY*`Y!0Ce>8g7+4l?iYB3(Pc9a?x~D)^=l=;9xl@3ClJK4QP~8kh~}LY)#V-o zT+1mSiB#zts0!48flvb>5cLFcY&aeS*y$K`&IRfd%|z>^ikP%ssxA|VdLf6X%YwKY z@R*DDn;WUpdZ{8htrwq#mGv&r33NrGmm_IKFI8kKdbt2}p8`O8$J33XLoK^l=OKEj zO6!IDxg%965X4IGAV`UfUXne4Ylf;;k(0bVmqAnBt!Ne)8H_>17WDaUaknQ8@rUhN*G-%4(rSNBH7Q6H=@%zu$C>arf(rxE;--D~)IajOzu%Fcr&P8p}EQ=5Q1R*46} z3=2OMsPF1$4$+BW(ey&jWPxbm__zVmy4+l|W(V~%Hfkn!G464RuV__@m|Iwa zy~KPe*!DN}f|QR)+|c$DuLAIBKx7uCVg!>uh?z_B8zyV;E(@j=bgLw-vJyM8P!&1j zL5Z7=YN2k<&u88I0SLcNiLqt_k+}O^*6H;bal}}Q88<1xbY#@_Jv`L=u-D{3t`0Ka z0h0Hx)oF#>9I2-6f}mqbJvF1W>m_cmCF_tK)OHwIataCN2vG-B#u}JKXr;l_#0p~a zB0`S~rs6cRKNr*PNJnJKq?iI{c7-0~jPcx1h8dlT`y z826~eSG>nmpAx&5m`?<2>P_POdK1}(Smn&Mf}iHqUM#UBzhR2J_cN+YQlZL5!Gsby zDNthjB$hrB7o%*6+?GK2RYr`}6o|y<(hU1$#1UilU|b6G3dei=Ro*XNR0I<5Q&rDCvlBd)p5jFE)a=#$S9YL z+KvFM95mf3U`+#*IKK)flMq$NTt(K3 zzYybLp*Q&rlg-shbrnidRAJ)=>^PT$GU{?2EpZ7J9um3t1L0R8G1lLJNVLNXE|Ie{ zBaRqr8{-`oUFGfS{X)>}jBc{K~o z_zQK)H<)rfYjhnk^*><_M|PZj*~oS=?ih)$sM{8)8e=&#xtEwL1#9X};{1ARKtj|T zbJb0+FEM-HLeg)T>;aur*PA4*vfP=Vkvm=;eaEXaI&<3OLzp)4TGu~-I7avV1h_TK zOq>1=)SVbRM;v{}t23Gye^BX+epDb1D#;=0vS99Kc*q^ENW>LNXEf3Npfb(E%Bs~4 z!@Nd%+H@2x2bIofvXyC5AJ8=fJq`l`<#tCp2x8SiFgZq@D?^1Mj2KLmwsP~`X6H;G%oq9>{o6~nGI{sI8xl7S` zg-o&S-by@BfjnN@DS6Cf9zWxe#CtCiK0(d}h6n298GSA=JV-;BH+;E=M4Sa#EI4 znDWU`w0kvhTm-N7jJXlRV$_*cem$Z(y8NDh%u@)e3qQi{K9DNaiJ!2;tBCEy#lrBa zZ3tTBj4kK7p&9VUJ_Y)1%pPt=tp3g(x5}p@-*T4FYzZx=zRD@OzelvV90Co_Vc4RTIUHrKYF8ep48hp@x7AXXq_#sz$)s#gB%icahjV; zM52}ismjFH&jOn>8d$%hCdL{Dg!>F0azm-3Zzy%%4wPeepd9az9a^D2#Jb0nLvAQ_ z-qn!4q11U#LpW=~i$t9dUPd-icM_h7ZP0RVE)j{lo@2qjM$j)9G1dXb@e(z+d9=Nx z!>c3FT+&g85|Y6EDzxS-xo=(%%6uNEH-8?F^gR0dy>)VbjKEto~t0sW2eu}O0-(H*AgDTvL68(74lC0RZY9p7q_8tI@j>pgH`#dt) zj|G~Xhu+6)_3=-uHT{s(;fTIZfnpoR2|17O#Y-yG#n}LZ8_wTD__@*|BcC*hs-O71uCQ}b>#~njC|B#wka!xz$X~@~d#Ni>=xy*-2pd&#|z;6Dt;#vgZ&x!*;VLkZ$;J(8Bp=(L1eQ}e-(kAC~}r!h>lwa zPUd;|jc6&B)om_1<;57Oo((q^#aq=7uUno}g3_RP}m>okBaEY$H~5 zPC-cu8Bkw>@d>l`W2FG4>4`SfPPqL)_TB_Os_N_?zsn4BU_!{sP6&i0kW4}d>m-t} znF))sWhQJYWF~+jOBNQZFafo#$^dE?O9J|Ku>`HQRtaFOZIwX9xAtYx)-D=EZMCn# zrPa2E-}gDoy>|lI*0;7F`~Qn`bIS_1tDfrlX@=Tp1kv_kaI8X8{@nppAl{9m+<;;brPK38Id9FbEW-zla0D30f=x5M) z)_U~dMh`SqbNN&myKy8jvklcghfTAKHcsJL6ReS#PvI3H1OPb&6MqJSCoyF(GL*ES9IYQR67O#(lW~%x zjB>Q`RF=x99RV8kMO^f0So$8b$q!3x`ZxGt+kTAmZOntzYDgN{8&vy4-a`7_co`fu zUGTbsMY&$p!9f;T6{~i5~c=k1rss*J}~>`KR`{BZe5=bm>^p^u{4a5|8P=1dVdPD69y5Cbu~BnQx(lEDo|F^qEwJLL7###!VB7xG@05@=Hh;gT1&e zYRF?LW>PtkY*!b7xN-$?j|DW8Z{Y{$XKy#GjLd^5GwIglNt_A)ZMS~UQ4T$B>+)n$ zj&>XwW!_2HOz=JF3#s`z4x)g+8+;)Zb(wpY3rv0vUT?mbK#D;o)+YjD)?ieS>hvJW z!GBRYLgHCgj@sQQ+LGMT>!?V! z-arx1`ur=J(zx(C_d<#gl#h`}u`LfB=kLJIqYqiBNq;H7DtJMk}&$USO3#p&7hj1xHU-~12(RB{2 z9-+C`=g=fQ%3~&X-$*p@7^i`Ers_ zRD|`>3Msz3Y}6Dymq2G(A5f)V^NPk)_!y6&+CaL|%==KsXn~7uA>I5I>|6)GNxVQx zRL5Yt?SXxllKdAm$)sDnC=QvWFl|y&7UFj9P&9lRb3_R&@f!TmW@B0moz@ibzbJnn z!iC|pvzwDpr(-pBB@h1ejy*i((z;PLVM5JRWEnMfQH?iI00{hqUGI=qHji;oDf05v zpr+(P-Cw}HPe$#bYaWZ%K^3}Wy${aRL-5`XKJF|NEEb600P*9Bt4w%uUaPQ1FW&|b z7tPIMm|Ut(Q>oAZGo%@!38aB=cLIDJ^4T#L&C+OCO0JX?-Yg|Wjs?;0D580FHY=og zFL@Rv-@}QFo}tq!e(3|ElPNrQKU1gReLXbwBoqOCnC=^axm^ig-UDcpNjEyRo;46{ zmf{B;3ALzC`W}RwtHdpEv~=tLDk>_eKsnlPkx?>k8nh^!?%|7()N%07)VZ;b+>%5(zX#Jecj ziR|uBlJ%fYIY)Tzj7SZ(XHcg?PU$n!@jU9wNKGR|*64I3NmV}-)xqZ1=v1uFoq>k( ze%_STcB_&-sAsI9G!+r|rLapEeR5#g z0#J8?pVMZ7-xG%j>k>LM5S|9=h z*TmK6Az{*Ac!qvC_Eb79G|PE3t^9&$Xyo09$#f-5chhTv5~howRIJSk6g@`7xkIO! zrJ4Mbm`%FkO%x=lo(CilYtntY@s(#Ohd;xfq`{J5>T{W5iM>M$_ zMu&co_e4!DIGP>g&G7xbDJ${y23`eg4+4?*p()o}_w!3{#C++8IXQvpmh>yrwEIca zKdTeW+zuO^X9YTVndUd4@O4Sohoi1Z_b$);mvF!49f0~B2Xz_Ry(HSAaU^YY}x?t@mqy>;hV^x;G%P;`H=t^2nn(jgMyR^|36&d z!1-q}QVedz&oAe1gi1BYu_Q%%xg%a#W=*kUmSOeLYeMv12E7YJpF6!Ppf=#AmE49d zr_)l7H>j%wtvijSj@phl_y)w9w4>6u5bmrO8&qMfsKjw97C6ljI28+==G^6i3R}u? zn#5zMrSuoHSHc6S^*J*MZVG@6z)zc)P!8ORk89dlLQ+_S;^icoYb?t62h&XP!8CJa z+#!Zc;Shtqkv0jHyUoRg62y7rA;t~J;vY;iSMt4YuB05b_sx}2o}#@^5b(MbTwM?0 z!ataXM*I+CC1tC$Mq$3K{6iVvol55&1|AC&G}{=qc!JMvV3e=yB_ zh}w#0%n5wru|eqRyEot#kwKI(9VD2NLK&{_<3|z@%1G`z6Z{X!By*six&y$?OkILWC9TRF#Ki<+H&f{QZsuU&VaQ^sFHD0I zJj*`CcyS1757mbOAl_sM*ds<#zf7Niob+pPp)^BAuRr!dfmbJWwO2kmH@oYkefGKu zyV>la*Q2hMm;f(lmq+NntBV|9$&caoLDWbx(DxsHTzepZRDC2-%W9&xU!`56rFHpiOj>$#)yyNacJZkuz0nrE1&4LFVH>36Ltn>?Th3b_CEuy*mj;&KSKaX9!#Nb{j zKNOu+sGLbRI-xeJ2ij0OQeKuAL@uPfO#T*XQTEkTw2btEDuaCRD4hHO%EHKRwaV5Q zbWC9GzIp4^%Wz7n*NX1eK^u92x}zJNxaX`!)eha&+TEoB6$1ALezR-qmm^-vpfe3^ zvJWNg$nC&yD!mR)-)<0XX_I3pF^%plgkLEyx!s^CCqHnhD-$*EFlbHmIaAAD0#dsK zQcpl)T#u%ibfYsuDn~-0IoM?*)s9*O`~-fOei+qXG5CSb?svD4gH8XcAslQ|w;?`6 zZxrxL;7@;+;M0xXgW!Ko0Rj9*4&U7U<`!^ag4~9mI+Kt`6Y+m~bX*B9$9nYOzQ?m} z1Jp~;#wb#ri8tz+;dy2qsL@k%19TNn1V=}1&kMKWXwG9^j~5kszK=T0^Oemy9)S4f zO?aBs^T&FG=y|S2PJ-uT9RlM#KWosnM9=!qL+kW(`5Ydo^E9KkWKS0EQ#^XDuBCeZ zXDhxG=Gle(bkE6Kbgif7v9-F^%aa6{y**Fh+Q)MqIP~>2qJBTm-Dun2^X?{H8{qj1 z?lU|+kw4J$Mf8>FIe}3O@)RR~uxH73UCZ)x+oo$nJoAx1)UySB4fDK#u?+X@09M(a zk;ot6c>O|`38C^@+70jVoxS;yUg zHP2v_9n(AmG2zEGk003lRP$`YpJz}LRZf5f^_wFUJ>4DDQ%k|c+##J*a7Z4lWD^R9 z!@;b#7@UW=I3M93wrMe_P@hvu$4&ZSV>?oKontA1(2p1dLZ3732y$-*_xUn@oPFFb z6Yvb(gt7^)Rxgm)i(Bt6v3LNKg4YQiHYl4=NG1r6LsxMjGnL+Ng1<^?6~Bx^{kAR0 z)EDqKK;EZQ)&hE)g8M%GRovs?l{zY<_n?#n=E7YAbxc2M=orf_j`18ds8EgPm@ykE zYdpuD<6&sk7e79p9x@@vle`kmK0pus^<#V_$Lx{Zf}&r-k>Wy;7|AhfBqePqEG66M zltEbi8b9bqD{%CH94Z86{1en?jMtE|FnivK+3jf6gdfN3PMJ`c8S|iK!f(=FKf^IQ zV`DZDMW26%FgqhLJ7Zy%ctbmh6%tw{e?Yxqzrggh8HC_p-8PbK1{DHH{vE(qjJJ^@ zB>9H`&lw}hHpNkmAdgoi(xr3+slR5B6JHMsEAw@O4)SqK#HH2m4APtR`4vwA9+AR1 z^!q0@#5ZL^t2ir*si-T^;xo`86Wa7vWc?aHK?}*4ek;r;=n2;g%F)PA89Xy4kdusW+ZVuN5jfCc^(Yw708_6x*pd; zI$)Mq7ZT7CdZ+$Zu@?9m2H|>C;JY%2*(x!q5Jm;JLnfPNP0J1uJxnp_Q7&C5CiBp8 zDSl#&hp`GxtNb3IxNp}zFFgXxJw=Zq={f%}39!2FlK@-x5LV1{`~h$atz;=$6m_7= zOp~zqyoXk(oMST6q(Xd!W8rUgErwg;c2t}Y#LaZ9$zt5#SW{nMlB-9bGrd3Bj>b>Y z8@1T@5_!yK%SSP1oA(hE^(f|S^CVBgX-4_f3qev&GiskqHF7=#?f@d51)Xiuw*>%1 zJPWFlkh-q>QF%ZD(0T*il9zyb<{q=zCY5!`>Of|XRI(RP#D|n+YRNRDI-Fzao$3>& z+-qhbj!u3-XwleDyhntO9{7aMR*$IS5m*$`1lb-ix0bvEndDl~-HWBfSz<|?{)Le=* z@gu&R4d$14vEoPDOd+l+Mk1TI%sqg906)$~?v)9xqFfeJ(GOJd_hdqwJ`4CP$4^Qe zdKxx)6Ph$)dinzgl5A1al5B)S2RsliWC~UjwPr5)VHAcwpmq(sU4z~3SrlD(nP$8} zwrjB3m1vckwyhmQ{<%rh^MYfFZZxS-P0@{fipcFn;<4mD6b*eF?arChW@|S-wfo>Z zLJk$`bHvo1v!{0IN|e54ehZ~EwcD>l@^$k!NZPFacWP>HK{ie8tAPGKetc^GAQKu_ z6eznJI_5$y=jCf(>e7b9yqTzk{#<_*05l*2PEStJMHw;Hpw6Tj)3 zcc<~Ac^~JxEgk(riR#KR@75dW(@4mO+?%xYG+J7MRY+4VM^;GlU6QsGZ;kpj zmaf=ER9%rslwI071uHYjMPT*0BvDJmJ@@LCy1tJ-^w5;m1)4rtB<4>&51ydU5Y+rb z9JZVUY9YGOU&bAEbGgn*efPRqk?!4D4tgRom?4&7_v(d}&^{?=uGo;!Bo(S95i~EL zZN1S&81C-DnE=;JH@di!bPf-7LOBn0nqNwmhrZdhnl##Z)9caTcKo!Gb=PRx!-#s( z|I0;CdZzK6%prY)zjYbSF4fPF0)U2%`ik6q-kF?LUz^*xzCHHF4~ zOo0C0i@LUfK+}!3g)m))L&*Qa4Ua`ay~DUC0W$STQe#huc00ftzC-QkMtd4nDo!Fv z@qq86pWf(yx{eFo09#zYf*)af!opUYTzoYo1@c*nLiePLoJbgd2OYrvLUi^hsJ$Pm zX3~v*0-eozQMCfZUsw<)H=-5+yOscQZ_RIA!druwNAlLZmPQX74efe_) zpKkP%1V2{+0sM0UJ~W}pkD(U9egZ$?qWXhNxTu~($xo2`-}ng^)n8n~MKufXP9pck zROO;F-Q=RuL#5n7<#KZe)%>Ze!Cv&PZocGWC<+P3}PaCww&=<*DH(DkU#^K>hOK+5jYE);OqMZ=AVI8%Eo-rbZ;1n@d$8^*CK zm1qNhEp|f`K~!RgUK5FHg+Ih~f{U8QLyJ$9)Gvc8>wf`ql>2IIiHdZ=Ye*`Nar5J; zU};|*cjVnXYrVytj~WxITeOyw@ud zN}O;jCEHP<8><4dz4dpl@&Ij;h!OuEs!BWvpAFMz~ub5jtTaUC4iH&HR& z=xJ13M%v#_(Yhy&`5UR2ZnS-cGt&!WoZK=Nw* zsLE|_8ooYHn{_R6{#)km6br}g-VBL-`wY>3Sa9*m8Ra0ZL2qnL4O|JryA7Cq#K>;&$ZU@N9o%xb52cUb$K~L+Wdi!mA5o_(TyFjK zN8MyJJnFWruhfX9wPDI#$P~)|qr87mtTr#3;y-@lrVg*=otE5(>c>cqz3Qf%l0F<2 zey04oo8FkBc0He!-|*;ygC-G6(*xvf* za{=I2e?|38bPE8Cs;`G4U?G)2IR=fPNp_M%IlqT-?;XdVLUfyHloO$mt8RN!&R*<0 ztK0s_N&FQYDBgN{ICSZoeC6pD-DXntpU^t1l^;Sm-D$;|WGC6kDP2a&X%hF6y3Jh5 z`TqML$z+)`igHpZ-Y7-pj6qJ~<}!%YnIw4<2i<|&(5|7lT@HPo&81gQCC*)d+bQ&- zuEepcaJ!n`I+eI)D{eQwPq%qr!0q&4CJ^5M(c&G)gQDH$1b|=q?U#_FMqW%g-=jHI zG+#<6^yed|F!iPH!lCQkM7J3EG^$=q>!U^efBoVPG%veGz;sjzsQ-M+nhr= zpTnZ)zjD)7ahsLMN&Gr-rgVDeMdFHP-1emRV3eMMA*?5NAy$R{G5|dV2=^F~kj*hz zLj5Jd-0G2=nZ|P-$5vljfwSZu`7-Aks?z|W(u2RN0(d`3bq;`&TX4cuXCLfB3(iwi zX9c8=1!pDIc?vt+f^&@ObYN^2oYhq4Il@rkbAsw*Kq6Ui)={1NVM1GQo})T9!JlBk zsiQi-CCCcSDXQ}>_Mio46V-XuiO&mEXF8aH1?NVpvkdMa3(l{o&P-651t&^%zDYBt z=I14 z-yzFmFjT>tns-uW7bA8KnQn8{nmWiR!~Yugj@vL%g?U_~evdATAYe7ugJ|1j=MA_u zGHfw z$rPDnp2dLcPL;_7PZK56WHQOK6CmB`GMVN%M9H2q+1vA50@X_<`+Fu*X>Xa#^cE)i&1S(J8!y%V>PTY^=X#D_B20X_D zaJv=h4ZQL!&jxBcS*OW0vKDx5qU02rtn@5(BRNf?vBYyTm0qrYmsh?$^fI1 zL%J8B69{+eqdWLF{&TzLA|v5P&fG$TI0FGagGS=|pcGtB+>RQjZoAAiVYr}De|?}g zV{QgorKh&6(~oDQX)TWA57q35qasu2zu5Do=WiY!15u_^Hh?T9$V9g3Mgsb z4Y{Z}Oi*EOt;aHe<5QPJcfh(0t$;fcuDeI0>Tt?;&7*l+Rf;m#uLwXcAHhR-C4;<; zS+~i3upTS*YVQvzYo@}!Z7-V58iz7q@4f2VNX?$jQ_S0O4^mfD@l=Ah-vOkq+{{x+ z-q)yX&Q6|6^LEVy%(=}x)!TbJP3F9x@>GBC>(t-;b3B#lT}fpN{=!p3yf=OoP%4tU zQ198^bxlYGhx1gf_m9*rG>NB1d7r!=Wt9tgYK(V4Gg1phYJ#`tmyueumX{TKpZ^w8 zi*MtpQtwLybIJWYHO+g+14u3XF;4}&&)kR9Rlnw`S>8t|b@jVEHOD)GU@q(9AAQFuB}UE^IwSVykmsj!wZ6a&?h=!(_L!Jn?9a7n$1 zYPnssBq=o8deT^|VbUhC*2T!_LDQ}eMY|-rp!IyprRnEfLFKNZTv`TEmk0=Tw^A-G zhn<@wi@rofv^IjghN6C4=MPgkt(K!aS3rG^ifHNVBJ}kJ<QWKv_CiJqEvcSF1gHk=qsp|J0t7FTEv8WsEv+b$xmQyzEwP=;0iug~>L}Swvs5Pa(pPAZZ5!*jZ{p6yiXFijru*D|G%$ zm55YCk1;Vj1Ch~#NJiw|BXY-5E|HD^NDIctfWGKUwyv&3Y1Q9AWtWHF-iTbci!#!h zaa%!D^&QTDN%}s6pI(vv)EQ9ggG66CK8X5T)cXZB{ywiqbX}NZ!#X9Y^4q*Yuh$u>E~26z@nKMQ3M4=JJVBT|$(zsb{Y|R!;}20An)i@I z)_VhGw5D{Wj4{aQ1N-?|ns7bX`(`TpZ;r+MzU$CtWWVlgF@F87uSJl;8G@bB zC`ZBd8o_+uhswPlq1z9};+78nw1oH3jDB30;NYIH=}PmEK%;S%7)ZNa190s@kiSgt->wK%mO&I4} zSB1)J>NojTtf}{{Sy#6@zpA!AzpAEgP2T)}2)5N50no~>sK}f=KXY_m!MHpeKt=Ur ze0;@Z{n${J3XTQCMo;RJg6q)4RIi!X51OpeQ!^9GQ!!;jaO3q(@?waox}Hi2zn4B! z=I)MoV!AC)ozM*`rz@`1lZ|%$yF*2Wj*t0pJpC zaNT8RT|{SzgpVi%8F7$Z1jr<6PVnJ0lU?y1Qbax^jL4-v(qvs=pPmNw0K9Q$aDHU_a)ls_Ch zllOv6Gj|*sxt&TB8aN^1qXPgu&?AwM(DJc_&U zX(aM@5OJ^g-OxKvSEP(K#R)jGck>O=SL};^*1C8V!2b4h(_{}&G?PJ?(;9OMcR;mi z*g@#jbdZB$yt4bjVokH`PQ;oLG4o+?niF|L$8uCb%W8xr2{eSy#QNJju7{HmCZ%H| zfbWS_ND-@$dhsfx#V;#(pJT>p5_($ug{D?5UN4(-;*ovDb!ajAI0>(Bo}5zEj?;na zL1hvpI5_J7MF4n{U+1a=#jv#bAFVi<6}+mB|zmwzSz&9YPhY(i|ci$#i?Ud&<55078&jDXHI^DtWySxSRul z5Qx3t_1C>PPgd3X*~$TwOIx&q1=zIAnSf$n0~JAJI{J)H9k(s7cNlp!=D(4TDC!U;#Mg_0xCxH!pB?Vj=U*h?=m`w;@h? z8){*Mw!<79Avs)afNbK$oRkDN9w`VbM3OHE`K8q{(f^$7*IC``c&Y8|k3yoQMx@xbG znBA$O%D=*yZ%_J_HqJC*b8L-#uCoE}QGuE#$(a-Ad|RDgp!Bf{YkA}K^dNy02rF12 zdv*|EYb`uB-9o#vjqW0mS)PiwIAIwUi==M4wpa<==QL{tg2+Dwx^wCyN+|uawUUb|kml{9ycvF_5 z9Z;gPr5Zv{r)=jo4ozckMO}TIYu?u>`bnvk*0HUbNTElXiGz-y+A6afimlj1nRatq z6@X%^RDr=lZf1#P#Wz9-t)WV78)iu%(mLXaI6Ix!9pNMsn*)!;9&zlZ9DBJ1YL|0OL`!om$u^`5h%B;}onS*&I6_FK6pi$!>m`96~2GMJ7w^QcdHEiXsNp&19zp zhPt90YEy*_&zhbJWoxALn_V}5)>~~77Okus!-JlAhrLD zax%v%SY|}LwO<78cZZQcV5OClm! zmom?#%yUXt#k#n0ZnNCK$;kxo%2M)ch}u@PXGwX-DX^de+H_9yyc1uuY186u0>DTB z(Jc4!m;|*ya&5r0HOQSTIW{HpF5Xc2Xy9OuqikZN1_idPCLSg=11eEg6=xe`2Ixv% z9jkU9-pr@=IM|gkJrtf3>@0g{PK@8zeuImQRx zq$Whwm@J3P&N>!J3l;XbAg|xcd8V|5lRm&V?3dR&r_>q34>XbYABIj6U zqP?8lh7zn^HJBwh(rg=Ri)-Lii)#HHCtGA066rZlw{XzK#6cILoNR|z7klTB>F!bT z80T8$srev7`%H`E_i!*Uub7jB`2F79287r`Itar_7FAJtiE`p`%#s~D0TuBbcY>U1 z^9({JO;&Q#c%bcAi{Kq@?TEkO(zmCPsJf4xgiBBPb!}k%ED7Q0p}%8Y9oYlovu(1- zuxX6?bn5JGyQ|E2>UX;TQOkxlIDXTRJJ_*JhtRxnJ<1-L^a1nr16eAUpxkC3DSiG1 z&8U;jF7XTJk*f~qv|>!GdsoS*v1r|FvY-lJIKqvTpy;c+bI$E?C&o{&+8#aRbbyFx za+BmN%4D(=mTHm`56SK#)m|vjTIUJ;$cgH_vEnD>-*{~79H%`>nj(jcNEWgy#a1vT$HyDFBnYX3aJ<{9 zpt2*=6lb`EQR}qSu}ZQ(@ElSO!BAAxh7vV6#Su0szNkr+KKAs+v46oX9WHp{R}LpU zB?rpN(ztM*<)G~#v7UqN4fTHs+d_VTy&T|KPMZS~McHW}Tov3jNYOBOm2zu$RxKq+ z&^(DoiZhUkr)|<=PKGNZI9t$&!y7CJL!C5>qbiXnPnzKt7E|GHmpDvX%kcRuhVR)D z(Dp0X2M#s`{uA80D#U=tE)bn|a`D;%5;96fE?`+npmlbR*xEYi=+d+{FrLmc1)Wm} zi^W@&(IVAyMOiXAMEMYg+63tcSs`juMhlY-pzwjmGzKviS3*!25VVYavo@nKNF&YmRMQFJ(M5P8IybIJ(6ORB@Hz-PO6d< z*m;~NM1t}-LEE7{EQ8a8e$-pdtl-5;$FT{opCCm?IO3TA$ zD<#JYavx`Jfbo}Lv=apHnW&1?0gT_?O`qB>`4_Na5saYRAAA9Md>heioX^V^V0awD zIjh8#Et#Dz&RPKVefP@kp^2aZxakS@v{rb4RR)q6ji}92B999ko)NZ>kEaO=rF- zwJ^T%9i}nNh-JG}K($R5)VQ-(CSEH1oxzbrAwv~E9OmSb!=22LB4I2- z9TCqQ72}kuc8;7-n4OYs;s7t6SLWH!Y+jjf^U6_H*C6x)>5G!$Vl>)H2|(ha&@pOM z9%Gk+eadb)&lu-G8WqP&s8T*q^no=#2PegMo|P6~WNY!4I=G`1v5xLYc~<05BDP(r z-Gku9>c9@zeQNCaU%vSqs{#HOe-!3aVw6VJ*-NU7bfGs&ZRoReV1CKaAM(`?yI4gU zekq*`Uq)4QNCaisfkHP|B=t8!fk0^vvE{S7=2nRUl4s}JlCyJ&nyNfX5OIOcEFHl> zpPKCW=W7=i3(d|aZ9+ZZ8itDK>f{e}%V%fJ>~MJoX7(~W}zZBI=pgBa=JaAn9X?N?j@GX zJ_xzgrt0iyRMOjFM$$qJuo--YV)_G>qMqplZ10zNcaXiK)KId-dMmvRJn^&V4zT5U zQapQ)4}H26d+&Vuq1d}HNF{sc1}PB(_XXG%Rd1!S#hp6ZbKiMc1u1k6FYe^uQw!7C zyXT}aTM>^}JseLck?KL_r$ZCrPbrb$r=h6FOQg~=+^LCVJ4ngW63Cw{fe|e_p1^ek zND*|-F-T8Dj1={x9LeaG8p0}7ek#t(xiqnQL9DUJ5S8h1TSupgrSlOWzEgS8$Ee+) z6e_;W$591}*dH%w+@V5!h6KVzjLW9Kr1;fW)Q;Jq)ladPl#;1Vl{L+=PoQh2+k^rJ zX14>y$1A119qqs>`p9;Cy5mFt>^;d1PTSEjzyT2;Y{v@{164=?%uXVmL1M=Y{*Px{ zm$CxweUhrC1#*X`C7l#D;U$wCs@KJ813gLWFbq4}e72OrQG{enHV~VK(Sepj)KN^8 z11gW#R9Z;fv6g&hf3WR%$PxnrTT<-hQZbsgWX0hFJ*kr|p351bWa3B_Ev6V{&c)P` zD>n`26F$`)si>+^o)Vk+f;XsmOi=R2C^ZP(lkcdYfIb<;=W^~)9@0l8)EQn@A@>r% z(jN5Ks5(Q-m=i-gGOcU;3U;%nhWMyAeqj<+T-awqd^-mWd7)ONhoUZr)|n*c3_0S# zu4JKwrr1;I0Fdfji!`yc5amkXd?x0`IfQskRk4AOd=B5s-vuD_$v3`bRti=B#;t+`Ca&ya;y#I^?4#m2O_fr?PiC_z0 zVj6ssmD(2nXpkZZ9A*%N43Z0$1J}v!9By3V9hO{$f)q~%cqqt82G$EM2>j4^b%UNu zle!t9>3lK`DuwdLaTd(I1WIlwinHPo1c}+ts43P=ilc)ho#(@L96Sy%`0fUN1xiGW zR@5p4Orgz3;eP{H*7)N;Dk9M)XN1zL4xuzU9}cy{=q*jPa}d2`U3|Pn(xb}HwTmTG zl+fJMbI5YqC`r#DlR%ZFDvX|kDYb>?WLw#tqDH5V-uZLL3W%EBX;MsD_)fPNrj>QM z*uG`<_67Lm-^ptd+Deu&?F!@o>99Z zelOefG|Z+l745;PFI(-yOIUsminU@r6gfH`je+qO&oh)?9UTzQxRe1%)ZLkwJDY)> zX}j=Z+8!fld#p{{w7WUp4pJWfA419w*9Lg6^O+7L6+z2MS0pWyX->N^-LVzWl1xF# zt6&Pst-y&x8G`b3qK~5;_6M1Q7M;e6EPLk+kfb3&INnR9sK2udM3^aqY*_hfB!_=OTZ`GjS!fcC%EF)orpdp8#`V8qbggdDK#FXOINaqYmr)Q^w zYQ96%Dtz==HBG<6_esf~HeczbW?Q|@PRwRsdq;jIB#3jiFptWV5Ha=Me7+l$>zFp1 zbKcc^kmTVwKQp5B;NC@B68(cOwZX!2`x3o5MOzv=j{b?TC`47V z6iWI8FR&jN7kJ{8HSrR&z}6H;+j6c@sZc^e93wdjUrRh#scF^&;Yz5Dx0wz;jiZ`7 zRqVJY!fl<>Z*K@V1cXQ~mNdoH!^@m{<|HL^OQ;$7E*%efs|lPehX{0OD%7KtGC5U= zIZ-;zPU7QJmlCd*cb2AQ7ALec#Y;a@DK_*BdjUVjbwYKCE}Tz7I&=d}`oH#pEv5X$ zy`{=|8r}JUCMO?Ihr*m-RD1?DLFeZrsSOPpzBobS4Gj314aGZjF&*=LJeO7@H2 zef{GlzC(4iNsp9ADFTR29FH_1G{asrDpLlb+C{d~*xB25si+>na%{~@zPeMVNm4imPh4+q3TbF*tXp0Ktv^W!%L`ShgrLSrN)(xJCH&Jw6J{yA&AC5%P!<^=mR zLA(aY$po-uYI9B$n<6f>jo^O@vd&4Z%HjCw2Y_;g!Wno=gsHmk9J&-w;b~ILND8M@ z2e}|b;XR#-s5*C$$5ZrTH@TEzqsVr)1e97NTv5)LN9SwZz+%)hWqb_ki87v0A)gXV zrbAq!-5?7!B>3x7XjgZ7fr?{CT5+v-<$$e?LfJ$@x_z=0Z@^n^c@@q}ROlPnL5_-f zig#wK9jYuTV1MZdC6d3N-izCm0_}KRo7w>rEb#%{R3?{>f*YwU+9Hx|;PWMl5vbB) z$8=&gE^~_9IQ6vii`;B^>vW%RBBjN}0$L6fA^oS?Y!Yv8b4ugsifdgCR2{6t@m>_X zZ2%Cpa)qAK7iL(y0?6~X3#g|U;*g(ZGa6zN>SY6*7Oqh0!j%^CfHlV!;cBYp#FRSGJd8fl@6h1Y-*-+{p_C>=f8gJin~8QNF#ajBd{ zP=zp~uCixUC=OSv3_eF9@0w4|LjO0gPp$+&sT0P7C#Q#c+TuF9EcTnei+GOe;`1o>42m%9XQD<(}5?{yD%k7 zoHjfHb;A7w~Q?-wX;{z2OY099M;V@+uaOB$mmyBSmy{wk0^kF3RUQG2yQirH2QX1ma~N5MLkOi&0f7Mya4O>Kfx zTCCH-7_SnHQSnURD;cJ2jLG~gnqxErM02!3Ih(Xu#y{rPjQ4QFvrK!9c}$mL%e^hS z0NZf7G?7#;O-`fArO6XY$CP}ovs*Ks8QE{2zIgQqIjUM3q07##lcd9 z3{_eof51W=Y$>Y3V-{)?(Kb;27a&i`5rUVERLm>K(l)R;axFCm2_8tHR!0HPlY0yc zM$q!*hLuT2SOv6ErA}Grb7G+tD2E9~pvKsmoO*gwLUq3K%EA_FG(iebOb?yTNj^%j z_)GZ&>Z-RQYiMZ6-^UlvJT9~Mk^Qz{IcFu8Vtf=oZ}Fi>2Jqjav5z!EZHaJLXfbCASp3fG7myRtg9+s*0mGi|?BvBP5 zsBcTy%l@C>DsZy0|05%JGUb2g`IK`=O3#juf3x*$xXo=-pR;fxs4QzJ;HE?3^$y9x z=_G2HqbKmD;mX#sp9*#I3+Xa|o@+}rTXVq!PHI2-l==&nP1xj<`pZ9YqXdS{p45S> zWVp&#CXK&DcnQOu=86-j&dcR+Wal#^bCSuK zHdC3Uq$N28EV*(;JQKRIvl2hYE{AF>#1zdWv9)=fZS_mL2W$lKc{`^v4i#5C20_3= zP61XaIua|fP-wb%A3GmAMyAI8348;fxOm@yFh=5h1IsXG>7Dr)jrZ?}-Bclzf8VS1 z#3tyb6jnrJ+8dCJ=mfQIyA#pU#!f^9DM6@0589C8t$}zq9BoOi;VRyeB8p|?HqE)? z@lR*?Xy->j6-_wn@Bm@8SDgi&1O06Jp&iiI*1;SPhC&u9;-v6kOV%O&j9wn;j6nOC z7cJt0=$d+vSdxF1Z5<79^Vjj?G*P^wEl#tg0np3cNVBzi&$dyq$RPgvbBEBQp{>PL z*Z-2(4ObljGMfHrd`%Bu4XCMGh0p0x51QM!JF7c03-yfLj8I0{z-J%v^<3lioi1i( zA=7WTMb1-qA;&ALWrTBceHj@UygEK04&-mS82S3zn*0@Omeu9s%YXSRs;crY`ov#; zVcwX$vH8ow%T}$aT3sKG;03k$;(yfljmay>E8s0RtPHQtUr|%1X)Ann%a*T>p3wA~>ZWMr-AzGbXws^pa6#l~V`D+&Kr~bku54`l zuce`aqD}Q?SGLu>;iTF9wZ z7Gg7Yu>cGCRtAH{u++S!78Yu6-<7+7?Tf5nm4{g6VK(Cs%k|NZ4L%wjIiqRhjKkSz z@;F;R$;e7SP=37a+jSw<9&SBKmsWNl5~&8@KqOGkG6Kg~Mzry~k)3kD$Vxe1%nljD zlMb*`2aE~G2_>0bPqM(tRkY6i9i&H4&6aqBV6NLgchm<8D)e|F9CTcQo;8sC|LVY1vNIj~%p zZl2jvWrRT+?_kOet>mKR|Jy5xr2}QCm86BM^m>`uTYrKz`q;hYEZE3`&HVo$u*tyh z0IQY%LNxZIC~`v$M~s{#AHT3kR)t^#3kFy%uFbS8bUh-$Rhr${04zvN*cWZ_cd*K6 z*xazgOvriY&@pyJBMTpX{HX7VT))3O=tI#BIam68>JGJyE*SPxeArVy*{~xuHEU}G z$;w@rl#G#Q>i5NV#hM;I)Dk;%B!WqZFu(X6HIs58ECY!QUsD5Xj#M3suy#rYeUYOq zm>-D+Yf*N#iT*Y>QL@?WLv4aJl@Ux{u#)Pj`jkF|Ph9GHPd<*Mi^id858{iYhW53K zO7j0z`?_`&xW{UmrdlAvx4NCRoU({!X7$3%S(`l)>?pW+t8ccp`WbWM0JHncM;v?o zR5)00Z**JpDzVeeXSd`C#=!;#jipJ?d>lBzIkr2Xan3O-y3JUU^o+$i-rHh4Wa`*7 zF}=!VnoU~{7XPmJr%yyjv6E)EiQp~IXvPBF%&amaC+q9(y!%d6`r6j@A+zfabJO~$ z+09s?m$Ojp=)MazH8tCIpRd_yW*B=6y{-5{q`7+L>0^h2;jr(uSZs#xnHUQh>wAXo zZCt^E9Y@UsR$+Fp+G*DAH`CaFnsAi0>}q*xL$rpSHO8f}db9i12o)yn3A2`+$URzp zrfvC#mfClsZ6UTd4EDxC*etPo*^$!?`0oOH{s?kwTJG4uUU_^$bxq5+H<-y!8@}{Y zcZFHywitUg#*VYVY!+C`ZaL&{&mI46`SCh`OJF#*Sd0bC)QRj)mSK8X1q=CGvdwNe zF${5%?)Mi_twQtKiDuvR+u1^vi`~uky~{$))yCvB&~K>C-}(b%RGN{WAGBa6e$7I3d^F|rA66B}#{0o;F}?i0qi z^usLbqaXXJF{D?EF_Z&+qQ%JJ6Y#h(JlPjlZILk?)pDp>D8AZm7TDHwt|bf^RypR{ zQ)Vs5g}PKK8CLHaUDW8ZjoOwY{>TZNa2%hw+aM#)3W2B)RTFmW5=jX#C8%i}#t{ zlg8N8Q%&uA!_m{bc9|Q9O4mnzXpBq7y5e%A83dmj$v<+mnT57LZeQ#9y}0fZ_az~J zpk{bMu%J2|jf`exc~K)PDcZ;~Dw`V)u?VX)tDoLx_FLcl_G#pvZefpY#L|b%+8t(( zJ!ZeBcVXm#4siPJIWHHT_Oo3zZR~)*w$|Llv0}Mxko0WMIx}G_dvKwV*Yly>xl!M} zhA+i`9WjZ8Nza&rs?6m%EM=zYEi*UeghAW`X8ZEbwX+3v+YaBt_MyA3tfG;Xvw`hR zkrtM5o@Km!fCa>z+3l_H=_t_n#^o8KneRXwTYlpf|LC*P`!CNJ)zZwW*>1Yr-Q3>H zc49>0-@v8*7B;f3jjh|pGH|znExMP@eCO?b&Db~@X7{&vaSK~l$BQ@9X4(W1A2t(q z6#K&dnf_QY^B-q(%8WFwr#$x5O#?@@v&YP?`~A%=E$pc}{4jG3 z)od5r&bGaXc^kwk&q4gKRJODEym49T?xr^O-JR?e)BAL+@!4?fRE)i3c3U574mX># z-ZFoq?Jx?HSR2c2zJEgvi`A6ZeEIW@_2x1oN6!Zzd}G~PX74g^zYi1FoBgX;dvm~8 zm-MrTn@QLkD-zE@-bWf)_NF5pXx;1&k2SllXTfMV91HI{VAih(5wU>{lfVr##;+K4 zZ?nIpmCf5|cCES#e5dQyu)pKXFScPNJ~Xdl>&@)_?U)?=>VpkUEk~o-8zZlrZn z&kg5}U&-~93^2^odH&{Y$JroY-W&{cl=}k<+5891%@fUTWerAQdNn)K!U>f%23s$% z(9JFFQTAXn57%Wxg+k!i|moS}3FqQ5Fcc{(wzop<5a{ zFeR9jU!Q1Zb*!>IczC;cWsW&^Pq;CB)W3n0al1eEZmcDG|HjxWu|p?V0XFJ4whjQ1R5a{vZ|E2mZa&c-G*=%q`>by;@{%F) zzN_oOP-A1QdE5GlW>+IyH-E0-YJ7n~m3a&LfT4Xtm2B1Z_*!|KN>;fFibaNw(KVkn zijwZAGv=l?KtALoMUJqTPyC|3$JtRR=svUS%SLwcsnd-{Rx;}d7=a{XSaJh$+4+ky zli7e+AXpnLU3dBv^ELYC6|}ba*ZeXTI+X#1<8&Y+#9GWcFsGCIGD6{uU{N4w6eKZ! zMzq}A%yLX`l`$g8pdnY%C*c2`I@-FLwN;VYTHF32gKXv6wb#WNWG!o*IvNbJ@=s!r zy#TFhTGGbOY8q*`m(ck-n|Ga+G^l(nQspBBY)eig=qsuV!LF!TyP>+M&g^bv>GJ|C zHE4Q`D|J>LXbm?+TAwgRB|+B4U9P1n3v?EM5i*o45nMu(3Sr|&cLr~|EF7-khL6k)uc}>l zwbS~Mc4O(S*ja~keNPdqxrz-K4Hb?RG2aFLAFFI)w}2l-nhr;pkL5*bcb#rMz0F(% zwPqyC!Q9-tmF>ZpU)QR@){GJ9tP#=yCUiM|zE)#o4@~c=FdGPEz|Rh`W@BVhbNg9i zWU{&GEwkHxmeIi0uK=7XW1Ma-s4{cc1KL2g2m7Phm;|@QfC4mcJQ{|^Qr_Nn)ZFm0 znfO)%E6Yd5tn(~V6bYmG!&{AFyZ!%Y05CtfEgUjRliJuZQD^T~<1*AaDEfFsV^15w zwws5yR+-1Omk(2Wvw3R{K$tIU zRR@YsmA_qdo_gH+wE3Y{WoEI8|9=_&?aSbDn>)6$3YUuwnD265#~xtNUEyTIwfQs) z-OI9yS_AAn@@ujDV0Qk1xfUBDwW5{{YUyZcX$hY`#Q#4mSRsP}0}U#f!Icz-@y2#G zhFeHmZUkkMo9tMO+*7}SCK_y5iGtIk4zc_T@KqgPyM1gU`ysehu*2}DzY6BY&YE2z z!Pm2PvIPx-%qyzfpHZjJ&p+5#9r zwa_0ziC>DsY)LQ-X3o~un@cOqVILla>fQ+QePl}xr__^6I`NCz{}1zvvP-YPM{dpN?LRon^9Qy-(a}?*fwCsV zEx)a;3x^}s$cDmP56tQ!o9d8q@fNjp%c`yuP0+qJLM3R9`(;&itJbcul5j`j9!KA( zbM5u(I^9c$WcFc9@L5fVeKTOi&V>*!&6UNC;pp4Z+R6t4m4WJzF(Iuo!VauB7H(|W z3zdak#+uC@IWV(Y^6MI5lAj5Kqu`9f?0PV?>J~U+7A!hvEK!Pr6XtNn5pi)tWH08o45M;Z<@y;O$qpYH6?>*3w`x z$e|nk0p_ol?hodR|HCXcD!eFiAV1ukA7&YR!1GYk(2D=z0c+Req{(^WknjXLOVy7U zX_&hI;!r35<51&`9*`l8BbPuA&{wdXvDyamE!lT$CLC)+Q_9U7CSJL>J{*V^jh!9& zsK3SLceduBFn9b+1DfQ=cz7k4dCvdU;wXb`r$=zT4pEZ2Kp4h zG=;Hy>$c!F7Nj&1X2p6oV`1CbYGVi-JK;VBVNqvSu$p!7463w!>(=8?9&tpL>$^9~ z8Y2-p9vcMzWYY@RO|Lex7I?*c)pS6?76t+}0i1hfC!1rds#r1qe{U6QTE+bN+lp}L zGkzg!tlfz{#CG~vQ;RV;#n`4N8Do=Jhq39Be^0Y0JKSI%-ZGIB&{ce?r+l)d=KLbg zSMcNsOjVkW)4xM(p*UE%4(!0trhc*>)~+MI6W2xdv*@BguZEbYB~jt{*WkFP{7*X# z->Gk7tOh4=Sn^;c6pTy%3tc)}=3d9HC~xck3Or>DUcRE_-eygX*^8ZIvtf^gpC7*) z{(Dx_$ozW&{_WZs*@2>&kJmJ_np3RE7@yqH(rk=Qg38m5|7+y01!^A8a9o>Pa5Ry7 zw5=`HQp5iRS^_QQu{L%pz)s~8GEtl_kdqo#`1v-r(D3y%CMUs;I>pN>+uNGiz;e<6 zo8fn1ryQ5@l(a8nk_9w&09^t*K;+Qd&pv4Q;J|6aHnM)qe-=Y;hc`dTn3&9R&*Cgs z-uRN49|s0W^gD!u3;>&y#7MjAV4-csFw8pZFdx{$_QM~v!~F&A2!~jTiO2k5i*|6XjK!M&R%F^i$8#)^B%L?p53f9g#TFmrUN)4fO0#RKQ zYctICWoF-(_xNx$j!TVMQw2a@5H{;=dIhUtkfRwp!{?){wyp63|DUCp*RD7F?r+$| z8bXW8Sv{J3ZOa}X_56Fi>Z~#3V|nN@&KM?tf_X%U!quI{%d9srUHx<%!VL)QYzjwe zf`$j(zrZ^w{RExByGE{nI5tgvj3&n5W0_Hy8Vya=pbu_e1bvsXA(Tzwv?X>j9E8J@ zMqXJKtz(TFW5ScYkxYl|Jq-lN*#PS_FaYBOHaC0=J~HqTn4{~*_}Kn0oOQHwbZ@p} zbcOn)ZIfa?ID+mh#tC3`d2_D+E`OjY91Z*PYZf==UJl2xQK$#$fFbO!d7$3>%GQ(S z@3p6ESY7p{om#@dme<%5Dnr|1DALsF`9+`$bs=Zi{MIvC{P+@lc@PXZ^o1b))a@57BN>;aaCJVHNP)YO_e@AdR zaM42}c6U=SYQ_*gav7$03n!Q9pKL4CuUS>MvL>=D?4+19ErDclv9H({@%vWh2J=?r z264uGsJqmk?--_G^d=DT-r_%Ss zh0RCmDsLthcjv-TtTF@-CjDDj7dspafQg|J-#ZgHy;XiPR2;rUi-$Y%EEb+?0LA~& zbv7NrPWd?J&gZIKIKy0hau2%)nZ+#Q>|uDopuLSP2>Z>|FPlHxvcIYESmZ#pf8m1a zqQJ-*h%O5GYxlOdL|AJPjzBKQ;d!~gsm)lF)KIkT5ZJiix7!ab&PVMcyV$_SNxMbU z=4jAZp44=vb#Hr3EW$Ej{DvXl8d!N#TeGnssiArsc=jEF&HqWOIK^_Y3mU&>ZZ>Mc zO81|GEHwx3sbcq5u?yyX(CBEd{*^D|<)3WsE_TtfmwY zKfzKi+hCt-5K6hdF|afpXEHNzI{gfcLzuToQ4%wt>L`5l z;GyNZ>D_OxWCzWDdsta1Y1F#&_~tKL`1wuHSdx4IXY4sT86HqC5Lkt2#@UitXXGM; zo?uj%{r4CJy;#H;+LK+t8GTU^o#!0a48MJza~Pc5n44lOOA)0-Mu~lp6Tmsng5+Fd zSub=m3S12fbkO{X_A-u5E!X$nPIq=1D=N#>-}sz5=%=;#1z8bX4nepY4#Xa-+YBl_ zcB&l~Ui$?WXs45ark$)H-1^M1Ru&p<85|Kd04}Eu*}=;~r�p19j%2J!baH%^+}p z3<3}aqItuIo1t>w$KGbq2*P|;=7!JXp0Bv8nt|x45Ucf-KNKZPw{m9~B-OPl zkjIK!k2H%I+oSmN^Lnt@2KG#pBZX126H&yYAn43bf7z+FmRJz+NHCUz2jGWhXUO!s zp6FmdJBF4UBruvC5`=R$VJ6yx4M3AOGDf8aBP!9#4GQeSV1&IFB^=Q^2wQf5-MOg( z)?owt>2_AgPJ=*xiP=H0+XW<^zrfD02l4L#_5cPI+J`Yewdo+u>W@8D$62sFcp5%a z_Da(+Y=N5c?T|5CWN`ME!@V<~&|KzQyRIe@7lnSwt$b`MwsN-4vYMe@B^bl>Se|+P z4zq8Cc}<0x^&z8R>zqI328$42^(O>5Wx?dnOZr9YcW~gUtTg%yrCrc<&|!no`IWH9 z7Mcl9@5zU9@jNoXVS|x_l?b9U#w4*=7%dwRK4LD!3e}jy*W;cz0o#p@+OlOLjuv$D z86Dm=%H4q%u;c7X-kLI^3kfqnRF1I(|*Nl+!>9*J%JW(9#>Zyn){VY6FBfNk%M10!te zx+8P(lti>KV=tRuZ{>+PH8kK{6T+XW)wJU- zBR9sIEL(35uRur>quH#!5Np_(PI{2UWVu|PcrgSC}v{2-V2oWhQTOm zv4Nk|>4;nmu#OcJ1_n!IZJF8cAnH74Fbe)wb;ec&u;TUbLJ|R*>&nbt`>SK;`Hl{S zd=DVBhVKNZh`-elkDL{2X_;x(8bfr1YM+bc?nRu%L~|KMacnmzt3H13O~B83OlGROtE;Q4tE;Q4`&XNNu~xG68BFIFP#M~XpQYVM z>{ZFRufFpZRQ+6y=!0AJk(xYRF*xcS+b3~zWfIDJ$baC(yJsTWcO?Z|v3$@EN+)?1 z|2;Q*2G)(QWY!}(wg?fKlcK_#KlX#@-bat0d_(kKleMQHXR!xo2S~zzcyR6gHFfXW7p>WL!-L~%qQzTio|Srf zcEUf#|JEQM;L_}2cW(VDb|9tNSu>U(U#&!Y4z>x$gNx;J6&LGq221VUnetan_QN=z zrJ&y|oNvA4i!$XxKRc3SJT{#VEj*OXa0Y$iI{(0}vp+V(@|V8L$a+4_lw z`H#cNDqvUk;hGu!ckPZ|oY?s2K;y*mJ8nic1dd*w-FjBT)(3a=JTxmilJ8mGgG1zP zt83qV@C!XVmTZW6F1dam9Ed}9_mp?^Y#-k{xpl`~>POGgy9!Ipf0y)d@8E==L(!s0C(l3ykZTadiH3}Z8Eh<;>WiF~iS zZ&4FTFOQf_J+qeXyrsV|xg`4J+m|*heK2}-)>%D^*F;O_@7y~%iQ6^LAmqQd_Sl22 zqZRq4Iq*RWg(X{yH_a(bE?%-FTevj)mYW{kvUu^p)A!-Og=nHMnO(Rj`?XB%oSMPM zX7xv(!abp-lMPGDXC1Tn#IvrBUIQU7!4jwQ9o@E(bd_xvu}*nH{dudDj`ej zgxy=Pv|e&>Ve1~uKlUw5K)0YWr&i3)wtfNW<$L1)ayCsOMTJ*5WPE&5vI;zVpn>qn&DDwGMgy~h+#zw9pUsBHv+ zfB8Yr;$3K(V$R#aU(YpE_(5EEXgdslybzuBLhaiQ8izH)pVvjZdlqkdA?lmxgCDbP zb#xs#*nMTRr~ClQ*0$mb#x z%B46Wcq^>MZngKMg93Yh{=atnYJ*w~)io>Hy6QjUi&)8GiN%=k_F`#(2>GZ5)%?jm zkfK6nY}s`%WAWWBlTx1JIAt?2d^B?hnH#9&zCZ(cGxIa)TS%GtNhj&6_2 z=Pz6gL;b4n4Wd{nn!RsB@z$=h0D)iIc=0vUYT!14Rx$h`rGlZlrq}qI! zR?Gv;3R|1~d`-UVTYGr|H;Q; z7LJCki1#8O^PP*xg_z8)hcn-^=kfc1F2(|^36CZF6=7; z_|F&L1mJU6lIL%|%lt3(rdZNnk8?N}VQ;^#+jVfVy? zqigYNIXVws>{1NweG~Uhd=dYr|K2|bzvBYb)2nq5^29?BjIO<>=HTe~CAVT-#2G?= zbPBA*nx=v4dM3Bub;5PEC(r2Lht>6eHevIzdfUKuL`*0uiCxF%FUZ$^IE&f4TFvB1 zZzfmCpW2T!DRF= zZ+l5|R^6_Cly6sOv-ez5djVp>4RI_Oo+C$tR~%d_J0aoI5fVOm_6yh6V(XYC-O=6f5i@7W5+xb)_|Ky1Ag!O2qXF*Bkf(nxydT=oF` zZA93*5f17pef?AFTnyAe99l8}MLqx6o|EB4^vpVI*0#HrUO%gU^{h1~9{bL_jyvm^ zvj<=!exHE~vyI4R|E)HE8T{RyYj(p4AK2OR#YaJ?wzKBZQf=qqcb6`k*t@tiXEHh& zSHG9+fx6s*>6y(wS-T#-MGtgovS&4J^6mu(k6~9h9`$^Ga?9kF!sPDBM|a^KPj?wj zo_lB9;56mNC(YlTB{zQOJHf)TKio#YW=FesW)JVi-V&hbTWDkw?eu)4Jh*LV!)-7V zM>bqOZ}sBik2r7f;>UI!pWXZ>I8xZc6;3R6jodF4gdiLzQWWzpetuEd;UfdoPO_=|V3$CUxKeX?$8tj2;uc8$F z5>&c2L&;$FB3W%}DLwZTp8@d}z5ER*{r%Y*ijjWrqUfnxkOQ*%n%eHy&WS!!dKCW9 zw!5RZ)xP63ODJ>Wq(j%-i<_FY%MZU72H}g@y6)^o+$pa;zvkYCLhTuc)Sfj1cNA`@ z{XT5>otG}cN%a?QMhs*#;=0ez`c^cfcIDyQqBY-+R{pGzT{%13baixean|i)pS-qM z!bSB)Y>*b;w+X5JwT&~z)&H9h+c8nwd}y?#v}N8h3Y^|?>Fn%JGnYp9M-AWqKGwK- zTfYCq_pg0AI{M^UmlvX?Yt~#7y>n|n1R7lmhG%Vy&g(DDyFa@N)xL#lKij?)Zu;@H zPu0xWPCpNg?w>br)^*r)%^N32AOHISc<-5=o%2+G)Ns}1^X9GDwsk8OqN^K9J&!d+ zZ$iRM*JWFuYUnBbFAL0r>YR(v!K!WbbGHJM+{j zdrp{tS@zI;c69dYsJMjwGv|b2^uU_c6W2tS*B*E11WqL%oChEM(7SP0rtYSxvr*Jiq3n%0f<(vgvPy&`l(d(jh6ytmdsa-Grd$HyVa73&w{pz!Sn z@4RNsuEM;<^9qai;4f^mZ@vrnp^rVdfqtks&|YmRq{NI-N?g!B;CkzPqcjs&wT{$gGKYaHvnG#<+9{G0recI~FABx^~?c;k9m)=5m$Upw+X#QAj>!I0qcV~}|)*}Q)TclrH zn5PRBAD)&+L=9Iiw-E3NbyRmi_HIC%4!$+IzJQag=#7YZ&)ZojMjO?iJ<-1c@Fro69D7(7&cATJuoe5EU&04E&}=CW$nH2m`D+ch z9lsjLCoJSn8~N>v^P=XYLGEloy)R#UX^eV>atV_rzNHJU##=&*cQ)+a6Wy#i1vxy;S1gdIbe}AEjdvx|CQyJ377?EnON-;+!}7Q%_XdGo;-3Xdd1| znH?=^Sc=`^?s?Ji*>$yN)m$^4J$QW<8-bd4U!Hw+^!w6Y+%NszI6`JO?8a5F$=wK+ zPWEg({_VSZKK`lsJ(Rq*9d8Vjb{~<=&CVYCJRTO>`rtgAU#^bk?|c#e$1(i;9S=nF zUqHxg{*FD-xkYfkW#iTA2G13*%xkI$xxRVV&S>cPojdnEsoqzJ?t=UOqfP3LBkoal zLl5tG1cfH9WfpDMgpa;6ZR9g2qCa|B*u`$SC*^1$e#%L#>^#_X%V5W&N~DZ8Qj zES#9$j+2mvvu|8}{LLL3;1Oisg+sKP@Jr9OeyqDUUXq`OmF2fJ$V(#`eGpXtS6`JI zNnVxPNw3PysNpx_(7Wg9Nx4_n=r`lQ89g~gx0JDuyC|xkHtoHLG`tQl`VT$e)_{K( z9EAIb3#T7&`nGJ0I~%xp4(>3jg#TOx96h(m^%(wsz>f>S?*n{h0R9BvZ2|bfFTN_m z$<#&13p}^A3h;#j zF59{hxORbKS`PuiTT>TZEZ~yX7T_e`Olt?=M~ONN{}SMD3BZ4n0?*Xi^{+_5vrJz3in?gNs4sQz^Z<_A zy%e|`M7?EKWv`sJ?SPoCL!-LrYJopv+q5gujTnC`@K;p8AN|U@=o*1{`~6wq-&X;D z%B$+4VS#74^7!2ad}#b0PJ#ax@ackHXg(9||BFu2yMA*1k<19b74V;6-n(PT_1-fb z(O}UA!$0J}ncgFSX9Yc$G1q(Spt|U^0KM0}x-KdRIMcfb@S6pkWzO_oe{fy&dV%M9 z&49}}DrHUm9tZvnq8`(`2JlM-JS0=nQ@lZ%p%()~c93vOfpg_X@NIyjz>f&Pr_ZqA+=pWTZx!X){t!>+0e7gtF;63aOI>342LV4a zQ2z6P&kn$!0{jF4r~XsB2OnA&bqTl}JHi)$KUUzm{eJ~K#MkElKPFKAhk#2RVLER< ztS&kuP(Ba1w7Y4#aq27Z4HCSG=&qkcpKzOjd$U8I;2#9sT{{VW8{lrg2>uY@GXr#f z4R}WYe$?ygytR|)91r-%MS0c%!aWL{v`M5l1phPOa!h5NnXmWPO{%jDa91WY=7ie} z+*ZK@+isTG-+>Rw=71x@vY7+;OhJ$7EC)O!n=1f!{R-mi8o+N8bYwr9-eAvJ?#tPL zZx?mkzB~cE^edRR&%UWHnjz{je0K``2Y{0fN}EAE{{nD&RFvV&*9(9zfbCIrXUD+`1n4{_!bjl8OzCZDLj{|33eg=3YUTAa2tN2hYEKdxNA3jA>b&+`7217}_jZLW*%66IaFehK(30?+NSTu*NCeR`(78MsQk zJ_LM-*FQOMruU}S%Dg@Rd?j8NxB0xXe6|6%Q1p}G-vs=a0Q@%&oOwL7y)L?2lxKM| zy)OeVZ5qQ*=&1Ad#iU~ez(ag}6z~vV-*(_UPJaUY4#5}cKezp%&M;4}oNM#MeLNZP zZwOj!Q0G8jyOUkmsw(GItNFW^TBIJf^p!2emm z-S&$ohU;Ag_;&*JShn3K)kSX?_yt0?7Xn9o@qA?-uStR54tS?1&uu&bc%OjF@jK~c z+pp$2*8#perOxV8>Y~#Hj`_MN1^yGj<=&mkA8~3}Ki`!CzXk9Gfp&kA0-w1c%x3}c z5S=>!e@lS=Zoo+ocpO+K_5v<-nRSBkA6-}%JtOL|pTYfq-)VKxQi11sj{#l~y6(=A zxo6n>JRY;b=f{X%O($am!KzQ^9A4z3&@-6KGf~+ z>6xDcdhECsk1^x_8F)GWUHPnDZO4Dy`d84 zr{(IRRiZxA{Q%(S1jdc=&-B(s*9pGdb~ohfqRRwb7ymclr-}O9Z|3W{f~~KieKqm& zZ`jn(lfXX@v_<1b_*2feb(rlR;kE(i#tjI5R|@=lfV*oamH#{7t{e$|_FC8u(N8G{ z!Ve8&E?2-`vJN&qFb*MkP=7yucqT*d`nr2+#ytbvyM?S+7F6%FF@HZz@a2HJz81kZ z0zOmFqOl|R2LX5E^aOtx@K=fQ%+uq5hx`kwbK!d5_Nq1j9}={r{t!M>viES@*71P5 zvSGf@1OOHDZ}mpZ_26LjQQeF8Yrf3~~a zzXt(#_paRjpB)^--!g8;j2S)$a5-Mo9`(BuaJil@G%<6oS5B#SG2lNCJhLt1dfgLs z(a8eO@at3H-%WwPdPA7b*??~d(EmE%(&yxM|B?bfZlmq%arv_V?+wtu+bPdu^&P-l zMR_^CwVUiVSoUuNT<%3#hKwHuezl+}_gpk~Uk6^=DQc7XdF^I@onzbz;FbxxRFB)- z0o-*0=knBWfo*@6nlm+~y&m}UMSaQB6TnHCN*SGap{?soZxC>|kId_Rz)cU>TOPv) zE~<+f1utChZ-B20)MI?{63`9UX~vhfc(IcBoQcNeIpEK(P=Cp`y6BYx@7lYSSJ-jF zwDsYEHzBrqr5~pyJ_)xLxF3oBOZ_4I;;ZVSKM6eR0pU)3FJjn2Mp6$5|IUA|iv|T= zu7!mE+P~D{_58%9dHDC$MURQLUHk|CwJv&>h-EG@XOJ|uME{T1*mH;bJpbA{Bn+pw zn|r@~hR6M4y1xRRXh~a4?Hzc1x}2MU`;n;Q%K4xh(&b!xV`Vwd{6J+nzxRWc<^0}% zt1Rb#`cP##@7fWTbIr|_<$UyqE6e#F;H8{-{2m5e>LkmO@n5;MF8Z~QHP0Q!-}R9? zTxmm9@I0sL}7m+7_M5su+;z25;ZeNM7lq%W`iXkA1Z!mLMfZaoLw z`vi{r$TY9|nD1K<&HDkrT+Auv@zgt^e**6I`Av7(XOhh0sesQGd`KSG0{346$8zSn zr{8UlldRkMiOM?N^U2CO{iRP;*6ACmv4%|(G7nkN~yXvBnz_X5g4sdx699koY@894snx0E; z68a(AApE)a`Mwmv{}XUmw+a4Nz^@WKaeoMR$^CWFCk2l6hWIA@@n3}95O{{K09>9G zhx$Wh??+{NzF7LQ4F8uD_zfxWTL3@G;f3gb1@O86{2{;(4Zwe#0)H0pYGXvaUwbsZ z7>lQjXA0V>{YP1P_V`p$R`nn7VFym*e?Q=N1Ad+;&-Q`zlkl(jvc31A@nl?M1>Ct6 zaF+#e%;#Oe9U%DOw(bFZrhpS4AvsXLzJWk1y`FrvD9`<3{9C?Z$4Xfj8NUs985ecy zFZrf@&dYe>m)ie6@F$7(iC^j?;SSqv=bvz$69AX{6IrLvsl$9;47l7U$n}ES`X=yL z9^$oz>+J>nQ~`JE9ks`gNfW(xz+F2=@NU4z1wG08gTP5$XE{8b0)HOxw+LEX{>=}B z;imvj{o?hM`*t!zS%$Cm5e_pq&_Aw8tB%Mdi6r>R{# zLh!vQ@M+(+%cs%)IB3wD)T5Xz+;7q&f`9Oly68c%R?%2c-w5}f$Lga06n*BtG5&!QC1yj%~c{?XsBi>MuLlk1%X_`-t{IQ!&j{1488eR;;Wr3ByOz^OfgKLWU12e@B^ ztNB@7^gn_x*)PIB2mGMGbH9jx!WVuXj^ENa62AEt_Fj{Dx&rXLpi4Y4?iauruo%uD9izHLbxn`sCv(bLJ&uB4T1MA;iq zmgFdPg5dW6ex`s+8$SZs7@Nslb}N{980@N{U`Vk;4&YP$AR&;Rlz?2{Dp!)w|>u`?c7*tXQ};X zfIm&t=XQ_%OI`E<0p~eMa-n)(0-kA%9*(R0euA0inL{PijDHv{hKEtNkG z@K=jIF`dp7_#(hvf0pRH6L2^8l;ER)zbZg~a|(Q03jAuorw8c#drJBL12~RX;xS2+ zbaEgnCT0l^;yT*jkmya+y{2Ia;4W4#ZxL3K`Sg8z-@op*>fqz(}N0pMls z7UPL8!haOcamjP1(@kzY;l2%AQPAdj#&w&g)q7_G%-6etd%vj5bB*!)fWKbgnJm~6q=N0u<9v}CMX-@)wqo~Vx=IQLH-m~{a_dLLl61u_lnC``|tWRD0sQ%Z1m$sVQ z`zhdZU(N7(JccdpKu8Cv>{qaXpog>N8pZH;0*-BVEGOcX%3lolpG9A!UJ<@jUvK3G z@Y+SV&jTlE(wGqZzW{$kw8djWxVxs;N8c0vDa(%QUV^u;yPdje{k^9Z^B3i3i}Ine zMEi#*OV3_+in81n!rcShn+1;RdZ2R734iB^yGGRihi2AWIT0@Xv+=_8cELaEe@LdJgEw>_uN!rwFU@*OxH(7p zbCBTg09^W&tha=_6u2*nah5z1{=~P{M*{-SJkl5u{`RBmqZt+OpL;vjg$nqmj;W76 z6p$hJ_k!8=(Q(3;lKs8?gnBDZ!aO|=xa=?6F~(18thaK^c|9i`r#}4!_z^KK%uAuk zS+mR@kLtV+xX@mWaGwKC`nTL3^K({neKaZBV;OV1*_L`MZ%mHg*}(mikgq#_J6r3c zcLr#4+tb=$pGAFcoAHmg!_O0VmL>D{>yCQsJ{U+!4%SXdu@M$l$F^K}lMs!p5VHv%WuCDzx^08YQNoebFz;_uP<@HaC0k2zB5Ag&U?4Lm*M%q^}hnVTz_2rG4H95<_WpG z{p#(lk4_Quk@;r&x901kKUS!JeX%}zx2W&Ze|7*mEBfu?e>_+pj0dsY{&UFJNs>$U zd|M~E{NaF~E80sN^RJu&9~Wi67w8+&BK%py_1^sgg5L*tuV{m0MesMStB;-%aPBM9 zdmi}f1fJpBN9;Mn@Vfz*dr^j;JX&wv@#6N+0sIL;U(RphZ`N47b$^&_7Qwdz{-~(O z_MC8i>+7v^O3rQLy1xXzBxFc+na}ge_0iFSF7vqs@Q(?dVV&c8$850uT5jvBfXn@h zZ0k3`oi5tqI*l7`-(J?a0ywxI@w&kL-4FQf0?u+|nz>E&*4a1FWZX{R;M&GCCGJV! z9&>Qq=g)1fk5&jA!wRyKZvuR$DDUdp9^l_9@XX(@0RNbPOa89Aus&LrGL}EO zs6JXQ>M_097u#zZ(PJLlFR73IL)2j&8UG95zaPMJ-@kk*_Wpt&uJ`1Y`ePnJ@p|u$U-z~3R?MDw4%rFn<1bFbdU9R8mm|x#&A^>6`araZf2#L1aBhr| z;J*VLM?^7yT>kL)*GDr0@D9Lfo67y+^2313SR(VZ0r0y-dCAjTuD9bUBvayPA>b3D zj+~Q({{rwbe#P~k23($h@cP3%&c4B3w;8?|aQfZt)4KpaQoy;L3jvq9z+=kvcHC&s zf3Ei=;PO6()D`O2u{YWNCik1`KLPwkp=)ltD{rxF67zF0;L;8-z0Ux?T0Y6B{fcgA#O8G~e@+`|I0pBb7 z&329HeeF(vJ*R#@3HY)=`^WDL>q;NsKN98Lc22pg-a1d@_Rj;He&?}d_$c7=%phd* zsO%3hq3I>%-GT<`1HoSeyg|TO{|I;dC+n^AGqyW~D+1@*LV}M0?%G0ve+clIq8;XI z7vQcfr1HN5+_i-S{~O>TTS&OuKjqs(f`0?>vqalG2bqUg-(%ZCmd$4XKULI|{r@9y za$m%C4*7IS%oKdI0QZcrJ#zes&)0p{_Klh5GQbf&j>li}aVc=e3LN+8V}Q%^2B!5L zz&k~GN$bGR*?V!CAH>%(z%Lecm~W=}An;oRevw%-sqT``+j3%>1Ay0vIVWum)f@bR zU61>9CE#!gVp%Z!n}ADyk=uFYWPS9YXou}2;~&`teG+))gYg&NS08;ifaiAK_{Dnf zO&#LD1Mo({C(|1MT-pq`z0UxDgwPR}-*11}jz95OFhB45O1+hr!DIAgz()l?H15pP zoUhtvMa&b^oCN+@QJ3LQ0#3iPU1EBF0{k69X3S%neY)suJXQA%-@hgJ2LNvtZLq!) z?g8N5BXHC{!H@l>9na+U8UF#`f0|ABW<1G?>R<4n-zL|+8@Qi}Hd$7TzxG@8(fj#Yk)qm!@h!cwX4DWozwg*fv2lx_E z-fi#Wz{~mO;(reOC4wJ$CP4fYAFq$D4CpiS_3IxXo-W#F`163f>kH9~{;NJZF;M<= zz}!X>V^Qngj)cd^znJ_5N;iCu6zl;32=A)Ciq7HpDEfQ zUJ3qHz+Jf${4apJ>o>tOKdukn`6JwIz>)0am=OF+fVT>`?8hH~lYL~ly!j`-T$tyx zfRlR?hMy03NG212hh%aK;4=kZOy^60hh*|cz(X>59`M@)9ofGRKN*(EeSph;%Q`=I za4eHUpYmnGxKn{c7%rB*q<1lJA-TL4@Q_?S4R}Z{-vvA*mjm~P<#I6KX>$1w;H0k5 z@1!f=0sI}JAJW$&{E<)Fa^wD=1$f##+63G@K~u`+KY$C#=8J%bWb-q?L$W#Wr(xO5 z2Rx)RX8?Xj3QxZRE+m@+pRs)pS2inwmpa9=xdiYu+1v$On%?{ZxR7lA2zW>~Z~R$U zHYWle(wp^whh%dh;AwjErk{spGZ*kmdh;*9hh+14z-K$-z`FPpaB{!L@@Bby=@<3Z zy)M!#uKORqg#Q~@I~f0ee^sA)*O2tQ^EdUWcMTQ(w|4AOuIq%K{=53ryM}}xde)8; zai2a7xT`B{7k>;~$nHK5ct}s8KZNz93GmPydI#VkJ-HI_ke*x%c$%Ix|IyYH?%#62 zr5;FIaDjv4vHB?BY4HV;<$M2Z?{&DXj{+`zFWJ^Jz`aT69m}}(FSbw4@Yez^{b+7u zG2pF&j?}@6fCGE+njn2$;`?FX*9ko95Vtw^uXdXZUkiArsK@ZzQ_4REILVUz0xth7 z;DZ9r@;>)(mF?Uez{~cz-j4vE6!f@1jKA^!)kj|ycb=Yd}-Y=9h_bDpcW-mi4W=C8m@-FERGdcHpD7j1K2ndcXQm-Cq6$G_m8 zRZ-th0{nJCk7dJseG>Rkegf0|?TcaCP@kD@?PrumshJkTG; zA6q{?`nJHc&N2Saz`sYxnDH!+?t`XBCknij$91os9$hglu@PLCd4BC-)2)3jx0wU{ zFM=nxuidYiZtYLG-T>euf)|!QxA)jejj~CbFa_frgMoXJ>x$@8j7_kZsh#^&- zU$Gx$yL4Ig^$m;okDNqaj^gNdv1^G_i>AOLOxScr|^m*q^ENdCe5s z@|7%yPGQKXb!!ZI$6yQ!xpkuj8*V9aKp4p^M|CP}QBAP<;nA|e<#W0GU~dW2G^AUu z?#5$MDh?Mh;Lc#=2aEZ&+RRkueO>P+r>Y!A%{4ePs=R8+qUC3t4)b9N+0i|#tI9%D zWKt!g30 z#!Jo^5f6snWw~Zd|E4x9LAmaXLm99Y3r^3B4j0sn_2lQsPU)pG?5ctOp^@HU*f2{} ziS7o`mUQ}uN{N}^nXL#6Ra}AA4UKSzO)XW4M%LUIyBz#3{v{X?P+pi zfzEa5RaIHE?#zOfD;JzgQ?zH9B^H|vW!Q&ChQ^0_he4Sa2IDnY6$?cu+~{V1o!nR& z!t&`&9VLn2LTrsL%}FvRy?HGER)ZF&n4ZH}@3ByW&504x_@Z${q~xK2zz%J|D$zTf zGhT#6Rk4+*j<##$j^y+du?kx(6pGHGGE&@_+t54g)yN5B$;#xI9=+^!sqr}@Lxjk1 z`IMB4hmoZf3r><=uDUZz&t9>x`^;Qd=7hn~b;T0~hDHW3bxtS@mB&vQ$mbhc=QPb} zY8dT1zf6CgumP@|MLQ9KGJCS;hGB`~egP7?H2dizZ(OhpTrfDL?znrDeX2Ad zx#Dnd-)IS{kQu_n1b%8!7+ZZ?7yWoUA9lW z0!}yylYDRTIGS2JT02|XTRW^ibSV+4&MGEt|0o$fM;xh4c;4%pOkrqUuE}at5o3iL zER;OoXyqAQ-7A-;)?pp>3dCX;Q&_Po#LX@tEvyv?C@&{q0^=sUp7I=%4Qla1Z5L+7 zM$0gM8)8Q}eN3cyxT|7X5E`qfC?yv>j5kZ$bXpB!qJcamv>ZsWv7&7#;!}1dOm1qY zn|snfF+7|ji>2ix>E(@Uof+;O8ORK3VbJsxWU%8(XxfUU`=D#7b(qW>OBH#4?q1z-&AI**2*kDV4>7I zR4(QQN3r=QL#>S9&}c4KeYw@D&wAqT<9IlQFQIjJMNWAXRtFO+MP|cCsbyBV2Nq7P zw!WY2EIDIV9Z#0GAtfuazD7LWi573mD<(OI;-d**^d@647tt#jIDHa9l5HMTXk z&OCOkR5bgp<7W1cmS!$mzMyO7q7}G zs_w#%QJdIa3=;M)jcy^$GVB`SEieND-H$5RwmF?0Rr@n6CM*NErW=aJgHt`w!V5Fn zTY@1bUG;)#0V$-C5KM0DEsf9`#M}s!8j+9;jAxOE8(qf$DG{t2#kw|?fEa2g;jn}h z&%@#-qi1rePvmnDKyQlLn4yssXk+2_DA5gsI&!ouxFw9-X#98^k}x<{8XYM0u9Ie6 zwy3r-@djK~>#8=OR+y@3uFDQ}A{Wa;kwoOo)vFK_x!8F(Sk1|htt*95GY#B^gZiTj z$<{zl1J&GyX6HxQm0$?=K*K{LYAv*jn)zpjfQuWbiR8vJhD4vZMo!^Do3O%Sd~;@T zFbwA>N+pUMjt{Yi#bk7a!Hh9#{k`L?I$VNm479rhtFuuKKjX(H#t9rZ>A}rXz;N|% zF5LAIG-0~W#np5yZW=;#KM!>nvMnyHuYpc&8Y||p;%G}`ONfP>%Q<|-4Y4f1Oj=bV zUFNZ?*%(m<42|@gz!*c+zuY%gOXl7faxNQllFRoQqr)g8Y@08Iv_X=DjWLW+_org7 zbi;|sVn&oPMuaM)5o)yZeIi`MwUm09DhO$eQ!rDSbq<0Me54N{#-VkZdzP5)S7*Q< z>gVZL8plRMFVXB0YV(#ACZQH!#s#G8^y!6Mb~#riIhe-iY?oN#XEu%+;c# z8Q6aWPIwInw8Y}m9<>>dxy?ac<1WK$!(q%}88JLIHFY*3=v?V2ETEG-C`w&Q#Q_A> zI5KIE-r9JOOU3-CC${+LwW+zS9o}EngIAY27BdQyg$F9xBG}a|?njJe4G1`>>snH} zL1RX6kQ$u1j)sSr98p#co&yQTodWS}R!7vbdV+zO$`1|=;{@AmF72+aML>eIC?8~S zt!}-@dq2BwVohYztVt+4qDv?v*VNcDx19%2mS=@FJ*6>01-Gl(r21tH5oL=swaW^6WNm_ac3H!l zC_n)Rql3m>(p|CS!Nx`}My>75@zNq&O*8`D!Pw{sbS8vO%!|ZY?I~>$CS}oz&JLOi zau{5Rt2)I_Ni$(cyFp>xP=9dxCY81BrYd(l3ti*K6pYTLn~)G+rqbBp=JF7N$mz7% zZY1tPh@3X*@sXV^JkwSc3gAD;MLgKr{Rrx|^iSLZJn{}5J^h*++d3*)XuZ-=)nOcH zC3b-tVgH_$Lc;o>!Ep|U**ygmpQ_{%xhz`I-qu`250#@Rhk*MB@_|8Jw4$l8vmJdj zx{V=9&O_~CGK<_;cv%N_)Q$@2={*r2hY;WDc-^6)=vy^{MOc^wV3vO zrQVW>JEn`Kqp>5|!x+cK_#Nf^J+F?k#kLl=y5#idK@ay zLW@*5m9wN1iZ?xDeYr7j*sEX{**ng;Vd)yu+0u!*<8v13g_&r&u(0KBO0Q5>+aIDj z)&M2r9B;#_Z%IZd5|ZxgSYGQ;a4TmOA+6{g2+jeV%D_hxJ#B6?S<9k}_!Um#@KCSi z=<`Sz|1)ffWBq99Xi1jbVAw6i$x>D}6kr2aRxd~38>VWPqQbLSYrk0`(^YIF-VVEp z8+Y9V!qoNw=|uhExQ4|h#iS5k%pVv{Krd zo4Sh*6|-ZY@Gd5b=Z0IcwseQSyu}nfW|Mu6t+@CrHsc)~orxI_vXd%h$LEwR$NHi-l~7((8F7(>y`SbloEeRX%rQhDq-n_ER_5f==!ccD(xRNPs%#ylCmDN0uXZDu8> zDp<>))}GKZ#TkC0liX}F;kCrvV|!IjFKjVNPm6>?ZwbAk$raxeuuGWLTz0FH+_aR1 zFBbMX9TI9!tbJTx50i-{b{S?)Y2O9m4CBO%AWw=+sb)9E(%m*(^co%BK%qub8aflo zEz5P_2&Sv0)7(E$B2FsNT{lA)_RaFX<3g0dhd3tXmcw(fX(N!*)iPJnUgj`_`g~!H za{!$ZI2}Ro(lnpz!f8>TQ^Isegq~uq)bN_R1!N>(Jd}G!&BD3wS&pCQIOM2{D%}fW zA>?{ZSlt{b+dr2W0 z=_c%-x|%wgsZ$sYI?;3%Q?mpsLE+w$LzzTpl3?{e${U9;;}l$5d-Rz#+@vxRFZ3xh zOMXp{D^)=}Ni2$cF0fA1W)>LElX5B!<#Zrj)^YeJZc&!)AMPD6D@lwuw<9szF!iwH zn~iR9hUFC`TyYq7+vSuqWmC!sz4II7T#L)+Yz)^^I(uWIIEQuZWR2)~xJ zv85F)1%W`c9M|ZVo zGv?Y~s|_qUu^khe(74O4bSZR;Atdt6E$yKp?827F<&io~%M+?nl15icW22UtZ8s*y zV6YKcSJ^3;UCVNvq${m0M#6S!n>FZ%H?69Q#%P9R{SZel6)B&`8AU0!v~^`w`>Kvr zCK)mAg*E(`T`Bh(O&Cb>A`)O?Y9z`c0u{>pqw5HqjS!c>Mem%|CYE{AgkJzQKb@c^X|-q{-Q{%Bg1$5=;OBme3z)5eBR?IHBE9LwFbpO^VRc zs!V`8pGhRbWLZ9r@Iz882h6S1xOUZ0yK(@?1~fVyvbcjf)6&|4)g8Te`NA;e)*)kh z2y1&f6$c}dzCcp#>v-*Sy%viV%zP~9ouyD127!XGKdDJ{XGV(_6V#@m54!0PN8 zSYk?3mTJ-tt%MU797QP!BXN-v7UU;6AK`2%OvqyY&?aZBQJMWJTDcvpY&gx}tZeLR z)77NiFj)X37LAP4f#Xh-rZgHlc&Sj>` zYM0aK>2RUE6@#pk@{<~w*4OVm91BZX5G)6a#l$}HgwMVSD zUc~X1SO=skDknNV&xnhtiA9SNcK#SwtYz3EX#c=h?fwZ0*@S#;w z0xr6$jgW;`T}#;!a#acyFq>wt=7LMwqXub1wWMx)u^&7-W}Q$uHE`uF4S%+nw--*X~s82a zcPMAYbIyp?wJ0zsC*d2h*PbJuFv^Tlo5UaD- zUvKNn{WZF&bWc}LcJM}9U<#UyAIh4XD4ALh+$BTG4nbT@==kv;M+T-zxwtqbl$30f z;Lnki{_1J0>=5@i7Lky?+ak=M>;X)oTY}<~HcyGug;lYwsgF%HDYH}CWma!$o5_`L z#s)jEl(;oaBtvx1U3^j}l8)Rs90^(E$k%hwZu36F?o4-U_zb%>j5OW27C9tlag0YU zkF4%eb?b}#4!UKc9DuU&SZJ|sYDwK&IZG2<9oi}^%yq&{AQnL5)7mN*H5INmQ-bb8 z#hVOsF`hi0z&4{oSKVlsCr7=1RjSfqI^qmg1?pXuifWCI^Mum()D;?7<1~O+U9Ipt8bK8~OtxY%MXM(;oJpwJA?6K0%Ath_h&U81cEUj*r-s#LAT(+=7&%>z zoNlwZaOa`eopDIoY08p=98shcU`Xd;MF{y>qPNO>QsK!C6KeK7PkMNWj2e0AG+^$+ zYfY&*CZmXQoLF&TjFwvU*};y7R49r4aG%oyw=pmD>#ezPmnN`n#XxF5xZiARY{^*d z^QGCCI|>xC2aEt1WUJRqcR}eNo+uA$*EHy=Q!8Rv1L}`CE=N^c7(C>_6WtYu+KcNQ z8qPWs9@|L)S}>`VWpHYdL$AUjK_(3mW8j>s)_hP;ra1*9_c<(q>P05SH6#wR#Dm}tJ*+N*q(aX^=NIn!ilwzft!EwNhqpF`1(Y7#VBv69Xv|%gsH0+- zW>&kiMGG*OWd2p9;M#?>mfV%r8Y*ph<97?4L9;|_IMg`?{uy5vwo?(yJ)V$MK0B*ynf`hhb%)Q&$628X%6SM5p-No36QWYtDNKr3Qm!Wn@v?K~#|cwa-i>-K435HnR(A(R zu;w`>9N3GsLylrvR2?U?tD5+QB#w;iCzI~DR608joim9}X>;XA)%KGkcl1TX4bP*& zoP?~vezxIijphGQsK*PaOMNxUm&|`>9>}p%@{F@ZLXv78Z48(ae^dt_8mA9YdpoUT}u+0CIRCE(_yMwg`ZFa*@Bo=6^8 ziOq=3jH3ccq&XM}FoKF7xe3R=Tz?3)czxCOo(vowA$EH14x-7YP=l!B=*u$YQa<1s zT3zyE7~b9h0XI5DYHe12W3@TSo#tDpu_UdbQVD+AEpl@V<>)Be?#GzBT*ps)6RugY zTC_7XLOz!eynOaI=|F|UN9?+gD{3-miMu$XqSCPGyh!W@Fv}4K3+A-AE?IA#L0!zYdNNl$L#5e%Yz@{_B#xFiY2f+n>@c#1#=F`-JyozuAG z@DR6<*=}x$BW^Cg@{!t@l(7VXr6E2-$IPec**w=QZSi}H7{4keWA~5e#+HyC9DT@@wF_a$@TCcU#+^{`O^_KQvh)a)5uCGXovst7a zaa)6znzR8cIK`xmg*mfc3)>d7oMsAyd_~%_Hnj$guF@xC7Mz~YxdiQ3wSjbyWE)}V z=yOzh52fPX<~oqf8wq)Ph(V`YJlZCwq`HzSQ{q{2E+rn_G@YRLPg7F7T)ha`y*Ozr z?hf4BAv`kdbYIS7%iepFnT}1(67A4%^Z&5gs^zvbm~SInth8W+{S0ysTUymZ?kbOr zulv*0td6n$BkSs(;Y-$pQP0J0x3tvO0|fDyS+hpFQI51yM-^gIA(_Tto^qvX>byzk z`*{wb?33+p@(9aLg$LN8A&(Jb!NmPf*^h+RWJ_2yfgMrNG|^Mj{6nnLz){Rv-Plq& zhxphP9tCylR-D(gH*D!Jx%U2vW_rW!a*|%sT~X3YuF;`JHB;SPeG(6H`X|T47;uxf z?hi_e|L0C1Niy-{$a|KT<=k32jn)q>NovNU@*`)mkY#>+Z=S6x45KYKV4>|%X#G~9W=(>&Zcf)ymnf&4B~02y#kVI_ z0!N#7O)9+thfW*&oHnc}3x`8}ZOJJk$tEkDE+mbO=`evD3L&rFDIyz5Tu?s}Cml-4 zn=<=&k*wq@wADpre)Rl|pE8KYIyKp6>em55%QkVT@jW?-)tNRMe18*H)g27^GE$&& z@$*F*R&lX1hg95`YO*76hSs95>)9D#mCEbffsW3(w9{3uyptbBshn6h&RDZx&8m2p zFLhBo+7%CPit31aT5bedq}As5)~ds-6tiWgV7AG-#r?#o)(DJDn#bsDB%Bu9j{1Q$ zcaBu@Mrhk%0)SIg1hcHCXVqCkvn-pJCuH{pL6piCdR0qnm5e@@Anw~a;O!YQM$;^MY>gu4zrcYy74HtLW2x^W(`6qzc{hgD5r)f@ zFD^P93p%^%usv5?KjCdtLlO>WLA&GW)=cud$d0!*22=FZAzPkQx2*h>0;p2=nAT(jiE!P&=O_XcVY!<+5+VaQyQ;MF^drj z?tAMzO{df_m25@0yRP*Bd+bh{PkL2h0|~epL^9N_x@SSFQ(Cr~z9aNv4tA24Lo-%u z97d?X1@=%-64&Be6AVX7-i5CzEeXNVrE|KJCwjykL09!t`1Xon1T5?4;QvI<`9b(vNRE{=){6YIvjBOUF&_4H6t(Y#UF?W zmw8pcb$UvWQ8NvkV-SbSfKJj}@N;DN@|U4XhYxnny+w(>;N#6ByseLmYl-2caSx;k z(Nh+wt!N)w315EbN|%R@NUgQJUu=A^?lB<|)1dYxf{&4y84ih>i`5m_a{M%vv50dMT|=4*`rVbQ87E#wE1 z=LAvHCo*h}fJoVwsJO&ndLT0bbF_@RZn$(zOPN04Ci$70-Km$(%zQK&Lms1!wkaKP zI10I}*#99bi_R2Vt3U0OcuxLCdP>ASWuQm$pNPh;yZr>MoFCc=ryZ($awed06Uez$qp=B5i?n73PZ>lN(xQ!q`!5N4Ld6Xv zPpiE(*xN$o++%}^50xxTVLo|dI?)L6?qx7F2BW!(@8ZX`Dz;wr6fNx@5;^@8KG2U{ zIDM$tWLJhR!v{0mEj4vQXy*EtA7i&>{mb+aAT+kL+OLdrWt<)=y*BLfv6Rs(ERML% z6e{n}1E-X|E4*!sp+{&QKuBkMOwSNFRHL4XK&5kYIXR zE{zxImBKL5+X^IMe(}@+zCJ<`Lh>B=2{Sw(RP4ptAAZKn5>7nHRPrI`c{OWGcS<;aPb1jV(Ai7<#3S^wscQHx^V?^i8XpSGBBag}KCKs#Q%b z>Q+_js=0V1vCZjW>Mc%MJiRL@6g&!fcXDjwZFuljlPsw`OXP=;sfFG|^Qr4J`|n@-J?d>J=0Nr>ECYuMSwuGFCoZ4F&)hg6yyy`{oTwLsj1R9W(r z>JDQs>vN)#fpoz3VH~m+lQOl=*KAqTi3-uiu8FpiCOI}_?yL<15<%&!beNUMTMFf#hU3P{ zqUv{Gy~(cjjecAyB?sDah+=6f{iod9!0QJ_^TQ4b1u;S?97<;P>cMG`@ff8$r{aXr zo39p8XHc0{>;`o(L%)-lz5tp|nFKz6=#6m>#hg5EPB*Tfh*N$a87zlEam`u9B56r5 zH@0jhAtY;O;?R*QX)mGf!BillE3^egNBzTJ)e5?$qG@tBZ?xEEIna_>P2`F!KWr6i zLi%l3X~iTNKTT0cEEq+VrjdrnbulGgI_{3-)0LJMWb-5@c0 zAFcuySHE0G%;LLg6C;H&dZM$vV@k)QOh$A}wT#3cG~dQ|-@0>%8aFvji#l;o)WDyxc4GWOM>Lc^L@rRC`wsQTk8Y5HKLixZZQKCo!F zm9C!2UQB-mEq;uM1>{sk7=;wOv9;-?Dz;YADQi-^UNJ*LDdSW<#upv_knKFZhM#W~f8zD6qV_tiC!@#ur!V3yu7#-5kza z#*6f^cyq92kG~)%Y=kaj+!XqvHhfs@0Y}O>j=ccan%RNTD+ou?_ztM37Z;5EHi4{6 z6vDGksuP)+RYg#Wn^AY)=(D&u@(r*yP6N|qkU^Zl)R7ZSAbmiSCc8aD2|!=AzHM>h{=Z zd7QrWi|1$k8DPu8xYKw}9`{w~0|MSafK?nzELzctuTf0NPKsV@ZuoPNIc$7}GW5Me zuaU|cj3|S->k=4-%2mCqv(yEBE>5mbQ)@?SXG?o)hsP1KuC_h4%+xI=no_uBfY*F+ zL_CgDevbl$ZJYk zR8efSkG{C146`1wI835n&+&%Q)a4C3?MLX8iZvEvlwV76N%~iO6;U*4c9k@ww1VLy zN#xI}3lhRZ6%{J0zLp@RKfn~=J78Lt9^d%9!4Oi-;}tSEpqW^CRDDvZ@j(jy`4*@$ zQzRC$>ns-08%Kcr09>GCC5y=W0R4zfSZ+>Bc79EuJ*T`DtXY}4xEfb-<;^cRb1@+n z(Z$eeP7KpQoc@wjm|-Og`#?dDpD{VHU`{A+w-OLsL`7-2Glj6p!`|_;jA=M3Tovl!8m4nD)8^ zgi3Vv5KdopmxWC-4!3BdS`A;GmFJ6UGSC;N9djyNy&&QXfkKseuup9R)g5L$G5OZD zS`BkxVv3P9tX9JunpCTSX&LB1<^Fs9@rQjs3HVyT-LsrYzgXpVQg;!Rt9kvaI$pfE zzI;*o1HGTT`r{s4;Qe+&=2U2pwHSMbL7St*yY>nQ_kpaQhv%$B6=@Cn-Ie9wx)*|T zRwX^G+T;ZWiv1?#L8^2n&1CH7R9fVnHr!R+>?%|f6MWoPl|^#Q)g9rnA%CmL>>4+Z zR#H!>G-iXyh#3y-^eT%pY!)pYFsm$hTO0!ZG56bwQ|_mAsNUVm%BkKO2ndPIXmx*udt>A;9fDY1dciPh zHC_*iLQqg_sf~k;Z1N5MVE`9Wn+9dh^TVTo6Dg}4l$u>Q@-U~AkYPG1b28!%s@bX5 zX0LZvyNW-zac`Zk=yCnSR@2xLgmkou)`X*3jw-muL#_M!bIRw?d&vhUX`2OW;?Zs8 z4x~(0Js>bqOcmSA7x|mjv368D=j9n&C~h+GZ{Y+@;q=E$2H3X1mU6#(s)r(@E!7nC zwzw&w7^}K_efj~ z2pTW5qq2_4?ZA3U&wGbA_HHg$I3RB3>%c;0@&RxGuCgYJ(7xGt@q6`QTgI|Bwmxm~ zsBAoRGtCNad@<8Ljw4JYU9F7vOXKqu5F02XlSuM1-zG z!iJQK`tLF&ZYvQlp#n&Hg>gF%?(vV4s#1l@+h16ZMi>ESE#?u1$c&>?@ zVJhU2q{@@0Nk7qKW{*wL`fFV;F0w01p~ku6DOGTg-aCR6AZ&8z7&(5J+$tVR&w?iH z#yv3E7+s~20sR7!(Ppb&OwDv(OE94^f_x55A=Dp>l$oG<)b#t|cP!8$DGj#WKZRc&m3AT&H8 zVC9$MyJe)8Wb;B2VbutagVx4SJs3}`llgJZ!LU2P^ew2AijElPdew;QA(uJ4R=w)O z!_-tp5GFM4=tCx*GQU4eG2DNx%Q2mH^Qbr0S_+(wPnh7AP15=cT@8tk#o{zOmC;ld z)@oz_#G={RpcNQLd-T$m)MgPj7Wp;&$dTQ!^_Ln|rT6eGad$$+>Y;m65>kaZX*Cj< z?Z!HqRh?(q1ol}<3)B|3xt-oUtmN++h1SwBwA6Ifwvn#^Sj@zNuQrT$*ds7(-sI-B zO)XGUs^RDnuOa~(O#MqHsTyQ_=!#x#j@QBR+M)eXRx{V^6{|yij$QZ>iK3a`GSs&2 zoKQ8hfzknqruHUet5+JWfHcj>hy|IZKP6K%#YsGkQ`-H?F-|TeNGMXAq?M1AlCGiQ zEl+_`)WN7{PQOj3WuJ^oVgM57zDhf+sG6`hm?}Fj z-lW*H92T90Kcq}S@24^uZ#Ajx5$xY;y`Orye}fd7^;P<+*Sb)}sWuI9z0B&+d*$zi z$T0hs9t2zfd+hNYWlW>s*gM?{wW-=dbTal)5-X>StMc|?8-&B(VeTfAzhB1AAk~$h z8to8QQk zwR_nXS1rIVtB+<3t9is~DEX6Q_zFX)O;yIqleQEfCj%-rhDXuyZ+IM}p3#~Y-0AJ# zsJgpG-xG_k@%SjZ;1ci*s&cSD+uzEfs5V?IP)p1KTj(vUuCGSnzF`wtv4~aQGFqb- z?`?1qOBh^VwsD4t-5PhOf>`vB_!Nzkig=gFv^-lpSb1ZR9xf3~iMNo#n;jf7hq$a_EM7vDII3l@G$yw9vX>f7HN=;YMma}1;Vtt+ zBM4)RBZ=b`C7_EQYBKWd*0@~^}W$?x> zqKZT=)Q>7NHJ)~c8V3W-LMO)F7NHy2M0(JEwXXC{L{C;YLkK+7lW2oN_y%f~L!k%Nni~=lkDAqRU{dh1DT8oU9XqBNT(5a8Q%5>U zrh5f4Dl{2ld&;t|sCIVCQx!#}@SId+y(B67%?86q$4@uBL|*oze^v{Dpl@(K?4MBF z{jb$z`rgi6bXZZW2$wn1?#|HZ3<)x%7tC(h25V@gdKSZS8rb$v`$J$P7$jFjgc}oB zPH}xa#71ECrseF6P}%*R0>ZEH)sP=*G8mkDO%!v;mK+^PSKVZHXePHK3A?GFUehGE>~7FD)xY(ICodD&jHr;s^nUM*2tb z<~He3d3-JY<>SyXeA}6xEXt@Hrc$Onh-Xb_A|am2s&nWJjgZb~&J2y|?@BTQ6uUt= zgt3sZI6g6kSBL1j_TbRKUgYzZ1)cp zhjGPR%RQ6Fz4+m(=V$0+|Iok*cuH(y)0}(;AGtQ-&8+LiAG+aK5JLmK!{b`PNK9j+ zsta07U<-mA-Kd9)MoX!O;(VmI(cFMn>V%%)xzZzWM7mrY*ns1$ z@yt5YIQ2S*5?aP|=go+iG#x3co#0UmCPx?hIs>z{8h~!>Y9i+IQnr>QOfSiGoXCK<9@28jG9lC2B zkM>Z@5FEb$kW-yeGZt9yy$@mpXdZ>k zZP3n%&8{hqQE&*5fb{^V%RCS{LPE(vQ?K!Wm1abZOw6z1Ua?CSqzPp34>~q6GEpwl zFCAP;4@pL}X)FOJC+P--*{$9{G8bS7YEg{ws=S3#jQC*1`(SZ+ zEWo?MC2vnSB5E#AX_BZW!{UdLz*6n=q(A5A!zo`t70-VM)y0t*`ZGpZW4dbj|qo=k+j)fk&Sp(r)ma8YL{$Ae395Zqzzf9&lByfw!B2kO?HK^wyS^7A9aZrI;=Z!Rf{}bd`lt?>3Wb0`H2gqE$fE z#c)|bIXUUobY>Uln{8G>Rhy-)WLgECd}7J;Ge!M*3kR2=Sn9{EVb~=0zH$z?DI@|4 zXbo&&!gEi^St36)wuVX|#4(#Gk_g`j;GTGeY#MSX1Sy+M%mS;H5-=;9%a*TQ+7?(8 zx>DM;Cx2q@t;+uR`V&``u}moso)n?gkqv>Kr~~n-Qzf0I#-R@AvNV#xu?^ZDI73w>AeH4L+A3QMnju*xUi}WyY@}4H5 z$+)A5AfvpZX^N|stVPZ4l9Zhq2dh`Awlz770l~Whe&aaa|cw%&QF7&j0 zqi%vrcMakmFpdPYIkvQfi%=^NyIs#Tts=lC;4+nMoTiy(13!3-i*_O|N7O26tI)QZcapr)0k5APAjfPdKJ061 zjznVt_(XE%xnPR{e&$R9`Q3jDW_AM-rnq0Uq7{LDxa^_fpw0)yN&^|-usr~4@nJ@u z`Yg;7suC7Pr9D+kh^@qIaF=8{FT<#$rF9iXS#8^%94&38@GH4HQ&}c-{bZS7da5Dyhw8ZcE!c?C z6s{HS04%3|rB9>1J|r0@xc*&$rgycf>o1hoLQ!?KI-Ad}CHIcwT68p{UJst`D7}Yt=t&SvFs12DsXNg zmc5a(*0;F23WMV>2aK2Kq{NWikVcXBsxig5Dm`lCipDyG7g;oM?cNej6lt+YW2j4! zwWQaQ&fPkcBh0hTvlZ*nI?!`esK@?9j@kfM}>X$iQ6PMAn)5mUGg;0FXBx@M^zk7d;(sNeeu&&ahauN9NGYx@L1d>CB2c+ z9Gz5apuR{zY$Ri)ye{Nc!A{|&HixRuv1iM=LRNEO`XC3?!pu<}?{zq^Y?u1xol_v# zzB_%i$_LavSi1|U7Wj^VN=lr{vTG!sth@0Lgmq8tggAa3mvwYUk9+D^VZE{Kh(A;` zoJi7d%Je3tUED@F2e~<#h5)LMw9(5cI{IZ@lM%&moKJ;Rb`K?mbDj^j7NV3(%)CaU zuGJeWD@yAYX&F~v;>jSNNm~Qsx(R%H>QPrb=J650SN5KoSL-Pfp8}I8xZvWnFvM2k_L| zO1i7sn~J@W>_D$z2`Gh!GE6cUBT8hVvs|1yB0;b!J+7)1l>frv8>V;S7KY&n;59c_ zI|NUvlB()Qv=W$XhRKbiVWcL-y`uf6+cEEDAX(ZgtcP5!C7gt+Eu2Is^a!%W)RfYN z)lU^w_Mo&ukwDr5;;a`v#2bMUp=jt+;BroXwiVGe3Sl+NH)BPE7(Ha7CExz7Osz7O zB6&$$dKXqzDUdlr>?B4@Eue@Mm^~?cl5Vrc1~A4gWlRA%o#bz*&%u~gL!HUDH8+E# z4$xuP<&XT!)3Nv=|rZ9HiHr#sRnRW%E*i(2#5EG>HBJNe+br<$Bh8;OZ~HWw4PRC zVf9rQ23HZVEN&XT#PX(qfM^Y^aU|kZ3IW zEJkyI%zR>FbeKPKu4PFpDj!uCCZ@!gYmJD#^olg;lJZZlVXQ$;A#*Q?I1P8Ul1m;P^yMW zD7O$(?j8>yGOtZY$YQcM+}npQ{i>i38~3y^4ojWva$;?$t}=I|t^3RIX;uXzWLw)~ zt3l`1cFut5S4c8?x7^lAM$_z;P3aK56&ZDr#O(kNI>ew(5f-dmx!_#2>Mv`x7_Y{G zb{wloTPv%u5eu-JE#>gJ3v8##rNo^|8!nH)RHvh8)1Dl99n)sp>TyVlta!4Yw8d3| zw`zyvKUIQ7^jV+E;7O4-_Y();SFoA>N$+$SN9P@m8rOm?FbxDXsS zS6y*!L#HkrsA)svj9_D-G(;~E?`H?C;;gg2ElL-vg-M0-U{ocL@>+{WUgs_u}I-s5VrRAM|)D4z$Tea@svhdRPga!+yzCL z%!FOJRoqd+tuxcORf8GwX(hqi3Vc)?uynKFd`ZwWAX70aw3+nXH(IC$s}t}TxSzB> zS^`Ldtcv7(E23bP?Xb=EEJ}z(flEq z_|BGuwcy2t-r+O-me5LamDEG`j*qSz%2V{ZSTeInP<7agZ*7Po)Jdn9*GQnJOp2;k zU@uV9qh6tU73y8M*)@!7W@k=m?-X}B*+0dgTrL)*@jnDAO$X5R6jU{V(w$rWoRB9E zeb-Nem2AwuMD2IzPS})sOEr^@YC1aL;T@Q2B%J`N36wlugRlbfjgah5iEJ)XA1%at zuasJdjL;lk>DCsc5u8URpIRn4d4QA5Qiv{E(caubp%98$a4bZWMOX54)tHi{(71_g zi2_N#koh!%p1ACh-qOKUoI@O}j3mRHW?a~@P)XjP25?@>lndmS*B>a$;26zpb`nx@ z2P~kaB7OKSKuU<7Iv_=Fwh#d-EiRve3Jst+g-chU_EwBqtIFgJj~d0e0^H_D$4qoC z;VRg6a0ujrl+>quE4M%Lq%0|kC}fgW@c2RlUZ5%D=RAA;?4he z?Y-AI>)am3-v9IY%;o#+b@pC+?X|CGpMB~|J!}q1>tJ+`>qdza5>P5FE9E^TJ>8uw zcOGc0Y5X0V#i*;jt^J(^Cm>3&-|{bewv&q=+N!0aQ+czyxJaa#`>hLFQ;RC0wiI5I zQe)zT5;sSASy?!fD|-D?I)aX##S469yftljb9An~44%6CQ_sPL8?bWEI(x0LQE2CF z%qCQGTQQ2h9)D0kzEGTpsJ7e0BG0y8S`GS|vhfz={p6A_oFQKjrb;&Hf~cFbai;B` zm9W_eu1EtMZLQ_iCDJs;M@Yrb_G5;%FIuWw;nm_(XTIo3jQ z&c-G^FLH^**ViI{;srNzi43@nxC!a&xFBB#alCHXFcQ6@!(8Q$n2`&^tqc=}d6$H|GMHPCuTQu`u~6TXY$C>E^Z?ncQRJ!KY>e(|S@Urj;Z%{VI=(4s z!#{Y{Z~vlYS&79xt&5g%=uytaa?zsxd^^ZX;_^dU`}-FeU47y8FXD6_DM5cmjQ12% zuAz~Y4J$ODQV-4vdwGqC)C$2qxiNF;0#|Wd6wp~2ujEG1oM^>qXpzi3Cv?q58$TKd zPL#DP_wU6LES0q`4ehA8n7tu|X7BA>)|aXQ=E|@yAd{;_3m5iFl?<8;Azzs&eA#&G zhjFq=7|%AvY68qlq_dtYQ>XmPTIb2ZLJZBbwp-XMJC^eNnd7xOm=o!XKU8-DGX&)-Z-X~?0UpZtiSYhL4T3wTB zo`U#w)71K=DN~y!)iq6Q$dsh7_U#?cSukX_T%txQ8>B^+4GAr`7&03u+qo8X%~>2L z=X{Wzc5_Vc;Qi9I<#~19)%9H=Gi!{)1S2I3XH+Wih-^z| zdbw;Cs4#8^<$P|Jhf~+6`X(9X5Oh06EfXe-lG15pvon|Zwqyr$Cfea>LyL(;c8lc4 z&$(cWXdv^etTd2??XJ3hYV?rmfSjLY+cwviN-We(`IF!5NR=oUqPY!gMa>}P#thb>!RME0-vjaTGTO@$~EJpX|9SjWh~;VfFu&^!TSH=ZaFVT&%2SkA@WV;%Jz<4>6)?u z{=nDV;W{-fs;eB|*2hyHY_w%bHWRz;+_Om#PX~3nTa=_v$y^<&kPY(ZmrHdDVLLNi zCi38KneV0MYY&$7T{(6!%6r;Td_$MLNL~`1U)^kCeRLUY@Xjd2*~XRHPH{b=(eBjS zAu$w)4(Ty&nYcl0zVDhF4+&gXlTn9OrF-GR-fS+7`2PA@3&6Z?>gE zl4a^uRtvdpX0CGPpvzy>Z%@K9`bquE*IbM$9Yi(_-|FUe)J3h>gxZNs6KW?kO>L^z z$GhVhy^JWrs3GlAKAZV1rcCOM>2gY5MqxVfqvdFt&@{2BuBpB$JGOOW`F?h4nh1@R z=n5+g_p6 zExw&wCp*$>=Xl<^%vrJ?!0Jp^qo{Mw%A+jLHsnr~y5<^pHF;?3Tu6_bO+`n-*+ks^ z>EfEk@UgJv^6j)Xdz6-|F{K4^=xC<6`gvF)o4WM%1w)%eH<{lMCPcE4yY4xaHD98c zt}?Y!(ZngrnH;#ghxvVu%Yu|-RtcWLY3(zGxO10knv_Xe*7Z_-zAbbLNsc!Si4P$K zJs2WxO{6yF8#&5A)~jT4Aqj^NmvC?K;^2jyv_1LVfP9Q{X!PV8~76=%M$@qq& z#ab3*)R8$_R2he|B|Hq@;`=kkY1q-i9tDO8*{M337>7026j(fONsfo8cCsp05E*;Z zCpAq9+h0xE&OCWddeAoOoo*oL8~m*EnDvuvAPeFg4V|~{ef?SM`Qp8Jur!R1JC(Hz^Omwpq@vo`vKJqdo}m?V03vm3UYYO|Fi zXDG zAI?CEa&S?LJL_TRHgv-dXQ_mGZNAZnA6W7+H&2{XITPUyq0u8eHP6ju+18f2zg%*T zmNaSP48bRdV3yz-QK@hu_Ykg%v#w5(E>(BJw9RnR^M?GeshA^f{2{iL$nUt~g&pvb z-6TjVgJ>p|VNshNHg9y~fv_mc)Sc zU209H`m-0?A1z-{)p8n#mhc!`!rj;y5o)D09CZ!c_O0}Y(d%*R8L!V1Y?kFs1;*S` zVl)hG)>!&hIi6 zPIu%LujJTi>leH4Ot0ldtgPW!^DdH64yQ-Fju=iZb+MGx-&yjVAJ4@v;k6U8o5HQ~ zxZ{hhWkU0iwoY&}eTLIJSu@YLiRnZunG9A?tT|b~PIm7gac|vldN3N3chPWU5YMT* zs9fpzeEV!$B`H4RohKIuB|E*uRn1Wr)6J6BOk2WAL<#tHKWsaX2Qs=A^ktfbg)OH4z{Trj zBoMiHIP4&$p|*HdvuxgWx+BVuGmn!^5q-SQqaW?s{A+&XU;j=M@fz8;;e?z>EP>+s z{Evum%cP}WS0Vb^=eC3!ByJ0csMi<1@tZ^?X7@Np%c*RTk8-G2xs4=T3U|~t@P5zQ zhA;z+ww6f<+pY*{kpKJ?DjPZdaQv{o*C{C^7l(x+H)8KrMdK${LE4-=$XS4{1&njGoH9z)XY9vae-?N;YDtSk%Q8FLL?_9|)HdgSnpp)6mBg<|h<_HvnsleO9N zyXcWBwRiFIG@}Z0;^--ioLIu+Up}OnKmIoC$uXT_VC{ z{xa?&QO8z_x*h+dgzHuPogI0aYoeTNLVG38$eP{Rsf)tS6#tS{uW?GkMe7Hp(soGH z404($M-kh$NjgEV4I|~;=rlp|TGy}%CNEuC(&2EWwr=-)8UyO)2KUf!afaNgRBpEi*sxXif2)H z_jyyUidHV%qf8}VZ0q7mVlBfndcACE4lQLWa+5b-`76lg)NIipzj<&KySQY;zsP#7 zNy5g$mXHZw5jz--u#%B`LBfWKN>OYf&5U_buk6Rnjo%rmsHMuU%c(qw-{eMZRcEQq zY2%(2%a67~4bMr@RZ!Y;S_$TH%~RcZ_W2RZIE6bJv>tORTEXj^R}G3?LCRVl&eO9D zqgU{xe9_n<*H(G8IX^eXs|zhJTE*w;rd45og6#jyuQYOxK;EsGtEH9$+VWsPd`?Fy zh1{wUt=|PI0Xo>o;L! zdepEMN7Q+eXBmVCJx8AIjE zH4kZy8YSndgS?#Am0no7h(d#roc>`z^!lu1rG1fy`^zSYf_z9p=!wNfI{r7+jilWm zGmcIRXog-#g^_I%nR0Mzqf(vzy9%I=Cr=mh;$T)}vq{96mc1Pr4dUP)MiUi+T?bWM zGo;U`aCM>rck+^HJt`|s-!v{muiYHy>Lp*_ykPOymd0(Kw}31vaGg z^BP=J^Mdv1g!|kc30dRo5VLaoqiw!h=#{RGm6E7yJ6jH!osiuV#=UrkdA%h!yoyd^ z$cb6T9i-z2Iq41O#qvW`V=mjCM1?R0u<_-cC@sf9FZL%)BkJxExr%DG!^m=YL5yC? zy&r`GnOWEA3KiL0j$LRycrdO%wRy_PxNH5*aPI?F;ZPLbU<7yx6E}AnIzn!xywb_X zDX_BbmTqNlO3pKQGG;Pav?+8^3Fk4kw?;ML3k$B3O;OnxV}WqlQ}nyH#b>4hc`VrFlP)U??kzs5Yf#h`V?kX?mOSFgnr0m z#_Vz}xm(~gK^^iRCmCh3;O}@yMto5EhMv126E<LqHeU%(X?}Gcp3M)c&`In6&ZcWO7cYa(yU;B^rdn$KOS%!^GK)Urn|1{ zq%TWpKO7M>~5mFRJy|nQy}4b2?cqbR+Lo_O}Z;$!syTEAhsAQzrDS9RJcPdr`B) z0RK>KvDGB$Fb{Nk%CG2^o$i}veYJ&K?C^fs>{^Udi|xYNo!ozB7B7qVlif()3>?!2 zkc8Y4R;HIR`Hc3a8#68FU*M{X|H=sK!%vw2aU!eDwi%DeYu$b z-nS-_wV~uZx~df{Vr!6&gT^w;ZQY`WAhNVN!Py=THdc|yfYZm<<-?h z_VJ{k&tbUZOPTDT`W zy4gk97dEfP*_#j=nzRNYkyjB58hv-UD_tp`9GflX>6geE(~0dYyRO9uV~q5*QOh5{ z15+k@p)pchLdO2S+FoS7;aD6F$jv@)grRa1_K)bB2;z2E9QzgYBY@qG;76Pdl@oAG_8B>k0C;tecXWf51j| zStQCb=Y$(61oyg}bVrbQJlMEP-mu4ZqIp^*JSwza#=5?u$vCaJ$a&RVrc`8J=W4uq zlXB|%IDx(v% zQhJAy&dM`tQ4H}hB=YEQM#3%D`t7ni2Ty=E{lViJoWK}36pns%w8styt<>5G69j(%2S~}G_A07+h#RH z&E6CiI9hneg1^wInVS#W2IdNcNknlBc4p4JJhxZ(OVj<)!!oIkMk1G&a#rXGhtd~i zOehP0#sIdQ;$Gb4On#+1p-BbRI~v~ROrA|8>aMgnBI&8CwYamHlfwZS%A6C1*Cx*R zdDxO`jo1ll@@E_Uo`oC$!+QdJaN2RAyKH(-!Nihm=JKz%j^`zel8gWs>trmQa8Uzi z7qKcVEZB4z@}-vlDqQFeI+quH<>yD1O~Rzoxr3h+ck%j)q8`a*%*?L5?-mqW*8`L5 zNaiBG$KkZJCCe?%u7#n`OkTuo4$30x7p#p;UKVx8-YQ}&XzC=6sB)drG70CX^Dh>Z zhxE<5gwsrZ+0r*Aawh2I0b(&hdT7CLS~h~_4qo+%p#0FpSSlXd7Ub3)X;3glW-V!9 zcl-cOo-rds@K2a*<=#14%$e`J%_MHJjKLFQxOgySB$#%_jg2#_Z%?IX$u~l(U5^Gb zVuk2YnZ%M~JkxdwSdVh+>+z%~DpwYl^HUdz0?QN>L*L@LQL||>&QycpuRET`r)0vy zz0Z_k@Ee{;cU`XZHMpbSOw-_Yp`77kaXDxX&5SCV-G%1FDn~eTnu)Qp=-ET6=A@ab z+iX6S)8S;SJ(tZjCOy%Q1)`2tJ7$qDLxnS~Xa8cqOC`C7&j~rbWjtndX_gQj-b)V~uCpWO5VwD>ji=^i56fb^pzhagwd};* zZ3;!I*(AJOwT*Gw`pXuHOL1aQG`w(O{R`)}EMj=bQP)FB$yzFCL$2k9kL-e{V$uQP?n+f^6k6dk1;-4Jva zI)~s}qicR#oXMyoPos$QNONsEpFBBYLQRD<_0crXF6L&vf0t9W3hQ59$#4$Bg-ORv z#cXRvI#uh-Ik{?yJ8-A8_(6JUp}Bd^;<-_C7Ch%&Gc=5qGC6|VNG-NoNm%_?q z+jbJ;q1cOTn;>6B+uve67ut$cR59!gGs#_BcbIs%c)Uh&my^y^PE%(sDskw(By*{} z5h8w)&LqUYMyxrmV}AB*b#)${X|vq7yvHGa`HqX-cx3KrJEo}8XkN)f&p4 zBI#?}yW|NQsk<@)u5W1x2cNlUeC(`Zu_2lRyg2XP_8-RRrWr6v8i7p5eRfHf9g|J2 zxM#L(d5FA|w`*|nNjt|n%Dr9DnB#KlC(~0%@2PM4aypB#eHo`LF0mI5MdHe9^iQ`J z$-c=fFnF8$!9=?CkYrgpU`AkKX69fiIqowda&dd65@gyqH!wZbTxY6vd`rR?sp~mf z+Imr{xRRzj`-B6gYf!eGqyBT$A{&%AI!vGPa;c}BFg#VBaYIJFbtX6N+=x_@=zBot zE(Mu!SB2N3#q~exI!yfDT6rV2{D$2&Q|jX;y0qKa{hZDUvdlv5qg6LoxuWjUcbH4v zt}vFhjaI&nJD0F6R8nP5bk1qiL%Zki66lhi_59XuIUmPlDQ?dsIuj70n#-rb4|3o_Vy5vBMN5tz*)X`G4GnXo%hh5F-(sQq5+^)TXlL|UX=ip{zRwwD_{j+G& zq}Q6{xRf=GOa>)J4z%=})8zE&Wd0>sRs`L-FHPN% zRLu@Yv0d97ak+&(-OKux(Nh}jE9IGvzL~>*Qsp4pnVRL4R5}&=o(s=7EWCr zlCn6moQL3-4y_|g!g102oss(Fn^UT=OeFs%`zC*Kog4Pb%a18AITbPK{tNI7>4$Q@ zcEiln_n}hzKRipGF^8)qEKy;xxeHSlTT|I#hs#~F%fH;hbaf;2lP*Ypg@oDdqe+G( zF*#Q_oWz=!L52zO^f?n-SC7W#4x*A@@|u8XPq$tmw>|ROP2;GP=@dO)NiS2anZx%k zbcX_-HluFB_WGxk>xQnkUkVG}3v>Gm3tksS1~axIHt(mb=rGdeaw!$U;P6ZAwZ7l5~! z)tVv?4T;8uEZ530m`k_`uZ@VyJ-0NZE?wBgiC9vhqWj*WWw2;&U+K12PYP$uw8~9O zy$2og$Euk>%P(c0U{j__%$m{`^~Z+gU*X=zn!Z4b$j9n?R>}R@VTc*kx^Ql|zB^T| zypY!;riTa;mK&e9gr&WOVWJ&n zR2qkTbtNQGX31JoGLn@C z415i+jfz-2w5j@hLq)~XCe~d!k#V)cbo9*Y?@VYXBEGqiRwCHRRr+khU<_9&Q}GZu zohL~w8ljrl^n0pB>RVO3l@mfJyo~B0Tv}IoEo?eGdcwh3qHPZMIu_2Q{af5^&RvOW z49~T?`&P`EQVtrj8|fa6t`iCd=$@un?(^!7_(!p1xvGDhD6C*A&x0qOQ zZV^?RI(eN@>xG@^0abjXCX_vQDQt^eXazhu9@g98qIcp{nfeUz+8u2g#N8#Qp)ma) z*2G)fQ8Vc>RWT+mezcn{dHg8x2G&H6L`t0T6Zp2FKU);#KQH<#z?0_Vb0V7v1 zPV^Zya$&_nqRJY?$c4QMk>hsEor}kIEwQtPwmGh`OYDo1cnb>=Crx(tp*S-2sxSuJ zAf9SkH!!y0Sz_KymYlnq;AjeyE!4tf^Ji8CHaGM9uJm9zZ%kQf0Njeh9gye!9tds9_%8(wj^}{V4TqwA~?! z-#oMteHYq3zq+33f#M#_4w&>}GRNFJnYFm@HR==YU^M? zYF4J0WVl9Qh^^w8mg=VS5gqgyqsPtL#3u7K*%ebT<8JGU_n$mMs0~aTvyPyYwWT_U=Apfy>`^D)VUpASCf?7xMkxvN-#o}8ZmKd zG@(u}E=vksb#n6nuh5dU$xD49H1F&leJU$$tmKMuaoEnbUN~-9V?|FeP4|jU^Fj;W>-bJJMG~2XE(@N^FEIUS^$qOrb?=eZF zU7az8+>~M3kkLkxwyS%Z(M%3pCz9unUF~f&0ttUL<-xw@oWih0$dx(<@B;uHkfqafi^lp{#5x*25u&6tm8AoN!KMHue@H#xGNnT*S8rhLn~LT&%FSYbuqH zJ^!sSv)EXN78*&YfH}7fRYGDjYx?@N8Q!?Bax$N8$qJf{M31M@`=OE)J4&ZLDkxnr zZ`LRM2D7M!$~qsa`vijX znR0OZPErofDM7OLP@<5#hS44&6Q{1prBu@!jka#fRZ?#85K;3d-*QF9H@bTAD`9T? zZ%1jVh+UaW$24(jbOd=`@1p8gyXp2L#3!pFi4{pr&ov|d1*6f8 z0u2k-nl*@Irsdk)Ay6vQQ60^14?{AqbD3Y2Gz;& zH_6H~LUv6=uSu0odap@JEOWzK!)QwKX*}kg8JB<7`bArN3f|x`Xjoq^&A6?uKi=;*{rttFWq;;vhaO?Yd;kMJ; z*-XY&|Gaiu+hQ|GD;nCQJ2P!tbK{N%uf;puT}j9HNty^L{vIzo?~fZ#I>$^n6zrtXYa1SncqQ zbBa)^JxK2Dk)qI;)HtT|HhDJVP`_xbOObAe-NK$e864wlO>ANG8iXrC)rmH2O`4Jn zcc;s^rP{(6bxTl)kr#6D*rgjN^e3NtQvnz5jx20r1lXripk6RLgh=0t13O2h zqEc_3xRU~}&$DcJ>@n@s3x8LWJPdV zhq_}bQx@~5~<1Ly&Maik{x~ROV z>X>iXp%_1D*`#;y#@~dV={m(*j1u8;wY-prtZ+J8W*F%r4=tHI(aC$vWl=AlYBopj zAh%^>4U=+mmu*`VJ8Lm2rQQ_1q~4}p=?WHKlLm15*jY)k?q-5>3dmlaEgLzIs4uTZ zhjuAZ99g$%PIXWDZnKl_Fp-8U(~!7MOY#LIW3GS8X;Q-Z!KsW@9Ly)j9BI*n3cff+ zNgOy4lD;f4T}Td6+~uyP935u*_vWZKwW3D&MD#}ls#NIT&y*(u_ZX}oT zz;4Haw%%}Tv5jm|l(?L5AgNENtChXvmA1?K+gV;~a=|-5M1S38Vx!OG&FPw(H+Po3 zC@jsPymHxWdbLsJYW%wFg?)FH!=bFlJEh!80*8piC$0uv)%1z-j`AqtCVv;UE)jR2 zA9hFFg!TB;rokX2)6YKcgtMn|r(59iMB8on}Bi(fW$6m{Nqvn2!w|4RHrNR ztP1Jf6PhARiWPH#%cwy5{$hwi{=^%2vhn)p<({y45?QZx@0>FCta#|RP9`6d?Y@~P z&W_%AvxYCP5X6yg9j&|$k`|o}z+tCli$CRtmmswEwDT~uKgBz=df`GTeLo!y(urtI z5vI53hU?|XU$u|j9~OfBam4OezNpYp#^2RUBqbNPJ7C5bGVrH8Ol`;wQ5)TGuds^n zdY*j=@uYm&l~&5-Y*KP3BNZGx(m!Pp923ZF(F_Szc3{&nse-WwCb!?3a9_*P4~vCS zN|2L3Exth7d2m{uHw^7;5U^!gp}M%Vl6zi^CZRH=Z-FPu+S@ZorVCG7^k{o*h&*vo zVe(G7{PrjujqO?`b_crUSlu3|N0j8HHPptdF#a%_4sj2us)m=Kho)^pVxvol$Cj2i zWwbisJTK*>M!Q5=NNje`aIOW?jui$ULDn>pUJ)rO|Cra=VRSmASo35H}Z3IPN2Jtdp#q z)~VEg^F|_3iJ6B(hMs1!>Soh4+hjG;V2t=xq#+rweC(+&K{mfNJH?&0FO=_}NkIGF8H@$^% zD5)oluW}E?Ig4%sJPFHOkSCkMj;*026t*_!h!#{Tku~Q5&+7+}o-7)8 zS(*3|ZK_XCPCNdqxxmoUO^y}C$?QJ-;B-TaD%rK00+6MIl%uA{ybPTf^RiW@xuLMe z#RDy5?IKyW%}$g~LDy$$k}JlPhDLv1%7qQ5Gg{^W+pO2hP@&>LG-pPbqlJzHdRp50 zmnM6_M7E{SQhAD;T607(*t0uBaqqN&bL~>`pzn26hcj9xy7f*r-b%D#n_|!;x3jYa z;Vxn4C$}LAro>U63l_A}z8$%RAAv{$$)UL`Zf_zxWNOv{ldsRIdgaCt?mgYEp9uRG zHJ3WrE1X~FHh5XLw_UgvaXcH?xvgB*?1NfC!6Ee#e&spq_VGhdA-05Y12kMZ*?6|d(AZzETeCmYzDx{}Z`J0*@Z%g*xC9+e){dIw2tGzeP7 zy&+@alUpWosvQFn*;E_7y2Xy}1q6`u~@qZb*dF9;GNQnegi=+acZ4=vjt+%;wu*%cvg95x~*exFIk*C`*swq_XJiA;U$X z&bu*5yqqXSBqLO|i`hp+^_ol(C35IrlkJ*>#P?|z5>5z2?w6kV4(-{{tc|kA3K$u; z=#^7Pv=x+7J#y~o_$uTsF6e`egl`Dsi!l1l4kvVSkg!B3%H$m;^Y}->&7*YNkzRDm zHm=$i$z9Wg20jyB|8OTvhUVFOea0noj9Iyn%`CdG>Z1295--`)VoNq~IYY3@=_S@e z^6HnQlUZtx7m^beO1pDp2;avhWFyb6IEqNvJlh021t|4vnM(e$#`mjX~X}2ak=d9EAo$=_`TWW2@h5b zThq5b(q1Uc?c#}b4GbAFwYtE+Q^UMuBNgdZ@#d#BQbD_D{3|b;`Bg8aTHXMI*HyDa zfMe~$E&pVnUC}^cp(QgMuGEYqd^$2tmm16YPNk(G%5e5Zq?ML zijJT?O6WRrNB?f(knG%|?Gr2kv6a{?JQWUFTr1QSKLVJo_PO`d8M(6IL@o|{i<7Gq z35(@vpAhi5l&^B{cvO~6Cd{i(m=Pts>-F7x&1o+)c}>pXQr?@rAC$R1c}pdcz5L^l z5`_|cB4e~vgOlv#Gtx=3*@nl9MvZ-{9ZzWML=hOuPBWK>_?fkkrHb9_5Z1pk`AU_| zPOOkDiBzr2#GSIR-jL9qzHq9VRH9qg&L<1BpNSWHi1ijxM|Y;VtnA4u-~=|P`t^#`#+wE|sul<(ijVrAS_wy4Byu?$hYbe?l_XJ4}(~ z)zfrwFx%%wuB#1o?)C!DF}nUFky5iJC9}W8YD#@V&U==5vATT060K<+ye)U4WxCsq zuAktJ#j$I0uk{suf)sC>sDXF`gL6DN{)k$qmsa%-u0WrF9zuQO8?G0IXCaJu_ zQgJro7P#wK+NQ&&usEc}?RCrc$=^&qPR03OkAP@Q7y;P>oYm^CFbmeHitj5#e#TmOd^BGoPVXSe^#E7KnH!sh z#k$iTJz=Z#0&M!`P1X}67x_(dUW-uKw{>~b-8?Wm!BZ8>ncI7yv?rO3Az3ATLll>g z__rxexu7;-2Oqo3SHZ6JxWA5e?Mt89QI?k^ zY7Qmw&XDvc+piSaAoq!%oO&1S49XcDYO9{;<|K~XK3}pHBr9ev9cyZC_PTDoSo`O$ zym+rjWT0rSZsV%hKBl`A;b{HSFYhHv#TcewZ)QTv0vXqcgmq|{k~SsMNLQES!h1qA z-C(4*jAUzpSIt1mY1=O{GIiUe)&IQfKU>pc3j8B?azVol$v z$w(_1!;qYn(`AyT((=rxm-NqcTbx>pOAd{S^PHS;7Rx1_E^_NGHq+aQkS(IzM~VFW zCbVX5KH+BJ95?1Be9=?>l7h_HlIyeuD>l)MkAyCv3raTPsl5h?3vAz<>wu<<%8ty_ z9d>4wRx)^Y(nGAd60fQa*$-I|F}IH{p{}Wq1w+lG6Qn#Q8&^>~m5@wSv4SzMZE#L* z$<7;-dJWBRNk_Fsl^zAWuCZOp!F;95F0v$Yo!bX;>n(d%+8QF+@+M7S{2=enTw2MY zF4xOkByqZTa4UaOg*om%e4i|dM6u^pri6g48<`zkLv0D^P0aKzJN+73Jc|~!E|Zs` zCY}gN8r;+!yDc=QanI?T-NjUvME-s4@>a;(fs-o3g3c*)uLbR6P9CJrN`I8lMcm1a z2?|C8rmXVZE#d6{)iSs7=b{>AYjA!uVj}skl#pz+^e~A@*d|!mz1u493ZF9dQ+{9Ik&)HST1;XCYL14XNfJd9DJDIuAihSXFb^QgZB)GhUZQK<~IDlzkoTkHPcGQD&y{X2-BL$(wjx_b;!2 zlsR{a>507KbXi~jTzT1CYpK_L;W}Lgb8{D#IGDS+)Ze+dXMVH0!V5%iD=jT(WrEMS zb zB*Ymk62~lkB~GhtUEr?vdLzYq9Ot)q#X}kNEn6^${5gxch400^9Ob&WzpIC-Lq8?Z zHpiP@t`-HQ&{~#~nYj!4OTTzWsq|NV#-CU!P3A{G|KPik@K}B%Oh3Qi|L6F5iJx5> z_1jYEEvJ=At^8cT&sF^BN55ajcbA#(Pp>YOX7kg_&kla{qu*c1cQ2do4;)r1y|DOH@=x*oVQ==|uQ&2nzX^T#{xZI^-=D#Ejl?70J#6Hcj4YKt%+IIzxrZP9 zEGzi_IlliLKY!D*d|P`_JrKD&5M@SNVCGAN|~1@ckWpe_xROvyuN|!S|!y zP%4e)=Rkhm!H<6Q`$JRT_tut5{rn8@^BI2hqeZj}U(`+*Upqkp#^b}dKY#ld`M;g| zpL-=mZ)tqb!v2o&C!PGRxAwQrD~<1L?dvR!Z(r8Kh5m2e9xwBk()j)ko<|$cvm9LnEp$!P_>NBAKrQFGb+&V*Qfa&#KGa8Y{?GYs z1QKQI0@|nX^H`OXU*lceKAt&!NV8R1)*KP-n6sGI$@(KK6?+%Y@l`$qyCzXZ=ge8u zu|y@^Ykfk9(@q1hl>V!6i?P(;JNgtw^3(j0VdZAP6tD}ENDk+RO6KG`k?TaR z2G-B8@Q;+}?)*r6E09}(+)_Zp<*)oq;irlpkttSn!y;zGHWOPtIo{?gEtcH>9n zR$Vo$ylO968~Gx9L{>hh@$=eiuPqe0hgS|OKTPZKW&YQ6<$L*Q=I1{_uJ@C}%Dp3q zm+vH9iB{#?_@AV_epjO(HLu2mi=23KH$N&@gIo=An^8)_C4VZnnEyrBJ@|R)nqlRa zsMY)PzkW2`UcOMd(kjx$24ZH>sLuGbDxhGxz&e{D6hV? zTskm>$sbMkV?j=AvfSkr5aq9mM^1qaY zq{VK7(pAsdmXcfZ$X=x<#d*U=;~U05`o9FtZ5Up<@=cOM|Ix5fDY;k99a&n{ zqf&7khoFLw*6O1tgZUoY*m=a7Q5!%p5? zQQBM2-ch7o^(-}q(Hrfj=U^FWC;99aYOu72o+TH)-Sa%$v1{M>Z#UOc($3M2`EWn< zllICpjWi!=mps$R@{#t(vmYW!JLB0`0BKJ=OQ|s8h}aK#qbxz_Tw|sqdcm zlRqV?*Ph?#nfmM5x8zb!J&$qW`fIn+0s61|yIZ0Kmi$XE9DjBzF?=k3GVd_b$}bdf4jI2=@kmmH5;4 zux*0a>&wXNNBA*#kn5!;?!w^XDfkswJW+Tnyvx`TW$`rOm*Dfr&%3xl(i=w=|NNSm zm%uNtjd>${0N4BR-^kKq@adl)Rz8!aK&~(Iw~=tE`4azr@C?I;!LwoM`z3rbtRK-| z^xZ_b)JzF~2jT0F7*Up%L%1FOBCPRW1#f_*0!jE6;f;pB2R{X?J^lbcV|XtDwix*% z;XxCA61>guJb1g|Pr^G4e+4cb8K?Jic$neW;IiQ($Vj!}cf+F$UjUDWQQPJ326%tN z55Wf-9)u4uygP=gF?&+vA5 zzTrdZk`@}C2KO00AHLAA%sVbN`~ZBZ;jQrHhIgfl`4chTljB@GZk9z>gZ9 z13zwf1^ffU_rgCi{0#gP!~cSRX1InSz%LEI6Mo)sH~bsJ*TTOyyb*rc@N@8=4G&{T z@i)WA!2dKn1OB&RSl?@ehlt2{73jg!?MzK zvEj+^rG{t0mm9te{+QuA;ZGQT628XpHuyTj2Qmb`(QqUD8N+koTMVy+Z#Dd7_zuHc z;JXa}2foknSOykfF?>4wHN(B|LxyjFzh(Gg_))_zz>ga)Gi3gO;qmZ~3^&6+F?o^!^6hK z@g2rMY%jy_f=3$eh2LQKMtF?jZ^DNd{w;i%;cBK3M;Wezk2U;$c!J@Nz>^K%3BS$o zkKjhb|A0?5dUJM-9IZe%$a<_y>k>hJR%EG59Bj z{|Nug@F=F3zcf4ve+@Un|28}qe$DVo zc(%Ww?A8{jcHi z@NtHl;X1W<{r2ZSOg+F8X9QYQ)%i&uMe;&TW@Micf!+(PBGd%hz>c8RR;jbB< z4L@Y~O88rb?}i^W{51Ty;qCAb3?Dj<`fqp|{1e0H!#^{;3jU?x2jJ%oZ-swjc-Nz; z|AxoGFB^Uj{Aa`c@ZSu78vdu@P4K@B{|^WvK|4eK5u~!J}wSF9j=G>3h|u}&w%#~yaMips{(%!UJYw}--U02 zcMIWvgzq*y@~y1j7@i0}WB45SCBqlNJ7CP~@^=e7sy61w;IXi#_Y&L)Q_Y?H@bTOR zghvD(53h%{d|KdpVa?B{;IG5gLH;p#v*B0ZXJEDezQ?it1FL;cfp@@~-ZFTv332@Q zz@rWS8m@u0e5-2Z4)%yL(-NnD9o!6S{O^OiVJ)9dcmSRr^W$;SFcfhL*{}f(rc(;kA(i+3Orm(aQ*7BMK zKL%@gd=wsp_YL}g6|Sy}%kNk4IC!5BUR{U1V9nonxD!_Yd@np;xF22vYyDdTZ-DpK z^x#df>h}z+pUA%TBg#}`XWv%{KXG#GKQ;BGQoG?9@CsPt{}_C~;RoTZu;%B_aA``M z-$N!*Utul()8Pgaz7%dYd^_9=j|%!d2j6LU-^r|h!kXT@;p&E%2jB+7Ux)h*{|R0P zYk3_qh5O{N)}J%sEru_Fx51kKb#Tqp5#@%U-*@1CSg(H;9)M2@;lGC;gEc?%(*(~p^6l_CBmYTwgOR@(-UO?C?t_P&5Xb*>cr>i>{}HZ% zRsP>_yOBTQcjFG<#9yIdT!DHVZ>+=n`9#(yxgd1VC|MTz_ zMt=C)u)mQ%2wrF8kA+_}^5??((fT?29V5yNn_c~!OL+OjxIeoRu7O8}@O$7!Slint z;hC`Z7k`2KVfEhwPC!4yC&Bj{?t-6zHU3rbHWR)P9^DwnHwf3m>K}W(o%#%G{dz0h z3v2(<1g|o@4BlX_|2+JZ;UB=S!kVAoz@?K$l&6LK|1Ufn*8Gip2kF78&s*UE!|#As z8U7%=&TtRB!SE;HO|Zs)GyIeZ{{}p0!k>g+HR1mcE}b0f^B;JW;X_WOJYkJrb{W>1 z@H62?6aFE1h6%p}o(*exT@Ck|@O$6^6aGzjl?ne9yv~IG3Ep7BM>LXu6MiWClnH-3 zJP51)?}1-6;S1o>DRKCR;Zd-b&u8Hp6MipTYr=mBH=6M0;29?Tf8p7NN77LA8h)!Z z9O0w&Yk+X39j<;EeFCBvVCOVdV_8D_coz6{sGn!o4Z zMp&=^Gkk^#FVT?9GCUUUHu96;rSO3v{&&KwjeIw}-pF49Z-5UC@>j!88TtF+SB?C4 z;2rS6LH=2I%&D>dJK%A!>ObNX@&nfd`9tB^Mt&MRVC2t+SDNs-@LI#4fHxZXweTR! zG|k!b9=QC@Sf8ii8d&xD4crLpcySxtY2?SyP%Jg_N5kuk{PFN+BmW_Ii;-Ulmrff| zW|;2u8GvhHE#KSVMp*TE0Gj)qFt~kHngr~teo_qoBgmu0*>@@U)wLA`mSDWjPhd04T zhxp$Ozhc7Y!}?KuN~g#EI6(Ll@UU?GZSZ!(--oN;9ru6#fXBgFK1Vb0X*N6)UJk3i zABEQ#z71Xvj|u5L4sU^X3A_c~3adYs-bH@Q_4~lv&Gm=Dqt1xsPlsz@jqd~SSQCCZ zTyMfx!wn|<8}M{k^?wqc4UY@@JrA!i^5xUXAFSye0IxOSC&PEc8ebE<2|hf;*ABmE zL4{Q3rhZ{`z$aj+;Skr$KJR3eTq+biKF!JZZYm9s+ zyvfKfgI_Z8>)`E1{!4Jpd*b*Xfv3Z&?;qfqut|QMtBw3U@OmTvEqD{mG|S2V7~XE={{@%d8^>RL7XAQh{D;ELuig`zi8w?374AU_-}z5;8DR|o8jrO>hlYDHmvc#0MOg*Cq)fE!_re*wJI$ln03F!Fc8>tK!lLHHRX{~P#4BmZ}}bWR-qo=w;v z*8JAO(_z);WOz2L@i)V(jr=9>dLw@gya`tQKL>9&^52Kc=f?4Gg==7q|4(o;torQV zjQx%L(eMDQ@xKk;Xyn`B%|?C+JP6kZ|5^c$o*BpgC3q~X`F#{_gf;%3!b^?(f8Z5H ze$?66AFdDa9|k{TuQc*Y;dQXa|8aPWk^c(( zl9B%oT$&Zf|1KXJ2?WtnrV9*BJRT;X93d3%m(d{V#xb82L}b)gO%G zzZUl}3ILUI%OZe}%Ug`Gek%{f+!v;ZjQ+|B3Jku;#ZDJ_A;LE`n#n z8vjaojgkKT?#{Y2;hs0a)Yj zgC92XYvCu1{JroXtnqJx$F#=r{{bEcYkvO?H^LhKh*{X*$WMk>8u{t)I#}a>KfJ}r zUk<-y^x4!8l<{5}OwhgF{!;MuUYZ`d<||l^5268V2%Hm@J1s)>_fEwM*fZPAgu9^gGaZ=@xK=y z3u}Jc;6_;EUkoob@;AdPjQj?89jx&`0zYHqUxr^a^8X8$I^y{EZo&Sr=C=W!4y!(= z!?R(He-^yj$bS@GZ{%-;H^Hj^7vSwi{%N>8H;(^BxCYkv{{c6{s?VEdV}Bz*0Um%g z{!`$MM!p-~Y~()-55gM%DtPp~IR3B0V`0tj58y^v9FeaWq3BM@jnKyHuC=uUT@@IgEzsd|2}iDzmY#4 zE_cQ8p8?mv8vlpjW?1$47~F2;Z-NJ4jsGrqqmh3G-fZN52M@v;|8{uv`EmSjZo~et z=C=-Rgf;$C;iX2t2VP<12jF$E#(ypRjFEo`e$mMP5H8IhQJ%;j8UH*F*Tb6Mk?pMa zz^YFTJR6=8a#&@OC4A3S3?o$A30l18e;A;90Qhb3NQ`v{~ve|*7&PB zxj)?-$3GQ57S{Z}8*YS;3-H&x!D8cz6gu1+FpSAB6Rz_Gl#h%|U(v;kUuV0^bO4 zfp-u52)qr}^7@0s*B7TZaz6Hi)qma&HyiGRm%~*dzN_Iiu*QEcya85wY=$?&ql5g5 z@JsM6f&UJ_0&98)b~D~I;ctOU{c-pVc$DF#a1E^ay$T*{!taLbVb$*&@Chb-5I)0j zc>(pua4pN zT0al#<$j#unecX4>-S2yv?P{)2rk1_L7$i4(eS9i`(A**z^eb@a4o!l2(O2y8~JnK znXu|J0MCXs{rlm$u=?BY;rWISTts_f_)K`Q;Q@F#to7wSconSrZ-v*ws{bB+v@fvg zzd!thxqcixXyi|aUxiiw3*haB*Tba?WBs3jcZan;@6pfv57zW1!ed~KZx&nwtA3Zm zwXpivYPjBnKLAgIHNMB;8Sv;}|1EI4k^eW`4{LgdFUDSm&xNmm)&48st6`9BKYX2MU0 z58S(4zKiswzAuEQEsgCl0MCH;3Hp5sZihAg`{91WFThv8s?Ug}v=4@-!K-1l&rSnW{@p8=~sodnN>Rp0l)oko5!ywu2F314C4Z-iGH z`3K?kM*auz1|z=}-elxogP$_;qn0ziH1cnTUorC2;2lQ(Y`A<;tp8ki46OOR3SJLu zem@OwfYo2_f*&*TPr}a_`RCz5_zl6nufp4m{2MM|d~$KT|8^|Ar{PKPaKrC}M;JaA z9%Z-_euLp<@EZ+(96rGCXW)ZjEx)_rV`0tzcVYcR;~~P23i~yLYWM)~TR9P_u~S%#m3`(f4R@9+RzAL1K%8UKWjmfs-Z$MT(w zA8H7%zBIo6?eG{_+oxG@1FZhP0Gyb9L*-VU!b@?V4Rh7Stzo8iqy{x9$r zc;67d>*dr}6aE(X;DI>(6W~U8e2_mA?u9k|#qfZUzY<;vYx+0BcN+Ok@J3kE|1tc8 z3I7+o1J?XkU4egmBu@Wecm}NLp9ar{RemPi4Qu*c@CqZp8eU`MZ-Y0%hll(<0KaJD ze+_Rl@_&U(m&NkCeU$MQton?H>tWUBM7R-FeP+P3jQquLw~=2755TI=XW{imelvW( zk^eco$;kf^e$mM9cO~uB<*`0T!Uw}|3i+J^p8%`=t?(JJwg-LiEE9eU+-<_Y1TQz? zzk*kq@IS+AP540{!#`oIpKpa9HsR;NPnhfH!&^=Gjqocb{0s076aG`U`ifZp-@^yP zn!h)!pnjY1Bj6KE_(Rt0q+*B{}ge_%?W)3E%x1>Z=Jq3_ihx*TIb@d-EvwQ0npnRR;A&X)?}BUK zH;4Eyf~T4AJK$!+Ps8no{{i>In*TkoXMM!*7w;7-G5!`-l!|CR7^!}q`| zjr=#^s}27MUS)U?zSi(x;MK6kKjtRJcP9L3_;$m`!*?3_R(PY~8{o}`zYT9O*FO#a z!tih4t%kS3&l%qR)6^HkZ-iekd=y-|HZG3_co?ktc|SbbgwKb^nD9@+<4pL?@UbR* z6MTXR|1sQX!v6-(FyX^KL;W-1N5bufXTbeNz7<|-!Y_wcnDEu`N)!G7yw-$24zDxe ze}Ff@+J5~DzTbo&yq5OagufNuY{Jiix4`P(v*E2K{Bl@7+MkuKi{}$J5`GZ82SU=n zJq*{w+TXkg&w#c681-4^Z-!5RSHb&)>$~CmVI9w04?hKKfA$FcDy-w1SK#W^ar|R$ zraWQoe@=m?!>Z4GxEbn8n0`DE-`x89srZ~PM@4&y{-9q?GxY6*(;btTM2;2+r8RWOaR~Y$Y z?xg<1YVQxhcbf23@ZBc-G585s{b$%0SRa5j{^Q{tMt%`|@TX&a?}Td&KL<}UJnDPhnZF-vIyk znwSUS+gA-Q{|SRj_@Q^xf2|%~o)hHX2RDBv*0&9w4Xc0k!@aQ9=eyy5aQ$n$`uMiO zf4^~fxr+gk#J~4F_#^VegMKyeN^^ZPycVts;T`auCj2H?KiXbyB>aFNe;46f&Go;9 ze-EpD4!M{51($>TnecX4%ll&Z;I(o6y%9bZR{5{O`qA`f6Fw%y_g%u5!dhN0!K+|R zf5d(G8$2S&Pllf`+ycJ>t3E5?QJ;({|sVU7R$@D5n(|I6^`o8$Ua^(EQ|Si_Hn8)1$Az3?m(z6kDzwfxt> zt6;U)gYccO>i<)C6RhpmU*Vaz#PQdEnfPFpzX)CpYy97UH^7>oVPB!YgVkQs;aAM{ zSHsooVtf4r9tUfF_Pd|@4D0ph!LwnFe;qskt395B*TCBT9Q0MnAJ+Ij2yZs>pMeJr z{~X?Kc>f3RhtI|Ndp~?EtoFMJo@RIpJj=+B`WpJdGlD;y4iCbr|CMmf=i~PIQFu12 z{{KJlQWHLTBld+g{qx~LnCkDwE1!m|Z;ko;aD(B0!Ltlc{W|RltnL3YxF1&gJp`|Y zRo{QY>tXfpNe@z=;87v{KDe|#PX9i5G_2*f4X!u*)`#$4SmW!2JK?=Ue7C_Xjr`N_ zI=C@}@A5F^dC&0j{h_@(5ng`Z@bbSfkhFgn!%H3*UVecNMfjWW%x?}aKN!OQ2iA|a zFQwb!^N{!aMya$Ptp0N}TnnrJp9Rl=)&Cd4-LTs0CU_;R`Tqudr@8(&@Mc)^U;ZZJ z1z6KN1}@zmU;iHXU|8c{44(k2|6d0;!&-hD;7(ZMdm6sN$iE7&H9YcLj8_dG3qJvC z{?3A5g4O?e;L;s2e-a)8tNd+nBdq@aEqF7m`uz#sX84dz)Q3Cc@H5~uV9nohxEWu$2`h>6IOp{h6mweOTPXNz>oYa?$5slfBP51%dc>O`0t^#d9UE#yLz4l>qq?ge0ba!>fn!5Rh6IL#mk?T z3O@(Fjq}zCrajxg)CrH;r>cBBEc#svUk)E0cr|=GtoqyyKVtYX_&IpLApa})fqkpW zZwdTYSU;lQYboCQyNv%&92xv)OzExgrw*%f>*1o$2jCkIuX5uD;Y;8bPO2(n7N_rh z@J~;vDz}IH{uG{iYOK!=_-a_~d*I`oC-}~)@+sl^I`}>Cw7^a9wea-aef&M}FWy~M zZVlys1^l-6RF!83`P<>oz_$nfCVbLaRpqw@{v*5`etejZZ`fwe+iR|J{lDaA9Q=c` zWBb1g-u;}a@)hCw3*f8ZCj(y(pL=dx{tv;A!h3}LzW{ffS5-g93 z3KKr+`;3oF_&ea$hUda-3||YcHM|j?X8h$Tcpc%I{vY7!CVbZ)aQnW$s=OuS=WzJU zB~|4mfzN;+y11%5BG{t`-oCu5yddyuxZ}fwhw}e2yl9}R{PA%8&)^;KnIU{TtRJ!G zh$m=Y(Z}mIrZfqD*yLvx+<0YNUv7ry!@mmgZ-E!DkNxRC@br&WMf(fi_Cxxo6;)+< z4~zKI68QaBRk`;(34aN`ab;C`R%kz7f*<*KRhhzZ@^8km9{EI7G@tqa{I*q9<*^|@ zH^TL|Rh1c5IQa+QmTRlZp9uU{c#rF1{ZIT6=h?!l{}u2XZ?7utp@j{#2<{b3?5Ev*$}a~#5x(nlRpsvodvw4XC=aclSHX>U#rc00o)7w^A0@SW)MnGk*}yx?oGJzj>l!*2@VHP7--_=rCrmEyDEr@l`6gN*oF zdn&veo^9&mGI-pBRpkl6|2_$?YvDapTrcnYxEXFY@^`|Gv*Yml;qxAf>+g5q0pv?H z{`wyY6JK?R?`QB6T(9--kMJ|FZ=c4L{tgeqYlHm%!upZ?R{ua;n;E|I+kS_}TD=m#fO}Bo2wcCl!7PJpZp%04hsXV+s(eG>4e$W^k8#(JEPVr> z`cLX34khVth4mx${!@zo4L@9}j>_|mzrY{icW{whUkB?)uAi3TbK&oyKg~Jz*uOLz zexSNK8n0ar{~V?na`AmGb^Vu8{7rbpFXR0O&%m$lQ(f*3?ZwORtkKo(d?wMa^h+Wp ze0Yfe0C+gOci^|e2f&SiPlV5dwLLi-UJ5sa@cHlt_|U+Y!B4`61^zVrCzIdL!TJ&V zd?CdTr1(+z*fG`ac^lFH=Wr{0e#qaS;2#`VUH)`Pue_E1{-Emeje(DXcNjhuzV6`a z^7}$~JN#S2m%&pGsV=V${q1U4Kceq#@b1T}Kkr|91YW*1w*Me})+yCdeR~bQ9#;Dt zOvk$RhivUe+_^2 z$m;U3fp>kbRJ!Ob)#amue;)+jdR%q6F2p|xeiqjBX28R0tIK~4;pfBufO`U81Gi78 zj@qk-;ZMNYUi}gNDy;SGkmou7dSZ2XW4Qh#c(=N0IhM!y_xbRd@CSpwpMt+wUtNBG z2)_qj(^y>|7RviO@UThLk0Ad%{OsiF@_vE;1;0F{I;#I;2FZUzwOfA{|CtOw4a<9^ zgqz^)Q>)A03h6C@zjl0exhbS~Gd%q5)zSF!5qST1RF|&}@_&H8086(c@$K_#%In1H zvb?uScmk{+@t;%Rb-#)4FSWsY8GpJA-a`0jE|U9epNIeY-sa{GWp3d-|Q9%=6&HE`H~r zo{#K-%}3Secet)7f5UHyUsAq?`uUf^F@60`Kb_wIIJ=)eY%gzy%}3>T*GW7N-iN(t zKqBQ|ybed?TiyYmC!YT&951fN?}2}?`%f-|a|B-vHx&2Z4A11cY5#}duLk>_UwOW2 z-&f&}if#LU2LC#U_R`mn!m0o9J3niVqhlHk^gAzWz6{!A;-} zf?L78M1DQt{vy93xU)z<2A=Rs4QH_X{F=Vma5r)N8Mv3=*Wtc`H^cn}e+&B#+Wj}m ze&q1{({=rPOl(IF@jD;u_NfDRE%7@exUTxADZC2K)!YhhFx2nt*4zs|0ULk50G>X~ z%Iod$64;FIxp3Rz{&4(aIouPbSnl)Qg)bT5cM3Fr2~US{g%oGT`vI~)*qS*p9epy z(=UYIgD=#)7XATVsCfrG>lVM$O}EDp_{*_=r-!~??+4D`jkEfx1sojjcb4hvJ>h*Y zZnImy;qaTc`kf1Oeskbm6Z}rOZqMi7zIXVYYBfUX*TUwb#?wZ40`jQ*L8WiLQ9Q_w zpFiPwu(^H)6U})ynDG|pYXt8RgFX2d6%1{ehY&&I9mz zeLV@zqx`rr?(;h;#i~E5f3AW%(OzWl>bqii{a?1d#=$8sVh?qH-wVgBu=;udJm_Wm zUzcws{N@_JGo1WXeK)`>*ZST4tBSvZFI#H;<)d&%*!auQDEhu|roR6icn)mZt0lZ# zT<-uMf{lIr4_uq_Hq!SieK(Q%8GUyn*Sk@E*7_!Y~o;K^`1oxU&p4s7(#jqui2{mx?D zzLVi`tNhO6nxBLlyzY0;C#d#a38%q{I=_$ML2x(Czrf4kb98@39z-7LuY7&I0h~a8 z-K{whHXkJ~ZQ*9`SpRh(eDnK$_x%j&`BUH}@E(2tVtD2Ue&@fsyj$UWHduXi08ZY> zb)8;02I*UE`!|EL;V$}mS9lR@+G`kWKB|0U;jugLpY`)*opk+ib-&OLufhjPtUlTT zALBae${i2;;pVL^`*7qF1vi9K1-F5lH>?>xuiF>y#dSyLHw5kvQ#?2Sac~FH8~6Uzq6M6ReNuTAFf{`JU{ydZg+NQf4jOKaftcwUaMcOfOo@2 zA54Iws)ycBq|(oW-`M95$N#>Bm+j~Ix;^6#6W{v5AC9N?fouHi564sQhSLxD!|~L& z75`-I-3j<<>SOxv%p=Sf;q!ETn!%?XwfeF>Tn|px*9XF#;Z)6|;jwTp&G*3@;GvqA z!x_KZ`!~Qhz-Byu2R|jQ{{?>nEB{!vN8O|NqwrwO&EWyZ?0D)3FMv&cgWxY=Ge4UG zPo=+&{+R(^{iomQr1N_YeiSzP;T?Dte7U~&VUGVY9(0ZlHZy}tCd`{Ns*Te6^ zM*jE0cSh9++jHj+;$6`-!uF>Hyd5_FQ8)P3m>SNbI={higV-A3`SI=WD7ai-e*yjh zZmanlxS79(vr+R2_z0Y%%OC%z&)2Ue?91`mRV>HI#0KdBdbU#q%)1pWhlLf>BtMLHy|M%ce>3MauC`ugQc z(dv)Vm)+rc$fuHTHQ(tEFFhx;KUL*l0DlOd!*#`_@ON+x&9}nM`MvUxeyi!50jCOn z9Db1fB5|az&HQ^Cyq)-X06vrazJnV+>o{4+kK$^_*$=|+U90?R<1aRZ_i!G<+}{~a z9Ut2Nq4LXvCu;w%HsvpauT8SoXTT+;(a!AZq5PkQ=d%B*mM+hFcwV04JeL@{{tZ0( zOX54ad=V$mzm(skZ>u=nmS+S!e^Tgtg(}Zv_~AxTPE%c(XKvH_ou+S&aCMS(BkP*ek5u+jwf_jXQ1CRkV~0q0{Hgq(gBy$fS_}85eJ<0_+XbJU6XkrV%l`-5V}vdL z`AF$Qw}j4PsPbG6KXFN{!!U5`n+Gou@-qSM-#D~?LZ!bOp8BBezcui!k48CT7+5^59NRa(3fUWVJrh3j)ktTRe%^oJd%lcvrtABM!F3a@yv&4C$hEIR{T!-1X>jvYTfaQ` z0rnf5ugf~U`y)=T=IhqL%5y__ z*_sG99;@ze1vm6DpVaBEfv#I>iQk9`ds8*XD{=M)L#+w;`bt0F?G^ZOdW>lyE+zgoioofPTZjX56k>-a}kx#jiyR;lZ+MY#T?O1}s8vHp{yuSY~y^To4&%9QUy zxJ3JpYCK#C7qCC0y-q&_e&Et5=QmY;^1BCCp9Su9bQ7FECB}{Csq0JOwMka~--B12 z73=y-Zh7G7IgS&h$IA)0mtId-&re_@MCqVdcl}7E?+N#t8Je#u9t_WIV&!KV+=2Zt zW<1Y_*NOVP2X7bG55lLP9_2LF{TCC(_~Ct0;r4*zI>k8WYI$x4*E<^J#v9c0`@os_ z->s>?(uXB*tyii$7wh~c!-Zq4K9~m&L%xlEehqG3W}o*H+>QR}?6#-h_dD#XQPcT@ z{FMBk$w-@zyw=m#o4_re^Sk@MRe4h2!_0rK(*4r`?mpXbR_pZF!-@4{-TlZa{cZ44 z&KH>aZh)82zDA$#gMCZ<;r91MSMxn`X=uNMx<4LHoMP|Kgg1R-R>7e6m((*hO z?)7$bczn-<&tU%BT$gVt+_}P4F?>`sblVZn1 z0FJ{yF!FFM?5h`whpF-pfvbNP@`n{qhff(0Lw&xhxU{#gs}5&CftJVoRmN#Hz( z_(M<1qx$PSc;MTi_<+jqGI(ZMXn&o$eiOV+jK7Bz3;BNu_S4^{KR$-vJulWhzp3&& z1dmRz?N!fD{rGg}?@azKg&VCz-)VUm0GDJ%J0moYfYTOMclvAjz8h}Jem2t|&%>=b zFKXmtE1dg!b*Gt@?*s6dS**Xg&-43YaJ=sl`u=?Qj@{8tM}0j5?s^mZuQd0EOW6NE zQ*$}|^yRVc`h}|BEcki7zfI|bSKz(7th{^~zDA5QQs@6Fe8*c6?s;$ZyiefAi2v2m z*S~@NF;+f~!Rvz7UN@^n|1I#l`_t6@0eC>EwXY@cV4)vp!F}gMgyrpRI9>QdpTf6& zU){M>_y0jyedfC5;Xk#j`G$OL?P)VueVXv650A&+M=KEH`_p5X>n|Az3;Bx}Fg!HLw* zO-yr{1~0?(s8O@52uf>PVxAHZ|R zg!T`q`@e^mw}^H&>G5|0_R&9P{57qEeHQwl4czQXo8NWt^%0@<36~cwL?+ z;V7X$R>7;Ew)cMuPh@->|ISypn(x);?f7W`uV6ffQ@3U8E5mG1D`%5 z6#r1=Sq486AL(49%d-`(HqY;D((ShkzHh%1)(GyZDVtLD4-RmUmQ?cV}cpOAfJ zt_C+Czj(e=_g@PiKg-tV7C8TCv^##)^#|bWwozeyyA)0o{r3T^KJU5tah3&6FSq_( zbbacp_tz-<)&Smc!sg!=-n-5EyE*XA$yPs&g=;LFAHkHJIm7the?&txIJ5#!&lIRTy`^lvY?PrXQIl-36$ z;5DMZSHQKZTYJ0_?l0>1J-ix(+ShUcIksz*B0G`@rZ74 zx2Np$X28d3pHTXmz7_C}zhm5Zx@!OJ@J2Bo{0+Xjt}TD{2FNe|R%pD(`I^Fi;&1iQ z?UN4AI49PP->Lkrhwofy%X2&Yewo#0tKdaNw*NkZYqhiGJq+K-`#Rs%`a1eN>?`eO z>~BN3L#9pN0bX=zb!S&pNS>~Pv-;Zk-_3CPCo#_5y1!<^5%`xzpF9WmdoR|Fm#Ol< z3(pkeZx=jZY^0N@^FIc!?rO_(7J=njbwc~U)%`8t*DkaEV?Q`T#CwLr&Bgrj4mgGV zYG>*8d<<^(i5)L1;WICbbgtL>ax*-yc1`CX>6O3mGyG%M>dp_*q54M=h@2|?l^}er zu%~_CCBmN@2hS1y>|^lCD8F-`F3(DMm+%k1hPTxU#p6|d|ALPTdlVmE&6mLVH1qe? zaI;53`dTernyHMexhQzr7Q_^%<)l=EKQ%M}_^Z zx8cJg9^<>Pny=*_kxp#{T0Q?9c(u?cEnvU!pW4CySs3G7t;;_i{(4<>Sl`_br{gae zefy$f5x@KrUL*ALPw;$E->AmSABbOU)A=`pr-=DeSNNEa$6@dU>{Bz+EBkaO{ORPV zu)q5>oGRvfAHx5^-@Q=h|0BHqG{5teW~T}E8u>T<)doJTm5p}{gl}tX=dYvTJwm=8 zg&%Bd^~1~X2-c&FKK~F_pC<0}i2cJkZ-nCOYCIl?gZL{9M|XTSyr`OQcT>OfkoK3; z;Z1+r`9@dxoO-e0`Fsg{5AA96?Va!$qhj6oz3Sf;a6SCTR_^otzD@9`N1~k3ntz0^ zK8N{(9zWHZV&BkrM*m+3zfd>Exm?R%2HctXQH(BcKX`2u>mQGVKm0tjpF=%=HoQ`_ z&vN+qh|u{mRsT(J`l1M@lg|G~_&5ANV~=B-VZVsisPyeE=iU?J?#EH(-3sUCvRt4hPMfOSG{>P-vyk1yHVeN4%}GylWk!2ndx39b`H;78s%)z?UN7h6Z+#e`03L_ z>+PyN?t?ouj||7tm%+Y=t-byZzACG_^RU*Jf5A&deDVAi)qJ@6Mvfy_nlUs4N(BDEI zWWY;kf72h=z=wC)^_4PsuZXA4hUXmm7Jf(M|1I2}@kI9M*ZRKGQbO&Gm?2;6 z&4rf`Ux?TF^?|<|9_w7M`4%`wjK@{*SoVtPs^?fQm{sQLLeV#vvzxkBknWCR}4m{}sJ6~!A|8TF>H@R@pfe7b$ zUH|cLI_rbQI={!^*1{k97~X$nlrvSQKL|Gv@sb8<%!iLy|Mm*_NfF;41phrcI=tR6 z9@G$W1$Zk!As`Y{4(Gb=+EA|{QcmSVtkaq*$rZy zoAvc6@X;R}r@n5lC*f7JZ@j*~0iM1o+Ibv-QvLZoyhP}$8X1iD`7z=3*yiv~F<)Q*iCG_K6u=1XlJN?{@3v4tjMtb`U`#- z|3US#>ub#!LdblJ$o?ROxU|S;ihNCy8G8ueIAA5*3+MQ zJiZ3c74efT@K-|qzl6UP@r~c%Zp`O!$KCRrO+l`CCEAIP4sj4(b;NOcYwiut6#l|k zc;lO)^F69OkHD>%pBwwQ3U2wX)$bp{jTxUj&R6@i`o5j;OgJ=N>ihnHkAENQ?k7_D zo!h>e?}j>dKT0b&GrFd83HnyG=hd+9=g|Hv#UtU)B3|&4N?)zIbF1#3kKoPtV@95i zz-{le`qHl^W_)t_Q{%A#yyi}u{xY~R{*j7*s^|5FJG~g`^wavf1U_C6dOw0H|7~z* z5kGkx9xL?MYw9}n583DXzAbR(FQMNPQ~Cb{=P*B@_-_B4fD?s3b$(Vg-!}^)!t42M z;Rm+HI`33rwc{5f1HSh;#MmYm@{l0+Lig@y2 zIHHSfpR+m;j}Y~31@C^>uD|t#2VZFCqvi1Blk9w88rs5Fbpj=~Lkdk^U-pwBTWI_k+>SI{myEaEX{d zdq_)7?RB>1 z1b7Ahc8=!W@MaOOEr<8eKgM5p3eK!k(>XwT)n9AjxuX9!!W+bXgM)Cp_11rl?8^Eh z^O>=TwQ9dh;q+L$p4|yPfjzuHm*-meyv3pS)2Q_0;H#dFaNgI~r^AbhHyHondAK_9 z3^Tv{0KRBf^{{@}1E*qNjlMbxj}`W-PB-L9_^Ykq)na|@I(WkJ8sYtdx5LfE{CN@V zBYt7Z|2q6cM5L3Y$Io7PC-ETTFE#3pe|M>!-=)Fn_+Mr{V<>zSdvE5qGvH5m+xFB0*_mGHIb3p2itz<;qHroA5jwR_ROe@8o? zP+^sSGMp~ty*HdF<}dfaO_H5({C^QVR>Vs;!OOn2@wj7fe7`8?J_d}+zwT9xhcerr zm%=ZyKg0MlZQ<7<{qFClsPtFCON2i<7`~>R^=Bu--}Ah9-9FF5^On_c-*=Alg9_*;$i{dM6-pK+YqG$+EJ)C|2ZNu}=&Zx-Ww0Q{h^ zS2wHcV*lxb@WJ!7|A_oN2_I*DI@gsq)^p(zLjP@q_Xznq0C&FueWBBzfIs{?%8AwT zRhx;~8j=2DxV7Lm@I7rJ!}IMv@Q=jf(scc9gd1bujQrdK?-BmM3vew_-`C;T`PH4~ zx;;OGJB#}6hTDnsf5Gd;e(;uk=}!@#xB}iF<_kmM?rZIS(@F3Anc(uzuctc!SWF5lk#opNMek>Hf@sr;Unn{5pMixDN9RV~+~q zeKR6l|NBf|jPC~cfnbz-zDmjCM0jzT-7onl+*!n%Ho=+ih0X`5@o)exV7<@mCy2d< z@q0#WIG)xJj>lg!`fnioEb$q$-Z~O~JDT&My8Wlaqb5bU=OI*iUWVtdu=B0m@K)hJ zoPaZG#f0@oqyFe8)>n;wx&}Td?E6T#uRkWdANM}E1bHy>IuDKz>vKEd^NDwTt;=@^ zPG-N4nIA?EsOEc${br4I`(Fyj<3Ht)Ud@-Y;Gx^>{PsHdK`}mtzy;&2zMlwZqW_Hk ze**T2_2IYSGpn&4q@TAH{`&9g;r+7*)cx;7I}5eH75N|L$3h=m0B;lWp9!xM&&!36 z=Gp!q18)}hPlpScf5+&ICPxEt#+X8eqWgZM9IefwVcQ;CW>uIL_j>BiN-`n`dQP&b5Zx-V` zr0vsr@OjwNNA>gD!KWXz`e*>$-Ldwh9G+JzGQ9pb8y@nu-4Fa6oLep0nW^_HybX62 z{{Bw5`Xkn#I1KL;{@*3nVbAeLOnrO7?-FlO{)!q8!{A<@T6voe_Z9NJ7;cUJH1huu z+*sK2UtmA>(zH+Q>#_f=Uzzr40oVB3ar$a|&;@RXJvH&O0q|p=T6r#mtFgbt_)m-A zmWQl={uaEG{TW6+w!zaMiF8`)`Q*=Vd;CpR9#y}%Y~mrT_YKk95)QPDaXRY$>IUB$ z73<8=*RO}?i~V$C;GNT~KRO$ZV1HP)PX8<%kAG<98#~~MqW%7WyAUrk>oK)*7%zLG zom=(&$?!np@k-yT@^*yx2>pF6TrS4TFn9#}@r?eP36I9VFzd(5;9jgJchmWO2(J|K z`wLuG#4{2w^i#$9bXQn?Qp|YK+~3WQvvu%IYoeVD_d5C=UjBN7vr+R?@cFme@xB^< zpYe5$d%xee1wM#88T)n^?)6-R`#vO9|Jr%fSLmlp;Pt{@Tn=v*_9_o9E@8f`pI-)V z7y4%o96|eW+4Vo?!w+A}`;&Be*1-cAkB#*G+u>R7MLIkEq5k*{o+#p%jc~+Q{$SUG zGvQQWU$24JiSm`hOnpHoD~3ID7EJQIJ*tmh7f-$;&iCg}3t2|v9v^gaXCA9LXY#E*^rc^>{| zgY~yJz>7bv?!;^V=X-di@K;a36NElKcM#(X`)l+;2Hapt==UO(f0GCACf?dom**zf zztig92jTu={J#LF&a?XUXSlqU^)G#ck@pPiZ=DVAVExUscT0F3@?+$`HGEk3yF=lX z;`(iH1o32JA0ARH{L6JJy(rJ=#rS`7qule}sy#1+atPPO_-g{6i+pv`_jiWZ zbAF+*9`D8Q-M>YI?b9Uqz3;3%JPt?x8tc9vNY(EpII~(!=NIga>d!6k#(^=;8Wfzm zz88Ll_ir@U&x^W&_0O@^e?AvpA?6>=;Y{H_b%fQY(6yJG&4#xz9!-0WgqKo3)RXHE zPJ<^f-i$td9-hto#EkzB;1**4(gC<@v^^hHy@Yrt<-LIXRQa301-y^RJg+mHD(3UI zz*9v0`XRWM&<9)K!9riv9*TVt_Ov-Xx5&oNI>QG{~B* zr-%>Dg8Pc`wi?c1erMYM2YBu))*p>1BR%bDt~Y@XA|FvaPsOuZ!@FS99#_HfXWRYJ zW$=a=8(*9RcSy4R|17LN9}^H&?ezxSpYv>Q^R?=a_uyT$kBKk-3jfwD+F8p0Ro9(z z5)x0!;a(*l4dEl4Uzz0U56%y&>tg@cFgT9-8vAsw;;yzltKb6s>t^Jq^8Xkf?zihT zKf#IUTUBZ`AFVkOeUM`BPk;|HpPjAm?*!kR72~#_%I|u3k2t@651cN>*Gupk;$6lb zZ-ys`>j&W)*iR!*(WB58!X8`-uMz%t7dYqn8qR&#Z`D58@L{2Uhrp|aeBTBa2>F-? z#|D_+Gr(2(Uxk;5{jOeqG-aa1!~c@+5Y_$7;cJEe(*y30 z{Dj)GzHbyfR>bQbhL0_@?fWi#g!z%NFMq=$iI=w1&p&rG{(y)FTn3*%B-(jiU+)9= z!X6lTo(ON+7v*$DVXE>y2xq)z&jT)l#~{zQ>HD|A>J!hOlGiPW`w^amCrpb8pFe&D{$9k-Hp35z^Os-2>qNZv^l>5iS?sna``6&O z$83Kk!Og^csta7Ldgy)Ls{GmT6j9!r;J)}Lrv0CWulbLiFT4)#5&qx~xb77Dyg%XU zoNqSqhI-?fUkZKM6>h{hegQmK_(!+E%g?m-<`MXuE|JcAI{h1Pgzz_hgIkOF z%GtMaUHBWV;N@919?%>9R?MFV!6QWfj)sQ}v-9nH;jFW(JB18RRo=yLJNBoU_|^w- zEwTUSPxuYu$pKy7xCz9&#QCjMcr-rwDyf?>6+Y*k9HHP898RJ-nIyw`RUP65fZtGycF-xH0~t8855h56_Qr zuGHgoE1W9gSI6OPan>H6cRTU0PEpQiXos*HRy&FK>a@lv?}w6uc|b z%G3MsV*DF3|N0g_F8q&+?x^PbnfT+yI{(YzTK7B7>Dpcogg<3ePk<-Pw)MFN z-YM+ic=+iwyI)-;?U+%Ks_ocpmgT8(c{(NFoI9^(J68p1x zU)oJNeFEH-{xI^}18yzqHv~S&d5Kb;{x*0;-O%rEsQS!<>x%szE8$&YKD7mIE5_3= z@Sb_q!|%(9o{ay)e*fM&|3>iF#Op55+zQ@YKgNAOvwB`Hxa5~uXNkUE2*=~EoAsaD z;axx1aOY>L{~myY&7H9PJr7S1@t61DImGX3lb=fe4cuJBSN?)G;Ln-)#6@@Vd=ane z3zrLjx(uE#?C&i2`nMeCEiHe~!SB=G3G3AD$xol^5YojCZrXv>yJZ(8h=M!z*B=e^h(N+{O43^3W76 z5%uc;&%yu5(&=;Iji=l5!z1CJS${D4e-=DfwEtqbT*Oa5g3q3A_0jk6O7>fu`Dm@X zVd3AlhgVR)kbbJ~D}fIR|Lz`m%FHPD_ls10o`pw?@%A>Hm~8v^AiM+rCs)@e>K@`L ztS6fJP78QltLn})93qw974XuQHvX6kuO=R1_TStN??OKs`B?-fvwzX(^LOAa_;Y4{ z`yJd|jQ79bTiV$DH|I>H{9-=W7fye~+UHy0H%0t^8hk+1cL}_e_=|~;y#?13=Yzk3 zYvCUmd+(cuf4M%&*+d7b`qqQzvVXIKZl8wmO4d`&e5WUTSjbB`+*MQ^yt+4lWbCGaHr-{_~Qa3=Yg^ef>w=10cA+6>?Dh2zZ9^VOf= zRG|-JW@9gey*nG8lMv~=p!+iwp0&{GlOFI`F`t?ZC(_SyZOx5$z+u>QPC%xwC z8_o~G-^9f@V>Q15kNX>c3WcJ|vjI*O`t@6Q7yi4EpZEuu|B35e;msoccmq6B)c1C{ zf$%36!|RD(n*Q4kUn<7uF?grw|N0Lye`y`*g#17JO?b4h2d&`-Vn28xoVVG&f9qEG zC-kL>@7@c~FRvaxFTEHpN4`V)qrPuFoJqXc>^J-#-o^fo>k%u}J~ba={w>b;HG#Vc zdB}ugSs(AH+jjswM~tVN;4|NeaW13*RDMsw-)-UdC3O0?;LgH+{|wg^`lsH*yf5W; zyFd66xI=qu-`c^)m=78KF&b8%*WLX2?K${hBi_g9vfuX*{LmP?-tZh;hxM<;`uawF z|E2o=ui%{rr_mk3Vnvzvg3%mq~W~Cc`Dd zz72*mDZd%tbKqi;-%@z+INSc8z%RXO>-P(+K9l)V^Ecn)%$LRZJs<8b+NUjCi}*=+ zz6`Gr<#_;JI@rc1mcl;#>1JfD{Fg1TANwBA1S8GrV9IF){PTe~*THv)|gpi|4{0BX3Q0{hx!63xDfNc#K$I z@;ycV`|bO|&VlC&dzAey;i$IJ;rGcEz^S7Aij0ciTFcCAHM~6!~UE2&-d_Z@xCwrbFgUdmhf}2cDx7yKV4IocN;u|=i^Sf{qrNd9s8%`S@lot=ZT*q zzf2ch{hSQH&VE9ZUvIcXtal8B-w@}8?|?5TxBmEp@D$-+tcG{+zNnjYeDOWF7y7{1 zt6$*l%!duveF6Q;csKq_2Y3tqyV1`%@H?MbdvP1w>Y`X@xz2wP{P_(wKKCZvKf~(B zui@udKUMZe)xZ8y>W9B?o|gzeBjmLoyl<`D?|&m)PJ5dEm;uL=p6q<_$p6Fes$JIJ zu2%Pp`QsPx8o__S{}ujsy%({sv~MF_z9cwa$WK@J4$dc<{T_L6+`(99i%vfpZp8YA z8SnSQ4=;-dkFOQ*3HDnVeexyTO{|BVfOEw8w7Sdihlwwa)cI$?b>Fr7&$`1KsDG&c z>ide}xx)Xt6OI%9;u5$6^G~BscfemPx97wDfcpu1ReL$(UE2$_-=G2fW_5eMGYC)S z{Time{oqM=+xJ!73U_0?n*Mzi?#KJ0j6bv$_KWMWEAZ!ezrrPSu#%5-c+Q12-2Oe& zSHss9{_tXce_FRk4xGgL`JPmQp z@E?DNuWf1HA6MrU{D0A2m%?+Hf0_Pm1218|Fi__|5Pm0M{n=7@4DlDE{~v^BavtCk zo&Ht0mv}$vr*Nj2Z=A6b|CI9@-|O^Oz*B@jJrFK<%*yW=xEy^H^7nba1l(BI(QM7-r0c(sT}z6TE$_HZwJRlxSI?=|F)_pc6e%j@@D1h*FZ#rnYN z6N>lpTcU6&@5gGa(@%oy1nv6R0(c7kh8d4-@Ib zD(2g?uliQ`AD6<-HpV)`bv&*+JWuSexB>1a`fnOs_^IEStnJ4Fc-;&3eID)&{{59tTjeL%WU%D>JDbUY<0FK2zJ*o5C z3aiggF8h36zz)x^4y*e97fyV@%2T`7@!!~Qc!8VV@9PV%7;o+0VEA+4U)&B)WPD$w z)87ZbJ<7gc;W@Y)>+42eAA}b$Uo-w;^c!49Ul{-AQuy+*cD~;Mer&0I|4Kf*PK=L{ za4-7TtoO`(eay#KD3 zzJDcrNlp9yfY0Ea%%_dMj9SC{P7c`fI~Tx-!hZFF7ZZ;(?L7$o^{g1@Yr0Lz!#KDl z`q}s|kHEczep?5>RLAPC&)})Tejb6R-C*0Z=31psY=2w{FX#OOPwDy;!HpR2W_|BA z_^uWDVP&trg7=8{>rr^H&`)*WMxJ?px{2Q< z!qd@*Mt^jMKj~N9`H%^QdVVf^RQOlp;LYsMF!tbnc*-c-zR$z&;NP6*mXG)4z~|!+ zoBY3le?UJOeH*zB{YHD5@!T99L;cNufh*x%Vn2QkJdXWDM|6AN0*?^$-??zvI=i0p z0{oKDZ=b-uc)x^+5Bc6<{hs|jA%BANPViC@|7->CUK|njPx`|NpId!A2EJ~ZeIMzA za9ph2Pq+qFpU!T3@SbaUjF?aU48JJiBeCy>(s$G88^JT$So@O+Zx`{j9L30+sm~qo zRQl_3_kO?cY1qelQDa#7e{0}1LjFF74>Er-`YHB3^u5?`(-r=9DE^3+&wO|v_B`aT z#`z|}>&1SfRd6ldr)>O<9dI`>UaPNXK7XfeuO{#u(cV|W_daa*j}*XD8Q*3;H3mL3 z!|n%s5?-^shWmS{O8(!5AFgT7lkSK25x+C`zV`dnFVUX=X$fEPrG0-yS2*LpvCe%| zP|1HDJc9iV=K15{U8U9^UZk!Id;c!HQrNpga9`Rp)Lu1xjXq#KQ0S+2@YCNr&a>Kn z4S;Wqw(n1v2!FwT8O*U;o=4!R!k&Bs@853i$#HnwBUT=oeu#fYyxa6|SNNG`c7A>X z93lL(+u;c!{j=_>iU}zPO|2&;X>gL9fIT8-(sG3(FXR%-elj8lmX8b z``i8lN3ZldG?QDuk#GmG{&6onT#T2O)pgO{pTg=B;ok4_eGflyqkTVIt&R8(!hh}s zfBlzzzvxJ~(~Z`Dm=1Rn>v12#)7kIQNVoq1_;8AqNA=?V0%4CE!8=9#qBC6gH2Z$^ zQux{hwten}n+bdU3cLk>exZKeHn{(aDCY^y`{BdrJ0nl$eZ+X;`Gikhe3=WoW}8Ey9) zUj}bw|LW)p{?*iXd!_)L2R z;LACWW9Hla;I*9JHU7g*@T^VteTsA7S0A4)QRrm#O3Y{j2wYW;=F;SR!ongVC-j&z0+{8jfq2_F>t_gUzfu3#eC>0*vI?O=eqJx(^mrLa$dGn=QkOa>u1y89?Z9meO{_qjK7VrkM~(@ z(D(li--A9f_Pg#j)HCMms~55#SnYqu|eJk5D|OzHd65Hpi|XEP@@z zk16k~@Gbj!zoIVhcKFvOvEkn*`W233KajEKwLd4GK)i2}etrP%ioa^wZvcFZ@onN? zli{U8UY4utV*GxgSm>u?@MFZ6<8}V=U+})7K6bq*171YDNyYP3`}c>tU1{yZcsPRj zxRIZS;hOwDVJM!(@42Y-_;1D@?1NwK8STu~{>0z#0nuOQ>|lRA{@DUuo=kY~@+kNB z6O?@PgXeuw!)c<+a}&H7{cY^|9Jn0+$M9OXPI0v3*X{iYyp{fo*ZCiY4`Xjk`I2@r zK7@RCfz@Y>o1Wj|h4%>ma+JQFrLRwcci<1_x$O5Xg4?&S@3(#j?l1h!@8K0fe@1-C z`$33LT%hm25H1k*w-eldqFs+31YgYfXF19pKa=2nw5KYyJ3in?h(~nL*O$Sy7Q{G* zb$fgWfAEBTzruHL10g@Z!XK@&`xmNzg?*;Hq4tXN)raTt`=E{8=hgHD;I6z+{Z9S7 zK5&nYcK_cPc&yluGZQWm`vaH44)I??J&%{0`cheMF#X*O zP8aRf1wJ6+Cu8C6%-5#t{AR(`zK?Z(4_wLD3b^Jj8}Hi$KSh6r=Ci!N7GBAEpLsv{ z3Ha{4);^uT3;V!+eKQ`~!p(V~j)@=lhwmmHV)S7#>=Wa29DK9b&pR7l#{LUq&z8aW zGk;9h<=+6W5$mn{;BmyOuF%*2g0rblW8L59@5X)z`MVN+Gidj37sGeea-4WQza9@a zxZl2ij^S+DiWVfeOGyFMHHE$2ZtI?jhWzh-cb zXpb)NJs;cm0p!E^_y-9({T=X3i1>tW5Akg=A5Dhu zV!YulxZ|}eT#kM=`ltv_C%$j&)uZss#D9m7Udii+aE_P{9e~eEwfn*R-=TlS^V-AD zQD0SRr5_66S>pFm?u1jBADH%>2S3UCg^m2Z1Fwj+@w7egc`OC&E2;%ePux zuVsIqatoX}+v=mE@C%~7&)&!W7y4Vp?^OGzz)R1o;iM^f#h+{q4>-gAK2SgSAn8@D zRr)eGT9kJdeCu~M-n<;1FP`@i{3h{VKK99sr`O@_!hhHe7wom?yH3D= zFrV(K@2__Ne;ohGjQ{R%2js!brw73W`DT3ZdpvMw+A}0CHGK=<9n{zO`|rcMIlnkj z=l?UjM)(Uy;GxV%O+4y?pU7XVAGd+;xhB$?p#Al0U`LGSx$xQSr!eb_&%(#Wc-R7W zAbx7*yFbFu3VEvaGy0nI3XS#nONRH|W5-iJxH)xCh1P#)co2UWe;`NqR}kJQp4SuJ9Ef&WF~C&$i{LMK-Nmj;H7J$o!fMO z^-|Y`KRXQ0JZ9~~TzFVh$GKFO_eHos?Em``-Y(9QABHyzebn+d=6Aw>=moDA{$4p; zSIj5oz*BU2ReX6dd_e4n{1i?Q^V4JSo?QF;%V!=^^8+)!>iaH(&3=$t=;O}tD}9N7 z>-rCdx3{(9^)9$3>;G5MhN^#_h1DnIFVU{>9qdmu{_f9kxhQ{Q9QDoVj&pTX=>B%_ zJoJH)|1$Vl=Bu4_{!`$G-nILy=EJ>3{PSga{80Q^?H|1d7l{7a1E0-&!q|)d!V4P3 zhTrdf))B_@w>BP}1mD8%8yJ76A3SCfzrU^XFNPoD_iGmF^38$k9*hY8zSL6qxM<%k za9`1%N8lV04~##Gy?WE0XKW4og?+ycZov5#6JHwzU-Pqlf7l#&rs$vLu=&LEkN4mW ztPh&`#36VS_7-*L_TL%56W^=JW3HWaITfCs~xHxv6e>itRj`gXr$TX?aH+ibk= zW_X@xkNe=w#D9!Eei7a&-WT=(9Krr#)BmUc7yX7jnDycm*e~pNC%Ev+NN1+5&mg!t z&r?#R{IzoUz&Cb2IRox6-sbllyj|Ge*WeGSU%YO=Z{P`!+44jlXMAy8y?;oxUlVwZ z@DIDde`4>9{mp~Bhn!@Avtp!v#X0E{5}1Pf+z&`EP_r;J=`*UHfqePGEhu zpT1t}1mkIeKP;c|aCPoi@i29NYdD_qVcMe;+(78JV)#K(zbWt>$~#Tp|2X^%@l><^ zx(YtZewZ8e^^f5Dvw8oL);9;>^?yYem3Cu-^V&LWW{7zvu@qV!e{? zbn819-n-TBjMx6?ZLp8>nfg5f?-*?T?>FGzm@gTBYY%*mc;D&iew|<{K^IiWr5bNL;x#@?%*(rAYWGejfD!cx^ z0`6XH_1EWcj_}V9!-uhNW;|V}UJSu`q8D{}TESnjf79s0f$*`%c)yE&ekoj^cu2fX z{~&y%SEO^l);}-9gISL-^0goCg*`Iza$3Y`z7p;?@u!Axk52Y{RXcd1SYN*#K9Bg8 zx?i=|Q*fLZFCW7F*-v2nm(Ss-2C+_mo&HbQeB${>bmVEi0iQ*NfB*JESbZ+#PtB=Q z-~(d4sHeVOsITY3%Y=Tt8}3DUX&!gH`f~G%TMQdsUYO9wmypo1Y)n}};fS)9#VP5* zmW3rnEz8PtOUt=dJgm4pA>aL95&!0&El1^+wk#hyqUDI;rRBMU3e~+WN{aK!S`OmB z`7M$Y0xe3DTi!Ih^oEvsBa2H4S`-u(<&G>VZ&4gf54ISQPvT)CN4FR>Y-EdJBg#u! z=9i6ZnO|C7%+vC7OG>f_4IMr#+kL)|ugl6u78UW>?Ch+*J$q+&>(Zxhb~eez1w&1m~BWs#{Apnnjg;f|F5Jpu3qJp3%6l$VPRpo5krk- zS~Ppm;DVCu^5G*?8@KP>yZr#)B{X^QuuDQMPXi4r$StK0@`evDDa;*4U2{vyY<6z{ zRFbN^bmXZM@ys5GUY{zTrHgs;LyF58DJhBJI#qr>>0hr``D~SW<!`U>)^lD%VpgFH)G5>_rN* zlCAG_l8LO)+g?;oR@g!do~T$ScXb2rS9GNG!>`h%Cvx$Sldc2rbFHNG-{{^@68)Lw=GcrW+L!INW6Zr*yqlWR?G-g?24b4_mE#)2o;Ge60b?@2OmW5JX6Np9Z8f+zoz z+`NqiPaY__c^eDfe9&A^_A}SZNXW|d(gj($UdBOIu9ptT%Jnh|vU0sNe^#!SF_4w( zrSY?Jy^MgYTu=5h*OUFs^<+PDJ=xD(FZMGl*OPyi=SjZuJjqv{C;7_rBwu-+4qRp?2+3O&hJp(pt&^dw(}p5&|0lYA9=lCMHf@+CGe z{mUw5p(pt&@+4nHp5&{@lYA9S$XzKT4_SCJ?AD)J;>MV{oV$dh~(d6KUp zPx4jdNxq6a=`T;ah1iKw>4r8D&8mE}N?GBk!qVdMG1(>jgAG+`*J@R}1x`+TQ*P<7 z;$eflCNC^49bW1+aZzq@$;eXAMX9R(Cl|T$M(Ee0%herw_i5iPyGxJ09XoaGT~#S< z!rmQ8UBw2V;$h{5gVbid%AZzRsCI=`er;H8`AB!uXyunj3@Pi>A+i5&P63TRW|=xuPVkA zrxFUr{L8?)yl002?(ov14Lz>yLe*VU$vyvCw3E`8=jN$B-2dxi^lcuVR9aXzykul~ zF$aje-^3}7{~wjz3f86JxUBma>{C|B|_(so9bBE6V zrE2m<4^PYIKt%cQ>{AcakTBciry8^s(tA(@q4XX~Op=fhwTHfv5|R^B6XoeB^+j?O z8WxG~nVg;74+Yn!@8v3Ginui;Avq~sevzua2>eT4DI%|=^q|NqkdT~`lp($d@D^2AqKLUL*_ATmo=U!?t8X0l|d!E|wNMnZBhF;#q#tG)~3tEeJsPc|1RIfiKtC?=&Oq@*OtFH+SPRr!A^ zFIldXB++R}frOM)+4M<4^+i=pKl-EwOG%ZDpOlu662K3&B~4dfRMq%yX0l{~jG%95 zF0&>zdrla|;X&Oz;V-kZ-GAEoYshIh`Fc|Ja3UVrr%E=$9-68=pXBUQCee>NWjYeL zWkPFIP*5iq-K4W2yUL4(LCGFolzpn~bh0EHnXEFqWR>5knvDF&%R|Dl8%xViRXCL< z>6BGasZQMw1%-o@5h@j{?v>Y6r68e7Uu92J)kBrq4K`_||5Hx;B{5G>wt>q+g(N2P zMbHdY(fR$<;i*vipctQtDJp$s`Ktp`I=#$4mGo(q=8r^$(x=J%11f!``4i~X>1F;w z(xYGh(YF26-n~%zbeVseN?%$2YPP7;%ly+xAD+s}_EG!qLg_PP{uwHLrTK^Jn<4Yh zO<+e_W#w0U=-m8MD;TvrmA=yaO?^`nW&Zi3536EXezgxSl)u!!i5##`O{y$^wbMWLT}< zA~dI}RJB*)zKI45U;U@&#%@aKn5ZF^E^Mzmh7ihs$n2oPaukLNisg>B4j4B}7fB5$ zY10zbhzZ*?Q9xHugmQlbR^AWn84<1O1~+J$rQ=-4nOcxR$Q;g$-&V!y{Fi z{zT-zQh5vKgMqC??9?zw6)r@gl5?Ec%FBZ&+VZ4|?oU+WF5L%Lp2O~gXdSmaDxYw9 zr00;R#2PhZE2`u+-MB|09}G~%=1CW|z(Hd}q;Lma@ysw@{7KnVsFmzud^2`Jir&KG z;)_apE4NHVlf!KjU?hjDkc8v}@D}YCNKT-#v6Y)YyiDd&VSphy0UFfig5(4O#t9Ww z%H?eevPyw~7z0TNP9P{GG6}&6RAyLIVTfDXItAs!k()q;7DsLZmDvMTnhM!StB{1) z1W@DukhXs65Uwk(%5AiDMoR`zhv;yq%DXV|7Uu& zIXsj;N#vi5oCQ(im83V~9hCBujFt>Ci>oBPsc$e@=8pgdQR9`Q57#$2;2Sn_DC>Ip zD#9zmRN~w0?EK*)#*`Kh8eC3jq*(0L3FTZN>BwPaM5D#3c_nF1ouY#4R3ZOLou}lK z@QkrSVk3TBPm}f3_9N^eRJbW*B8KITJjt`GG!Y}N>ayybhG(C={8>qxgwmQfm{b*S zsiX`i-EykZFx2x0o9NN05_`D*Pdl0%MDtWq!-C>btdCfoKsqsaaA}i+K_R`^TfQ(# zw?f6kIq6|SIx$^LBu)~4qSk z44mX8q%+~LniB)f7shh^GbfxtlN0HL^}>*+r=^*xdxaZI3x~Ru(XBu-VOOx^8CV2S zf+D^^JSu5Wl@Wqq3P3W^oY?Y=6zRHS%QI3FD{Wtuk!lm|(vnQHF4jCFh|6rPNs9WS z%BrD}!zBtPi>hJJGt$#VYZE--3!~Qm(MF{ zVgMKH-)=QC0TK#PP%c1XfbieH-D=Du31!W37LpQWC@~2~fN!cShv-(7P8I`?A&KED z`U7tuDLEVqtI&?BIfS&UbW%p}3vkS2URZvPr&KC#DlgHwDxJ&=A0R1B&Ks1K=bI|) zDEe2W6LnPfJ~>g&3zMh3%zV*+NsmzR=kx-Tc zIZIL6%XR>A#y3^BnH-xWlx>Ebr6}!XGege!#zbuXSu!~`Nhr&KoTVu3Wivz0Qc|(3 zRkfKMnG>$(a>au$v^5 z3ermjX)8GUS{rpyVv0a<9>CvkGG~ zLwbz?E? z$0iA7HIcJaCaEGbrsOO`j@C3KXBkzw2b8SB*d$IMS_nA{B+Au}G~|qLs%|qm zHUo)r#Ul+l3nWVSARRg5n=0G`N+!o92}R$fBWJ8nh@qd3obgQ+nzrMO73?Mng{DnM z&X_^V%#bs_`S;As2q2-%3^@y=$o@@7&iJN^Hlt*6Yz9(fU@;vz3#3Q~IUPCUn}5$N zT(T7DAg3c|ERo2vB4>P4MF&ta>C=)>b^vk~2*?GsbmWY0s%|rBH%TbVq2w$mS7pk51BOluV9I5(=SBS8^7V?m>o$WU^YmQr<_ z$+1a7(PkM+&MHJuGnAaARplN~GC4L$D9fSbOldD$G9_o}RRu}Ntisq#mkK9C$(hn# zHZvt>=~cN0IJItV)-vM@73yLRk(aXBl#>GDFE(MtD8?B+<~B zg-1Y!bdWQUGgh%=n;~Z`TvcIE$V`q+5(+uXK+b|m(m~Ee&Vor*xd%EkQ!)~Y%yN-4 z#9dT87dhjbD*Q7tlVg*FqEflYSujNgQFD5XjBlzK z=wv3xCJBYm<|1c7wR<8gXSv8(5XY!;BdjwEm#o4HelBtrRNBjChMe(D)omunCJAMm zA!k9Qy=-R48Q)ahW^!zjP?kfuKmS3^IO*(P+^-Qkq ziS4`Y%oi?+q9k@CQca4EW-;%034uD?N%pZc#>v4N0=2)hNN7N7;~(6@f^`sB)lgI zpCgKjC&QgCBPK@3)@i5b2)aJ4xY-<;>3A~a5cP;L#}`?Lnj{# zN{u-uF1{YyO`sNxmKX$EzI=4I_=dATl1#!C%=GWs3>OZS%;4$`TSO*B^=7-|aaKt_ z+1KEDaj|y*WHO{fs6HVb+_D_1&;GeQZ_nL&r{(H)H}S3Y?r!qk=qq^E=TFd2qqoiY z7mLB1tpz3lzj*$%X=+GLQOc4!^%5cE;XBdZO@wf=ew42G}iN8_755> zJlKq<-KHAxgWK8N{Vh--omxAl`3UT3K|1oDwXDwCTPtd?OphN+4<`In44)VEGUW`m zQbz1^6;b0pzl2I$tv2`aEq@82)HkBJv%TBQW*gO{kDH=;?Sc1R$p+f{BoB-&!`dBKn}FQ6a{ zzKD@x!KAFRaXj*rO&nyow3_+T_fl96cfvIhxGPagDN1e^Q)$@8Du70G;>mcH%A#MtYI z@h{dpmW)vL#Xikmj=qG(B1GAIu&eD7%GeEJO^nT9ldAO;2j^aACj}4Ay$1X{bjrpt zT8vgAOt672?Ua73rsdi7=_+bXJbC^G0qui*a9dqedSaJ`Q_Aw2&s^gOLD`KrNRm3@ zE9HVWe&zWwU3e3q@5>u_5e|N(?D-p{=p54=f}GPi0=5_%Ewh&e*?Hj2NjpZ`9XRm_ zfXTQ=ixIq#g=Q2*t>JeJ1ZPdZg50d7C3G3#Ztg;JF<^@J4bzg%&h3RSmR)%99DbVp zlZq`s+Yu!4=(e|Lc?co|KBk)_BhDwldKwWnzTj*ZEs|M@WX2cp#}-M6WJWv~ftiN~ zW004KR`!cN5s@!cYCHC7xUp5cZp&Wbgv^1l>pkOf;{zSqP2<7iLtPg0bovSA^TgOVoCU*Xx8MYlaKRztmrpB3^ZLollOdxyNwOPF zMs#%oZZ1ZYT1KvEzeE<}XkHEPCvSR*G@K)vw#bfdL(FKtP~rPa72KOf_}%qA~62uly~bI(xdZ8sFuw7NALT(js9T4-%I{zBnFCq2?Eeb)8AhutlP{ zL{G!`MV>ew4Cx~2U}%zDxzAocfi0D%_KFXNWDS2n><;rY%7?+D-{iUUu?>4!pHPMF-iozcyT?-hfaZE^syD{EBsK$t5aOUyt{qS$E45s`p;13 zyPXXjZ3ZThxt9S^2xpsVWgk?4TO@H~xRk}U(t;g`e06$TrH-IoV#)9p<5XM{ zQ*Z^N5XRFEM%74gpi$1CVV(ml#iuYo_szkpnV@0*CX9lYIXUL(Pk4Z2ys4p}%(#R> zyCk~d#)Wy28s?!++4J?@Iq+650YsH708b>cl`>@JeDJ&*iqUSt zkPq3GM$^1OIB@wis{lAji3hLt4VJ)zrpX}y4;(TMl9v@8I6QcEXfRtQnr6?y3HxT1 z=NTXL2#}V^nVGtTrU?b$s(4+W;d{XcLzt;}{cw_(iPO48&w$V3^|PE02&)qh-i(%+ z2lHh~i$jC?GM`l-dV^E1`OpQFTs#==CcNoz{^wvUTBglBK^_Dm zi~U4y(eI8@cAewGY@0U=ITNS=^Rin;)7xOewn-g?iVT|$9?F(No8ATlw$1y4JRc+q z^i{f8hZ!SUg!J{9zBKICb1gW7J<*!lazg4__V2uQBB(E3vy5T8_PjiC?s-`*qW*R1)dF}C;HyY)2+ zoBXxjKm2{nSyN6PwDJQhJ^Z>xffiD+(-{#a8|hddfB9dtf4uuJJ3-2D!t2}lAJ}{t zg8a|b>^5D&pet@0tUD{IYH{}U&=_oSXpn2A-X%80`YA6U_nL1xlf=8Ei!teg6&9@cCd zdkqzwFDjg0(k-AvwvA0rV4yrQQ!$`Kw~ZM;AXCN5JT#LqpwV=#O%CAY>qi+^XGHc9 z!YUEm&3Mbj%_*D&DW|9zy=yw&JZ&~FBkpU4=uQ;ZKl1ZUhkc_cMi~gFi?gN&THRFx9=SRRHAp(lR`+Ayl;`~y_BFQ&*}#W4+QJ?OA!pM#YQk5G zZ??Kx6g3duw+y@+a0jN1HV8{*?B%8|wg@&99i^`EK!(90Y)ABW0()5*yx<|M>TpDV zXDfBS4a+nkjCw?W=QIqU7Ve0|E*up(roS^EW;m7pU_Qv>-`9V~>uZADzRE{v;Bt_{ z6nkc`y&ZP1D#nNOu~$7S%X_E29dfU7b~l_9NSSj5H;}0B?Qm&0?GtD zn29yjc6n!NhPIY$uMV4i$lg9al<6g;(|S>r{y-g26mZR+LbyX& z3Z!&7Qh6FJe?fDT`IQDi7uFHKcR58DIEMQ!5Tr4mS5@%%?8&R2pq2Dp zQqnM5B!or)8XxHp6KjINjj#Na$qgZDbQytxT};D3izHYP#732@(OPos08MaO=dAMK zB!j7WgJAL9X}YaX7u`1k`(U`YF(;bY|;e*6Yyfo+a->+9NCr=IHD>2a^j9V0NTmeX$RPSq0_E$Wz3A;WuSGOWr|QIT?>b!vjMciKIu4as)ygGtzMg{(zDGKh5h1;y7kfN0QF|p^hi4 z!{Z!Fc85ngk|_5NbS%m4ALV$0-apQR$o;@jo6hz7K$4$dM~deZ-`_ult0N@R{t+P2 zV0A3x(9Dm`r>s`vBw{m=}D)`V1Sd*7l)Jp*nJ`=(^79acr!kNp6) zZGQm8e-xv>{QwT#&wgOL{{pIsB|Te+P5sbao39tR%KYKm_O0B+btG2Zw|R^Q+0yp( z<`$P{9#j@vl#&aEAKdFByk-x>cX?doG>mLJR0tjB}CvIF0$^|*(v3|sR9beVcR zXtwBw**+Bd?6v)&UJr%^@#3K?x?r^S!6=VKvD5ZPJ3e@6HpK_6?qMH!DC|g8AAkSw z%R}hnA?CMWe?RtXj^pyh@Gc>Ij2ots=Yd(DtXX&@ZzL{z4IK1yj|H(Ir+my> zPRD)^Svv;=YBiIG;|ukFkDaUgP0%N~v6!5Se6FJhF;5Emyg(|?hNqM+7lQ)2 z{&`gD%if-Q5?1#112VUXCWqSB*&nHOMMf12gcT}D=KW9ZqWpO5D{5MdZSaXky(v3t zC`&AM%~dy;(sS!p=K~eGZm|dJ@G8r*x?jygS%-)3 zl`IWkJ8k$!MmU6>N6h08DI7V(Uz*90M6`D*M^o6rQH~+My@PNk57Oq|5soC>y<;3t z)%%AzMDlxkAL0jlJ0Hah_Kq+xtRFyT_r1ybfZhjL-QJlW$HDdv@$Ddc+uMEQV0ggt z_pr{rpM4--RoB8)l66XiZPZ%wWK$V_tn=6tbv%H6fIjjm$jHss_gBA(qwNZlp=e(Pw9z|@7?<;rNw%8Bwe1jGQi&S67t(V zB<`EvKdkxH!TQMftE*) znsEjAnOxgPqcsubLH)``Kd4(kO?q8!?jAGjxP5YZe)b4|(XE6(8KSzJU7@t;VpBc7 zM6ooss2)GPlvU$wX-RPuq z@ZR=tHhVVl{CWL+wfIx2+jaxVfU_%^>gI0AiEiZ&8aSvESk`6_P%m9nQF%REEo`>& zR#rjeTx_>ePxySZL{%B??)Sx$r#h`@eR>PcY$Q>WP6M#+>3j+mQ(xot7Z>|(c);hJWw8I0B3 zo?f2vW6j&;cE+55^Uc@h#d-rQwhyDg{I-Qse&2N60^J8-#nUv8L5mxf?ioCvD>Yz9 z;Fu1f$GP8qd}3HqKv&u}vr@1JNOe=2Hk|q8?sRiLqoAZQn$z^TqY)Jy2kY^oZpg2P+LTn~809s|?-t?SdbZFMz9DpI)}_>)y~B zl!hOp(k3#43km7p%n`raZD`1{Hiiz?yjtL{BffZS^Ub5gBTY8HK`hY7O+c&TrA9)p zOiM2Gs!C1iqKuPFEAD=IAwSaMig1Y%BgxAiQ zo1QeC-+eO|Z+5y4l4VOPpWLwqVMqKJsjKb-FqStFWi2n|2Pd{=@{t!$)x8 zQ}@)r@`oQVL)4RCC?1F4aPALQiOZt;6BEnxZpsFn7a!HtAfrBC9M^fkl)dZf{>jT9 z=*D7yPhLH|<7P33%zN_FsHZHM;yC0G#5?8kVs>`Dp5yEyGQm)mX|it?@HPDQ482@I z6s_hsDEjQlo6*p|ZPkc8f$a!6fuDO3^ti#E;8q3EjH~82VqQp7j-=~MMokY+zC&Hq zOdfpl;5ZEy<9ODOjN(`+wIo@d=r4@|+{O{tzd8@xy!KbdFpS4p@WDj7ois$JVq0TA zE(JSkfCDt(q(%JgzU8Fw1Siv`CQEw-TKMGqq>)dyfxKas>QPgjv1s*ZB$_@tf;3_3 zU?n{!#0HM|4VLz>!JgnG>@kD5vY_Po1Qo`P>D8{IqfneT|B-PT3PlC09~q^gP#gjN zE2Dryae(r#j39yt6|w%p7)GJEb?4!O;P$Zx^%9!Honsw&w=BB1 zvRDuFe&o?eQF|X63s-u$iAmZ)D>ng@Voz+DzhQs+x-VY$NqA=#;9S(sv=BubzI` z?#@8_KwjBGo8JfQ*Q1M@JKqR<4CqwN2rYN?`N}{tAOfG3gyiJXI5&^1U8QHpGmiY2 z#q`CjbbvpOU6lC=p_sZ!fX|5cIwyT)?pOFiuvqtEJpQV`V}BH5c6UqjBZ80M)=^)r zpq;#g?-Nj?&x1x3YquDGYn$Y^kFn@oaw9+fIzRvJ>w!IvzwEz4v^x9rR4J@`e6_f~ z%@37SZlox-%}NIm4iq!hXCD^-Zl266M(!($2?z}gpQ5-&^&xb@5fk{E`J6iq021xC zU{2s!k4cff?#HKJv(J`)DR8eA%gZZ6D}Ab4h~K(eduYDXzPagco3-2qCO2Q^j`eHa zdzs&!uXl9%O?9qcx1AxaP<5Nbsc!;E;mZYoph<)$=~wa44PGW(7`)9mF?d~Yqj?GA zRhQd5FDN~HZHA;_wei}lSCob2ro*w+7obCBm7)xhS`0@}bx0|2*nn(w_~LwVdnX}; zvXO(7cNdCC8!x?UY_K*uYj&+`E$>ByZYwv< z$ipg-g2J84$UZ2ClhKy8r*~lSX9%eb zJJO#iw?hrzx~e&RDc}$qK`omx1yOD$piQ<*dp6m|$5O1BY$ii#>~90FKi#m?vsa?w zdu2{{o5iBxPJCp9AwQEgB7kn+H~g!8-Ey$@eaFMv1`QWWudkMi&FN--WpSG{JIZHi zIKNt6XC{z(AN5`k5bit~TZ6r>52VkPpH+KopgJ#H%PH-2K$${||WHmW&#`>nz3pa&={N7B3#JhaG%O}-4da$`CL1Q zG(pZHVnp-tAaZl^3n+100dRC)=2mo$J8WkV<^J^1#@LV0 zJ<@~O{1$AXTa31zaXAw$1UH<9k|SBhrj-dtNHW|7p#=#x7#mS#NeDqCceYXBxVVx2 ziY{%-`T9Dgq6|mOaF7Kf){f6jtRXvhY`gT!k}Gq2dUs{KHccvCrB9_!EF9Urxtq^6 zB5=AlX3|YJ==zzD*q9e)O}6S9v&^$?0SAajFQ?wm7QiHrRSp{U^Hyqo{Pi~3iTDHF z*PC0V0hdM9!{^I$i~HA&pX(RoAz+d)M;=|y=4W6#>kA5rNK>m{p_>KT(^%|CCb3>! z-*4|%E*Ll`_O98ajK}|EIp|F*;pY#FniqXNF-1QhUrB596BS-Rw=$x7{nZf$;IUnV{^=H-I`opxh{wVFOKgxUS&&uBNNp@~I zn#*%~n`g89NL*X_L3pG?d8NUIk`PpKZ)Q0&xyX$u>Ga)!T)<7D)vP!gxaghNCwkbBv$Y1SBM z)tpd2V9*0G31lUO)>$oD;|)WAd_6TqqxwXVnen)wxKQE>$zz8I?uVn=&DK2kKt(j!cWJireH`LH>At zkA3xgpy?*hRXjfC!o%c4nF{`?o?A!3$A2O-AT^OcXQ-C-gl19@r>AHn@0KB0}M*p_ddl=Y)V?vn^A z`0ig=lR5DG0bNbeQ&(GLs2w$B?^-g{9@H&os6C{kWdm4Ng7xG-6lm4T{ow#rD{<6} zF+00=iQm3K9P5nNdx-(wzTED6dA;{-NV|5-B`y~je(Yl6MNQV~tw?4=9v^|&k}98H zXfIJMB>%mifwnkbVlVF2n|qCRHDD2P5ch08D`MYKMk{7!H9C2A<;1b};y~ofh=bV+ z%bMpa#xTq<=w2d40QPD1DH8#a*=>Dn@e(X;yU@eo(?ezd>pM?Kw7&U$^)2x$xpSv5 zegTnmYUZYsus5N1)T`=-Gf-%NK$v+o2OV?jt#uZYkcV=*(Y1T^9=^`=9EP&_31BDL zpuso4AK`3hP_u<8SiV0-=|#tKXXbQ+QH^2SRqLwa0-HBWKihjW5);YOpp&4nF`$%3d>)u2i!l@-a>T5 zAGK#piFrJSEr=NX-PLaO$7h~;AwL7Fhf@oFH2aN<{La?b{+Dtt^phP^rSRz^{>?%3 zZ!eX{bAIsd=zWNTQ?gcQgBOM1V4JHMclqRkITwLx@^5NQzw(K=qgwZZwlaMIJnqE1#DLQveI6k4Z|T(A zVLp6(`|l54`L6~;bwa;eB9K>Zl73#{f(b085_}ru_TRqBdi4G{X*q1k%nY5b0hXttSo5#e#=TlNpJJNR{9Xb)` zi|cEywnGt?ftY>z`1ThCWU}1AU~r^uj(o7~-TSF!5g!UB2shHaKx_rv4?AGO$v;27 zc={5hJFy)!!T@e*r}hl?Oir5NQ!>!|5gP1P++b|LFaPNqPM5QU97>{Kk07Fs14jm! z1;YDalEiXN$(cRv)Nr*S4Tra9{*^s_WXDk|+v=0aiFO6|2t^)j$0H z^XIp}ju7I*M@;x+^afm9;UHmdctYS0kyOSp*T6TG>z!bNyz21pzZ;?nDgev$xb)22 zp@z0XMTS3o^hv+zGQ-&??fS&69VNf5a6!jragN)Bet-Mv!*Bnky{A!oxq?`fG(RSM zPVFJM?+XJ7L22s}{+|E5p`lACeObj<6}Lepb`{h%Es68Cj=G03;u-s%LQo}G)hGCra%JB!+yUZ{8?(#uyA+tzMQ#zCWh;kgNe`B~D52g6;c1kKf| zg>(-$sPRYrCr}B~srev}P19u5Km={=0Vm#GEiV88=4(RSUSMAHj0rlg(7td(6E0ZN z;sHi2B#GI={kpP5eUG0jO`w4c@bx*x>_8iL>%%gjU!#B`5KZ(En+akZr@vZMM?!ZR zjpR>S@GUNhRj(0ujmCpr{I00aSKt)XfODdap+c*{Em1iLz^^BUIXMOB8jw7%iSeUd z5FPVH%`j2Of)xg+CbU$=ieW+&b`TBpSWa1M=fe`ph6GfPKA)}E*9)XPh#CY#*d|RY zWGgXAq03)!rC>!*ST4?8nEJBXA=kI1L2PHfpIgUu+*I!pK2h|8miB0RiQy0OYu|;^ z9>`phtl<$U|0)bG+9^x>&tl4!u#q`w~lEH;K8-NtX!cd$x z5$0gi6$gTSSmRXAJp$;6h~;x6`rOX^{|SdB^u&vGsMZC>z44c9KfCz(-TPnP{`Xrq zm5ND;BT!o@e@X>Z)+LiRD@YHf@Z7$bK?+LXDvz>!_MW;B!DcG?%S8$@Y z+27j*3mU)%xyBE}B=n$ZvR-9zG{%Rr{;%T7ZIx~pIv+lMyaqoTNWl*u!2?ZCH0H1W zB>XV!Z>Z7qm+IE@$uBr#_N)mTUGuhp1T8hvgV8!D88FekSL1J1ljSE=3v{&xNlkZoBx=0B!JWDa8nT<#6T zwRj%|+x)y15^<^gbCJ%4nuSYKqOCUZ*i z+h&ENfZ9g9gL#*fb7NQ5abIk;mR@!lHLt(W9msx>XYdrcUqoS5XDGkbr3P!q585!S zA^=uhD^%d1JP&#M2gJ#rkc3o#ui+BDIW^_aNMe4*^rTaWGZCaNWkr>JK7ym2?BdZa zS5F=GZ*`2&5KKa;Qq>f}iA8Yd>u-xQ-vxp~*hco*iJnW-+suR+H5=n4rrRJV!j5>7 zUAA-#kH^kupOhi*YeNlGXW32JOa<^bf>@Ny?13^0oEXT}V&QSM~N zl5wSJ4tKxS2?vcOTPvf68!8yY@nK?p#1|yjK8_{$qV|W35`(S19p2qHi3W?p1kw5L zMWXaG>@ar>Lft8Blz*u(D)Gn@#3RZ=%|>SmL5Si%UufCA9ga!Y{u6;!LQ~2wNqy=> zm76Ed$zV5L&SQcJlEP2RG<^vUEE?_Ni#%~(q_=3tAnnb5{Xe)j>7B(NDu5axisBDM z2Jt8`D;L3LeeDo&Ug8#LC%*(1u{@1VuXh_9c{2^k4^huR<(J==w`MXY@HN~~rih8T z&8G2qOC>iGntm^Pe{*_&#!8J+5AW;p6du*p<-d?mHd>h&3(sR_n!af;33WmQRp*b? zQ`T#@eY*2N7CmJtABant41&Z*&4kzs88NMorxpI7-_p-A7!j*)D00n$O3<~$p3(Oj zq!dZ-%504K^z^28gc_n-n7+MVnMkfRnY53T>%{)*&i15S%TJ5iSDLPBn?)LhHboAt zc-RgDJUn?iTVKqoEP$FdFK(bi)H8JPbFl*tEaB+*p!fzFrbbw5C@qw=9Au{H5AxR! z8S$ZFVC4$6@inBPxf`6@v5}i=h<5DH|h8 zeBkB|=WAf=8gBp(K;aj0ZSr5f2^U)hSy9~w8w@Z0H&^MC?ga=DIpJQohi`kZYB*Jb zEgyC&z(O11#g{Im9h^nMs#zV%!9w|NHd{|{Iy(<=6$1j`l_JW1x}uf(Dj_4-0pTnd zh$XUoN}+dp8u(-c51lTYUwOlvc-1K=(h$4jnl@nEZFw**W75>SyuNA61$?##Tb^Hm%Q`XyBkg4_w;jlX4~l;s zp#x8!7%c3=$6uF-$=MFk|H@$TEs$KONwg*9wQtk6J@h}i#iG9S>(je`{{73l-+q1D z`xloO<<131$}Kp(Ti+lt3>H?qMT&*s_RCAajH;d1=`Gwg*oV)y+TOFTQ~Mj4M-thW z4RZgBeY9lTB&Jwx6V902OL!Z8$)z704sQdnOU;G9j~G$eVso}7+O?nVGeO|Yd0nf^ zwsm;|8q|PQg`P1*{z!_`o%Cd#nut*!o~|4uhpOwLeoMtAdAnZ}9L>pbV9Y{#L*wdwb1oh-ue8zZCxslm?vN%pqYwX$B7N8uImsn0?a}FWIf#xXQ{fbO zT~;bfm{Lm=dcrJ`#eSDSV>X&1G!1$L@avZtU_D>*WCjz4Txj~9hU032D*#O(lxu5W zLJ0hid1gAN(~(TIR%86Oujz>ZQPugNTh(&W&JQV!iBiWUU`bP_5K!-?g@c-lDR*E-Uk7=RQK0}^ifR|)_O(1*SwfIOrElp0E2XkZ__~4$ zP2RN~g#@+e`I+!>C=76$I;PO4fZ~kj{I?+k@kGYm8VaRH=hryXkOhvg5Z4mavVPe! zfG^Kr=+%KPWxJRu*E_NE$Yl6-yr~A|xxu6gIEe1S1ugK1EzhJb`D|7{c_2Xz<1ItQ zm5&$+J;EQt&HU9qHDm<0SNB^~f6FFFafwe`JV;P2?nK8avyKDf#qZZ zpm9ePMViET;>SiN8LLA3w|Dwa_E~fa!$Kq_x>-Sf92O!#xb`%Qu7+ErJn+*O`%Z zjq^LwV!-mm3VQ$O;^KO@y~74#q5!dEiP$%`m5jBACQH@VzF2xw(|4l`?HD7r3z{rILk@ z?UJPEWH=t$zO)=G{YYpH<{0g^djHOOn4$zR?F_R5sN}#_nuCbgUh;w&IIf;v|9N_k zDw2MI)L0mHZb2uQmP4j#%Ce17U<2R-i()n-_R;oCoOyHWqys$?@WuNC!VxZJ~f5OZK&d9Ui!$>Ic#=-$W ztBWJ-?ig=7h9~P>0gJ<2iBm_H*Lnt#$w9xQ?$WSvhqj^>^i z+j?4(xBLBv-(xhN#b75XT}ryRYB;@(M|w7)6WK+Lh5&~f5-;Jh6eU^qZ4a1uZUZPp zvPJR$9Po_urrmDk&=g1OcCLKbE}ej>KBiP*8`8YehlHJ(S~2dZ8hCPUDt0&U`11bU zf4%+v)6c)n-o5|)_MdMNmiHuP$F2zx*ioWT+b9|!n^y%R7`YL5QKyAC$F6e(Nf{bp zhv;gs%q)%Mjx0+sb}K$ZQWUbkakh}xs|Z9Bkx}e#?wxx%o9^e^kp~4e#16E+u zxz$vT^zEwpy7O?~P_OtHNk;M|$W)-tU{!=~KC(W>;!uPKBQUjXpA=LfTtb8`Vo3rS zg1&>HBd#@&Izx-_(e?WD{J(CO|0zLp1)qB8%%v+AwD1W=9DMNG*6)nySr+Wca(>Y> zF6@xB$NEOzN-qTy2BrAt@R#%E)gP30UX~vUE+INZtO-vM7cMK z5g2zu$pOU)0fg@}Tw)+hnI>|C66y8KGZAW(G#8kujJ$iHTzZH6bVmoG+LO_q&B1XF zKbJE=G6`C{ua!bgDMT|6lHOQ(H+*j;ed5KV8ziP=3DigyNs*IqaT1;G;9?O@eLS2T z^dZy2g7;PjQCi1|yFG_&P0s63#FnFQqJl=2Mv~Tgvp&kr6h(a0LNiCGl|KUOJE|i`5GUX2-axuV}2u*W1M+5 z#4n#6>`*X8F$%Q7U{53o2hMwfW-y8v=lZAFV7Sr`SDz<~6?pAG807M+Bs(s7zuT`{!tYH1Z`5Um_2n z@yLd=H~5@X1BLAdhRj-bUhpS$ zZVy(N2*di#NDy}*prsqz&VWo8DWlwZB}$TLvM?%1)+!?Y(#fgl&~`TI>v{zh&Xw5* za>jl$WQIYPwu!FA3L5c{w}nGPElm2arHN}i$|07Rz3Q7x2_HiXiA!R683G(!&^O{z zBC8hqQ~Mv=5oin|h|rT9A)-5{S6YZ2FbZ1@Utv?L&7*L!=vS{M7GEZB3K|#Y?!f`u z0B3+iwOlf=I38=pKfvW2+bpBzgVuOzk}e;pY&5B>jt)id9&#e9I5yta_?ns3<&c+A z!v$&vh*MKAFg7K*N8p=vDsZL%d1jDIEcXj)Hh7HGFt;{Th_-~u%tf%BEiAmbg_x9- z7&=1~57aZ{{L=XYKB2muzaY_P%2!yhc`7JYad*XDIT|-TyI^kav!LM}1%wjqX%Pvn z&Sk2WxFPM3ATY;Hwijdm_qVX<3-8KGBaf)G8`4BFD$_o=^_{zOBGQqE4W=^kkeYwg z71YRsQZntWgs_y_iGp%0eZf_~3hq*{&FD%kHq9cL`p(`1))QQIY}=)bydZ+inIuX| zl<}fxEw1u!b9G95%}Aj3T8xR5Kryah`6`9v_N!Mrs0Jdc$bNVvh1klO1dXX9qhL%Z z1ih|CZ6xKKawuU6V}MzRwEtL{yR(Z6NfJGn6j>Sn`O7&H=Ysj-4ps89?k^pT1&C&J z_AJ=LY_@~G#tKo=N{-(k!LvJib5QEB0m`=V{{fz)#HI5mE#jLV3!%hqgwGINJ(8HIeD>3^0^XJi;6;?SbtEipif&7d#_zB6I z)db0XFgZ0kpc-^pi4|KcH*!| znGjDXo=NZ~SEliU$0bQo7- zeUs8G#1$Z$9rjUiUH_vWO|}q2GEvryZs~0t$U`I*DMIAm!IIXQ1yc=E$h8sC`?FoU z@A$&El0fLh?XpNT438p0m_!9c_}1hia`DUv%hM@w*G*xUT8fD0m?VpROUkk&tyu<# z^Ii8v>yC&AFQwMf^D=3}Hn@|xyn4pRQ_M^?rHVyhs6k}<4sf}9iMnL+rrBjI$ytM2 zmzCOQZRDSb@f6l5juxu_EbXR#98MG37g5n zD7sCF$q&S2sd9k&AxW2%YK^QxJD$!k+r(;_**ry(+68w>^A;cmZ}zNs$piY@7n3W~ zTUq+Z0Hq7hcj=Aqv8U2o2uDSE1a6?A=6b!ZVhx>Dc85qHd8ur@JP!*-7M0mQqd#OA zNvLSGV~vY}rGKMXu`j#EtP@n=Jko54&W7?OI@4;|zKb=wr5QvCMBLAfMX4&eJl&bX z(3kX>6F4xgHbKGh4eCL;rp~FU($^9>b)VTLrs62uSY1=$2Nc?}=v<*P0+b8Jk(eLW-y@VlUj`COm6)Cr`4My2ih=4v>**RPe6L;sWc)|p{0IO77e&c|r? zG{^-jwj3cjGuz^yzy18_v&!jr?>~M1^zQ$@ttOc);4mvI z9%ihZ$2h4rC2r!&bUk6B8hi*Y>>81Y&1QDJ{DAI-D;j1b`rI#6%`q|@4qVNY4tMyn zH0PKDBJ!2>)DDD=deiL$ilnXFj~v7W)&y(f8iCnl`jJ=6S4xlQ z?q!lCNP?qgB^h8pU$`o|dbflxJZ{ z$>~z80w-ki78kF0TiNR~>md+XqfYNg6%HS$@nAzBO$g_a2Af6fjYQzi8kVOVINd7}I*un6X**ls?##C#$ZqPke3{j$WIyjp7e64L_mwJ4YHF+6{vcFS>RqNC0z zsNIuOSiot-At;Gc#Sh&#*UgB6I6^RAvW{lA5q>nbyAUBwv;?Zm`V^nJMAR#zuXa~h z97r@znDN^`bXuW4iuHO)n9v-JqJjh*=N*RSgk!Kn34O>e4U^0$Hg!u~KhbFyVeVr) zj>R1&?Z+*(#vdm-9HfUQ9g#na56-}R9{Ix~K8YJe-1ma;33xJtC@UN^!8Xd4s1P{T zHoq?#iS%|CByTlw=AHz8^`-PYGBTXwnNgU$V@Cr8I#^=xoTXJwU^}9@&?U4xm{OOzxiyuJl=t#G_m{NSJr9Qg3T#>}M|mp~o;|y=oImNyL6& zHZr3D#t$tc%mJiNllfj^be>xoP|!oJ+QZqso8qayuTH=8TKlX@CZFjc76RbzLSGSj ze#E`45JUiKE%hH`E-5Z<^XDxSmcHH!!nz*V^eJbarJ544cHn`2>k+L>wu>9DL=^-gttQ2Wf11Y==u>JmB?V`{ zb-9n3V2hapP*SsGSAz^vm?A2J9$f!OoHDI9WT}!#l2kbe1d-L!S+10t^i7F-JG~So zTzym)s7o74N)Wl)My~+Kl1)~JBahv3;y;(TSe084xo?H#Zk9Jnphs_8$^afP(tcCx zofD1Q_R&@ml;70p(|H*NiX7E`qSQ5kDSGhWUiKZ@FO47-sYQ&rVvaZs!uTUXPIjm) zHgU(2m~InRRqeB?s34nQ;?h&(fFx%RH7c$jXFJAu!aT&(sCqPtXI4a|fW~O6H@&!y zBSDCqdi8`sMX9T(>UQ%YARO$|*jQN_*XLKf03eGyAh<;SvqVIA9|8KRHi8anqG--b zS}V=oEMvK_QV>iY{J>I}ge2fGYq$eilr_;e9nUFl!N#X0E6DbVCxMz{*4Lxs21!WN zlqlKKN~>X%Xi?4P`dv;6YMT}ylN^c8o~oO9?vG53h(@wNJ>|Nx8%jQW==zxn@V60@ zJw9WlhX`SWkiZWYr><={eQ=F>jc_aX<&ESR01v2T2&?!ysMkSYP1)xIyP(+3Ig|{q zhR72X!LCiuM(>@j+VAdHdYuz>mYp8pmr#{E`jbv+ zCQP>o2d!{ZKy^$+xrcKE3yIe(O_X#fklq0$qt7BOZ|n^T^wtUX<{=@ z3lvF;kpw&ae5X9rNQT)~IbF5mMCRl>;RN2rZS6(HlMIzGxSW2~xdf3*^x3bKjHi~J zqO@&3N-9blkNl(!tXE+-Zp8)9SH^G$lIHYms~oBFQpuj3&abq{xQ-3>R?G?!D*Dr5$m7=V%ALHvwqXT7KvtVrDhM? z?iL>MsAOn|e8~n zYHWeBHI5W|Lsqq)`Z@d`x$8pSai z*HiZtEMdR_7d=WXtqBYQPcPMJ8az^-pg^wFK10`%i^Ld=wi`3?O_WyDRx%lL!cZBK z?1b5B=~p;E01xPrDD`;?Yis=D6G>54AF<79&-BVzt}EEC)4|__6ATqhc*(KL6-zl3 z^$r|RQAgQ|kAP$(fH!O^Bkf8q$OWp+mQWe7bGkYGR=)ruGb5LU&8Bdx3JVuoHip0t zM=kf_NWOwEP8*6RW5)BClZZ*B8f%0#o8`5UlV@cLhm>*Tim{ujro}+0)EU;kFFi|f zN!IhsPkF&m{mUS2&k~2l1S>$Z+q~%FCZeLJFg3 z3ra5r$j2AHNS?_{--;TDJo+tb5*$kx=*B7LkT;^VTmGyl&#ElbXP%^AoYY{knVa>> zVOksEpK3ZN4#x1;K?UJbIwb|71vo9ymL|e1aMGr&28sUA@(1ls+H0jJ2+2%-Di4~pCLAk;Pc0AEn;FHh` zoIGz>-^R}4=ttBRHcA$=%=0_)3G1wM^)N)YT%fSZ<5zktNe4bPiD0%YBdcq)lW`+h z%~QGt8PAFAW}(VIP>1?GORld0Pig48xD0s+!AQz2W&4yRy0*a8s3_B#nm1ZuWSHNW zZ73)%wzl8`B_-ZIo#eIe{QiwfRqX|?&JydiXdRsj<;2y_B&d>{G5{m#9Y!Rs`7ytb zB;1JmvRw41{n#``hT$2A(6CpbVDdxfT|t76BcUA)~4_ zNZO(@dQL!~?-34qBjgMQrv+$C09Jb|W+1V`CpoDowsautkbGDsKsm)ZLn|pgO1Dy@ zQCFF5XzW#!hVh6g>d&%bBp(vdjsL(U6uO~5^QotJdZUUMYEUI6XhAA6s5yTGop&e| ziObR9eL)C}`I+L>LHaVPZ$rK}_+2c?E1Z!GnCW+*Zf4Fb8sT_@DfKkG;PsBOqMOo> zl{Q*W)b`(-J7bISOGVDC!K(iinTA4(w(4^Jv3vM{0cm0sGtPR`Z~MZt_aLXEw-YE}-O55C31k)jtaWXH)&(mmC1wWb|3UUae4Tb{4+ z#St3e;#!Lrx3kqrYecMzY63TRxYp?3JFv)xff$mh!Dmrp!!SR|+-!F8mi%{rTE@aI zshT!sT8C8pZk&W!@)LZ>?)7uFM@dPE?ND}<7E#g~gPEGd;^|32_8~0H~8hPyn!3oc#@$gx z(nJAnT8}2c-txNSh-U>74GJB6c>l}KpJNLPso|Eb?$C`f{9(}|KhfLE@-HU`g8x0| zEIVc1Nd1R)nw&tRV6+dBAXG^!C4cqrZ2bz9a%>9P>g?p7AD_Q^3TGO4K5Ihu@PdcO zGcpp}B6&=pK)n>)Hn)a0C=odNkl678*|PI&tEAezqi`0c5DK@dT2RmB0fOXDq_&Tb%KSPD zWHoxL7QJE>qV0OO@k@eBL?4F5!c#_F^+fhsSCXn`Ml7u7yc)Ev4N#)4P z09B=W#R~)C15Kft9SOg5c=;BK88$eQESeSlk}w2SM;b4eM}-AevCUaN_M2h)k*Hvn zGt*AVl-4+_X@D=zT;)sl!PrhSJu2&&2-Xh2l!CP;ifbR3hPr7yeu{4Umy=KZl#j)n zdez>8=%NG6&uA>JSJ(I3`_8-A7=NgFMX2#phCrFC2#+g%qR*OP4 z0Y}BrG!I3J;4`5YCATQJu3;EmNw+wkcJ3((C5>)Cm^1@54oC}#zN9-OUXG~*jFkFZ zZ@eW3&ikL=|B9JF)Q~T*A_0YG)(*yFi+v!MAQ~Y~GBe$^d~{>5EP@CS5N07dH|El% zyP?|K#7b3d?S1fEs6t;7Mg||&t-{_Rv)Q|3IVMtRU!(M+>-#BK%+~tySvQ>P8G+Cu0OfpX2Bwn<2}-~MTUN6sFlqj%-)kOTQx`} zOM3#7lBH#FbY(fg088bdQDZcXo8C(2Rc zGGlv#e2G$u;xC?8jl7D}OIDELlH5B?4)>lZGfK*_p;%87G6p)KT!QgZKcGZ^s@%gO z4<@!+O3d`Y2bEr(-tv-k8Q+E+IQFs2*gKtsd!(^jP7>yimiM*rT3M~LFufBSL|O_j zs~;mL%Qsm#B<xNI05S-U^w`3g0+@5hzgjWJ_M=p< zZY@PD*idG&Y+$lt0%MDRd9e9L*p?3~Ur!uCj{gZua7+_#jaNjmgn~o|$^BPYDbSLa zxY-#{-7l_L0cx|ZID2@L$h_PO=cwjl$Zq;j1n@?aqO#5ujq__2-uOuh(-qqfLbDRN z6(t{~bJ>-vb9V=tN}}p}V6abI(%z={OQVA&*zV^srQ$~;3N&dWbc~t}x|ShWBvq`Y zxt=lOHhvfWO=d>x!Ye!j6LU(WeF$aYCiqNZy7H5X@JU=e-M$60mvZVleD(>@74Cuf zYyge0HRjLkJg6d2@vSye zP($XW%Q3K61)k!EOSTb~T5e&gHRXDm zlesGdP_Hff#4Vnq#eND0_^A80q-GufnRoNa(BT{p^H_Z;-RR}j3X>u{d@s!$cb!SyBgt9VlcBVRLl73AKTbmQTAH&9fPB zvvta73Qbtbh|~AYjFLBXMoGQJcERXKI`dsgKt-UTY3qGs*fLFX6^JN&OZ0%~2-ID!F-A_LBzqMIri zK5)k2=SVtqv8z4wqZ=9EBGa;6cF>MDi*bT!Mf<=9ULrB~|>F#aCo>*eOcg2WHMLdEf&~y zLJ%X2@Vb}|O|ZV!nCoq3Y`@n1a^S)BqaCiAfpv(>fktb?c{y_wWI;!I6eWAmMM_^I z33H|H&8%4nnFQ0yTC$!G8gQl|7Yy}3m9=cK0D{k5-$mu~lTV|iVm;m=^Qy(`a5KsD zO*HF2x|^fXBqFP90W))HJFDdf{bb^bPgxYwXM{hExou6dJEOrc{kk$G-8^oa6^~RL zFR`pU_@!ZOOP|F2h4ZQlOt-oPGox+Dm=9m0VTtAXl;O%ra>7jb<2BBFi~rFP-ffHK z-Xfxa`+94=vy5(2|<7Gf$B zUpO1?W%N5M2~{;UXJ@>743_{N3s(Rh)gN^NP8522R<2?Z)CJtSOr;BhyWphYJ!Qt% z#b$|JM^VF#(Y|r~bcz8HIM*2Vi?WIuI)w!&&ilZ!43oJecY=#VqsHV)@r}-`Zm$q% znDQhNAp8^vuZ?O?#z+mUj2b z`Gn-I4phYmC1-~vz69>IGj;_7K#p04V5s^2bZE!S$7W&@3;&wVGLN^X#}6Wy%+Hlh z-?_v@iYs#B@hgJ@D7V7D3u8XFqY=M`AJa_+%ckP*x8%!`{| zvho@+!UhBASq?v3p@2Pzt@U;tr#=3|pe9P%v+aLdx;0*RP(Cf8EaEIK~YePtIJOsnM&K*tOd#GkM2=qT0cxLfR>N zz%BjfEd=G5$Y241%)$Vg{qwgEfB*Tn*@u7pO{kOL>-U>QVjNHWEg!9+g zhkJCeK*=qUc%1A*qa&p}yN1`9VNsQ}lj|0mQU@KOoZ{ly#OAFYIa!#XDl1Uq$nBrT z`WyP7^HF(F^FoMIBze#aK!J?mD2DVvX0p0Fz0FFe2fKK*mT4;6D~rgt=}pRs%K)LoewHl63;HH}gXiv-027^=gU7*aBhz zDeC5EUf@n{hXPp(%Y6}7B9MYd>Toa%Hr`w=Gkrf|<4wksr!5HWD+|$j>UNuFMJ|wF zU^Mvb7_7?S(8FL|E|+jWuXA}PDLI8_MFmZqqMn2wHwjB)u)tJI9^I?55?Q|`DyRf*ypw^$GrYxv$9}E?M;)6Go zXoQ4dU*UVpE$;3nSK!rOoyi?^mgopoCRl8s@iNzBC(go|#B)rzjOQ$Rg)xWGR>=~u zOWHfDfG4kt6H5uIDaTo&BaJlG3N*uGa24a?+96ZyFfhD`vISSb9$+U9``v(65Q0Wl zyOMvwLKnFTJ+X}8swV>F>xmQl#aRfHbkRjtbCC2wgO3OrJ@Kd{#}WnzzhgecxccCm zfFuRzAkN4tG1+@4vhEHNr)-s{&O;;hR;p|*gms~XibIMNf<&nm>udttdChFzq^%g= z%ATKm_&^0PRa!ma;sVEA(B;~rp{~pO!^OBkD#{Y+0m+LP+_d&elrz@{H5Y(zxwgZ8 z24r5b3pE9KUZFxHxhCo^BLB$ZZ1WTxbbh9wEs!Fpmg;sF%R}(OYLgl;la@ns!(s^a zPHXvT943MJzd+_hg}4&bBaW|EFuJTGXD`U5O-p!ivtCCv3&V5jmGrR-SdwTG&8v`O zMokXSkw{40J>tSSMbEr(FFeo~q6+Y)GL!CV>>%m>(;Am6ZJ`m&zG7PpNUQ`7n9Wcz zb?(fE6Hl%v`=TeMvyZG)KIv^5+C2CUFDa#OR}rsTO8>8Ijir|Ud$;5s z2`N|mDGtQlybe|mC{N+Q%}WQiRprZoR{*Q?Vn4;IQ3gXs!5FjV9MPAF4|(1 zsqC=6>&UIR&(w%hpZ=d%ILwr*(;I3k1J;8p@Sb;%!)pHESA~y6j4Rti?u*OEy>Jru zKWl=;_?I0U0Jee!0D5|jGMKQFIw{*zaLVYF(M`5+4oU(uQJ29OC*W8k8}W;NZsCM7 zpos?gN7!n(H-be{;XJP{F{(t9s%(u;IMOxDxS_kje!51kn8&rf`#2Kv5lBJdEh0wE z%$hXQD8|v@R11qi&Ss-)8P$nf18|#AxHe0e*Ozepz+7ojT@0$Q5uF*L9Ghq6!NuZb@HnFkWOcD@PDeI=-SH zFVCi9hqscIAxsoR;OC;&Yt-yj#wS&}P>AU6UpLjE=Jrb$QjB6K_~lGpVamaF25ElP z@pnw9QQ|a>K_HA%Wr+K**q9KG8og#;x66V2vlJ3mCdh;)NjH>s&;w8gNiIB3@Y2Le zO0_A1)*wqIB=#V!`{1*4!p^z91sMUc&zD0GvK)G!S1%Gg&iJ()$%|&*ZCEZ^-iCeg z`E+ynRYj1XLBP>bA-VN#g`K z0H^oGWds>>i7p?gL2irYszNcC_4)EED13?w*ZhHIU*;Z+1XKY9_21rzN<1}W+e!8y zt7npN2?S6m?qT{kV^I_lXA`B|y_-Z0K+N^#MWB+gT+Et5P_0qM#P*9kgaOt0K7+Bz z3bT)2ST646^giEl;o<21lFda zwhR+p);d3fFJOJa;|T~ebW+C7ukI6dp6r^uO&2wDP3+12j#2D=W3dGwK9JHuxv+CpWOuidrezb3F}2i;d*z8as)($r ziOuDii|29SUX?RGPpc?uY{G!uJ!MyXt~COeGmhOc&aQ$=mg@(L0x%t z>80YR`6pcv^hAJsO|SPzl2&rpcwkTZam`fQlm{aZW9N_n8F0u1IA%k-Yxs;)5($0; z3c-Z9nK|)^*1{16Rs^iMp8VLZh(%2yal#S0={HmM)f3Ym&Hm@t+3yyH`~}jC_Zs>% z_gHY>D&yDKivyt!juy%y_$;*upUQD(Nx2qp4plhy?c#-t;d749rQ6TPkX$hW>Qj zL_Mu8+^o?xNr7ViTJ~fzN=V)Ku*Q&?l4_Em_So5}VGZh}^0@(W$jI$_b$WKafY*)A z5SfPTRL*E9hNb;-w}YdhhGUEw)N{y(6cMYaUt%kg)8C7aySSteo^#_}(QsRBS+=X- zZK!y|j4d~^58}<}9wosL_&^bLU2pDvu~`i8K+obDrI$q9TC^mffge8e+B{PD_UlV3 zrV>w1`BXr2DZCnHAYt0^fB_`63L7W&92Y4m(YyirER+G!eT5@~o2tYBI zQqv;6Kf*iwtZYSChG>IjGV)PN4YkyZyUE210Ro)hX+fWhzgk6=htR&1bD2wMv`4jr zB8JS`9-aAMS=A}_(NJ3cq~7M*30-^j%qr7==8NlVN4CsvHDeJmF}#HQ%lfv^YmZN= zTGkqpV2sXL&hu|E+F%#h0=$xDsi%Tyt5&?)?dxO~CGOl_NvJF#d`=*Csg==g21qL` zDQ9KAvw0iN+o%dAGEBje_l*+T@fvp5`(Pk3B z!xif#_=SakYK>=lj|gOS!&~AR$}CvCNhg*}JW_`t)k1Di@gX%2%ZSyN+Ut2O^ef@~nz%jNR0I{|)0kEY?O3=X zPF(GwGfEVgWypOAFXZ|$4z}2 z>$86m_c#mRqr4Y=ZmzcK#Bg;WCJKrU&;{5u2sH~54XhYZyUrI7zc`D-yrGZ+MoJWe zw{SyIZb=SA=AcSdO3)G#ke7)Fy$H$Fm!Cx``hHkbW$Gh{i5q1eNFVTsIak*-__>FI zT#+)VR+4_vt%qO?z@qgvkGvU!;Hn)ne4CvhH8P@m7+Rz17NwM{rzX3+aKxxcs!mhM z@qxGuzM@ZYEy>-o0?Kw`wagB}tMn!+6kKBp=44#$`NsFfhB+UKHN!;*I<@nm1~;CC z&S2jaJ^e%qZ?(f-m{br+k6LC>yN;|_3uwA%+}Wj7KfSCjtui*Rl>r+`n6Z%vq8UoK zfSx%i6yqcGlwyx3kLHWzbyiYjUkju2@TJfu5>T5!xy-(?gbY)qu#_tsL;kZ5l$1-4 F{vU39VMYJ| diff --git a/lib/filter/sim/tb_fir_parallel.fdo b/lib/filter/sim/tb_fir_parallel.fdo deleted file mode 100644 index 9e15809..0000000 --- a/lib/filter/sim/tb_fir_parallel.fdo +++ /dev/null @@ -1,16 +0,0 @@ -vlib work -vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/filter_pkg.vhd" -vcom -explicit -93 "../src/fir_stage_pkg.vhd" -vcom -explicit -93 "../src/fir_stage.vhd" -vcom -explicit -93 "../src/fir_parallel_pkg.vhd" -vcom -explicit -93 "../src/fir_parallel.vhd" -vcom -explicit -93 "../src/tb_fir_parallel.vhd" -vsim -t 1ps -lib work tb_fir_parallel -do {tb_fir_parallel.wdo} -view wave -view structure -view signals -run 1000us diff --git a/lib/filter/sim/tb_fir_parallel.wdo b/lib/filter/sim/tb_fir_parallel.wdo deleted file mode 100644 index f0e20ce..0000000 --- a/lib/filter/sim/tb_fir_parallel.wdo +++ /dev/null @@ -1,29 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fir_parallel/clk -add wave -noupdate -format Logic /tb_fir_parallel/srst -add wave -noupdate -format Logic /tb_fir_parallel/in_valid -add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/x_in -add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/y_out -add wave -noupdate -format Logic /tb_fir_parallel/out_valid -add wave -noupdate -format Logic /tb_fir_parallel/fileout_enable -add wave -noupdate -format Analog-Interpolated -scale 10.0 /tb_fir_parallel/xi -add wave -noupdate -format Analog-Interpolated -scale 10.0 /tb_fir_parallel/yo -add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/coeff_in -add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/uut_fir_parallel/h -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {19450000 ps} 0} -configure wave -namecolwidth 140 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {25152750 ps} diff --git a/lib/filter/sim/tb_fir_results.m b/lib/filter/sim/tb_fir_results.m deleted file mode 100644 index 75a542c..0000000 --- a/lib/filter/sim/tb_fir_results.m +++ /dev/null @@ -1,10 +0,0 @@ -% Read data -function tb_fir_results() -fir = TEXTREAD('fir.txt')'; - -N= length(fir); - -% Output -close all; -plot(0:N-1, fir); grid; - diff --git a/lib/filter/sim/tb_fir_stage.fdo b/lib/filter/sim/tb_fir_stage.fdo deleted file mode 100644 index 9b4379d..0000000 --- a/lib/filter/sim/tb_fir_stage.fdo +++ /dev/null @@ -1,14 +0,0 @@ -vlib work -vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/filter_pkg.vhd" -vcom -explicit -93 "../src/fir_stage_pkg.vhd" -vcom -explicit -93 "../src/fir_stage.vhd" -vcom -explicit -93 "../src/tb_fir_stage.vhd" -vsim -t 1ps -lib work tb_fir_stage -do {tb_fir_stage.wdo} -view wave -view structure -view signals -run 2us diff --git a/lib/filter/sim/tb_fir_stage.wdo b/lib/filter/sim/tb_fir_stage.wdo deleted file mode 100644 index 916de83..0000000 --- a/lib/filter/sim/tb_fir_stage.wdo +++ /dev/null @@ -1,31 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fir_stage/clk -add wave -noupdate -format Logic /tb_fir_stage/srst -add wave -noupdate -divider Input -add wave -noupdate -format Logic /tb_fir_stage/in_valid -add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x_in -add wave -noupdate -format Literal /tb_fir_stage/xi -add wave -noupdate -divider Output -add wave -noupdate -format Logic /tb_fir_stage/out_valid -add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y_out -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_stage/yo -add wave -noupdate -divider {Stage signals} -add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x -add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1655000 ps} 0} -configure wave -namecolwidth 140 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {2100 ns} diff --git a/lib/filter/src/filter_pkg.vhd b/lib/filter/src/filter_pkg.vhd deleted file mode 100644 index 22be814..0000000 --- a/lib/filter/src/filter_pkg.vhd +++ /dev/null @@ -1,227 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use IEEE.MATH_REAL.ALL; - -------------------------------------------------------------------------------- -package filter_pkg is - - constant pi : real := 3.141592653589793e+000; - type real_array_t is array (natural range <>) of real; - - function FilterCoef_Lowpass (N : positive; omega, amp : real) return real_array_t; - function FilterCoef_Highpass (N : positive; omega, amp : real) return real_array_t; - function FilterCoef_Bandpass (N : positive; bw2, omega_m, amp : real) return real_array_t; - function FilterCoef_Delta (N:positive; delay:natural; amp:real) return real_array_t; - function Window_Hamming (x : real_array_t) return real_array_t; - function Window_VonHann (x : real_array_t) return real_array_t; - function Window_Blackman (x : real_array_t) return real_array_t; - function Sinc (x : real) return real; - function FilterEnergy (x : real_array_t) return real; - function FilterMean (x : real_array_t) return real; - function FilterScale (x : real_array_t; scale : real) return real_array_t; - function FilterTestCoef (N : positive) return real_array_t; - function NextPowerOfTwo(x : real) return natural; - -end; -- package filter_pkg; - -------------------------------------------------------------------------------- -package body filter_pkg is - - function Prototype_Lowpass (N : positive; omega : real) return real_array_t is - variable res : real_array_t(0 to N-1); - variable M : positive; - variable phi : real := 0.0; - variable dphi : real := 2.0*pi*omega; - begin - if (N mod 2) = 0 then - M := N/2; - for i in 0 to M-1 loop - phi := phi + dphi; - res(M+i) := Sinc(phi); - res(M-i-1) := res(M+i); - end loop; - else - M := (N-1)/2; - for i in 1 to M loop - phi := phi + dphi; - res(M+i) := Sinc(phi); - res(M-i) := res(M+i); - end loop; - res(M) := Sinc(0.0); - end if; - return res; - - end Prototype_Lowpass; - - ------------------------------------------------------------------------------- - function FilterCoef_Lowpass (N : positive; omega, amp : real) return real_array_t is - variable lp : real_array_t(0 to N-1); - begin - lp := Prototype_Lowpass(N, omega); - - return Window_VonHann(FilterScale(lp, amp/FilterEnergy(lp))); - - end FilterCoef_Lowpass; - - ------------------------------------------------------------------------------- - function FilterCoef_Highpass (N : positive; omega, amp : real) return real_array_t is - variable lp, res : real_array_t(0 to N-1); - variable phi : real := 0.0; - variable dphi : real := pi; - begin - lp := Prototype_Lowpass(N, 0.5-omega); - - for i in 0 to N-1 loop - res(i) := lp(i) * cos(phi); - phi := phi + dphi; - end loop; - - return Window_VonHann(FilterScale(res, amp/FilterEnergy(lp))); - - end FilterCoef_Highpass; - - ------------------------------------------------------------------------------- - function FilterCoef_Bandpass (N : positive; bw2, omega_m, amp : real) return real_array_t is - variable lp, res, mean, sum : real_array_t(0 to N-1); - variable phi : real := 0.0; - variable dphi : real := 2.0*pi*omega_m; - begin - lp := Prototype_Lowpass(N, bw2/2.0); - - for i in 0 to N-1 loop - res(i) := lp(i) * cos(phi); - phi := phi + dphi; - end loop; - - return Window_VonHann(FilterScale(res, amp/FilterEnergy(lp))); - - end FilterCoef_Bandpass; - - ------------------------------------------------------------------------------- - function FilterCoef_Delta (N:positive; delay:natural; amp:real) return real_array_t is - variable res : real_array_t(0 to N-1); - begin - for i in 0 to N-1 loop - res(i) := 0.0; - end loop; - res(delay) := amp; - - return res; - - end FilterCoef_Delta; - - ------------------------------------------------------------------------------- - function FilterTestCoef (N : positive) return real_array_t is - variable phi : real := 0.0; - variable dphi : real := 1.0/real(N); - variable res : real_array_t(0 to N-1); - begin - for i in 0 to N-1 loop - res(i) := phi; - phi := phi + dphi; - end loop; - return res; - - end FilterTestCoef; - - ------------------------------------------------------------------------------- - function Window_Hamming (x : real_array_t) return real_array_t is - variable res : real_array_t(x'range); - variable phi : real := 0.0; - variable dphi : real := 2.0*pi/real(x'length-1); - begin - for i in x'range loop - res(i) := x(i) * (0.54 - 0.46*(cos(phi))); - phi := phi + dphi; - end loop; - return res; - - end Window_Hamming; - - ------------------------------------------------------------------------------- - function Window_VonHann (x : real_array_t) return real_array_t is - variable res : real_array_t(x'range); - variable phi : real := 0.0; - variable dphi : real := 2.0*pi/real(x'length-1); - begin - for i in x'range loop - res(i) := 0.5 * x(i) * (1.0 - (cos(phi))); - phi := phi + dphi; - end loop; - return res; - - end Window_VonHann; - - ------------------------------------------------------------------------------- - function Window_Blackman (x : real_array_t) return real_array_t is - variable res : real_array_t(0 to x'length-1); - variable phi : real := 0.0; - variable dphi : real := 2.0*pi/real(x'length-1); - begin - for i in x'range loop - res(i) := x(i) * (0.42 - 0.5*cos(phi) + 0.08*cos(2.0*phi)); - phi := phi + dphi; - end loop; - return res; - - end Window_Blackman; - - ------------------------------------------------------------------------------- - function Sinc (x : real) return real is - variable res : real := 1.0; - begin - if x /= 0.0 then - res := sin(x)/x; - end if; - - return res; - - end Sinc; - - ------------------------------------------------------------------------------- - function FilterScale (x : real_array_t; scale : real) return real_array_t is - variable res : real_array_t(x'range); - begin - for i in x'range loop - res(i) := scale * x(i); - end loop; - - return res; - - end FilterScale; - - ------------------------------------------------------------------------------- - function FilterEnergy (x : real_array_t) return real is - variable res : real := 0.0; - begin - for i in x'range loop - res := res + x(i)*x(i); - end loop; - - return res; - - end FilterEnergy; - - ------------------------------------------------------------------------------- - function FilterMean (x : real_array_t) return real is - variable res : real := 0.0; - begin - for i in x'range loop - res := res + x(i); - end loop; - - return res/real(x'length); - - end FilterMean; - - ------------------------------------------------------------------------------- - function NextPowerOfTwo(x : real) return natural is - begin - return integer(ceil(log2(x))); - - end NextPowerOfTwo; - -------------------------------------------------------------------------------- -end; -- package filter_pkg; diff --git a/lib/filter/src/fir_iterative.vhd b/lib/filter/src/fir_iterative.vhd deleted file mode 100644 index 24805fd..0000000 --- a/lib/filter/src/fir_iterative.vhd +++ /dev/null @@ -1,352 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: fir_parallel - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.fir_stage_pkg.all; -use work.fir_iterative_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity fir_iterative is -Generic -( - ntaps : integer := 33; - nbits_in : integer := 12; - nbits_in_frac : integer := 11; - nbits_stages : integer := 13; - nbits_stages_frac : integer := 11; - nbits_out : integer := 12; - nbits_out_frac : integer := 11; - fir_mode : fir_iterative_mode_t := normal; - rounding : boolean := true; - saturating : boolean := true -); -Port -( - srst : in std_logic; - clk : in std_logic; - h_din : in sfixed; - h_addr_out : out unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0); - ready : out std_logic; - x_valid : in std_logic; - x_din : in sfixed; - y_dout_valid : out std_logic; - y_dout : out sfixed -); -end fir_iterative; - -architecture Behavioral of fir_iterative is - -------------------------------------------------------------------------------- - -- Component Declaration for FIR stage - COMPONENT fir_stage - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - fir_mode : fir_stage_mode_t; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_in : in sfixed; - y_in : in sfixed; - h_in : in sfixed; - out_valid : out std_logic; - x_out : out sfixed; - y_out : out sfixed; - y_out_clr : in std_logic - ); - END COMPONENT; - - ------------------------------------------------------------------------------- - constant fir_stage_mode : fir_stage_mode_t := transposed; - constant ntaps_is_even : boolean := (ntaps mod 2) = 0; - constant h_addr_bits : integer := taps_nbits(ntaps, fir_mode); - - subtype in_t is sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - subtype stage_t is sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low); - - type state_t is (init, idle, start, proc, p1, p2, output); - signal s, sn : state_t; - signal x_stage, xo, y_stage : stage_t; - signal stage_en, cnt_en, new_round : std_logic; - - subtype tap_cnt_t is natural range 0 to ntaps-1; - signal htap_cnt : tap_cnt_t; - signal xtap_cnt_w : tap_cnt_t; - signal xtap_cnt_r : tap_cnt_t; - signal stage_valid, clr_xmem, valid, fir_stage_clr, fir_stage_en, cnt_reset : std_logic; - subtype tap_range_t is natural range 0 to ntaps_addr(ntaps, fir_mode)-1; - signal h_addr : tap_range_t; - signal xmem_din, xmem_dout : in_t; - signal xmem_we, y_valid : std_logic; - - type xmem_t is array (0 to ntaps-1) of in_t; - signal xmem : xmem_t; - signal y_out_reg : stage_t; - signal y_reg_valid : std_logic; - - ------------------------------------------------------------------------------- -begin - - h_addr_out <= to_unsigned(h_addr, h_addr_bits); - x_stage <= resize(xmem_dout, x_stage, false, false); - - ---------------------------------------- - process (clk) - begin - if rising_edge(clk) then - y_reg_valid <= '0'; - if srst = '1' then - y_out_reg <= to_sfixed(0, sproto(nbits_out, nbits_out_frac)); - elsif y_valid = '1' then - y_out_reg <= y_stage; - y_reg_valid <= '1'; - end if; - end if; - end process; - - process (clk) - begin - if rising_edge(clk) then - y_dout_valid <= '0'; - if srst = '1' then - y_dout <= to_sfixed(0, sproto(nbits_out, nbits_out_frac)); - elsif y_reg_valid = '1' then - y_dout <= resize(y_out_reg, sproto(nbits_out, nbits_out_frac), rounding, saturating); - y_dout_valid <= '1'; - end if; - end if; - end process; - - ---------------------------------------- - proc_xmem_rw: process (clk) - begin - if rising_edge(clk) then - if xmem_we = '1' then - xmem(xtap_cnt_w) <= xmem_din; - end if; - xmem_dout <= xmem(xtap_cnt_r); - end if; - end process; - - ---------------------------------------- - proc_xmem_dinmux: process(new_round, clr_xmem, x_din, xmem_dout) - begin - xmem_din <= to_sfixed(0, xmem_din); - if new_round = '1' and clr_xmem = '0' then - xmem_din <= sfixed(x_din); - end if; - end process; - - ---------------------------------------- - proc_xmem_pointer: process(clk, new_round ,clr_xmem) - begin - xmem_we <= clr_xmem or new_round; - if rising_edge(clk) then - if srst = '1' then - xtap_cnt_w <= tap_cnt_t'high; - elsif xmem_we = '1' then - if xtap_cnt_w /= tap_cnt_t'low then - xtap_cnt_w <= xtap_cnt_w - 1; - else - xtap_cnt_w <= tap_cnt_t'high; - end if; - end if; - end if; - end process; - - ---------------------------------------- - proc_h_addr: process(htap_cnt) - begin - if fir_mode = symmetric then - if ntaps_is_even then - if htap_cnt > ntaps/2-1 then - h_addr <= ntaps - htap_cnt - 1; - else - h_addr <= htap_cnt; - end if; - else - if htap_cnt > (ntaps-1)/2 then - h_addr <= ntaps - htap_cnt - 1; - else - h_addr <= htap_cnt; - end if; - end if; - else - h_addr <= htap_cnt; - end if; - end process; - - ---------------------------------------- - proc_tap_counter: process(cnt_reset, clk, htap_cnt, xtap_cnt_r, xtap_cnt_w, cnt_en) - begin - if rising_edge(clk) then - if cnt_reset = '1' then - htap_cnt <= tap_cnt_t'low; - xtap_cnt_r <= xtap_cnt_w; - elsif cnt_en = '1' then - if htap_cnt /= tap_cnt_t'high then - htap_cnt <= htap_cnt + 1; - else - htap_cnt <= tap_cnt_t'low; - end if; - if xtap_cnt_r /= tap_cnt_t'high then - xtap_cnt_r <= xtap_cnt_r + 1; - else - xtap_cnt_r <= tap_cnt_t'low; - end if; - end if; - end if; - end process; - - ---------------------------------------- - proc_valid_out: process(srst, clk, valid, new_round) - variable val_pipe : unsigned(4 downto 0); - variable ctrl_pipe : unsigned(2 downto 0); - - begin - if rising_edge(clk) then - if srst = '1' then - ctrl_pipe := (others => '0'); - fir_stage_en <= '0'; - fir_stage_clr <= '0'; - else - ctrl_pipe := ctrl_pipe(ctrl_pipe'left-1 downto ctrl_pipe'right) & new_round; - fir_stage_en <= stage_en; - fir_stage_clr <= ctrl_pipe(2); - end if; - end if; - cnt_reset <= new_round; - end process; - - ---------------------------------------- - proc_fsm: process(s, x_valid, htap_cnt, xtap_cnt_w) - begin - clr_xmem <= '0'; - new_round <= '0'; - cnt_en <= '0'; - ready <= '0'; - valid <= '0'; - sn <= s; - stage_en <= '0'; - y_valid <= '0'; - - case s is - when init => - clr_xmem <= '1'; - if xtap_cnt_w = tap_cnt_t'low then - sn <= idle; - end if; - - when idle => - ready <= '1'; - if x_valid = '1' then - sn <= start; - end if; - - when start => - new_round <= '1'; - sn <= proc; - - when proc => - stage_en <= '1'; - cnt_en <= '1'; - if htap_cnt = tap_cnt_t'high then - sn <= p1; - end if; - - when p1 => - sn <= p2; - - when p2 => - sn <= output; - ready <= '1'; - - when output => - sn <= idle; - y_valid <= '1'; - ready <= '1'; - if x_valid = '1' then - sn <= start; - end if; - - when others => null; - end case; - end process; - - proc_fsm_next: process(srst, clk, sn) - begin - if rising_edge(clk) then - if srst = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - - ---------------------------------------- - inst_fir_stage: fir_stage - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - has_in_reg => true, - has_pipe_reg => true, - fir_mode => fir_stage_mode, - rounding => false, - saturating => false - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => fir_stage_en, - x_in => x_stage, - y_in => y_stage, - h_in => h_din, - out_valid => stage_valid, - x_out => xo, - y_out_clr => fir_stage_clr, - y_out => y_stage - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - -end Behavioral; diff --git a/lib/filter/src/fir_iterative_pkg.vhd b/lib/filter/src/fir_iterative_pkg.vhd deleted file mode 100644 index 3d71626..0000000 --- a/lib/filter/src/fir_iterative_pkg.vhd +++ /dev/null @@ -1,45 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use ieee.numeric_std.all; -use work.fixed_pkg.all; -use work.filter_pkg.all; - -------------------------------------------------------------------------------- -package fir_iterative_pkg is - - type fir_iterative_mode_t is (normal, symmetric); - - function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer; - function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer; - -end; -- package fir_iterative_pkg; - -------------------------------------------------------------------------------- -package body fir_iterative_pkg is - - function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer is - variable res : integer; - begin - res := NextPowerOfTwo(real(ntaps_addr(ntaps, mode))); - return res; - end taps_nbits; - - function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer is - constant ntaps_is_even : boolean := (ntaps mod 2) = 0; - variable res : integer := ntaps; - begin - if mode = symmetric then - if ntaps_is_even then - res := ntaps/2; - else - res := (ntaps-1)/2 + 1; - end if; - end if; - return res; - end ntaps_addr; - -end; -- package fir_iterative_pkg; - -------------------------------------------------------------------------------- diff --git a/lib/filter/src/fir_parallel.vhd b/lib/filter/src/fir_parallel.vhd deleted file mode 100644 index a46dba9..0000000 --- a/lib/filter/src/fir_parallel.vhd +++ /dev/null @@ -1,208 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: fir_parallel - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.fir_stage_pkg.all; -use work.fir_parallel_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity fir_parallel is -Generic -( - ntaps : integer := 33; - nbits_in : integer := 12; - nbits_in_frac : integer := 11; - nbits_stages : integer := 13; - nbits_stages_frac : integer := 11; - nbits_out : integer := 12; - nbits_out_frac : integer := 11; - has_in_reg : boolean := false; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false; - fir_mode : fir_parallel_mode_t := transposed; - rounding : boolean := true; - saturating : boolean := true -); -Port -( - srst : in std_logic; - clk : in std_logic; - h_in : in sfixed_array_t; - in_valid : in std_logic; - d_in : in sfixed; - out_valid : out std_logic; - d_out : out sfixed -); -end fir_parallel; - -architecture Behavioral of fir_parallel is - -------------------------------------------------------------------------------- - -- Component Declaration for FIR stage - COMPONENT fir_stage - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - has_out_reg : boolean; - fir_mode : fir_stage_mode_t; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_in : in sfixed; - y_in : in sfixed; - h_in : in sfixed; - out_valid : out std_logic; - x_out : out sfixed; - y_out : out sfixed - ); - END COMPONENT; - - ------------------------------------------------------------------------------- - type coeff_array_t is array (natural range <>) of sfixed(SFix_high(nbits_stages, nbits_stages_frac) downto SFix_low(nbits_stages, nbits_stages_frac)); - type stages_array_t is array (natural range <>) of sfixed(SFix_high(nbits_stages, nbits_stages_frac) downto SFix_low(nbits_stages, nbits_stages_frac)); - - constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); - constant fir_stage_mode : fir_stage_mode_t := transposed; - - SIGNAL x_out : sfixed(SFix_high(nbits_out, nbits_out_frac) downto SFix_low(nbits_out, nbits_out_frac)); - - SIGNAL x : stages_array_t(0 to ntaps-2); - SIGNAL y : stages_array_t(0 to ntaps-2); - SIGNAL h : coeff_array_t(0 to ntaps-1); - - ------------------------------------------------------------------------------- -begin - - -- Assign coefficients - assign_coeffs: - for i in 0 to ntaps-1 generate - h(i) <= to_sfixed(h_in, i); - end generate; - - ---------------------------------------- - -- Instantiate the FIR stages - ---------------------------------------- - uut_first_stage: fir_stage - GENERIC MAP - ( - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_stage_mode, - rounding => false, - saturating => false - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_in => d_in, - y_in => zero_in, - h_in => h(ntaps-1), - out_valid => out_valid, - x_out => x(0), - y_out => y(0) - ); - - ---------------------------------------- - gen_stages: - for i in 1 to ntaps-2 generate - uut_stages: fir_stage - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_stage_mode, - rounding => false, - saturating => false - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_in => x(i-1), - y_in => y(i-1), - h_in => h(ntaps-i-1), - out_valid => open, - x_out => x(i), - y_out => y(i) - ); - end generate; - - ---------------------------------------- - uut_last_stage: fir_stage - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_stage_mode, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_in => x(ntaps-2), - y_in => y(ntaps-2), - h_in => h(0), - out_valid => open, - x_out => x_out, - y_out => d_out - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - -end Behavioral; diff --git a/lib/filter/src/fir_parallel_pkg.vhd b/lib/filter/src/fir_parallel_pkg.vhd deleted file mode 100644 index 1f8c44c..0000000 --- a/lib/filter/src/fir_parallel_pkg.vhd +++ /dev/null @@ -1,76 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use work.fixed_pkg.all; -use work.filter_pkg.all; - -------------------------------------------------------------------------------- -package fir_parallel_pkg is - - type ufixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC; - type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC; - - type fir_parallel_mode_t is (transposed, transposed_sym, systolic, systolic_sym); - - function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t; - function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t; - - -- Slicing functions for unconstrained array types - function to_ufixed(src : ufixed_array_t; index : integer) return ufixed; - function to_sfixed(src : sfixed_array_t; index : integer) return sfixed; - -end; -- package fir_parallel_pkg; - -------------------------------------------------------------------------------- -package body fir_parallel_pkg is - - function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t is - variable res : sfixed_array_t(0 to x'length-1, proto'range); - variable tt : sfixed(proto'range); - begin - for i in x'range loop - tt := to_sfixed(x(i), proto); - for j in proto'range loop - res(i,j) := tt(j); - end loop; - end loop; - return res; - end to_sfixed_array; - - --------------------------------------------------------------------------- - function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t is - variable p : sfixed(SFix_high(nbits, nbits_int) downto SFix_low(nbits, nbits_int)); - begin - return to_sfixed_array(x, p); - end to_sfixed_array; - - ------------------------------------------------------------------------------- - -- ufixed <= ufixed_array(i) - function to_ufixed(src : ufixed_array_t; index : integer) return ufixed is - variable dst : ufixed(src'range(2)); - begin - for j in src'range(2) loop - dst(j) := src(index, j); - end loop; - - return dst; - - end to_ufixed; - - ------------------------------------------------------------------------------- - -- sfixed <= sfixed_array(i) - function to_sfixed(src : sfixed_array_t; index : integer) return sfixed is - variable dst : sfixed(src'range(2)); - begin - for j in src'range(2) loop - dst(j) := src(index, j); - end loop; - - return dst; - - end to_sfixed; - -end; -- package fir_parallel_pkg; - -------------------------------------------------------------------------------- diff --git a/lib/filter/src/fir_stage.vhd b/lib/filter/src/fir_stage.vhd deleted file mode 100644 index c8c4a7c..0000000 --- a/lib/filter/src/fir_stage.vhd +++ /dev/null @@ -1,150 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: fir_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.fir_stage_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity fir_stage is -Generic -( - nbits_in : integer := 12; - nbits_in_frac : integer := 12; - nbits_out : integer := 12; - nbits_out_frac : integer := 12; - has_in_reg : boolean := false; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false; - fir_mode : fir_stage_mode_t := transposed; - rounding : boolean := true; - saturating : boolean := true -); -Port -( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_in : in sfixed; - y_in : in sfixed; - h_in : in sfixed; - out_valid : out std_logic; - x_out : out sfixed; - y_out : out sfixed; - y_out_clr : in std_logic -); -end fir_stage; - -architecture Behavioral of fir_stage is - -signal xin : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal yin : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal hin : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal prod : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); -signal valid, p_valid : std_logic; ------------------------------------------------------------- -begin - - ------------------------------------------------------------- - proc_in_reg_y: process(clk) - begin - if rising_edge(clk) then - if srst = '1' or y_out_clr = '1' then - yin <= to_sfixed(0, yin); - else - yin <= resize(y_in, yin); - end if; - end if; - end process; - ------------------------------------------------------------- - proc_in_reg_hx: process(srst, clk, in_valid, x_in, h_in) - variable p : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - begin - if has_in_reg = true then - if rising_edge(clk) then - if srst = '1' then - xin <= to_sfixed(0, xin); - hin <= to_sfixed(0, hin); - valid <= '0'; - else - valid <= in_valid; - if in_valid = '1' then - xin <= resize(x_in, xin); - hin <= resize(h_in, hin); - end if; - end if; - end if; - else - xin <= resize(x_in, xin); - hin <= resize(h_in, hin); - valid <= in_valid; - end if; - x_out <= resize(x_in, p); - - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(srst, clk, valid, xin, hin) - variable p : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - begin - p := resize(xin * hin, p); - if has_pipe_reg = true then - if rising_edge(clk) then - if srst = '1' then - prod <= to_sfixed(0, prod); - p_valid <= '0'; - else - prod <= p; - p_valid <= valid; - end if; - end if; - else - prod <= p; - p_valid <= valid; - end if; - end process; - ------------------------------------------------------------- - proc_out_reg: process(srst, clk, p_valid, prod, yin) - variable yout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - begin - yout := resize(yin + prod, yout, rounding, saturating); --- if rising_edge(clk) then --- if srst = '1' or y_out_clr = '1' then --- y_out <= to_sfixed(0, yout); --- out_valid <= '0'; --- else --- y_out <= yout; --- out_valid <= p_valid; --- end if; --- end if; - out_valid <= p_valid; - y_out <= yout; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/filter/src/fir_stage_pkg.vhd b/lib/filter/src/fir_stage_pkg.vhd deleted file mode 100644 index 8bccba2..0000000 --- a/lib/filter/src/fir_stage_pkg.vhd +++ /dev/null @@ -1,38 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use work.fixed_pkg.all; - -package fir_stage_pkg is - -type fir_stage_mode_t is (transposed, systolic); - - ------------------------------------------------------------- - -- Constructor helpers - -- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range); - function uproto (nbits : integer; nbits_frac : integer) return ufixed; - - -- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range); - function sproto (nbits : integer; nbits_frac : integer) return sfixed; - -end; -- package fir_stage_pkg; - -package body fir_stage_pkg is - - ------------------------------------------------------------- - -- Constuctor helpers - function uproto (nbits : integer; nbits_frac : integer) return ufixed is - constant result : ufixed (nbits-nbits_frac-1 downto -nbits_frac) := (others => '0'); - begin - return result(nbits-nbits_frac-1 downto -nbits_frac); - end uproto; - - ------------------------------------------------------------- - function sproto (nbits : integer; nbits_frac : integer) return sfixed is - constant result : sfixed (nbits-nbits_frac downto -nbits_frac+1) := (others => '0'); - begin - return result(nbits-nbits_frac downto -nbits_frac+1); - end sproto; - -end; -- package fir_stage_pkg; diff --git a/lib/filter/src/tb_fir_iterative.vhd b/lib/filter/src/tb_fir_iterative.vhd deleted file mode 100644 index 2621a05..0000000 --- a/lib/filter/src/tb_fir_iterative.vhd +++ /dev/null @@ -1,231 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_fir_stage --- Module Name: tb_fir_stage.vhd --- Project Name: fir_stage --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.fixed_pkg.all; -use work.filter_pkg.all; -use work.fir_stage_pkg.all; -use work.fir_iterative_pkg.all; - -use work.PCK_FIO.all; - -ENTITY tb_fir_iterative IS - Generic ( - ntaps : integer := 11; - nbits_in : integer := 15; - nbits_in_frac : integer := 15; - nbits_stages : integer := 15; - nbits_stages_frac : integer := 15; - nbits_out : integer := 15; - nbits_out_frac : integer := 15; - fir_mode : fir_iterative_mode_t := symmetric; - rounding : boolean := true; - saturating : boolean := true - ); -END tb_fir_iterative; - -ARCHITECTURE behavior OF tb_fir_iterative IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT fir_iterative - GENERIC - ( - ntaps : integer; - nbits_in : integer; - nbits_in_frac : integer; - nbits_stages : integer; - nbits_stages_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - fir_mode : fir_iterative_mode_t; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - h_din : in sfixed; - h_addr_out : out unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0); - ready : out std_logic; - x_valid : in std_logic; - x_din : in sfixed; - y_dout_valid : out std_logic; - y_dout : out sfixed - ); - END COMPONENT; - - ------------------------------------------------------------------------------- - --Constants - constant nsamples : integer := 32; - - constant PERIOD : time := 10 ns; - constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL x_valid : std_logic := '0'; - SIGNAL h_din : sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low); - SIGNAL x_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - - --Outputs - SIGNAL y_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL y_valid : std_logic; - SIGNAL ready : std_logic; - - SIGNAL fileout_enable : std_logic := '1'; - - -- Test coefficients --- SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Delta(ntaps, 10, 0.999)(0 to ntaps_addr(ntaps, fir_mode)-1); - SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Bandpass(ntaps, 0.25, 0.125, 1.0)(0 to ntaps_addr(ntaps, fir_mode)-1); --- SIGNAL coeffs : real_array_t(0 to ntaps-1) := FilterTestCoef(ntaps); - signal x_input : real_array_t(0 to nsamples-1) := - ( - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.9999, - -0.0000, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0 - - ); - type ymem_t is array (0 to nsamples-1) of sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - signal ymem : ymem_t; - - signal y_cnt : integer ; - SIGNAL xi, yo : real := 0.0; - SIGNAL h_addr : unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0); - - -- file I/O - subtype sample_t is integer range -32768 to 32767; - type file_t is file of sample_t; - - ------------------------------------------------------------------------------- -BEGIN - - xi <= to_real(x_din); - yo <= to_real(y_dout); - - ---------------------------------------- - -- Instantiate the Unit Under Test (UUT) - ---------------------------------------- - uut_fir_iterative: fir_iterative - GENERIC MAP - ( - ntaps => ntaps, - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - nbits_stages => nbits_stages, - nbits_stages_frac => nbits_stages_frac, - fir_mode => fir_mode, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - h_din => h_din, - h_addr_out => h_addr, - ready => ready, - x_valid => x_valid, - x_din => x_din, - y_dout_valid => y_valid, - y_dout => y_dout - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - - for i in 0 to nsamples-1 loop - if i = nsamples/2 then - wait for 43*PERIOD; - end if; - ------------------------------------------ - wait until rising_edge(clk) and ready = '1'; - x_din <= to_sfixed(x_input(i), x_din); - x_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_valid <= '0'; - end loop; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - process(srst, clk, y_valid) - begin - if rising_edge(clk) then - h_din <= to_sfixed(coeffs(to_integer(h_addr)), h_din); - if srst = '1' then - y_cnt <= 0; - - elsif y_valid = '1' then - ymem(y_cnt) <= y_dout; - y_cnt <= y_cnt + 1; - end if; - end if; - end process; - -END; diff --git a/lib/filter/src/tb_fir_parallel.vhd b/lib/filter/src/tb_fir_parallel.vhd deleted file mode 100644 index bb87e21..0000000 --- a/lib/filter/src/tb_fir_parallel.vhd +++ /dev/null @@ -1,189 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_fir_stage --- Module Name: tb_fir_stage.vhd --- Project Name: fir_stage --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.fixed_pkg.all; -use work.fir_parallel_pkg.all; -use work.filter_pkg.all; - -use work.PCK_FIO.all; - -ENTITY tb_fir_parallel IS - Generic ( - ntaps : integer := 33; - nbits_in : integer := 15; - nbits_in_frac : integer := 15; - nbits_stages : integer := 16; - nbits_stages_frac : integer := 15; - nbits_out : integer := 15; - nbits_out_frac : integer := 15; - has_in_reg : boolean := false; - has_pipe_reg : boolean := true; - has_out_reg : boolean := false; - fir_mode : fir_parallel_mode_t := transposed; - rounding : boolean := true; - saturating : boolean := true - ); -END tb_fir_parallel; - -ARCHITECTURE behavior OF tb_fir_parallel IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT fir_parallel - GENERIC - ( - ntaps : integer; - nbits_in : integer; - nbits_in_frac : integer; - nbits_stages : integer; - nbits_stages_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - has_out_reg : boolean; - fir_mode : fir_parallel_mode_t; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - h_in : in sfixed_array_t; - in_valid : in std_logic; - d_in : in sfixed; - out_valid : out std_logic; - d_out : out sfixed - ); - END COMPONENT; - - ------------------------------------------------------------------------------- - --Constants - constant PERIOD : time := 10 ns; - constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL in_valid : std_logic := '0'; - SIGNAL x_in : sfixed(SFix_high(nbits_in, nbits_in_frac) downto SFix_low(nbits_in, nbits_in_frac)); - - --Outputs - SIGNAL y_out : sfixed(SFix_high(nbits_out, nbits_out_frac) downto SFix_low(nbits_out, nbits_out_frac)); - SIGNAL out_valid : std_logic := '0'; - - SIGNAL fileout_enable : std_logic := '1'; - - -- Test coefficients - SIGNAL coeff_in : sfixed_array_t(0 to ntaps-1, SFix_high(nbits_stages, nbits_stages_frac) downto SFix_low(nbits_stages, nbits_stages_frac)) := to_sfixed_array(FilterCoef_Lowpass(ntaps, 0.125, 0.125), nbits_stages, nbits_stages_frac); - - SIGNAL xi, yo : real := 0.0; - - -- file I/O - subtype sample_t is integer range -32768 to 32767; - type file_t is file of sample_t; - - ------------------------------------------------------------------------------- -BEGIN - - xi <= to_real(x_in); - yo <= to_real(y_out); - - ---------------------------------------- - -- Instantiate the Unit Under Test (UUT) - ---------------------------------------- - uut_fir_parallel: fir_parallel - GENERIC MAP - ( - ntaps => ntaps, - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - nbits_stages => nbits_stages, - nbits_stages_frac => nbits_stages_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_mode, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - h_in => coeff_in, - in_valid => in_valid, - d_in => x_in, - out_valid => out_valid, - d_out => y_out - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - file fi : file_t open read_mode is "wav_in.dat"; - variable si : sample_t; - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - - while not endfile(fi) loop - read(fi, si); - x_in <= to_sfixed(to_signed(si, 16)); - in_valid <= '1'; - wait for PERIOD; - wait until rising_edge(clk); - end loop; - ------------------------------------------ - in_valid <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - tb_fo : PROCESS(clk, fileout_enable, out_valid) - file fo : file_t open write_mode is "wav_out.dat"; - variable so : sample_t; - - BEGIN - if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then - so := to_integer(y_out); - write(fo, so); - end if; - - END PROCESS; - -END; diff --git a/lib/filter/src/tb_fir_stage.vhd b/lib/filter/src/tb_fir_stage.vhd deleted file mode 100644 index 159f13a..0000000 --- a/lib/filter/src/tb_fir_stage.vhd +++ /dev/null @@ -1,268 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_fir_stage --- Module Name: tb_fir_stage.vhd --- Project Name: fir_stage --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.fixed_pkg.all; -use work.fir_stage_pkg.all; -use work.filter_pkg.all; - -use work.PCK_FIO.all; - -ENTITY tb_fir_stage IS - Generic ( - ntaps : integer := 33; - nbits_in : integer := 24; - nbits_in_frac : integer := 23; - nbits_stages : integer := 25; - nbits_stages_frac : integer := 23; - nbits_out : integer := 24; - nbits_out_frac : integer := 22; - has_in_reg : boolean := true; - has_pipe_reg : boolean := true; - has_out_reg : boolean := false; - fir_mode : fir_stage_mode_t := transposed; - rounding : boolean := true; - saturating : boolean := true - ); -END tb_fir_stage; - -ARCHITECTURE behavior OF tb_fir_stage IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT fir_stage - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - has_out_reg : boolean; - fir_mode : fir_stage_mode_t; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_in : in sfixed; - y_in : in sfixed; - h_in : in sfixed; - out_valid : out std_logic; - x_out : out sfixed; - y_out : out sfixed - ); - END COMPONENT; - - type stages_t is array (natural range <>) of sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low); - - --Constants - constant PERIOD : time := 10 ns; - constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL in_valid : std_logic := '0'; - SIGNAL x_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - - --Outputs - SIGNAL x_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL y_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL out_valid : std_logic := '0'; - - SIGNAL x : stages_t(0 to ntaps-2); - SIGNAL y : stages_t(0 to ntaps-2); - - SIGNAL fileout_enable : std_logic := '1'; - - -- Test coefficients - function to_sfixed(x_real : real_array_t) return stages_t is - variable res : stages_t(x_real'range); - begin - for i in x_real'range loop - res(i) := to_sfixed(x_real(i), res(i), true, true); - end loop; - - return res; - end to_sfixed; - - constant h : stages_t(0 to ntaps-1) := to_sfixed(FilterCoef_Lowpass(ntaps, 0.25, 1.0)); - - SIGNAL xi, yo : real := 0.0; - -BEGIN - - xi <= to_real(x_in); - yo <= to_real(y_out); - - ---------------------------------------- - -- Instantiate the Unit Under Test (UUT) - ---------------------------------------- - uut_first_stage: fir_stage - GENERIC MAP - ( - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_mode, - rounding => false, - saturating => false - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_in => x_in, - y_in => zero_in, - h_in => h(ntaps-1), - out_valid => out_valid, - x_out => x(0), - y_out => y(0) - ); - - ---------------------------------------- - gen_stages: - for i in 1 to ntaps-2 generate - uut_stages: fir_stage - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_mode, - rounding => false, - saturating => false - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_in => x(i-1), - y_in => y(i-1), - h_in => h(ntaps-i-1), - out_valid => open, - x_out => x(i), - y_out => y(i) - ); - end generate; - - ---------------------------------------- - uut_last_stage: fir_stage - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_mode, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_in => x(ntaps-2), - y_in => y(ntaps-2), - h_in => h(0), - out_valid => open, - x_out => x_out, - y_out => y_out - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - - x_in <= to_sfixed(0.0, x_in); - - wait until rising_edge(clk); - in_valid <= '1'; - - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - - wait for 20*PERIOD; - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(1.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - - wait for 150*PERIOD; - - wait until rising_edge(clk); - in_valid <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - tb_fo : PROCESS(clk, fileout_enable, out_valid) - file RESULT_FIR: text open write_mode is "fir.txt"; - variable L: line; - - BEGIN - if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then - fprint(RESULT_FIR, L,"%s\n", REAL'image(yo)); - end if; - - END PROCESS; - -END; diff --git a/lib/fix_std/fix_std.vhd b/lib/fix_std/fix_std.vhd deleted file mode 100644 index 6397ebc..0000000 --- a/lib/fix_std/fix_std.vhd +++ /dev/null @@ -1,1007 +0,0 @@ ---------------------------------------------------------------------- --- --- Package fix_std --- Fixed point arithmetic based on numeric_std --- ---------------------------------------------------------------------- --- --- This document describes a VHDL package of definitions and subprograms --- intended to support the use of fixed-point arithmetic in test benches --- and synthesisable designs. This document and the package it describes --- are made freely available to the HDL design community without warranty --- of any kind. You are welcome to make use of this information for your --- own private study and in your own designs. If you make use of the --- package, you accept sole responsibility for its fitness for purpose --- and its suitability in your application. You are free to modify the --- package in any way, and to record your contribution to it, but this --- notice must appear in a prominent place in any modified or derived --- version of the package or its supporting documentation. --- --- The author wishes to thank his employer Doulos Ltd for making --- available the facilities used to develop, test and distribute this --- package. However, Doulos Ltd accepts no responsibility for the --- package's contents and cannot support it in any way. --- ---------------------------------------------------------------------- --- Revision information: --- --- Version 0.1 06-May-2003 --- Alpha version, for review --- No division operators are provided, pending detailed --- consultation on their functionality. --- Some subprogram implementations are unnecessarily inefficient. --- Version 0.2 11-Jun-2003 --- Fixes aiming to make the package portable across all synthesis tools: --- * Removed deferred constants, made them package constants --- * Removed all variable initialisations in procedures, made them --- procedural initialisations in the code ---------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package fix_std is - - -------------------------------------------------------------------- - - -- Integer subtype specifying legal values for a bit index. - -- At present it's restricted to 'natural' to conform with - -- the behaviour of mainstream synthesis tools. For simulation, - -- or in the future when synthesis tools are able to cope, it - -- would be possible to change this subtype to be the full - -- integer range, thus allowing negative subscripts for - -- fraction bits. - -- - subtype Fix_Subscr is natural; - - -- Fixed-point offset, the bit number (subscript) used for - -- the bit in a UFix or SFix vector having binary weight 2^0 - -- (the units bit). - -- - constant FixP: Fix_Subscr := 100; - - -- Type declarations for the basic unsigned and signed fixed point - -- data types: - -- - type UFix is array (Fix_Subscr range <>) of std_logic; - type SFix is array (Fix_Subscr range <>) of std_logic; - - -- Type declarations for control of rounding and overflow modes: - -- - type Fix_Rounding_Mode is ( - clip_LS, -- Throw away unwanted least significant bits - towards_zero, -- Round towards zero - same as clip_LS for UFix - to_nearest -- Round to nearest. Exact halves round up. - ); - type Fix_Overflow_Mode is ( - clip_MS, -- Throw away unwanted most significant bits - saturate -- Saturate overflow to nearest representable value - ); - - -- Defaults for these modes: - -- - constant Fix_Default_Rounding : Fix_Rounding_Mode := clip_LS; - constant Fix_Default_Overflow : Fix_Overflow_Mode := clip_MS; - - -------------------------------------------------------------------- - - --------------------------- - -- E. Extraction functions - --------------------------- - - -- E.1. Return the integral part of a UFix value - function Int(U: UFix) return UFix; - - -- E.2. Return the fractional part of a UFix value - function Frac(U: UFix) return UFix; - - -- E.3. Return the integral part of a SFix value - function Int(S: SFix) return SFix; - - -- E.4. Return the fractional part of a SFix value - function Frac(S: SFix) return UFix; - - -- E.5. Widen a SFix value if necessary so that - -- its range adjoins or spans the binary point - function Span(S: SFix) return SFix; - - -- E.6. Widen a UFix value if necessary so that - -- its range adjoins or spans the binary point - function Span(U: UFix) return UFix; - - --------------------------- - -- T. Conversion functions - --------------------------- - - -- T.1 to T.8: Unsigned conversions - -- - -- T.1. Resizing an existing UFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_UFix( - N : UFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix; - - -- T.2. Resizing an existing SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_UFix( - N : SFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix; - - -- T.3. Conversion from integer to UFix. Provide number of - -- integer bits and number of fraction bits. Note that - -- negative input is tolerated! - -- - function to_UFix( - N : integer; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix; - - -- T.4. Conversion from unsigned to UFix. Provide subscripts of - -- MS and (optionally) LS bit of the resulting UFix. - -- - function to_UFix( - N : unsigned; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix; - - -- T.5. Conversion from unsigned to UFix. Automatically set the - -- range of the resulting UFix to match the unsigned value, - -- as an integral UFix value with no fraction bits. - -- - function to_UFix( N : unsigned ) return UFix; - - -- T.6. Conversion from UFix to unsigned. All integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_unsigned( - N : UFix; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return unsigned; - - -- T.7. Conversion from UFix to unsigned. Caller specifies - -- required number of bits in unsigned result. - -- - function to_unsigned( - N : UFix; - bits : positive; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return unsigned; - - -- T.8. Conversion from UFix to integer. Up to 31 integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_integer( - N : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return integer; - - - -- T.9 to T.16: Signed conversions - -- - -- T.9. Resizing an existing UFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : UFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix; - - -- T.10. Resizing an existing SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : SFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix; - - -- T.11. Conversion from integer to SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : integer; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix; - - -- T.12. Conversion from signed to SFix. Provide subscripts of - -- MS and (optionally) LS bit of the resulting SFix. - -- - function to_SFix( - N : signed; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix; - - -- T.13. Conversion from signed to SFix. Automatically set the - -- range of the resulting SFix to match the signed value, - -- as an integral SFix value with no fraction bits. - -- - function to_SFix( N : signed ) return SFix; - - -- T.14. Conversion from SFix to signed. All integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_signed( - N : SFix; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return signed; - - -- T.15. Conversion from SFix to signed. Caller specifies - -- required number of bits in signed result. - -- - function to_signed( - N : SFix; - bits : positive; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return signed; - - -- T.16. Conversion from SFix to integer. Up to 32 integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_integer( - N : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return integer; - - -- T.17. Conversion from UFix to SFix. This simply adds - -- an extra more significant bit, set to zero. - -- - function to_SFix(U: UFix) return SFix; - - ---------------------------------- - -- V. Copy-to-variable procedures - ---------------------------------- - - -- Range-aware copying of an expression into a variable. The - -- ranges of destination variable and source expression are - -- used to determine correct rounding, overflow and scaling - -- behaviour. - - -- V.1 to V.5: Copy an expression into a UFix variable - -- - - -- V.1. Copy UFix to UFix - -- - procedure Copy_V( - target : out UFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - -- - -- V.2. Copy SFix to UFix - -- - procedure Copy_V( - target : out UFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.3. Copy UNSIGNED to UFix - -- - procedure Copy_V( - target : out UFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.4. Copy SIGNED to UFix - -- - procedure Copy_V( - target : out UFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.5. Copy integer to UFix - -- - procedure Copy_V( - target : out UFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.6 to V.10: Copy an expression into a SFix variable - -- - - -- V.6. Copy UFix to SFix - -- - procedure Copy_V( - target : out SFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.7. Copy SFix to SFix - -- - procedure Copy_V( - target : out SFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.8. Copy UNSIGNED to SFix - -- - procedure Copy_V( - target : out SFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.9. Copy SIGNED to SFix - -- - procedure Copy_V( - target : out SFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.10. Copy integer to SFix - -- - procedure Copy_V( - target : out SFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - - -------------------------------- - -- S. Copy-to-signal procedures - -------------------------------- - -- - -- Range-aware copying of an expression into a signal. The - -- ranges of destination signal and source expression are - -- used to determine correct rounding, overflow and scaling - -- behaviour. - - -- S.1 to S.5: Copy an expression into a UFix signal - -- - - -- S.1. Copy UFix to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.1. Copy SFix to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.3. Copy UNSIGNED to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.4. Copy SIGNED to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.5. Copy integer to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.6 to S.10: Copy an expression into a SFix signal - -- - - -- S.6. Copy UFix to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.7. Copy SFix to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.8. Copy UNSIGNED to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.9. Copy SIGNED to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.10. Copy integer to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - - ------------------------------------------------------------------ - -- A. Arithmetic operations involving UFix, SFix and other - -- numeric types. - -- The operators are overloaded for most of the sensible - -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER. - -- - -- IMPORTANT NOTE: - -- Arithmetic operators return a result that is wide enough - -- and precise enough so that no information is lost. THIS IS - -- SIGNIFICANTLY DIFFERENT FROM THE BEHAVIOUR OF numeric_std. - -- In the detailed description that follow, "scaling" means - -- the numerical value (weight) of the least significant bit - -- in a fixed-point value. - -- - -- ADDITION returns a result whose least significant bit - -- is the same as the least significant bit in either operand, - -- and whose most significant bit is one position higher than - -- the most significant bit in either operand. Addition of - -- two operands having the same bounds therefore results in - -- a growth of one bit at the most significant end. - -- - -- SUBTRACTION where one or both operands are signed behaves - -- in the same way as addition. Subtraction where both operands - -- are unsigned returns a result whose most significant bit - -- position is the same as the most significant bit in either - -- operand, and whose least significant bit is the same as the - -- least significant bit in either operand. - -- - -- MULTIPLICATION returns a result whose width is the sum of - -- the widths of its two operands, and whose scaling is the - -- product of its two operands' scalings. - -- - -- UNARY NEGATION always gives a result having one more - -- significant bit than the operand. - -- - -- ABSOLUTE VALUE always gives a result having exactly the - -- same subtype as its operand. - -- - -- In binary operations where one operand is a fixed-point type - -- and the other is an integer numeric type, the integer operand - -- is first converted to a fixed-point type of the same subtype - -- as the other operand using Copy_V with default rounding and - -- overflow modes. The operation is then performed between two - -- fixed-point operands in the normal way. - -- - ------------------------------------------------------------------ - - - ------------------------------------ - -- A.1. Unary "-" negation operator - ------------------------------------ - - -- A.1.1. SFix := - UFix - function "-" (R: UFix) return SFix; - - -- A.1.2. SFix := - SFix - function "-" (R: SFix) return SFix; - - - -------------------------------------------- - -- A.2. Unary "abs" absolute-value operator - -------------------------------------------- - - -- A.2.1. SFix := abs SFix - function "abs" (R: SFix) return SFix; - - - ------------------------------------- - -- A.3. Binary "+" addition operator - ------------------------------------- - - -- A.3.1. UFix := UFix + UFix - function "+" (L: UFix; R: UFix) return UFix; - - -- A.3.2. UFix := UFix + unsigned - function "+" (L: UFix; R: unsigned) return UFix; - - -- A.3.3. UFix := unsigned + UFix - function "+" (L: unsigned; R: UFix) return UFix; - - -- A.3.4. UFix := UFix + natural - function "+" (L: UFix; R: natural) return UFix; - - -- A.3.5. UFix := natural + UFix - function "+" (L: natural; R: UFix) return UFix; - - -- A.3.6. SFix := SFix + SFix - function "+" (L: SFix; R: SFix) return SFix; - - -- A.3.7. SFix := SFix + UFix - function "+" (L: SFix; R: UFix) return SFix; - - -- A.3.8. SFix := UFix + SFix - function "+" (L: UFix; R: SFix) return SFix; - - -- A.3.9. SFix := SFix + signed - function "+" (L: SFix; R: signed) return SFix; - - -- A.3.10. SFix := signed + SFix - function "+" (L: signed; R: SFix) return SFix; - - -- A.3.11. SFix := SFix + integer - function "+" (L: SFix; R: integer) return SFix; - - -- A.3.12. SFix := integer + SFix - function "+" (L: integer; R: SFix) return SFix; - - - ---------------------------------------- - -- A.4. Binary "-" subtraction operator - ---------------------------------------- - -- - -- NOTE: There is a special problem with subtraction - -- operators that return a UFix result if that result - -- goes negative. Our arbitrary decision is that we - -- truncate most-significant bits in this case. If you - -- wish to avoid the risk of this arbitrarily-defined - -- truncation behaviour, change one or more of your - -- operands to SFix and get a SFix result using this - -- idiom: - -- SFix := UFix + (-UFix) - -- or copy one of the UFix operands into a SFix that's - -- one bit wider, before performing the operation. - -- - -- Subtractions returning a UFix result take unsigned - -- operands and do not exhibit bit growth. - -- Subtractions returning a SFix result take signed or - -- unsigned operands and exhibit one-bit growth like addition. - - -- A.4.1. UFix := UFix - UFix - function "-" (L: UFix; R: UFix) return UFix; - - -- A.4.2. UFix := UFix - unsigned - function "-" (L: UFix; R: unsigned) return UFix; - - -- A.4.3. UFix := unsigned - UFix - function "-" (L: unsigned; R: UFix) return UFix; - - -- A.4.4. UFix := UFix - natural - function "-" (L: UFix; R: natural) return UFix; - - -- A.4.5. UFix := natural - UFix - function "-" (L: natural; R: UFix) return UFix; - - -- A.4.6. SFix := SFix - SFix - function "-" (L: SFix; R: SFix) return SFix; - - -- A.4.7. SFix := SFix - UFix - function "-" (L: SFix; R: UFix) return SFix; - - -- A.4.8. SFix := UFix - SFix - function "-" (L: UFix; R: SFix) return SFix; - - -- A.4.9. SFix := SFix - signed - function "-" (L: SFix; R: signed) return SFix; - - -- A.4.10. SFix := signed - SFix - function "-" (L: signed; R: SFix) return SFix; - - -- A.4.11. SFix := SFix - integer - function "-" (L: SFix; R: integer) return SFix; - - -- A.4.12. SFix := integer - SFix - function "-" (L: integer; R: SFix) return SFix; - - - ------------------------------------------- - -- A.5. Binary "*" multiplication operator - ------------------------------------------- - - -- A.5.1. UFix := UFix * UFix - function "*" (L: UFix; R: UFix) return UFix; - - -- A.5.2. UFix := UFix * unsigned - function "*" (L: UFix; R: unsigned) return UFix; - - -- A.5.3. UFix := unsigned * UFix - function "*" (L: unsigned; R: UFix) return UFix; - - -- A.5.4. UFix := UFix * natural - function "*" (L: UFix; R: natural) return UFix; - - -- A.5.5. UFix := natural * UFix - function "*" (L: natural; R: UFix) return UFix; - - -- A.5.6. SFix := SFix * SFix - function "*" (L: SFix; R: SFix) return SFix; - - -- A.5.7. SFix := SFix * UFix - function "*" (L: SFix; R: UFix) return SFix; - - -- A.5.8. SFix := UFix * SFix - function "*" (L: UFix; R: SFix) return SFix; - - -- A.5.9. SFix := SFix * signed - function "*" (L: SFix; R: signed) return SFix; - - -- A.5.10. SFix := signed * SFix - function "*" (L: signed; R: SFix) return SFix; - - -- A.5.11. SFix := SFix * integer - function "*" (L: SFix; R: integer) return SFix; - - -- A.5.12. SFix := integer * SFix - function "*" (L: integer; R: SFix) return SFix; - - - ------------------------------------------------------------------ - -- R. Relational operators - arithmetic comparisons involving - -- UFix, SFix and other numeric types. - -- The operators are overloaded for most of the sensible - -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER. - -- Note that in all cases comparisons are exact; if one - -- operand has more fraction bits than the other, the less - -- precise operand will have its LSBs zero-extended, and - -- these zero bits will take part in comparison with whatever - -- LSBs exist in the more precise operand. - ------------------------------------------------------------------ - - ------------------------------------- - -- R.1. Binary "=" equality operator - ------------------------------------- - - -- R.1.1. UFix = UFix - function "=" (L: UFix; R: UFix) return boolean; - - -- R.1.2. UFix = unsigned - function "=" (L: UFix; R: unsigned) return boolean; - - -- R.1.3. unsigned = UFix - function "=" (L: unsigned; R: UFix) return boolean; - - -- R.1.4. UFix = integer - function "=" (L: UFix; R: integer) return boolean; - - -- R.1.5. integer = UFix - function "=" (L: integer; R: UFix) return boolean; - - -- R.1.6. SFix = SFix - function "=" (L: SFix; R: SFix) return boolean; - - -- R.1.7. SFix = UFix - function "=" (L: SFix; R: UFix) return boolean; - - -- R.1.8. UFix = SFix - function "=" (L: UFix; R: SFix) return boolean; - - -- R.1.9. SFix = signed - function "=" (L: SFix; R: signed) return boolean; - - -- R.1.10. signed = SFix - function "=" (L: signed; R: SFix) return boolean; - - -- R.1.11. SFix = integer - function "=" (L: SFix; R: integer) return boolean; - - -- R.1.12. integer = SFix - function "=" (L: integer; R: SFix) return boolean; - - - -------------------------------------- - -- R.2. Binary "<" less-than operator - -------------------------------------- - - -- R.2.1. UFix < UFix - function "<" (L: UFix; R: UFix) return boolean; - - -- R.2.2. UFix < unsigned - function "<" (L: UFix; R: unsigned) return boolean; - - -- R.2.3. unsigned < UFix - function "<" (L: unsigned; R: UFix) return boolean; - - -- R.2.4. UFix < integer - function "<" (L: UFix; R: integer) return boolean; - - -- R.2.5. integer < UFix - function "<" (L: integer; R: UFix) return boolean; - - -- R.2.6. SFix < SFix - function "<" (L: SFix; R: SFix) return boolean; - - -- R.2.7. SFix < UFix - function "<" (L: SFix; R: UFix) return boolean; - - -- R.2.8. UFix < SFix - function "<" (L: UFix; R: SFix) return boolean; - - -- R.2.9. SFix < signed - function "<" (L: SFix; R: signed) return boolean; - - -- R.2.10. signed < SFix - function "<" (L: signed; R: SFix) return boolean; - - -- R.2.11. SFix < integer - function "<" (L: SFix; R: integer) return boolean; - - -- R.2.12. integer < SFix - function "<" (L: integer; R: SFix) return boolean; - - - ---------------------------------------- - -- R.3. Binary "/=" inequality operator - ---------------------------------------- - - -- R.3.1. UFix /= UFix - function "/=" (L: UFix; R: UFix) return boolean; - - -- R.3.2. UFix /= unsigned - function "/=" (L: UFix; R: unsigned) return boolean; - - -- R.3.3. unsigned /= UFix - function "/=" (L: unsigned; R: UFix) return boolean; - - -- R.3.4. UFix /= integer - function "/=" (L: UFix; R: integer) return boolean; - - -- R.3.5. integer /= UFix - function "/=" (L: integer; R: UFix) return boolean; - - -- R.3.6. SFix /= SFix - function "/=" (L: SFix; R: SFix) return boolean; - - -- R.3.7. SFix /= UFix - function "/=" (L: SFix; R: UFix) return boolean; - - -- R.3.8. UFix /= SFix - function "/=" (L: UFix; R: SFix) return boolean; - - -- R.3.9. SFix /= signed - function "/=" (L: SFix; R: signed) return boolean; - - -- R.3.10. signed /= SFix - function "/=" (L: signed; R: SFix) return boolean; - - -- R.3.11. SFix /= integer - function "/=" (L: SFix; R: integer) return boolean; - - -- R.3.12. integer /= SFix - function "/=" (L: integer; R: SFix) return boolean; - - - ----------------------------------------- - -- R.4. Binary ">" greater-than operator - ----------------------------------------- - - -- R.4.1. UFix > UFix - function ">" (L: UFix; R: UFix) return boolean; - - -- R.4.2. UFix > unsigned - function ">" (L: UFix; R: unsigned) return boolean; - - -- R.4.3. unsigned > UFix - function ">" (L: unsigned; R: UFix) return boolean; - - -- R.4.4. UFix > integer - function ">" (L: UFix; R: integer) return boolean; - - -- R.4.5. integer > UFix - function ">" (L: integer; R: UFix) return boolean; - - -- R.4.6. SFix > SFix - function ">" (L: SFix; R: SFix) return boolean; - - -- R.4.7. SFix > UFix - function ">" (L: SFix; R: UFix) return boolean; - - -- R.4.8. UFix > SFix - function ">" (L: UFix; R: SFix) return boolean; - - -- R.4.9. SFix > signed - function ">" (L: SFix; R: signed) return boolean; - - -- R.4.10. signed > SFix - function ">" (L: signed; R: SFix) return boolean; - - -- R.4.11. SFix > integer - function ">" (L: SFix; R: integer) return boolean; - - -- R.4.12. integer > SFix - function ">" (L: integer; R: SFix) return boolean; - - - ---------------------------------------------- - -- R.5. Binary ">=" greater-or-equal operator - ---------------------------------------------- - - -- R.5.1. UFix >= UFix - function ">=" (L: UFix; R: UFix) return boolean; - - -- R.5.2. UFix >= unsigned - function ">=" (L: UFix; R: unsigned) return boolean; - - -- R.5.3. unsigned >= UFix - function ">=" (L: unsigned; R: UFix) return boolean; - - -- R.5.4. UFix >= integer - function ">=" (L: UFix; R: integer) return boolean; - - -- R.5.5. integer >= UFix - function ">=" (L: integer; R: UFix) return boolean; - - -- R.5.6. SFix >= SFix - function ">=" (L: SFix; R: SFix) return boolean; - - -- R.5.7. SFix >= UFix - function ">=" (L: SFix; R: UFix) return boolean; - - -- R.5.8. UFix >= SFix - function ">=" (L: UFix; R: SFix) return boolean; - - -- R.5.9. SFix >= signed - function ">=" (L: SFix; R: signed) return boolean; - - -- R.5.10. signed >= SFix - function ">=" (L: signed; R: SFix) return boolean; - - -- R.5.11. SFix >= integer - function ">=" (L: SFix; R: integer) return boolean; - - -- R.5.12. integer >= SFix - function ">=" (L: integer; R: SFix) return boolean; - - - ------------------------------------------- - -- R.6. Binary "<=" less-or-equal operator - ------------------------------------------- - - -- R.6.1. UFix <= UFix - function "<=" (L: UFix; R: UFix) return boolean; - - -- R.6.2. UFix <= unsigned - function "<=" (L: UFix; R: unsigned) return boolean; - - -- R.6.3. unsigned <= UFix - function "<=" (L: unsigned; R: UFix) return boolean; - - -- R.6.4. UFix <= integer - function "<=" (L: UFix; R: integer) return boolean; - - -- R.6.5. integer <= UFix - function "<=" (L: integer; R: UFix) return boolean; - - -- R.6.6. SFix <= SFix - function "<=" (L: SFix; R: SFix) return boolean; - - -- R.6.7. SFix <= UFix - function "<=" (L: SFix; R: UFix) return boolean; - - -- R.6.8. UFix <= SFix - function "<=" (L: UFix; R: SFix) return boolean; - - -- R.6.9. SFix <= signed - function "<=" (L: SFix; R: signed) return boolean; - - -- R.6.10. signed <= SFix - function "<=" (L: signed; R: SFix) return boolean; - - -- R.6.11. SFix <= integer - function "<=" (L: SFix; R: integer) return boolean; - - -- R.6.12. integer <= SFix - function "<=" (L: integer; R: SFix) return boolean; - - - ------------------------------------------------------------------ - -- C. Concatenation operators between fixed-point operands, and - -- between fixed-point operands and other reasonable types. - -- Unlike the implicitly defined "&" operator, they preserve - -- place value and return an appropriately aligned subtype. - -- Preservation of place value means that some concatenation - -- operations are illegal. In particular, operations - -- [SFix & SFix] and [UFix & SFix] are illegal, and - -- the place values of operands in [SFix & UFix] and - -- [UFix & UFix] must match up - the rightmost subscript of - -- the left operand must be one higher than the leftmost - -- subscript of the right operand. - -- Single bits of type std_ulogic may be concatenated with - -- fixed-point types where there is no risk of losing - -- sign-extension information. - -- Because of the way VHDL defines implicit concatenation, - -- it is impossible to detect all these errors at compile time. - -- Instead they are detected by assertion statements at run time. - -- Tool vendors may choose to implement compile-time checks - -- so that the run-time checking overhead can be avoided. - ------------------------------------------------------------------ - - -- C.1.1. UFix := UFix & UFix - function "&" (L: UFix; R: UFix) return UFix; - - -- No need to define "&"[UFix, SFix] explicitly, because - -- the types are incompatible and so there's no default - - -- C.1.2. UFix := UFix & std_ulogic - function "&" (L: UFix; R: std_ulogic) return UFix; - - -- C.1.3. UFix := std_ulogic & UFix - function "&" (L: std_ulogic; R: UFix) return UFix; - - - -- C.2.1. SFix := SFix & UFix - function "&" (L: SFix; R: UFix) return SFix; - - -- C.2.2. SFix := SFix & SFix -- ILLEGAL - function "&" (L: SFix; R: SFix) return SFix; - - -- C.2.3. SFix := SFix & std_ulogic - function "&" (L: SFix; R: std_ulogic) return SFix; - - -- C.2.4. SFix := std_ulogic & SFix - function "&" (L: std_ulogic; R: SFix) return SFix; - - -end; -- package fix_std; diff --git a/lib/fix_std/fix_stdb.vhd b/lib/fix_std/fix_stdb.vhd deleted file mode 100644 index 695cd11..0000000 --- a/lib/fix_std/fix_stdb.vhd +++ /dev/null @@ -1,1910 +0,0 @@ ---------------------------------------------------------------------- --- --- Package body fix_std --- Fixed point arithmetic based on numeric_std --- Compile using VHDL-93 (required to support 'ASCENDING --- array attribute). --- ---------------------------------------------------------------------- --- --- This document describes a VHDL package of definitions and subprograms --- intended to support the use of fixed-point arithmetic in test benches --- and synthesisable designs. This document and the package it describes --- are made freely available to the HDL design community without warranty --- of any kind. You are welcome to make use of this information for your --- own private study and in your own designs. If you make use of the --- package, you accept sole responsibility for its fitness for purpose --- and its suitability in your application. You are free to modify the --- package in any way, and to record your contribution to it, but this --- notice must appear in a prominent place in any modified or derived --- version of the package or its supporting documentation. --- --- The author wishes to thank his employer Doulos Ltd for making --- available the facilities used to develop, test and distribute this --- package. However, Doulos Ltd accepts no responsibility for the --- package's contents and cannot support it in any way. --- ---------------------------------------------------------------------- --- Revision information: --- --- Version 0.1 06-May-2003 --- Alpha version, for review --- No division operators are provided, pending detailed --- consultation on their functionality. --- Some subprogram implementations are unnecessarily inefficient. --- Version 0.2 11-Jun-2003 --- Fixes aiming to make the package portable across all synthesis tools: --- * Removed deferred constants, made them package constants --- * Removed all variable initialisations in procedures, made them --- procedural initialisations in the code --- * Fixed definition of extract functions to return just one bit --- if their results would otherwise be null ---------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package body fix_std is - - -------------------------------------------------------------------- - -- DEFERRED CONSTANTS - -------------------------------------------------------------------- - -- THESE CONSTANTS MAY BE ADJUSTED TO SUIT THE NEEDS OF SPECIFIC - -- IMPLEMENTATIONS OR APPLICATIONS. - -------------------------------------------------------------------- - - -- Fixed-point offset, the bit number (subscript) used for - -- the bit in a UFix or SFix vector having binary weight 2^0 - -- (the units bit). - -- - -- constant FixP : Fix_Subscr := 100; - - -- Default values for overflow and rounding modes: - -- - -- constant Fix_Default_Rounding : Fix_Rounding_Mode := clip_LS; - -- constant Fix_Default_Overflow : Fix_Overflow_Mode := clip_MS; - - -------------------------------------------------------------------- - -- END OF DEFERRED CONSTANTS - -------------------------------------------------------------------- - - -------------------------------------------------------------------- - -- IMPLEMENTATION CONSTANTS - -------------------------------------------------------------------- - -- THESE CONSTANTS MAY BE ADJUSTED TO SUIT THE NEEDS OF SPECIFIC - -- IMPLEMENTATIONS OR APPLICATIONS. - -------------------------------------------------------------------- - - -- Severity levels for various errors - - -- Concatenation errors - bad sign extension, discontiguous range etc - -- These are only warnings - they just give the wrong answer. - -- - constant concat_severity : severity_level := WARNING; - - -- Subtype direction errors - the present implementation can't - -- handle fixed-point objects with ascending ranges. These messages - -- are intended to give early warning of problems that would - -- definitely cause other fatal errors at elaboration or run time. - -- - constant direction_severity : severity_level := FAILURE; - - -- Assertion error message constants - - constant bad_direction_msg : string := - " has ascending range"; - - constant concat_range_msg : string := - "Concatenation bounds should have contiguous ranges"; - - constant concat_sxt_msg : string := - "Concatenation corrupts sign of result"; - - constant concat_signLS_msg : string := - "RHS of concatenation should be unsigned"; - - constant compare_meta_msg : string := - "Metavalue detected in FIX_STD comparison, returning FALSE"; - - -------------------------------------------------------------------- - -- END OF IMPLEMENTATION CONSTANTS - -------------------------------------------------------------------- - - -------------------------------------------------------------------- - -- DO NOT MODIFY ANY CODE BELOW THIS POINT. - -------------------------------------------------------------------- - - -- Assumed bit width of INTEGER type in VHDL - -- - constant INT_WIDTH : positive := 32; - - -- Single-bit zero values - subtype Izero_UFixT is UFix(FixP downto FixP); - subtype Izero_SFixT is SFix(FixP downto FixP); - subtype Fzero_UFixT is UFix(FixP-1 downto FixP-1); - constant Izero_UFix: Izero_UFixT := "0"; - constant Izero_SFix: Izero_SFixT := "0"; - constant Fzero_UFix: Fzero_UFixT := "0"; - - -------------------------------------------------------------------- - -- LOCAL PRIVATE SUBPROGRAMS - -------------------------------------------------------------------- - - -- Min, Max: Find minimum and maximum of two integers. - -- Useful for determining appropriate range for operation results. - -- - function Max(L, R: Fix_Subscr) return Fix_Subscr is - begin - if L>R then - return L; - else - return R; - end if; - end; - -- - function Min(L, R: Fix_Subscr) return Fix_Subscr is - begin - if L FixP then - return Span(U); - else - return U(U'LEFT downto FixP); - end if; - end; - - -- E.2. Return the fractional part of a UFix value - function Frac(U: UFix) return UFix is - begin - if U'LEFT < FixP-1 then - return Span(U); - elsif U'RIGHT >= FixP then - return Fzero_UFix; - else - return U(FixP-1 downto U'RIGHT); - end if; - end; - - -- E.3. Return the integral part of a SFix value - function Int(S: SFix) return SFix is - begin - if S'LENGTH = 0 then - return Izero_SFix; - elsif S'LEFT <= FixP then - return SFix'(FixP => S(S'LEFT)); - elsif S'RIGHT > FixP then - return Span(S); - else - return S(S'LEFT downto FixP); - end if; - end; - - -- E.4. Return the fractional part of a SFix value - function Frac(S: SFix) return UFix is - variable P: SFix(Max(S'LEFT, FixP) downto Min(S'RIGHT, FixP)); - begin - if S'LEFT < FixP then - for I in FixP-1 downto S'LEFT+1 loop - P(I) := S(S'LEFT); - end loop; - P(S'RANGE) := S; - return UFix(S(FixP-1 downto S'RIGHT)); - elsif S'RIGHT >= FixP then - return Fzero_UFix; - else - return UFix(S(FixP-1 downto S'RIGHT)); - end if; - end; - - -- E.5. Widen a SFix value if necessary so that - -- its range adjoins or spans the binary point - function Span(S: SFix) return SFix is - variable F: SFix(Max(S'LEFT, FixP) downto Min(S'RIGHT, FixP)); - begin - F(S'RANGE) := S; - for I in F'LEFT downto S'LEFT+1 loop - F(I) := S(S'LEFT); - end loop; - for I in S'RIGHT-1 downto F'RIGHT loop - F(I) := '0'; - end loop; - return F; - end; - - -- E.6. Widen a UFix value if necessary so that - -- its range adjoins or spans the binary point - function Span(U: UFix) return UFix is - variable F: UFix(Max(U'LEFT, FixP-1) downto Min(U'RIGHT, FixP)); - begin - F(U'RANGE) := U; - for I in F'LEFT downto U'LEFT+1 loop - F(I) := '0'; - end loop; - for I in U'RIGHT-1 downto F'RIGHT loop - F(I) := '0'; - end loop; - return F; - end; - - --------------------------- - -- T. Conversion functions - --------------------------- - - -- T.1 to T.8: Unsigned conversions - - -- T.1. Resizing an existing UFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_UFix( - N : UFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix is - variable F: UFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.2. Resizing an existing SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_UFix( - N : SFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix is - variable F: UFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.3. Conversion from integer to UFix. Provide number of - -- integer bits and number of fraction bits. Note that - -- negative input is tolerated! - -- - function to_UFix( - N : integer; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix is - variable F: UFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.4. Conversion from unsigned to UFix. Provide subscripts of - -- MS and (optionally) LS bit of the resulting UFix. - -- - function to_UFix( - N : unsigned; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix is - variable F: UFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.5. Conversion from unsigned to UFix. Automatically set the - -- range of the resulting UFix to match the unsigned value, - -- as an integral UFix value with no fraction bits. - -- - function to_UFix( N : unsigned ) return UFix is - variable F: UFix(FixP+N'LENGTH-1 downto FixP); - begin - F := UFix(N); - return F; - end; - - -- T.6. Conversion from UFix to unsigned. All integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_unsigned( - N : UFix; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return unsigned is - variable F_UFix: UFix(N'LEFT downto FixP); - variable F: unsigned(F_UFix'LENGTH-1 downto 0); - begin - Copy_V(F_UFix, N, rounding=>rounding); - F := unsigned(F_UFix); - return F; - end; - - -- T.7. Conversion from UFix to unsigned. Caller specifies - -- required number of bits in unsigned result. - -- - function to_unsigned( - N : UFix; - bits : positive; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return unsigned is - variable F_UFix: UFix(FixP+bits-1 downto FixP); - variable F: unsigned(F_UFix'LENGTH-1 downto 0); - begin - Copy_V(F_UFix, N, overflow, rounding); - F := unsigned(F_UFix); - return F; - end; - - -- T.8. Conversion from UFix to integer. Up to 31 integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_integer( - N : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return integer is - variable F_UFix: UFix(Min(FixP+INT_WIDTH-2, N'LEFT) downto FixP); - begin - Copy_V(F_UFix, N, overflow, rounding); - return to_integer(unsigned(F_UFix)); - end; - - -- T.9 to T.16: Signed conversions - - -- T.9. Resizing an existing UFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : UFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix is - variable F: SFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.10. Resizing an existing SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : SFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix is - variable F: SFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.11. Conversion from integer to SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : integer; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix is - variable F: SFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.12. Conversion from signed to SFix. Provide subscripts of - -- MS and (optionally) LS bit of the resulting SFix. - -- - function to_SFix( - N : signed; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix is - variable F: SFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.13. Conversion from signed to SFix. Automatically set the - -- range of the resulting SFix to match the signed value, - -- as an integral SFix value with no fraction bits. - -- - function to_SFix( N : signed ) return SFix is - variable F: SFix(FixP+N'LENGTH-1 downto FixP); - begin - F := SFix(N); - return F; - end; - - -- T.14. Conversion from SFix to signed. All integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_signed( - N : SFix; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return signed is - variable F_SFix: SFix(N'LEFT downto FixP); - variable F: signed(F_SFix'LENGTH-1 downto 0); - begin - Copy_V(F_SFix, N, rounding=>rounding); - F := signed(F_SFix); - return F; - end; - - -- T.15. Conversion from SFix to signed. Caller specifies - -- required number of bits in signed result. - -- - function to_signed( - N : SFix; - bits : positive; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return signed is - variable F_SFix: UFix(FixP+bits-1 downto FixP); - variable F: signed(F_SFix'LENGTH-1 downto 0); - begin - Copy_V(F_SFix, N, overflow, rounding); - F := signed(F_SFix); - return F; - end; - - -- T.16. Conversion from SFix to integer. Up to 32 integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_integer( - N : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return integer is - variable F_SFix: SFix(Min(FixP+INT_WIDTH-1, N'LEFT) downto FixP); - begin - Copy_V(F_SFix, N, overflow, rounding); - return to_integer(signed(F_SFix)); - end; - - -- T.17. Conversion from UFix to SFix. This simply adds - -- an extra more significant bit, set to zero. - -- - function to_SFix(U: UFix) return SFix is - variable F: SFix(U'LEFT+1 downto U'RIGHT); - begin - F := SFix('0' & U); - return F; - end; - - - ---------------------------------- - -- V. Copy-to-variable procedures - ---------------------------------- - - -- Range-aware copying of an expression into a variable. The - -- ranges of destination variable and source expression are - -- used to determine correct rounding, overflow and scaling - -- behaviour. - - -- V.1 to V.5: Copy an expression into a UFix variable - - -- V.1. Copy UFix to UFix - -- - procedure Copy_V( - target : out UFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - subtype target_T is UFix(target'RANGE); - variable W: UFix(Max(target'LEFT, source'LEFT+1) downto - Min(target'RIGHT, source'RIGHT)); - constant HighZero: UFix(W'LEFT downto target'LEFT+1) := (others => '0'); - begin - assert not target'ASCENDING - report "target" & bad_direction_msg - severity direction_severity; - assert not source'ASCENDING - report "source" & bad_direction_msg - severity direction_severity; - W := (others => '0'); - W(source'RANGE) := source; - if target'RIGHT > source'RIGHT then - case rounding is - when clip_LS | towards_zero => - null; - when to_nearest => - W(W'LEFT downto target'RIGHT-1) := UFix( - unsigned(W(W'LEFT downto target'RIGHT-1)) + 1 - ); - end case; - end if; - target := W(target'RANGE); - if HighZero'LENGTH > 0 then - if unsigned(W(HighZero'RANGE)) /= unsigned(HighZero) then - case overflow is - when clip_MS => - null; - when saturate => - target := target_T'(others => '1'); - end case; - end if; - end if; - end; - - -- V.2. Copy SFix to UFix - -- - procedure Copy_V( - target : out UFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable W: SFix(Max(Source'LEFT, target'LEFT) downto target'RIGHT); - constant target_zero: UFix(target'RANGE) := (others => '0'); - begin - assert not target'ASCENDING - report "target" & bad_direction_msg - severity direction_severity; - assert not source'ASCENDING - report "source" & bad_direction_msg - severity direction_severity; - W := (others => '0'); - -- Rounding & sign-extend - Copy_V(W, source, clip_MS, rounding); - -- Saturation? - if W < 0 and overflow = saturate then - target := target_zero; - else - Copy_V(target, UFix(W), overflow, clip_LS); - end if; - end; - - -- V.3. Copy UNSIGNED to UFix - -- - procedure Copy_V( - target : out UFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant U: UFix(FixP+source'LENGTH-1 downto FixP) := UFix(source); - begin - Copy_V(target, U, overflow, rounding); - end; - - -- V.4. Copy SIGNED to UFix - -- - procedure Copy_V( - target : out UFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant S: SFix(FixP+source'LENGTH-1 downto FixP) := SFix(source); - begin - Copy_V(target, S, overflow, rounding); - end; - - -- V.5. Copy integer to UFix - -- - procedure Copy_V( - target : out UFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant N: signed(FixP+INT_WIDTH-1 downto FixP) - := to_signed(source, INT_WIDTH); - begin - -- Cop-out, this is very inefficient, but will do for now. - Copy_V(target, N, overflow, rounding); - end; - - -- V.6 to V.10: Copy an expression into a SFix variable - - -- V.6. Copy UFix to SFix - -- - procedure Copy_V( - target : out SFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant S: SFix(FixP+source'LENGTH downto FixP) := to_SFix(source); - begin - Copy_V(target, S, overflow, rounding); - end; - - -- V.7. Copy SFix to SFix - -- - procedure Copy_V( - target : out SFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - subtype target_T is SFix(target'RANGE); - variable W: SFix(Max(target'LEFT, source'LEFT+1) downto - Min(target'RIGHT, source'RIGHT)); - variable HighSX: SFix(W'LEFT downto target'LEFT+1); - begin - for i in HighSX'RANGE loop - HighSX(i) := source(source'LEFT); - end loop; - assert not target'ASCENDING - report "target" & bad_direction_msg - severity direction_severity; - assert not source'ASCENDING - report "source" & bad_direction_msg - severity direction_severity; - -- Make W a copy of source, duly extended at both ends - W := (others => '0'); - W(source'RANGE) := source; - W(HighSX'RANGE) := HighSX; - -- Do any rounding required - if target'RIGHT > source'RIGHT then - case rounding is - when clip_LS => - null; - when towards_zero => - if - (to_UX01(W(W'LEFT)) = '1') -- it's negative? - and - (unsigned(W(target'RIGHT-1 downto W'RIGHT)) /= 0) -- round up? - then - W(W'LEFT downto target'RIGHT) := SFix( - signed(W(W'LEFT downto target'RIGHT)) + 1 - ); - end if; - when to_nearest => - W(W'LEFT downto target'RIGHT-1) := SFix( - signed(W(W'LEFT downto target'RIGHT-1)) + 1 - ); - end case; - end if; - -- Do any overflow required - target := W(target'RANGE); - if HighSX'LENGTH > 0 then - if signed(W(HighSX'RANGE)) /= signed(HighSX) then - case overflow is - when clip_MS => - null; - when saturate => - target := Target_T'(others => not W(W'LEFT)); - target(target'LEFT) := W(W'LEFT); - end case; - end if; - end if; - end; - - -- V.8. Copy UNSIGNED to SFix - -- - procedure Copy_V( - target : out SFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant S: SFix(FixP+source'LENGTH downto FixP) := SFix('0' & source); - begin - Copy_V(target, S, overflow, rounding); - end; - - -- V.9. Copy SIGNED to SFix - -- - procedure Copy_V( - target : out SFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant S: SFix(FixP+source'LENGTH-1 downto FixP) := SFix(source); - begin - Copy_V(target, S, overflow, rounding); - end; - - -- V.10. Copy integer to SFix - -- - procedure Copy_V( - target : out SFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant N: signed(FixP+INT_WIDTH-1 downto FixP) - := to_signed(source, INT_WIDTH); - begin - -- Cop-out, this is very inefficient, but will do for now. - Copy_V(target, N, overflow, rounding); - end; - - - -------------------------------- - -- S. Copy-to-signal procedures - -------------------------------- - -- - -- Range-aware copying of an expression into a signal. The - -- ranges of destination signal and source expression are - -- used to determine correct rounding, overflow and scaling - -- behaviour. - - -- S.1 to S.5: Copy an expression into a UFix signal - -- - - -- S.1. Copy UFix to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: UFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.1. Copy SFix to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: UFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.3. Copy UNSIGNED to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: UFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.4. Copy SIGNED to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: UFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.5. Copy integer to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: UFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.6 to S.10: Copy an expression into a SFix signal - -- - - -- S.6. Copy UFix to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: SFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.7. Copy SFix to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: SFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.8. Copy UNSIGNED to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: SFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.9. Copy SIGNED to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: SFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.10. Copy integer to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: SFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - - ------------------------------------------------------------------ - -- A. Arithmetic operations involving UFix, SFix and other - -- numeric types. - -- The operators are overloaded for most of the sensible - -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER. - -- - -- IMPORTANT NOTE: - -- Arithmetic operators return a result that is wide enough - -- and precise enough so that no information is lost. THIS IS - -- SIGNIFICANTLY DIFFERENT FROM THE BEHAVIOUR OF numeric_std. - -- In the detailed description that follow, "scaling" means - -- the numerical value (weight) of the least significant bit - -- in a fixed-point value. - -- - -- ADDITION returns a result whose least significant bit - -- is the same as the least significant bit in either operand, - -- and whose most significant bit is one position higher than - -- the most significant bit in either operand. Addition of - -- two operands having the same bounds therefore results in - -- a growth of one bit at the most significant end. Addition - -- of an integer to a UFix or SFix is accomplished by first - -- converting the integer to the same subtype as the other - -- operand, thereby giving rise to one-bit growth; default - -- truncation and rounding modes are used for the conversion. - -- - -- SUBTRACTION where one or both operands are signed behaves - -- in the same way as addition. Subtraction where both operands - -- are unsigned returns a result whose most significant bit - -- position is the same as the most significant bit in either - -- operand, and whose least significant bit is the same as the - -- least significant bit in either operand. - -- - -- MULTIPLICATION returns a result whose width is the sum of - -- the widths of its two operands, and whose scaling is the - -- product of its two operands' scalings. - -- - -- UNARY NEGATION always gives a result having one more - -- significant bit than the operand. - -- - -- ABSOLUTE VALUE always gives a result having exactly the - -- same subtype as its operand. - -- - -- In binary operations where one operand is a fixed-point type - -- and the other is an integer numeric type, the integer operand - -- is first converted to a fixed-point type of the same subtype - -- as the other operand using Copy_V with default rounding and - -- overflow modes. The operation is then performed between two - -- fixed-point operands in the normal way. - -- - ------------------------------------------------------------------ - - - ------------------------------------ - -- A.1. Unary "-" negation operator - ------------------------------------ - - -- A.1.1. SFix := - UFix - function "-" (R: UFix) return SFix is - variable F: SFix(R'LEFT+1 downto R'RIGHT); - begin - F := SFix(-(signed('0' & R))); - return F; - end; - - -- A.1.2. SFix := - SFix - function "-" (R: SFix) return SFix is - variable F: SFix(R'LEFT+1 downto R'RIGHT); - begin - F := SFix(-(signed(R(R'LEFT) & R))); - return F; - end; - - - -------------------------------------------- - -- A.2. Unary "abs" absolute-value operator - -------------------------------------------- - - -- A.2.1. SFix := abs SFix - function "abs" (R: SFix) return SFix is - variable F: SFix(R'RANGE); - begin - F := R; - if to_X01(R(R'LEFT)) = '1' then - F := SFix(-(signed(R))); - end if; - return F; - end; - - - ------------------------------------- - -- A.3. Binary "+" addition operator - ------------------------------------- - - -- A.3.1. UFix := UFix + UFix - function "+" (L: UFix; R: UFix) return UFix is - variable F: UFix(Max(L'LEFT, R'LEFT)+1 downto Min(L'Right, R'Right)); - variable LU, RU: unsigned(F'RANGE); - begin - LU := (others => '0'); - RU := (others => '0'); - LU(L'RANGE) := unsigned(L); - RU(R'RANGE) := unsigned(R); - F := UFix(LU + RU); - return F; - end; - - -- A.3.2. UFix := UFix + unsigned - function "+" (L: UFix; R: unsigned) return UFix is - begin - return L + to_UFix(R); - end; - - -- A.3.3. UFix := unsigned + UFix - function "+" (L: unsigned; R: UFix) return UFix is - begin - return R+L; - end; - - -- A.3.4. UFix := UFix + natural - function "+" (L: UFix; R: natural) return UFix is - variable R_fp: UFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L + R_fp; - end; - - -- A.3.5. UFix := natural + UFix - function "+" (L: natural; R: UFix) return UFix is - begin - return R+L; - end; - - -- A.3.6. SFix := SFix + SFix - function "+" (L: SFix; R: SFix) return SFix is - variable F: SFix(Max(L'LEFT, R'LEFT)+1 downto Min(L'Right, R'Right)); - variable LS, RS: signed(F'RANGE); - begin - LS := (others => '0'); - RS := (others => '0'); - LS(L'RANGE) := signed(L); - RS(R'RANGE) := signed(R); - for i in LS'LEFT downto L'LEFT+1 loop LS(i) := L(L'LEFT); end loop; - for i in RS'LEFT downto R'LEFT+1 loop RS(i) := R(R'LEFT); end loop; - F := SFix(LS + RS); - return F; - end; - - -- A.3.7. SFix := SFix + UFix - function "+" (L: SFix; R: UFix) return SFix is - begin - return L + SFix('0' & R); - end; - - -- A.3.8. SFix := UFix + SFix - function "+" (L: UFix; R: SFix) return SFix is - begin - return SFix('0' & L) + R; - end; - - -- A.3.9. SFix := SFix + signed - function "+" (L: SFix; R: signed) return SFix is - begin - return L + to_SFix(R); - end; - - -- A.3.10. SFix := signed + SFix - function "+" (L: signed; R: SFix) return SFix is - begin - return to_SFix(L) + R; - end; - - -- A.3.11. SFix := SFix + integer - function "+" (L: SFix; R: integer) return SFix is - variable R_fp: SFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L + R_fp; - end; - - -- A.3.12. SFix := integer + SFix - function "+" (L: integer; R: SFix) return SFix is - begin - return R + L; - end; - - - ---------------------------------------- - -- A.4. Binary "-" subtraction operator - ---------------------------------------- - -- - -- NOTE: There is a special problem with subtraction - -- operators that return a UFix result if that result - -- goes negative. Our arbitrary decision is that we - -- truncate most-significant bits in this case. If you - -- wish to avoid the risk of this arbitrarily-defined - -- truncation behaviour, change one or more of your - -- operands to SFix and get a SFix result using this - -- idiom: - -- SFix := UFix + (-UFix) - -- or copy one of the UFix operands into a SFix that's - -- one bit wider, before performing the operation. - -- - -- Subtractions returning a UFix result take unsigned - -- operands and do not exhibit bit growth. - -- Subtractions returning a SFix result take signed or - -- unsigned operands and exhibit one-bit growth like addition. - - -- A.4.1. UFix := UFix - UFix - function "-" (L: UFix; R: UFix) return UFix is - variable F, LW, RW: UFix(Max(L'LEFT, R'LEFT) downto - Min(L'RIGHT, R'RIGHT)); - begin - LW := (others => '0'); - RW := (others => '0'); - LW(L'RANGE) := L; - RW(R'RANGE) := R; - F := UFix(unsigned(LW) - unsigned(RW)); - return F; - end; - - -- A.4.2. UFix := UFix - unsigned - function "-" (L: UFix; R: unsigned) return UFix is - begin - return L - to_UFix(R); - end; - - -- A.4.3. UFix := unsigned - UFix - function "-" (L: unsigned; R: UFix) return UFix is - begin - return to_UFix(L) - R; - end; - - -- A.4.4. UFix := UFix - integer - function "-" (L: UFix; R: natural) return UFix is - variable R_fp: UFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L - R_fp; - end; - - -- A.4.5. UFix := natural - UFix - function "-" (L: natural; R: UFix) return UFix is - variable L_fp: UFix(R'RANGE); - begin - Copy_V(L_fp, L); - return L_fp - R; - end; - - -- A.4.6. SFix := SFix - SFix - function "-" (L: SFix; R: SFix) return SFix is - begin - return L + (-R); - end; - - -- A.4.7. SFix := SFix - UFix - function "-" (L: SFix; R: UFix) return SFix is - begin - return L + (-R); - end; - - -- A.4.8. SFix := UFix - SFix - function "-" (L: UFix; R: SFix) return SFix is - begin - return To_SFix(L) - R; - end; - - -- A.4.9. SFix := SFix - signed - function "-" (L: SFix; R: signed) return SFix is - begin - return L - to_SFix(R); - end; - - -- A.4.10. SFix := signed - SFix - function "-" (L: signed; R: SFix) return SFix is - begin - return to_SFix(L) - R; - end; - - -- A.4.11. SFix := SFix - integer - function "-" (L: SFix; R: integer) return SFix is - variable R_fp: SFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L - R_fp; - end; - - -- A.4.12. SFix := integer - SFix - function "-" (L: integer; R: SFix) return SFix is - variable L_fp: SFix(R'RANGE); - begin - Copy_V(L_fp, L); - return L_fp - R; - end; - - - ------------------------------------------- - -- A.5. Binary "*" multiplication operator - ------------------------------------------- - - -- A.5.1. UFix := UFix * UFix - function "*" (L: UFix; R: UFix) return UFix is - variable F: UFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP); - begin - F := UFix(unsigned(L) * unsigned(R)); - return F; - end; - - -- A.5.2. UFix := UFix * unsigned - function "*" (L: UFix; R: unsigned) return UFix is - begin - return L * to_UFix(R); - end; - - -- A.5.3. UFix := unsigned * UFix - function "*" (L: unsigned; R: UFix) return UFix is - begin - return to_UFix(L) * R; - end; - - -- A.5.4. UFix := UFix * natural - function "*" (L: UFix; R: natural) return UFix is - variable R_fp: UFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L * R_fp; - end; - - -- A.5.5. UFix := natural * UFix - function "*" (L: natural; R: UFix) return UFix is - begin - return R * L; - end; - - -- A.5.6. SFix := SFix * SFix - function "*" (L: SFix; R: SFix) return SFix is - variable F: SFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP); - begin - F := SFix(signed(L) * signed(R)); - return F; - end; - - -- A.5.7. SFix := SFix * UFix - function "*" (L: SFix; R: UFix) return SFix is - constant RS: SFix := SFix('0' & R); - variable F: SFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP); - variable FW: SFix(F'LEFT+1 downto F'RIGHT); - begin - FW := SFix(signed(L) * signed(RS)); - Copy_V(F, FW); -- never overflows - return F; - end; - - -- A.5.8. SFix := UFix * SFix - function "*" (L: UFix; R: SFix) return SFix is - begin - return R * L; - end; - - -- A.5.9. SFix := SFix * signed - function "*" (L: SFix; R: signed) return SFix is - begin - return L * to_SFix(R); - end; - - -- A.5.10. SFix := signed * SFix - function "*" (L: signed; R: SFix) return SFix is - begin - return to_SFix(L) * R; - end; - - -- A.5.11. SFix := SFix * integer - function "*" (L: SFix; R: integer) return SFix is - variable R_fp: SFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L * R_fp; - end; - - -- A.5.12. SFix := integer * SFix - function "*" (L: integer; R: SFix) return SFix is - begin - return R * L; - end; - - - ------------------------------------------------------------------ - -- R. Relational operators - arithmetic comparisons involving - -- UFix, SFix and other numeric types. - -- The operators are overloaded for most of the sensible - -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER. - -- Note that in all cases comparisons are exact; if one - -- operand has more fraction bits than the other, the less - -- precise operand will have its LSBs zero-extended, and - -- these zero bits will take part in comparison with whatever - -- LSBs exist in the more precise operand. - -- - -- Our implementation is based on only two operators, "=" and "<". - -- All other operators are derived from these two, either by - -- logical inversion of the result or by swapping operands. - ------------------------------------------------------------------ - - ------------------------------------- - -- R.1. Binary "=" equality operator - ------------------------------------- - - -- R.1.1. UFix = UFix - function "=" (L: UFix; R: UFix) return boolean is - variable LW, RW: UFix(Max(L'LEFT, R'LEFT) downto Min(L'RIGHT, R'RIGHT)); - begin - LW := (others => '0'); - RW := (others => '0'); - LW(L'RANGE) := L; - RW(R'RANGE) := R; - return unsigned(LW) = unsigned(RW); - end; - - -- R.1.2. UFix = unsigned - function "=" (L: UFix; R: unsigned) return boolean is - begin - return L = to_UFix(R); - end; - - -- R.1.3. unsigned = UFix - function "=" (L: unsigned; R: UFix) return boolean is - begin - return to_UFix(L) = R; - end; - - -- R.1.4. UFix = integer - function "=" (L: UFix; R: integer) return boolean is - variable RS: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(RS, R, clip_MS, clip_LS); - return To_SFix(L) = RS; - end; - - -- R.1.5. integer = UFix - function "=" (L: integer; R: UFix) return boolean is - begin - return R = L; - end; - - -- R.1.6. SFix = SFix - function "=" (L: SFix; R: SFix) return boolean is - variable LW, RW: SFix(Max(L'LEFT, R'LEFT) downto Min(L'RIGHT, R'RIGHT)); - begin - -- clip modes are OK because we aren't losing any bits - Copy_V(LW, L, clip_MS, clip_LS); - Copy_V(RW, R, clip_MS, clip_LS); - return signed(LW) = signed(RW); - end; - - -- R.1.7. SFix = UFix - function "=" (L: SFix; R: UFix) return boolean is - begin - return L = To_SFix(R); - end; - - -- R.1.8. UFix = SFix - function "=" (L: UFix; R: SFix) return boolean is - begin - return R = L; - end; - - -- R.1.9. SFix = signed - function "=" (L: SFix; R: signed) return boolean is - begin - return L = to_SFix(R); - end; - - -- R.1.10. signed = SFix - function "=" (L: signed; R: SFix) return boolean is - begin - return to_SFix(L) = R; - end; - - -- R.1.11. SFix = integer - function "=" (L: SFix; R: integer) return boolean is - variable RS: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(RS, R, clip_MS, clip_LS); - return L = RS; - end; - - -- R.1.12. integer = SFix - function "=" (L: integer; R: SFix) return boolean is - begin - return R = L; - end; - - - -------------------------------------- - -- R.2. Binary "<" less-than operator - -------------------------------------- - - -- R.2.1. UFix < UFix - function "<" (L: UFix; R: UFix) return boolean is - variable LW, RW: unsigned(Max(L'LEFT, R'LEFT) downto - Min(L'RIGHT, R'RIGHT)); - begin - LW := (others => '0'); - RW := (others => '0'); - LW(L'RANGE) := unsigned(L); - RW(R'RANGE) := unsigned(R); - return unsigned(LW) < unsigned(RW); - end; - - -- R.2.2. UFix < unsigned - function "<" (L: UFix; R: unsigned) return boolean is - begin - return L < To_UFix(R); - end; - - -- R.2.3. unsigned < UFix - function "<" (L: unsigned; R: UFix) return boolean is - begin - return To_UFix(L) < R; - end; - - -- R.2.4. UFix < integer - function "<" (L: UFix; R: integer) return boolean is - variable S: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(S, R, clip_MS, clip_LS); - return L < S; - end; - - -- R.2.5. integer < UFix - function "<" (L: integer; R: UFix) return boolean is - variable S: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(S, L, clip_MS, clip_LS); - return S < R; - end; - - -- R.2.6. SFix < SFix - function "<" (L: SFix; R: SFix) return boolean is - variable LW, RW: SFix(Max(L'LEFT, R'LEFT) downto - Min(L'RIGHT, R'RIGHT)); - begin - Copy_V(LW, L, clip_MS, clip_LS); - Copy_V(RW, R, clip_MS, clip_LS); - return signed(LW) < signed(RW); - end; - - -- R.2.7. SFix < UFix - function "<" (L: SFix; R: UFix) return boolean is - begin - return L < To_SFix(R); - end; - - -- R.2.8. UFix < SFix - function "<" (L: UFix; R: SFix) return boolean is - begin - return To_SFix(L) < R; - end; - - -- R.2.9. SFix < signed - function "<" (L: SFix; R: signed) return boolean is - begin - return L < To_SFix(R); - end; - - -- R.2.10. signed < SFix - function "<" (L: signed; R: SFix) return boolean is - begin - return To_SFix(L) < R; - end; - - -- R.2.11. SFix < integer - function "<" (L: SFix; R: integer) return boolean is - variable S: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(S, R, clip_MS, clip_LS); - return L < S; - end; - - -- R.2.12. integer < SFix - function "<" (L: integer; R: SFix) return boolean is - variable S: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(S, L, clip_MS, clip_LS); - return S < R; - end; - - - ---------------------------------------- - -- R.3. Binary "/=" inequality operator - ---------------------------------------- - - -- R.3.1. UFix /= UFix - function "/=" (L: UFix; R: UFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.2. UFix /= unsigned - function "/=" (L: UFix; R: unsigned) return boolean is - begin - return not (L = R); - end; - - -- R.3.3. unsigned /= UFix - function "/=" (L: unsigned; R: UFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.4. UFix /= integer - function "/=" (L: UFix; R: integer) return boolean is - begin - return not (L = R); - end; - - -- R.3.5. integer /= UFix - function "/=" (L: integer; R: UFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.6. SFix /= SFix - function "/=" (L: SFix; R: SFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.7. SFix /= UFix - function "/=" (L: SFix; R: UFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.8. UFix /= SFix - function "/=" (L: UFix; R: SFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.9. SFix /= signed - function "/=" (L: SFix; R: signed) return boolean is - begin - return not (L = R); - end; - - -- R.3.10. signed /= SFix - function "/=" (L: signed; R: SFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.11. SFix /= integer - function "/=" (L: SFix; R: integer) return boolean is - begin - return not (L = R); - end; - - -- R.3.12. integer /= SFix - function "/=" (L: integer; R: SFix) return boolean is - begin - return not (L = R); - end; - - - ----------------------------------------- - -- R.4. Binary ">" greater-than operator - ----------------------------------------- - - -- R.4.1. UFix > UFix - function ">" (L: UFix; R: UFix) return boolean is - begin - return R < L; - end; - - -- R.4.2. UFix > unsigned - function ">" (L: UFix; R: unsigned) return boolean is - begin - return R < L; - end; - - -- R.4.3. unsigned > UFix - function ">" (L: unsigned; R: UFix) return boolean is - begin - return R < L; - end; - - -- R.4.4. UFix > integer - function ">" (L: UFix; R: integer) return boolean is - begin - return R < L; - end; - - -- R.4.5. integer > UFix - function ">" (L: integer; R: UFix) return boolean is - begin - return R < L; - end; - - -- R.4.6. SFix > SFix - function ">" (L: SFix; R: SFix) return boolean is - begin - return R < L; - end; - - -- R.4.7. SFix > UFix - function ">" (L: SFix; R: UFix) return boolean is - begin - return R < L; - end; - - -- R.4.8. UFix > SFix - function ">" (L: UFix; R: SFix) return boolean is - begin - return R < L; - end; - - -- R.4.9. SFix > signed - function ">" (L: SFix; R: signed) return boolean is - begin - return R < L; - end; - - -- R.4.10. signed > SFix - function ">" (L: signed; R: SFix) return boolean is - begin - return R < L; - end; - - -- R.4.11. SFix > integer - function ">" (L: SFix; R: integer) return boolean is - begin - return R < L; - end; - - -- R.4.12. integer > SFix - function ">" (L: integer; R: SFix) return boolean is - begin - return R < L; - end; - - - ---------------------------------------------- - -- R.5. Binary ">=" greater-or-equal operator - ---------------------------------------------- - - -- R.5.1. UFix >= UFix - function ">=" (L: UFix; R: UFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.2. UFix >= unsigned - function ">=" (L: UFix; R: unsigned) return boolean is - begin - return not (L < R); - end; - - -- R.5.3. unsigned >= UFix - function ">=" (L: unsigned; R: UFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.4. UFix >= integer - function ">=" (L: UFix; R: integer) return boolean is - begin - return not (L < R); - end; - - -- R.5.5. integer >= UFix - function ">=" (L: integer; R: UFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.6. SFix >= SFix - function ">=" (L: SFix; R: SFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.7. SFix >= UFix - function ">=" (L: SFix; R: UFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.8. UFix >= SFix - function ">=" (L: UFix; R: SFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.9. SFix >= signed - function ">=" (L: SFix; R: signed) return boolean is - begin - return not (L < R); - end; - - -- R.5.10. signed >= SFix - function ">=" (L: signed; R: SFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.11. SFix >= integer - function ">=" (L: SFix; R: integer) return boolean is - begin - return not (L < R); - end; - - -- R.5.12. integer >= SFix - function ">=" (L: integer; R: SFix) return boolean is - begin - return not (L < R); - end; - - - ------------------------------------------- - -- R.6. Binary "<=" less-or-equal operator - ------------------------------------------- - - -- R.6.1. UFix <= UFix - function "<=" (L: UFix; R: UFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.2. UFix <= unsigned - function "<=" (L: UFix; R: unsigned) return boolean is - begin - return not (R < L); - end; - - -- R.6.3. unsigned <= UFix - function "<=" (L: unsigned; R: UFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.4. UFix <= integer - function "<=" (L: UFix; R: integer) return boolean is - begin - return not (R < L); - end; - - -- R.6.5. integer <= UFix - function "<=" (L: integer; R: UFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.6. SFix <= SFix - function "<=" (L: SFix; R: SFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.7. SFix <= UFix - function "<=" (L: SFix; R: UFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.8. UFix <= SFix - function "<=" (L: UFix; R: SFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.9. SFix <= signed - function "<=" (L: SFix; R: signed) return boolean is - begin - return not (R < L); - end; - - -- R.6.10. signed <= SFix - function "<=" (L: signed; R: SFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.11. SFix <= integer - function "<=" (L: SFix; R: integer) return boolean is - begin - return not (R < L); - end; - - -- R.6.12. integer <= SFix - function "<=" (L: integer; R: SFix) return boolean is - begin - return not (R < L); - end; - - ------------------------------------------------------------------ - -- C. Concatenation operators between fixed-point operands, and - -- between fixed-point operands and other reasonable types. - -- Unlike the implicitly defined "&" operator, they preserve - -- place value and return an appropriately aligned subtype. - -- Preservation of place value means that some concatenation - -- operations are illegal. In particular, operations - -- [SFix & SFix] and [UFix & SFix] are illegal, and - -- the place values of operands in [SFix & UFix] and - -- [UFix & UFix] must match up - the rightmost subscript of - -- the left operand must be one higher than the leftmost - -- subscript of the right operand. - -- Single bits of type std_ulogic may be concatenated with - -- fixed-point types where there is no risk of losing - -- sign-extension information. - -- Because of the way VHDL defines implicit concatenation, - -- it is impossible to detect all these errors at compile time. - -- Instead they are detected by assertion statements at run time. - -- Tool vendors may choose to implement compile-time checks - -- so that the run-time checking overhead can be avoided. - ------------------------------------------------------------------ - - -- C.1.1. UFix := UFix & UFix - function "&" (L: UFix; R: UFix) return UFix is - begin - return UFix(concat(std_logic_vector(L), std_logic_vector(R))); - end; - - -- C.1.2. UFix := UFix & std_ulogic - function "&" (L: UFix; R: std_ulogic) return UFix is - begin - return UFix(concat(std_logic_vector(L), R)); - end; - - -- C.1.3. UFix := std_ulogic & UFix - function "&" (L: std_ulogic; R: UFix) return UFix is - begin - return UFix(concat(L, std_logic_vector(R))); - end; - - - -- C.2.1. SFix := SFix & UFix - function "&" (L: SFix; R: UFix) return SFix is - begin - return SFix(concat(std_logic_vector(L), std_logic_vector(R))); - end; - - -- C.2.2. SFix := SFix & SFix -- ILLEGAL - function "&" (L: SFix; R: SFix) return SFix is - begin - report concat_signLS_msg - severity concat_severity; - return SFix(concat(std_logic_vector(L), std_logic_vector(R))); - end; - - -- C.2.3. SFix := SFix & std_ulogic - function "&" (L: SFix; R: std_ulogic) return SFix is - begin - return SFix(concat(std_logic_vector(L), R)); - end; - - -- C.2.4. SFix := std_ulogic & SFix - function "&" (L: std_ulogic; R: SFix) return SFix is - begin - assert std_match(L, R(R'LEFT)) - report concat_sxt_msg - severity concat_severity; - return SFix(concat(L, std_logic_vector(R))); - end; - - -end; -- package body fix_std; diff --git a/lib/fixed/fixed_pkg_c.vhd b/lib/fixed/fixed_pkg_c.vhd deleted file mode 100644 index 68acdd1..0000000 --- a/lib/fixed/fixed_pkg_c.vhd +++ /dev/null @@ -1,7846 +0,0 @@ ------------------------------------------------------------------------------- --- "fixed_pkg" package contains functions for fixed point math. --- Please see the documentation for the fixed point package. --- This package should be compiled into "ieee_proposed" and used as follows: --- use ieee.std_logic_1164.all; --- use ieee.numeric_std.all; --- use ieee_proposed.fixed_pkg.all; --- Last Modified: $Date: 2008-08-23 08:20:29 $ --- RCS ID: $Id: fixed_pkg_c.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ --- --- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org) ------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; --- synthesis translate_off -use std.textio.all; --- synthesis translate_on - -package fixed_pkg is - --%%% Uncomment the Generics --- new work.fixed_generic_pkg --- generic map ( --- fixed_round_style => true; -- fixed_round --- fixed_overflow_style => true; -- fixed_saturate --- fixed_guard_bits => 3; -- number of guard bits --- no_warning => false -- show warnings --- ); - --%%% REMOVE THE REST OF THIS FILE. - constant fixed_round_style : BOOLEAN := false; -- round - constant fixed_overflow_style : BOOLEAN := false; -- saturate - constant fixed_guard_bits : NATURAL := 3; -- number of guard bits - constant no_warning : BOOLEAN := false; -- issue warnings - -- Author David Bishop (dbishop@vhdl.org) - -- These 5 constants are used as defaults. - -- There is a mechanism to override them in every function - constant fixed_round : BOOLEAN := true; -- Turn on rounding routine - constant fixed_truncate : BOOLEAN := false; -- Trun off rounding routine - constant fixed_saturate : BOOLEAN := true; -- Saturate large numbers - constant fixed_wrap : BOOLEAN := false; -- Wrap large numbers - constant fixedsynth_or_real : BOOLEAN := true; -- differed constant - -- base Unsigned fixed point type, downto direction assumed - type ufixed is array (INTEGER range <>) of STD_LOGIC; - -- base Signed fixed point type, downto direction assumed - type sfixed is array (INTEGER range <>) of STD_LOGIC; - ----------------------------------------------------------------------------- - -- Fixed point type is defined as follows: - -- 0000000000 - -- 4321012345 - -- 4 0 -5 - -- The decimal point is assumed between the "0" and "-1" index - -- Thus "0011010000" = 6.5 and would be written as 00110.10000 - -- All types are assumed to be in the "downto" direction. - - --=========================================================================== - -- Arithmetic Operators: - --=========================================================================== - -- Modify the sign of the number, 2's complement - function "abs" (arg : sfixed) return sfixed; - function "-" (arg : sfixed)return sfixed; - - -- Convert a signed fixed to an unsigned fixed - function "abs" (arg : sfixed) return ufixed; - - -- Addition - -- ufixed(a downto b) + ufixed(c downto d) - -- = ufixed(max(a,c)+1 downto min(b,d)) - function "+" (l, r : ufixed) return ufixed; - - -- sfixed(a downto b) + sfixed(c downto d) - -- = sfixed(max(a,c)+1 downto min(b,d)) - function "+" (l, r : sfixed) return sfixed; - - -- Subtraction - -- ufixed(a downto b) - ufixed(c downto d) - -- = ufixed(max(a,c)+1 downto min(b,d)) - function "-" (l, r : ufixed) return ufixed; - - -- sfixed(a downto b) - sfixed(c downto d) - -- = sfixed(max(a,c)+1 downto min(b,d)) - function "-" (l, r : sfixed) return sfixed; - - -- Multiplication - -- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d) - function "*" (l, r : ufixed) return ufixed; - - -- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d) - function "*" (l, r : sfixed) return sfixed; - - -- Division - -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1) - function "/" (l, r : ufixed) return ufixed; - - -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c) - function "/" (l, r : sfixed) return sfixed; - - -- Remainder - -- ufixed (a downto b) rem ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b,d)) - function "rem" (l, r : ufixed) return ufixed; - - -- sfixed (a downto b) rem sfixed (c downto d) - -- = sfixed (min(a,c) downto min(b,d)) - function "rem" (l, r : sfixed) return sfixed; - - -- Modulo - -- ufixed (a downto b) mod ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b, d)) - function "mod" (l, r : ufixed) return ufixed; - - -- sfixed (a downto b) mod sfixed (c downto d) - -- = sfixed (c downto min(b, d)) - function "mod" (l, r : sfixed) return sfixed; - - ---------------------------------------------------------------------------- - -- Overload routines. In these routines the "real" or "natural" (integer) - -- are converted into a fixed point number and then the operation is - -- performed. It is assumed that the array will be large enough. - -- If the input is "real" then the real number is converted into a fixed of - -- the same size as the fixed point input. If the number is an "integer" - -- then it is converted into fixed with the range (l'high downto 0). - ---------------------------------------------------------------------------- - -- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b) - function "+" (l : ufixed; r : REAL) return ufixed; - - -- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d) - function "+" (l : REAL; r : ufixed) return ufixed; - - -- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto min(0,b)) - function "+" (l : ufixed; r : NATURAL) return ufixed; - - -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d)) - function "+" (l : NATURAL; r : ufixed) return ufixed; - - -- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b) - function "-" (l : ufixed; r : REAL) return ufixed; - - -- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d) - function "-" (l : REAL; r : ufixed) return ufixed; - - -- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto min(0,b)) - function "-" (l : ufixed; r : NATURAL) return ufixed; - - -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d)) - function "-" (l : NATURAL; r : ufixed) return ufixed; - - -- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b) - function "*" (l : ufixed; r : REAL) return ufixed; - - -- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d) - function "*" (l : REAL; r : ufixed) return ufixed; - - -- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b) - function "*" (l : ufixed; r : NATURAL) return ufixed; - - -- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b) - function "*" (l : NATURAL; r : ufixed) return ufixed; - - -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1) - function "/" (l : ufixed; r : REAL) return ufixed; - - -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1) - function "/" (l : REAL; r : ufixed) return ufixed; - - -- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1) - function "/" (l : ufixed; r : NATURAL) return ufixed; - - -- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1) - function "/" (l : NATURAL; r : ufixed) return ufixed; - - -- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b) - function "rem" (l : ufixed; r : REAL) return ufixed; - - -- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d) - function "rem" (l : REAL; r : ufixed) return ufixed; - - -- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto min(b,0)) - function "rem" (l : ufixed; r : NATURAL) return ufixed; - - -- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto min(d,0)) - function "rem" (l : NATURAL; r : ufixed) return ufixed; - - -- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b) - function "mod" (l : ufixed; r : REAL) return ufixed; - - -- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d) - function "mod" (l : REAL; r : ufixed) return ufixed; - - -- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto min(b,0)) - function "mod" (l : ufixed; r : NATURAL) return ufixed; - - -- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto min(d,0)) - function "mod" (l : NATURAL; r : ufixed) return ufixed; - - -- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b) - function "+" (l : sfixed; r : REAL) return sfixed; - - -- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d) - function "+" (l : REAL; r : sfixed) return sfixed; - - -- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto min(0,b)) - function "+" (l : sfixed; r : INTEGER) return sfixed; - - -- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto min(0,d)) - function "+" (l : INTEGER; r : sfixed) return sfixed; - - -- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b) - function "-" (l : sfixed; r : REAL) return sfixed; - - -- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d) - function "-" (l : REAL; r : sfixed) return sfixed; - - -- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto min(0,b)) - function "-" (l : sfixed; r : INTEGER) return sfixed; - - -- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto min(0,d)) - function "-" (l : INTEGER; r : sfixed) return sfixed; - - -- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b) - function "*" (l : sfixed; r : REAL) return sfixed; - - -- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d) - function "*" (l : REAL; r : sfixed) return sfixed; - - -- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b) - function "*" (l : sfixed; r : INTEGER) return sfixed; - - -- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d) - function "*" (l : INTEGER; r : sfixed) return sfixed; - - -- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a) - function "/" (l : sfixed; r : REAL) return sfixed; - - -- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c) - function "/" (l : REAL; r : sfixed) return sfixed; - - -- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a) - function "/" (l : sfixed; r : INTEGER) return sfixed; - - -- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c) - function "/" (l : INTEGER; r : sfixed) return sfixed; - - -- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b) - function "rem" (l : sfixed; r : REAL) return sfixed; - - -- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d) - function "rem" (l : REAL; r : sfixed) return sfixed; - - -- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto min(b,0)) - function "rem" (l : sfixed; r : INTEGER) return sfixed; - - -- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto min(d,0)) - function "rem" (l : INTEGER; r : sfixed) return sfixed; - - -- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b) - function "mod" (l : sfixed; r : REAL) return sfixed; - - -- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d) - function "mod" (l : REAL; r : sfixed) return sfixed; - - -- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto min(b,0)) - function "mod" (l : sfixed; r : INTEGER) return sfixed; - - -- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto min(d,0)) - function "mod" (l : INTEGER; r : sfixed) return sfixed; - - -- This version of divide gives the user more control - -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1) - function divide ( - l, r : ufixed; - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return ufixed; - - -- This version of divide gives the user more control - -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c) - function divide ( - l, r : sfixed; - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return sfixed; - - -- These functions return 1/X - -- 1 / ufixed(a downto b) = ufixed(-b downto -a-1) - function reciprocal ( - arg : ufixed; -- fixed point input - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return ufixed; - - -- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a) - function reciprocal ( - arg : sfixed; -- fixed point input - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return sfixed; - - -- REM function - -- ufixed (a downto b) rem ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b,d)) - function remainder ( - l, r : ufixed; - constant round_style : BOOLEAN := fixed_round_style) - return ufixed; - - -- sfixed (a downto b) rem sfixed (c downto d) - -- = sfixed (min(a,c) downto min(b,d)) - function remainder ( - l, r : sfixed; - constant round_style : BOOLEAN := fixed_round_style) - return sfixed; - - -- mod function - -- ufixed (a downto b) mod ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b, d)) - function modulo ( - l, r : ufixed; - constant round_style : BOOLEAN := fixed_round_style) - return ufixed; - - -- sfixed (a downto b) mod sfixed (c downto d) - -- = sfixed (c downto min(b, d)) - function modulo ( - l, r : sfixed; - constant overflow_style : BOOLEAN := fixed_overflow_style; - constant round_style : BOOLEAN := fixed_round_style) - return sfixed; - - -- Procedure for those who need an "accumulator" function. - -- add_carry (ufixed(a downto b), ufixed (c downto d)) - -- = ufixed (max(a,c) downto min(b,d)) - procedure add_carry ( - L, R : in ufixed; - c_in : in STD_ULOGIC; - result : out ufixed; - c_out : out STD_ULOGIC); - - -- add_carry (sfixed(a downto b), sfixed (c downto d)) - -- = sfixed (max(a,c) downto min(b,d)) - procedure add_carry ( - L, R : in sfixed; - c_in : in STD_ULOGIC; - result : out sfixed; - c_out : out STD_ULOGIC); - - -- Scales the result by a power of 2. Width of input = width of output with - -- the decimal point moved. - function scalb (y : ufixed; N : integer) return ufixed; - function scalb (y : ufixed; N : SIGNED) return ufixed; - function scalb (y : sfixed; N : integer) return sfixed; - function scalb (y : sfixed; N : SIGNED) return sfixed; - - function Is_Negative (arg : sfixed) return BOOLEAN; - --=========================================================================== - -- Comparison Operators - --=========================================================================== - function ">" (l, r : ufixed) return BOOLEAN; - function ">" (l, r : sfixed) return BOOLEAN; - function "<" (l, r : ufixed) return BOOLEAN; - function "<" (l, r : sfixed) return BOOLEAN; - function "<=" (l, r : ufixed) return BOOLEAN; - function "<=" (l, r : sfixed) return BOOLEAN; - function ">=" (l, r : ufixed) return BOOLEAN; - function ">=" (l, r : sfixed) return BOOLEAN; - function "=" (l, r : ufixed) return BOOLEAN; - function "=" (l, r : sfixed) return BOOLEAN; - function "/=" (l, r : ufixed) return BOOLEAN; - function "/=" (l, r : sfixed) return BOOLEAN; - --%%% Uncomment the following (new syntax) --- function "?=" (L, R : ufixed) return BOOLEAN; --- function "?=" (L, R : sfixed) return BOOLEAN; --- --%%% remove the following (old syntax) - function \?=\ (L, R : ufixed) return STD_ULOGIC; - function \?=\ (L, R : sfixed) return STD_ULOGIC; - -- These need to be overloaded for sfixed and ufixed - function \?/=\ (L, R : ufixed) return STD_ULOGIC; - function \?>\ (L, R : ufixed) return STD_ULOGIC; - function \?>=\ (L, R : ufixed) return STD_ULOGIC; - function \?<\ (L, R : ufixed) return STD_ULOGIC; - function \?<=\ (L, R : ufixed) return STD_ULOGIC; - function \?/=\ (L, R : sfixed) return STD_ULOGIC; - function \?>\ (L, R : sfixed) return STD_ULOGIC; - function \?>=\ (L, R : sfixed) return STD_ULOGIC; - function \?<\ (L, R : sfixed) return STD_ULOGIC; - function \?<=\ (L, R : sfixed) return STD_ULOGIC; - -- %%% Replace with the following (new syntax) --- function "?=" (L, R : ufixed) return STD_ULOGIC; --- function "?/=" (L, R : ufixed) return STD_ULOGIC; --- function "?>" (L, R : ufixed) return STD_ULOGIC; --- function "?>=" (L, R : ufixed) return STD_ULOGIC; --- function "?<" (L, R : ufixed) return STD_ULOGIC; --- function "?<=" (L, R : ufixed) return STD_ULOGIC; --- function "?=" (L, R : sfixed) return STD_ULOGIC; --- function "?/=" (L, R : sfixed) return STD_ULOGIC; --- function "?>" (L, R : sfixed) return STD_ULOGIC; --- function "?>=" (L, R : sfixed) return STD_ULOGIC; --- function "?<" (L, R : sfixed) return STD_ULOGIC; --- function "?<=" (L, R : sfixed) return STD_ULOGIC; - - function std_match (L, R : ufixed) return BOOLEAN; - function std_match (L, R : sfixed) return BOOLEAN; - - -- Overloads the default "maximum" and "minimum" function - function maximum (l, r : ufixed) return ufixed; - function minimum (l, r : ufixed) return ufixed; - function maximum (l, r : sfixed) return sfixed; - function minimum (l, r : sfixed) return sfixed; - - ---------------------------------------------------------------------------- - -- In these compare functions a natural is converted into a - -- fixed point number of the bounds "max(l'high,0) downto 0" - ---------------------------------------------------------------------------- - function "=" (l : ufixed; r : NATURAL) return BOOLEAN; - function "/=" (l : ufixed; r : NATURAL) return BOOLEAN; - function ">=" (l : ufixed; r : NATURAL) return BOOLEAN; - function "<=" (l : ufixed; r : NATURAL) return BOOLEAN; - function ">" (l : ufixed; r : NATURAL) return BOOLEAN; - function "<" (l : ufixed; r : NATURAL) return BOOLEAN; - - function "=" (l : NATURAL; r : ufixed) return BOOLEAN; - function "/=" (l : NATURAL; r : ufixed) return BOOLEAN; - function ">=" (l : NATURAL; r : ufixed) return BOOLEAN; - function "<=" (l : NATURAL; r : ufixed) return BOOLEAN; - function ">" (l : NATURAL; r : ufixed) return BOOLEAN; - function "<" (l : NATURAL; r : ufixed) return BOOLEAN; - - ---------------------------------------------------------------------------- - -- In these compare functions a real is converted into a - -- fixed point number of the bounds "l'high+1 downto l'low" - ---------------------------------------------------------------------------- - function "=" (l : ufixed; r : REAL) return BOOLEAN; - function "/=" (l : ufixed; r : REAL) return BOOLEAN; - function ">=" (l : ufixed; r : REAL) return BOOLEAN; - function "<=" (l : ufixed; r : REAL) return BOOLEAN; - function ">" (l : ufixed; r : REAL) return BOOLEAN; - function "<" (l : ufixed; r : REAL) return BOOLEAN; - - function "=" (l : REAL; r : ufixed) return BOOLEAN; - function "/=" (l : REAL; r : ufixed) return BOOLEAN; - function ">=" (l : REAL; r : ufixed) return BOOLEAN; - function "<=" (l : REAL; r : ufixed) return BOOLEAN; - function ">" (l : REAL; r : ufixed) return BOOLEAN; - function "<" (l : REAL; r : ufixed) return BOOLEAN; - - ---------------------------------------------------------------------------- - -- In these compare functions an integer is converted into a - -- fixed point number of the bounds "max(l'high,1) downto 0" - ---------------------------------------------------------------------------- - function "=" (l : sfixed; r : INTEGER) return BOOLEAN; - function "/=" (l : sfixed; r : INTEGER) return BOOLEAN; - function ">=" (l : sfixed; r : INTEGER) return BOOLEAN; - function "<=" (l : sfixed; r : INTEGER) return BOOLEAN; - function ">" (l : sfixed; r : INTEGER) return BOOLEAN; - function "<" (l : sfixed; r : INTEGER) return BOOLEAN; - - function "=" (l : INTEGER; r : sfixed) return BOOLEAN; - function "/=" (l : INTEGER; r : sfixed) return BOOLEAN; - function ">=" (l : INTEGER; r : sfixed) return BOOLEAN; - function "<=" (l : INTEGER; r : sfixed) return BOOLEAN; - function ">" (l : INTEGER; r : sfixed) return BOOLEAN; - function "<" (l : INTEGER; r : sfixed) return BOOLEAN; - - ---------------------------------------------------------------------------- - -- In these compare functions a real is converted into a - -- fixed point number of the bounds "l'high+1 downto l'low" - ---------------------------------------------------------------------------- - function "=" (l : sfixed; r : REAL) return BOOLEAN; - function "/=" (l : sfixed; r : REAL) return BOOLEAN; - function ">=" (l : sfixed; r : REAL) return BOOLEAN; - function "<=" (l : sfixed; r : REAL) return BOOLEAN; - function ">" (l : sfixed; r : REAL) return BOOLEAN; - function "<" (l : sfixed; r : REAL) return BOOLEAN; - - function "=" (l : REAL; r : sfixed) return BOOLEAN; - function "/=" (l : REAL; r : sfixed) return BOOLEAN; - function ">=" (l : REAL; r : sfixed) return BOOLEAN; - function "<=" (l : REAL; r : sfixed) return BOOLEAN; - function ">" (l : REAL; r : sfixed) return BOOLEAN; - function "<" (l : REAL; r : sfixed) return BOOLEAN; - - --=========================================================================== - -- Shift and Rotate Functions. - -- Note that sra and sla are not the same as the BIT_VECTOR version - --=========================================================================== - function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed; - function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed; - function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed; - function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed; - function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed; - function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed; - function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed; - function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed; - function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed; - function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed; - function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed; - function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed; - function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed; - function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed; - function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed; - function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed; - - ---------------------------------------------------------------------------- - -- logical functions - ---------------------------------------------------------------------------- - function "not" (L : ufixed) return ufixed; - function "and" (L, R : ufixed) return ufixed; - function "or" (L, R : ufixed) return ufixed; - function "nand" (L, R : ufixed) return ufixed; - function "nor" (L, R : ufixed) return ufixed; - function "xor" (L, R : ufixed) return ufixed; - function "xnor" (L, R : ufixed) return ufixed; - function "not" (L : sfixed) return sfixed; - function "and" (L, R : sfixed) return sfixed; - function "or" (L, R : sfixed) return sfixed; - function "nand" (L, R : sfixed) return sfixed; - function "nor" (L, R : sfixed) return sfixed; - function "xor" (L, R : sfixed) return sfixed; - function "xnor" (L, R : sfixed) return sfixed; - - -- Vector and std_ulogic functions, same as functions in numeric_std - function "and" (L : STD_ULOGIC; R : ufixed) return ufixed; - function "and" (L : ufixed; R : STD_ULOGIC) return ufixed; - function "or" (L : STD_ULOGIC; R : ufixed) return ufixed; - function "or" (L : ufixed; R : STD_ULOGIC) return ufixed; - function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed; - function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed; - function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed; - function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed; - function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed; - function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed; - function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed; - function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed; - function "and" (L : STD_ULOGIC; R : sfixed) return sfixed; - function "and" (L : sfixed; R : STD_ULOGIC) return sfixed; - function "or" (L : STD_ULOGIC; R : sfixed) return sfixed; - function "or" (L : sfixed; R : STD_ULOGIC) return sfixed; - function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed; - function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed; - function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed; - function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed; - function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed; - function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed; - function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed; - function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed; - - -- Reduction operators, same as numeric_std functions - -- %%% remove 12 functions (old syntax) - function and_reduce(arg : ufixed) return STD_ULOGIC; - function nand_reduce(arg : ufixed) return STD_ULOGIC; - function or_reduce(arg : ufixed) return STD_ULOGIC; - function nor_reduce(arg : ufixed) return STD_ULOGIC; - function xor_reduce(arg : ufixed) return STD_ULOGIC; - function xnor_reduce(arg : ufixed) return STD_ULOGIC; - function and_reduce(arg : sfixed) return STD_ULOGIC; - function nand_reduce(arg : sfixed) return STD_ULOGIC; - function or_reduce(arg : sfixed) return STD_ULOGIC; - function nor_reduce(arg : sfixed) return STD_ULOGIC; - function xor_reduce(arg : sfixed) return STD_ULOGIC; - function xnor_reduce(arg : sfixed) return STD_ULOGIC; - -- %%% Uncomment the following 12 functions (new syntax) - -- function "and" ( arg : ufixed ) RETURN std_ulogic; - -- function "nand" ( arg : ufixed ) RETURN std_ulogic; - -- function "or" ( arg : ufixed ) RETURN std_ulogic; - -- function "nor" ( arg : ufixed ) RETURN std_ulogic; - -- function "xor" ( arg : ufixed ) RETURN std_ulogic; - -- function "xnor" ( arg : ufixed ) RETURN std_ulogic; - -- function "and" ( arg : sfixed ) RETURN std_ulogic; - -- function "nand" ( arg : sfixed ) RETURN std_ulogic; - -- function "or" ( arg : sfixed ) RETURN std_ulogic; - -- function "nor" ( arg : sfixed ) RETURN std_ulogic; - -- function "xor" ( arg : sfixed ) RETURN std_ulogic; - -- function "xnor" ( arg : sfixed ) RETURN std_ulogic; - - -- returns arg'low-1 if not found - function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER; - function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER; - - -- returns arg'high+1 if not found - function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER; - function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER; - - --=========================================================================== - -- RESIZE Functions - --=========================================================================== - -- resizes the number (larger or smaller) - -- The returned result will be ufixed (left_index downto right_index) - -- If "round_style" is true, then the result will be rounded. If the MSB - -- of the remainder is a "1" AND the LSB of the unround result is a '1' or - -- the lower bits of the remainder include a '1' then the result will be - -- increased by the smallest representable number for that type. - -- The default is "true" for round_style. - -- "overflow_style" can be "true" (saturate mode) or "false" (wrap mode). - -- In saturate mode, if the number overflows then the largest possible - -- representable number is returned. If wrap mode, then the upper bits - -- of the number are truncated. - function resize ( - arg : ufixed; -- input - constant left_index : INTEGER; -- integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow - constant round_style : BOOLEAN := fixed_round_style) -- rounding - return ufixed; - - -- "size_res" functions create the size of the output from the length - -- of the "size_res" input. The actual value of "size_res" is not used. - function resize ( - arg : ufixed; -- input - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow - constant round_style : BOOLEAN := fixed_round_style) -- rounding - return ufixed; - - -- Note that in "wrap" mode the sign bit is not replicated. Thus the - -- resize of a negative number can have a positive result in wrap mode. - function resize ( - arg : sfixed; -- input - constant left_index : INTEGER; -- integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return sfixed; - - function resize ( - arg : sfixed; -- input - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return sfixed; - - --=========================================================================== - -- Conversion Functions - --=========================================================================== - -- integer (natural) to unsigned fixed point. - -- arguments are the upper and lower bounds of the number, thus - -- ufixed (7 downto -3) <= to_ufixed (int, 7, -3); - function to_ufixed ( - arg : NATURAL; -- integer - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding - return ufixed; - - function to_ufixed ( - arg : NATURAL; -- integer - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding - return ufixed; - - -- real to unsigned fixed point - function to_ufixed ( - arg : REAL; -- real - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return ufixed; - - function to_ufixed ( - arg : REAL; -- real - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return ufixed; - - -- unsigned to unsigned fixed point - function to_ufixed ( - arg : UNSIGNED; -- unsigned - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return ufixed; - - function to_ufixed ( - arg : UNSIGNED; -- unsigned - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return ufixed; - - -- Performs a casting. ufixed (arg'range) is returned - function to_ufixed ( - arg : UNSIGNED) -- unsigned - return ufixed; - - -- unsigned fixed point to unsigned - function to_unsigned ( - arg : ufixed; -- fixed point input - constant size : NATURAL; -- length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return UNSIGNED; - - -- unsigned fixed point to unsigned - function to_unsigned ( - arg : ufixed; -- fixed point input - size_res : UNSIGNED; -- used for length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return UNSIGNED; - - -- unsigned fixed point to real - function to_real ( - arg : ufixed) -- fixed point input - return REAL; - - -- unsigned fixed point to integer - function to_integer ( - arg : ufixed; -- fixed point input - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return NATURAL; - - -- Integer to sfixed - function to_sfixed ( - arg : INTEGER; -- integer - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return sfixed; - - function to_sfixed ( - arg : INTEGER; -- integer - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return sfixed; - - -- Real to sfixed - function to_sfixed ( - arg : REAL; -- real - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return sfixed; - - function to_sfixed ( - arg : REAL; -- real - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return sfixed; - - -- signed to sfixed - function to_sfixed ( - arg : SIGNED; -- signed - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return sfixed; - - function to_sfixed ( - arg : SIGNED; -- signed - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return sfixed; - - -- signed to sfixed (output assumed to be size of signed input) - function to_sfixed ( - arg : SIGNED) -- signed - return sfixed; - - -- unsigned fixed point to signed fixed point (adds a "0" sign bit) - function add_sign ( - arg : ufixed) -- unsigned fixed point - return sfixed; - - -- signed fixed point to signed - function to_signed ( - arg : sfixed; -- fixed point input - constant size : NATURAL; -- length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return SIGNED; - - -- signed fixed point to signed - function to_signed ( - arg : sfixed; -- fixed point input - size_res : SIGNED; -- used for length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return SIGNED; - - -- signed fixed point to real - function to_real ( - arg : sfixed) -- fixed point input - return REAL; - - -- signed fixed point to integer - function to_integer ( - arg : sfixed; -- fixed point input - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return INTEGER; - - -- Because of the farily complicated sizing rules in the fixed point - -- packages these functions are provided to compute the result ranges - -- Example: - -- signal uf1 : ufixed (3 downto -3); - -- signal uf2 : ufixed (4 downto -2); - -- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto - -- ufixed_low (3, -3, '*', 4, -2)); - -- uf1multuf2 <= uf1 * uf2; - -- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod) - function ufixed_high (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER; - function ufixed_low (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER; - function sfixed_high (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER; - function sfixed_low (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER; - -- Same as above, but using the "size_res" input only for their ranges: - -- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto - -- ufixed_low (uf1, '*', uf2)); - -- uf1multuf2 <= uf1 * uf2; - function ufixed_high (size_res : ufixed; - operation : CHARACTER := 'X'; - size_res2 : ufixed) - return INTEGER; - function ufixed_low (size_res : ufixed; - operation : CHARACTER := 'X'; - size_res2 : ufixed) - return INTEGER; - function sfixed_high (size_res : sfixed; - operation : CHARACTER := 'X'; - size_res2 : sfixed) - return INTEGER; - function sfixed_low (size_res : sfixed; - operation : CHARACTER := 'X'; - size_res2 : sfixed) - return INTEGER; - - -- purpose: returns a saturated number - function saturate ( - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed; - - -- purpose: returns a saturated number - function saturate ( - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed; - - function saturate ( - size_res : ufixed) -- only the size of this is used - return ufixed; - - function saturate ( - size_res : sfixed) -- only the size of this is used - return sfixed; - - --=========================================================================== - -- Translation Functions - --=========================================================================== - -- Maps meta-logical values - function to_01 ( - s : ufixed; -- fixed point input - constant XMAP : STD_LOGIC := '0') -- Map x to - return ufixed; - - -- maps meta-logical values - function to_01 ( - s : sfixed; -- fixed point input - constant XMAP : STD_LOGIC := '0') -- Map x to - return sfixed; - - function Is_X (arg : ufixed) return BOOLEAN; - function Is_X (arg : sfixed) return BOOLEAN; - function to_X01 (arg : ufixed) return ufixed; - function to_X01 (arg : sfixed) return sfixed; - function to_X01Z (arg : ufixed) return ufixed; - function to_X01Z (arg : sfixed) return sfixed; - function to_UX01 (arg : ufixed) return ufixed; - function to_UX01 (arg : sfixed) return sfixed; - - -- straight vector conversion routines, needed for synthesis. - -- These functions are here so that a std_logic_vector can be - -- converted to and from sfixed and ufixed. Note that you can - -- not cast these vectors because of their negative index. - function to_slv ( - arg : ufixed) -- fp vector - return STD_LOGIC_VECTOR; --- alias to_StdLogicVector is to_slv [ufixed return STD_LOGIC_VECTOR]; --- alias to_Std_Logic_Vector is to_slv [ufixed return STD_LOGIC_VECTOR]; - - function to_slv ( - arg : sfixed) -- fp vector - return STD_LOGIC_VECTOR; --- alias to_StdLogicVector is to_slv [sfixed return STD_LOGIC_VECTOR]; --- alias to_Std_Logic_Vector is to_slv [sfixed return STD_LOGIC_VECTOR]; - - function to_sulv ( - arg : ufixed) -- fp vector - return STD_ULOGIC_VECTOR; --- alias to_StdULogicVector is to_sulv [ufixed return STD_ULOGIC_VECTOR]; --- alias to_Std_ULogic_Vector is to_sulv [ufixed return STD_ULOGIC_VECTOR]; - - function to_sulv ( - arg : sfixed) -- fp vector - return STD_ULOGIC_VECTOR; --- alias to_StdULogicVector is to_sulv [sfixed return STD_ULOGIC_VECTOR]; --- alias to_Std_ULogic_Vector is to_sulv [sfixed return STD_ULOGIC_VECTOR]; - - function to_ufixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed; - - function to_ufixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - size_res : ufixed) -- for size only - return ufixed; - - function to_sfixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed; - - function to_sfixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - size_res : sfixed) -- for size only - return sfixed; - - function to_ufixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed; - - function to_ufixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - size_res : ufixed) -- for size only - return ufixed; - - function to_sfixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed; - - function to_sfixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - size_res : sfixed) -- for size only - return sfixed; - - -- As a concession to those who use a graphical DSP environment, - -- these functions take parameters in those tools format and create - -- fixed point numbers. These functions are designed to convert from - -- a std_logic_vector to the VHDL fixed point format using the conventions - -- of these packages. In a pure VHDL environment you should use the - -- "to_ufixed" and "to_sfixed" routines. - -- Unsigned fixed point - function to_UFix ( - arg : STD_LOGIC_VECTOR; - width : NATURAL; -- width of vector - fraction : NATURAL) -- width of fraction - return ufixed; - -- signed fixed point - function to_SFix ( - arg : STD_LOGIC_VECTOR; - width : NATURAL; -- width of vector - fraction : NATURAL) -- width of fraction - return sfixed; - -- finding the bounds of a number. These functions can be used like this: - -- signal xxx : ufixed (7 downto -3); - -- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))" - -- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3) - -- downto UFix_low(11, 3, "+", 11, 3)); - -- Where "11" is the width of xxx (xxx'length), - -- and 3 is the lower bound (abs (xxx'low)) - -- In a pure VHDL environment use "ufixed_high" and "ufixed_low" - function UFix_high (width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER; - function UFix_low (width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER; - -- Same as above but for signed fixed point. Note that the width - -- of a signed fixed point number ignores the sign bit, thus - -- width = sxxx'length-1 - function SFix_high (width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER; - function SFix_low (width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER; - --=========================================================================== - -- string and textio Functions - --=========================================================================== --- rtl_synthesis off --- synthesis translate_off - -- purpose: writes fixed point into a line - procedure WRITE ( - L : inout LINE; -- input line - VALUE : in ufixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0); - - -- purpose: writes fixed point into a line - procedure WRITE ( - L : inout LINE; -- input line - VALUE : in sfixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0); - - procedure READ(L : inout LINE; - VALUE : out ufixed); - - procedure READ(L : inout LINE; - VALUE : out ufixed; - GOOD : out BOOLEAN); - - procedure READ(L : inout LINE; - VALUE : out sfixed); - - procedure READ(L : inout LINE; - VALUE : out sfixed; - GOOD : out BOOLEAN); - - alias bwrite is WRITE [LINE, ufixed, SIDE, width]; - alias bwrite is WRITE [LINE, sfixed, SIDE, width]; - alias bread is READ [LINE, ufixed]; - alias bread is READ [LINE, ufixed, BOOLEAN]; - alias bread is READ [LINE, sfixed]; - alias bread is READ [LINE, sfixed, BOOLEAN]; - - -- octal read and write - procedure OWRITE ( - L : inout LINE; -- input line - VALUE : in ufixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0); - - procedure OWRITE ( - L : inout LINE; -- input line - VALUE : in sfixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0); - - procedure OREAD(L : inout LINE; - VALUE : out ufixed); - - procedure OREAD(L : inout LINE; - VALUE : out ufixed; - GOOD : out BOOLEAN); - - procedure OREAD(L : inout LINE; - VALUE : out sfixed); - - procedure OREAD(L : inout LINE; - VALUE : out sfixed; - GOOD : out BOOLEAN); - - -- hex read and write - procedure HWRITE ( - L : inout LINE; -- input line - VALUE : in ufixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0); - - -- purpose: writes fixed point into a line - procedure HWRITE ( - L : inout LINE; -- input line - VALUE : in sfixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0); - - procedure HREAD(L : inout LINE; - VALUE : out ufixed); - - procedure HREAD(L : inout LINE; - VALUE : out ufixed; - GOOD : out BOOLEAN); - - procedure HREAD(L : inout LINE; - VALUE : out sfixed); - - procedure HREAD(L : inout LINE; - VALUE : out sfixed; - GOOD : out BOOLEAN); - - -- returns a string, useful for: - -- assert (x = y) report "error found " & to_string(x) severity error; - function to_string ( - value : ufixed; - justified : SIDE := right; - field : WIDTH := 0 - ) return STRING; - - alias to_bstring is to_string [ufixed, SIDE, width return STRING]; - - function to_ostring ( - value : ufixed; - justified : SIDE := right; - field : WIDTH := 0 - ) return STRING; - - function to_hstring ( - value : ufixed; - justified : SIDE := right; - field : WIDTH := 0 - ) return STRING; - - function to_string ( - value : sfixed; - justified : SIDE := right; - field : WIDTH := 0 - ) return STRING; - - alias to_bstring is to_string [sfixed, SIDE, width return STRING]; - - function to_ostring ( - value : sfixed; - justified : SIDE := right; - field : WIDTH := 0 - ) return STRING; - - function to_hstring ( - value : sfixed; - justified : SIDE := right; - field : WIDTH := 0 - ) return STRING; - - -- From string functions allow you to convert a string into a fixed - -- point number. Example: - -- signal uf1 : ufixed (3 downto -3); - -- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5 - -- The "." is optional in this syntax, however it exist and is - -- in the wrong location an error is produced. Overflow will - -- result in saturation. - function from_string ( - bstring : STRING; -- binary string - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed; - alias from_bstring is from_string [STRING, INTEGER, INTEGER return ufixed]; - - -- Octal and hex conversions work as follows: - -- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped) - -- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped) - function from_ostring ( - ostring : STRING; -- Octal string - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed; - - function from_hstring ( - hstring : STRING; -- hex string - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed; - - function from_string ( - bstring : STRING; -- binary string - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed; - alias from_bstring is from_string [STRING, INTEGER, INTEGER return sfixed]; - - function from_ostring ( - ostring : STRING; -- Octal string - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed; - - function from_hstring ( - hstring : STRING; -- hex string - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed; - - -- Same as above, "size_res" is used for it's range only. - function from_string ( - bstring : STRING; -- binary string - size_res : ufixed) - return ufixed; - alias from_bstring is from_string [STRING, ufixed return ufixed]; - - function from_ostring ( - ostring : STRING; -- Octal string - size_res : ufixed) - return ufixed; - - function from_hstring ( - hstring : STRING; -- hex string - size_res : ufixed) - return ufixed; - - function from_string ( - bstring : STRING; -- binary string - size_res : sfixed) - return sfixed; - alias from_bstring is from_string [STRING, sfixed return sfixed]; - - function from_ostring ( - ostring : STRING; -- Octal string - size_res : sfixed) - return sfixed; - - function from_hstring ( - hstring : STRING; -- hex string - size_res : sfixed) - return sfixed; - - -- Direct converstion functions. Example: - -- signal uf1 : ufixed (3 downto -3); - -- uf1 <= from_string ("0110.100"); -- 6.5 - -- In this case the "." is not optional, and the size of - -- the output must match exactly. - function from_string ( - bstring : STRING) -- binary string - return ufixed; - alias from_bstring is from_string [STRING return ufixed]; - - -- Direct octal and hex converstion functions. In this case - -- the string lengths must match. Example: - -- signal sf1 := sfixed (5 downto -3); - -- sf1 <= from_ostring ("71.4") -- -6.5 - function from_ostring ( - ostring : STRING) -- Octal string - return ufixed; - - function from_hstring ( - hstring : STRING) -- hex string - return ufixed; - - function from_string ( - bstring : STRING) -- binary string - return sfixed; - alias from_bstring is from_string [STRING return sfixed]; - - function from_ostring ( - ostring : STRING) -- Octal string - return sfixed; - - function from_hstring ( - hstring : STRING) -- hex string - return sfixed; - --- synthesis translate_on --- rtl_synthesis on - -- This type is here for the floating point package. - type round_type is (round_nearest, -- Default, nearest LSB '0' - round_inf, -- Round to positive - round_neginf, -- Round to negate - round_zero); -- Round towards zero - -- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD, - -- and FE_TOWARDZERO floating point rounding macros. - function to_StdLogicVector ( - arg : ufixed) -- fp vector - return STD_LOGIC_VECTOR; - function to_Std_Logic_Vector ( - arg : ufixed) -- fp vector - return STD_LOGIC_VECTOR; - function to_StdLogicVector ( - arg : sfixed) -- fp vector - return STD_LOGIC_VECTOR; - function to_Std_Logic_Vector ( - arg : sfixed) -- fp vector - return STD_LOGIC_VECTOR; -end package fixed_pkg; -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use ieee.math_real.all; -use std.textio.all; -use ieee.std_logic_textio.all; -- %%% for testing only -package body fixed_pkg is - -- Author David Bishop (dbishop@vhdl.org) - -- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton - -- null array constants - constant NAUF : ufixed (0 downto 1) := (others => '0'); - constant NASF : sfixed (0 downto 1) := (others => '0'); - constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0'); - - -- This differed constant will tell you if the package body is synthesizable - -- or implemented as real numbers, set to "true" if synthesizable. --- constant fixedsynth_or_real : BOOLEAN := true; - - --%%% Can be removed in vhdl-200x, will be implicit. - -- purpose: To find the largest of 2 numbers - function maximum (l, r : INTEGER) - return INTEGER is - begin -- function maximum - if L > R then return L; - else return R; - end if; - end function maximum; - - function minimum (l, r : INTEGER) - return INTEGER is - begin -- function minimum - if L > R then return R; - else return L; - end if; - end function minimum; - - -- %%% Remove the following function (duplicates of new numeric_std) - function "sra" (arg : SIGNED; count : INTEGER) - return SIGNED is - begin - if (COUNT >= 0) then - return SHIFT_RIGHT(arg, count); - else - return SHIFT_LEFT(arg, -count); - end if; - end function "sra"; - - -- %%% Replace or_reducex with "or", and_reducex with "and", and - -- %%% xor_reducex with "xor", then remove the following 3 functions - -- purpose: OR all of the bits in a vector together - -- This is a copy of the proposed "or_reduce" from 1076.3 - function or_reducex (arg : STD_LOGIC_VECTOR) - return STD_LOGIC is - variable Upper, Lower : STD_LOGIC; - variable Half : INTEGER; - variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0); - variable Result : STD_LOGIC; - begin - if (arg'length < 1) then -- In the case of a NULL range - Result := '0'; - else - BUS_int := to_ux01 (arg); - if (BUS_int'length = 1) then - Result := BUS_int (BUS_int'left); - elsif (BUS_int'length = 2) then - Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left); - else - Half := (BUS_int'length + 1) / 2 + BUS_int'right; - Upper := or_reducex (BUS_int (BUS_int'left downto Half)); - Lower := or_reducex (BUS_int (Half - 1 downto BUS_int'right)); - Result := Upper or Lower; - end if; - end if; - return Result; - end function or_reducex; - - -- purpose: AND all of the bits in a vector together - -- This is a copy of the proposed "and_reduce" from 1076.3 - function and_reducex (arg : STD_LOGIC_VECTOR) - return STD_LOGIC is - variable Upper, Lower : STD_LOGIC; - variable Half : INTEGER; - variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0); - variable Result : STD_LOGIC; - begin - if (arg'length < 1) then -- In the case of a NULL range - Result := '1'; - else - BUS_int := to_ux01 (arg); - if (BUS_int'length = 1) then - Result := BUS_int (BUS_int'left); - elsif (BUS_int'length = 2) then - Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left); - else - Half := (BUS_int'length + 1) / 2 + BUS_int'right; - Upper := and_reducex (BUS_int (BUS_int'left downto Half)); - Lower := and_reducex (BUS_int (Half - 1 downto BUS_int'right)); - Result := Upper and Lower; - end if; - end if; - return Result; - end function and_reducex; - - function xor_reducex (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is - variable Upper, Lower : STD_ULOGIC; - variable Half : INTEGER; - variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0); - variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range - begin - if (arg'length >= 1) then - BUS_int := to_ux01 (arg); - if (BUS_int'length = 1) then - Result := BUS_int (BUS_int'left); - elsif (BUS_int'length = 2) then - Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left); - else - Half := (BUS_int'length + 1) / 2 + BUS_int'right; - Upper := xor_reducex (BUS_int (BUS_int'left downto Half)); - Lower := xor_reducex (BUS_int (Half - 1 downto BUS_int'right)); - Result := Upper xor Lower; - end if; - end if; - return Result; - end function xor_reducex; - - --%%% remove the following function and table - -- Match table, copied form new std_logic_1164 - type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC; - constant match_logic_table : stdlogic_table := ( - ----------------------------------------------------- - -- U X 0 1 Z W L H - | | - ----------------------------------------------------- - ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U | - ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X | - ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 | - ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 | - ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z | - ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W | - ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L | - ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H | - ('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - | - ); - - constant no_match_logic_table : stdlogic_table := ( - ----------------------------------------------------- - -- U X 0 1 Z W L H - | | - ----------------------------------------------------- - ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U | - ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X | - ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 | - ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 | - ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z | - ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W | - ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L | - ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H | - ('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - | - ); - - ------------------------------------------------------------------- - -- ?= functions, Similar to "std_match", but returns "std_ulogic". - ------------------------------------------------------------------- - -- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS - function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is - begin - return match_logic_table (l, r); - end function \?=\; - -- %%% END FUNCTION "?="; - -- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is - function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is - begin - return no_match_logic_table (l, r); - end function \?/=\; - -- %%% END FUNCTION "?/="; - -- %%% end remove - - -- Special version of "minimum" to do some boundary checking without errors - function mins (l, r : INTEGER) - return INTEGER is - begin -- function mins - if (L = INTEGER'low or R = INTEGER'low) then - return 0; -- error condition - end if; - return minimum (L, R); - end function mins; - - -- Special version of "minimum" to do some boundary checking with errors - function mine (l, r : INTEGER) - return INTEGER is - begin -- function mine - if (L = INTEGER'low or R = INTEGER'low) then - report "FIXED_GENERIC_PKG: Unbounded number passed, was a literal used?" - severity error; - return 0; - end if; - return minimum (L, R); - end function mine; - - -- The following functions are used only internally. Every function - -- calls "cleanvec" either directly or indirectly. - -- purpose: Fixes "downto" problem and resolves meta states - function cleanvec ( - arg : sfixed) -- input - return sfixed is - constant left_index : INTEGER := maximum(arg'left, arg'right); - constant right_index : INTEGER := mins(arg'left, arg'right); - variable result : sfixed (arg'range); - begin -- function cleanvec - assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low)) - report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto""" - severity error; - return arg; - end function cleanvec; - - -- purpose: Fixes "downto" problem and resolves meta states - function cleanvec ( - arg : ufixed) -- input - return ufixed is - constant left_index : INTEGER := maximum(arg'left, arg'right); - constant right_index : INTEGER := mins(arg'left, arg'right); - variable result : ufixed (arg'range); - begin -- function cleanvec - assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low)) - report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto""" - severity error; - return arg; - end function cleanvec; - - -- Type cast a "unsigned" into a "ufixed", used internally - function to_fixed ( - arg : UNSIGNED; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed is - variable result : ufixed (left_index downto right_index); --- variable j : INTEGER := arg'high; -- index for arg - begin -- function to_fixed - result := ufixed(arg); --- floop : for i in result'range loop --- result(i) := arg(j); -- res(4) := arg (4 + 3) --- j := j - 1; --- end loop floop; - return result; - end function to_fixed; - - -- Type cast a "signed" into an "sfixed", used internally - function to_fixed ( - arg : SIGNED; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed is - variable result : sfixed (left_index downto right_index); --- variable j : INTEGER := arg'high; -- index for arg - begin -- function to_fixed - result := sfixed(arg); --- floop : for i in result'range loop --- result(i) := arg(j); -- res(4) := arg (4 + 3) --- j := j - 1; --- end loop floop; - return result; - end function to_fixed; - - -- Type cast a "ufixed" into an "unsigned", used internally - function to_uns ( - arg : ufixed) -- fp vector - return UNSIGNED is - subtype t is UNSIGNED(arg'high - arg'low downto 0); - variable slv : t; - begin -- function to_uns - slv := t(arg); --- floop : for i in slv'range loop --- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3) --- end loop floop; - return UNSIGNED(to_X01(std_logic_vector(slv))); - end function to_uns; - - -- Type cast an "sfixed" into a "signed", used internally - function to_s ( - arg : sfixed) -- fp vector - return SIGNED is - subtype t is SIGNED(arg'high - arg'low downto 0); - variable slv : t; - begin -- function to_s - slv := t(arg); --- floop : for i in slv'range loop --- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3) --- end loop floop; - return SIGNED(to_X01(std_logic_vector(slv))); - end function to_s; - - -- adds 1 to the LSB of the number - procedure round_up (arg : in ufixed; - result : out ufixed; - overflowx : out BOOLEAN) is - variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0) := - (others => '0'); - begin -- round_up - arguns (arguns'high-1 downto 0) := to_uns (arg); - resuns := arguns + 1; - result := to_fixed(resuns(arg'high-arg'low - downto 0), arg'high, arg'low); - overflowx := (resuns(resuns'high) = '1'); - end procedure round_up; - - -- adds 1 to the LSB of the number - procedure round_up (arg : in sfixed; - result : out sfixed; - overflowx : out BOOLEAN) is - variable args, ress : SIGNED (arg'high-arg'low+1 downto 0); - begin -- round_up - args (args'high-1 downto 0) := to_s (arg); - args(args'high) := arg(arg'high); -- sign extend - ress := args + 1; - result := to_fixed(ress (ress'high-1 - downto 0), arg'high, arg'low); - overflowx := ((arg(arg'high) /= ress(ress'high-1)) - and (or_reducex (STD_LOGIC_VECTOR(ress)) /= '0')); - end procedure round_up; - - -- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up - -- when the remainder is > 0.5. If the remainder IS 0.5 then if the - -- bottom bit is a "1" it is rounded, otherwise it remains the same. - function round_fixed (arg : ufixed; - remainder : ufixed; - overflow_style : BOOLEAN := fixed_overflow_style) - return ufixed is - variable rounds : BOOLEAN; - variable round_overflow : BOOLEAN; - variable result : ufixed (arg'range); - begin - rounds := false; - if (remainder'length > 1) then - if (remainder (remainder'high) = '1') then - rounds := (arg(arg'low) = '1') - or (or_reducex (to_slv(remainder(remainder'high-1 downto - remainder'low))) = '1'); - end if; - else - rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1'); - end if; - if rounds then - round_up(arg => arg, - result => result, - overflowx => round_overflow); - else - result := arg; - end if; - if (overflow_style = fixed_saturate) and round_overflow then - result := saturate (result'high, result'low); - end if; - return result; - end function round_fixed; - - -- Rounding case statement - function round_fixed (arg : sfixed; - remainder : sfixed; - overflow_style : BOOLEAN := fixed_overflow_style) - return sfixed is - variable rounds : BOOLEAN; - variable round_overflow : BOOLEAN; - variable result : sfixed (arg'range); - begin - rounds := false; - if (remainder'length > 1) then - if (remainder (remainder'high) = '1') then - rounds := (arg(arg'low) = '1') - or (or_reducex (to_slv(remainder(remainder'high-1 downto - remainder'low))) = '1'); - end if; - else - rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1'); - end if; - if rounds then - round_up(arg => arg, - result => result, - overflowx => round_overflow); - else - result := arg; - end if; - if round_overflow then - if (overflow_style = fixed_saturate) then - if arg(arg'high) = '0' then - result := saturate (result'high, result'low); - else - result := not saturate (result'high, result'low); - end if; --- else --- result(result'high) := arg(arg'high); -- fix sign bit in wrap - end if; - end if; - return result; - end function round_fixed; - ------------------------------------------------------------------------------ --- Visible functions ------------------------------------------------------------------------------ - - -- casting functions. These are needed for synthesis where typically - -- the only input and output type is a std_logic_vector. - function to_slv ( - arg : ufixed) -- fixed point vector - return STD_LOGIC_VECTOR is - subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0); - variable slv : t; - begin - if arg'length < 1 then - return NSLV; - end if; - slv := t (arg); - return slv; - end function to_slv; - - function to_slv ( - arg : sfixed) -- fixed point vector - return STD_LOGIC_VECTOR is - subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0); - variable slv : t; - begin - if arg'length < 1 then - return NSLV; - end if; - slv := t (arg); - return slv; - end function to_slv; - - function to_sulv ( - arg : ufixed) -- fixed point vector - return STD_ULOGIC_VECTOR is - begin - return to_stdulogicvector (to_slv(arg)); - end function to_sulv; - - function to_sulv ( - arg : sfixed) -- fixed point vector - return STD_ULOGIC_VECTOR is - begin - return to_stdulogicvector (to_slv(arg)); - end function to_sulv; - - function to_ufixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed is - variable result : ufixed (left_index downto right_index); - begin - if (arg'length < 1 or right_index > left_index) then - return NAUF; - end if; - if (arg'length /= result'length) then - report "FIXED_GENERIC_PKG.TO_UFIXED (STD_LOGIC_VECTOR) " - & "Vector lengths do not match. Input length is " - & INTEGER'image(arg'length) & " and output will be " - & INTEGER'image(result'length) & " wide." - severity error; - return NAUF; - else - result := to_fixed (arg => UNSIGNED(arg), - left_index => left_index, - right_index => right_index); - return result; - end if; - end function to_ufixed; - - function to_sfixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed is - variable result : sfixed (left_index downto right_index); - begin - if (arg'length < 1 or right_index > left_index) then - return NASF; - end if; - if (arg'length /= result'length) then - report "FIXED_GENERIC_PKG.TO_SFIXED (STD_LOGIC_VECTOR) " - & "Vector lengths do not match. Input length is " - & INTEGER'image(arg'length) & " and output will be " - & INTEGER'image(result'length) & " wide." - severity error; - return NASF; - else - result := to_fixed (arg => SIGNED(arg), - left_index => left_index, - right_index => right_index); - return result; - end if; - end function to_sfixed; - - function to_ufixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed is - begin - return to_ufixed (arg => to_stdlogicvector(arg), - left_index => left_index, - right_index => right_index); - end function to_ufixed; - - function to_sfixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed is - begin - return to_sfixed (arg => to_stdlogicvector(arg), - left_index => left_index, - right_index => right_index); - end function to_sfixed; - - -- Two's complement number, Grows the vector by 1 bit. - -- because "abs (1000.000) = 01000.000" or abs(-16) = 16. - function "abs" ( - arg : sfixed) -- fixed point input - return sfixed is - constant left_index : INTEGER := arg'high; - constant right_index : INTEGER := mine(arg'low, arg'low); - variable ressns : SIGNED (arg'length downto 0); - variable result : sfixed (left_index+1 downto right_index); - begin - if (arg'length < 1 or result'length < 1) then - return NASF; - end if; - ressns (arg'length-1 downto 0) := to_s (cleanvec (arg)); - ressns (arg'length) := ressns (arg'length-1); -- expand sign bit - result := to_fixed (abs(ressns), left_index+1, right_index); - return result; - end function "abs"; - - -- also grows the vector by 1 bit. - function "-" ( - arg : sfixed) -- fixed point input - return sfixed is - constant left_index : INTEGER := arg'high+1; - constant right_index : INTEGER := mine(arg'low, arg'low); - variable ressns : SIGNED (arg'length downto 0); - variable result : sfixed (left_index downto right_index); - begin - if (arg'length < 1 or result'length < 1) then - return NASF; - end if; - ressns (arg'length-1 downto 0) := to_s (cleanvec(arg)); - ressns (arg'length) := ressns (arg'length-1); -- expand sign bit - result := to_fixed (-ressns, left_index, right_index); - return result; - end function "-"; - - function "abs" (arg : sfixed) return ufixed is - constant left_index : INTEGER := arg'high; - constant right_index : INTEGER := mine(arg'low, arg'low); - variable xarg : sfixed(left_index+1 downto right_index); - variable result : ufixed(left_index downto right_index); - begin - if arg'length < 1 then - return NAUF; - end if; - xarg := abs(arg); - result := ufixed (xarg (left_index downto right_index)); - return result; - end function "abs"; - - -- Addition - function "+" ( - l, r : ufixed) -- ufixed(a downto b) + ufixed(c downto d) = - return ufixed is -- ufixed(max(a,c)+1 downto min(b,d)) - constant left_index : INTEGER := maximum(l'high, r'high)+1; - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable result : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (left_index-right_index - downto 0); - variable result_slv : UNSIGNED (left_index-right_index - downto 0); - begin - if (l'length < 1 or r'length < 1) then - return NAUF; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - result_slv := lslv + rslv; - result := to_fixed(result_slv, left_index, right_index); - return result; - end function "+"; - - function "+" ( - l, r : sfixed) -- sfixed(a downto b) + sfixed(c downto d) = - return sfixed is -- sfixed(max(a,c)+1 downto min(b,d)) - constant left_index : INTEGER := maximum(l'high, r'high)+1; - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable result : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (left_index-right_index downto 0); - variable result_slv : SIGNED (left_index-right_index downto 0); - begin - if (l'length < 1 or r'length < 1) then - return NASF; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - result_slv := lslv + rslv; - result := to_fixed(result_slv, left_index, right_index); - return result; - end function "+"; - - -- Subtraction - function "-" ( - l, r : ufixed) -- ufixed(a downto b) - ufixed(c downto d) = - return ufixed is -- ufixed(max(a,c)+1 downto min(b,d)) - constant left_index : INTEGER := maximum(l'high, r'high)+1; - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable result : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (left_index-right_index - downto 0); - variable result_slv : UNSIGNED (left_index-right_index - downto 0); - begin - if (l'length < 1 or r'length < 1) then - return NAUF; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - result_slv := lslv - rslv; - result := to_fixed(result_slv, left_index, right_index); - return result; - end function "-"; - - function "-" ( - l, r : sfixed) -- sfixed(a downto b) - sfixed(c downto d) = - return sfixed is -- sfixed(max(a,c)+1 downto min(b,d)) - constant left_index : INTEGER := maximum(l'high, r'high)+1; - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable result : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (left_index-right_index downto 0); - variable result_slv : SIGNED (left_index-right_index downto 0); - begin - if (l'length < 1 or r'length < 1) then - return NASF; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - result_slv := lslv - rslv; - result := to_fixed(result_slv, left_index, right_index); - return result; - end function "-"; - - function "*" ( - l, r : ufixed) -- ufixed(a downto b) * ufixed(c downto d) = - return ufixed is -- ufixed(a+c+1 downto b+d) - variable lslv : UNSIGNED (l'length-1 downto 0); - variable rslv : UNSIGNED (r'length-1 downto 0); - variable result_slv : UNSIGNED (r'length+l'length-1 downto 0); - variable result : ufixed (l'high + r'high+1 downto - mine(l'low, l'low) + mine(r'low, r'low)); - begin - if (l'length < 1 or r'length < 1 or - result'length /= result_slv'length) then - return NAUF; - end if; - lslv := to_uns (cleanvec(l)); - rslv := to_uns (cleanvec(r)); - result_slv := lslv * rslv; - result := to_fixed (result_slv, result'high, result'low); - return result; - end function "*"; - - function "*" ( - l, r : sfixed) -- sfixed(a downto b) * sfixed(c downto d) = - return sfixed is -- sfixed(a+c+1 downto b+d) - variable lslv : SIGNED (l'length-1 downto 0); - variable rslv : SIGNED (r'length-1 downto 0); - variable result_slv : SIGNED (r'length+l'length-1 downto 0); - variable result : sfixed (l'high + r'high+1 downto - mine(l'low, l'low) + mine(r'low, r'low)); - begin - if (l'length < 1 or r'length < 1 or - result'length /= result_slv'length) then - return NASF; - end if; - lslv := to_s (cleanvec(l)); - rslv := to_s (cleanvec(r)); - result_slv := lslv * rslv; - result := to_fixed (result_slv, result'high, result'low); - return result; - end function "*"; - - function "/" ( - l, r : ufixed) -- ufixed(a downto b) / ufixed(c downto d) = - return ufixed is -- ufixed(a-d downto b-c-1) - begin - return divide (l, r); - end function "/"; - - function "/" ( - l, r : sfixed) -- sfixed(a downto b) / sfixed(c downto d) = - return sfixed is -- sfixed(a-d+1 downto b-c) - begin - return divide (l, r); - end function "/"; - - -- This version of divide gives the user more control - -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1) - function divide ( - l, r : ufixed; - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return ufixed is - variable result : ufixed (l'high - mine(r'low, r'low) - downto mine (l'low, l'low) - r'high -1); - variable dresult : ufixed (result'high downto result'low -guard_bits); - variable lresize : ufixed (l'high downto l'high - dresult'length+1); - variable lslv : UNSIGNED (lresize'length-1 downto 0); - variable rslv : UNSIGNED (r'length-1 downto 0); - variable result_slv : UNSIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1 or - mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then - return NAUF; - end if; - lresize := resize (l, lresize'high, lresize'low); - lslv := to_uns (cleanvec (lresize)); - rslv := to_uns (cleanvec (r)); - if (rslv = 0) then - report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error; - result := saturate (result'high, result'low); -- saturate - else - result_slv := lslv / rslv; - dresult := to_fixed (result_slv, dresult'high, dresult'low); - result := resize (arg => dresult, - left_index => result'high, - right_index => result'low, - round_style => round_style, - overflow_style => fixed_wrap); -- overflow impossible - end if; - return result; - end function divide; - - -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c) - function divide ( - l, r : sfixed; - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return sfixed is - variable result : sfixed (l'high - mine(r'low, r'low)+1 - downto mine (l'low, l'low) - r'high); - variable dresult : sfixed (result'high downto result'low-guard_bits); - variable lresize : sfixed (l'high+1 downto l'high+1 -dresult'length+1); - variable lslv : SIGNED (lresize'length-1 downto 0); - variable rslv : SIGNED (r'length-1 downto 0); - variable result_slv : SIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1 or - mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then - return NASF; - end if; - lresize := resize (l, lresize'high, lresize'low); - lslv := to_s (cleanvec (lresize)); - rslv := to_s (cleanvec (r)); - if (rslv = 0) then - report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error; - result := saturate (result'high, result'low); - else - result_slv := lslv / rslv; - dresult := to_fixed (result_slv, dresult'high, dresult'low); - result := resize (arg => dresult, - left_index => result'high, - right_index => result'low, - round_style => round_style, - overflow_style => fixed_wrap); -- overflow impossible - end if; - return result; - end function divide; - - -- 1 / ufixed(a downto b) = ufixed(-b downto -a-1) - function reciprocal ( - arg : ufixed; -- fixed point input - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return ufixed is - constant one : ufixed (0 downto 0) := "1"; - begin - return divide(l => one, - r => arg, - round_style => round_style, - guard_bits => guard_bits); - end function reciprocal; - - -- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a) - function reciprocal ( - arg : sfixed; -- fixed point input - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return sfixed is - constant one : sfixed (1 downto 0) := "01"; -- extra bit. - variable resultx : sfixed (-mine(arg'low, arg'low)+2 downto -arg'high); - begin - if (arg'length < 1 or resultx'length < 1) then - return NASF; - else - resultx := divide(l => one, - r => arg, - round_style => round_style, - guard_bits => guard_bits); - return resultx (resultx'high-1 downto resultx'low); -- remove extra bit - end if; - end function reciprocal; - - -- ufixed (a downto b) rem ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b,d)) - function "rem" ( - l, r : ufixed) -- fixed point input - return ufixed is - begin - return remainder (l => l, - r => r, - round_style => fixed_round_style); - end function "rem"; - - -- remainder - -- sfixed (a downto b) rem sfixed (c downto d) - -- = sfixed (min(a,c) downto min(b,d)) - function "rem" ( - l, r : sfixed) -- fixed point input - return sfixed is - begin - return remainder (l => l, - r => r, - round_style => fixed_round_style); - end function "rem"; - - -- ufixed (a downto b) rem ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b,d)) - function remainder ( - l, r : ufixed; -- fixed point input - constant round_style : BOOLEAN := fixed_round_style) - return ufixed is - variable result : ufixed (minimum(l'high, r'high) downto mine(l'low, r'low)); - variable dresult : ufixed (r'high downto r'low); - variable lresize : ufixed (maximum(l'high, r'low) downto mins(r'low, r'low)); - variable lslv : UNSIGNED (lresize'length-1 downto 0); - variable rslv : UNSIGNED (r'length-1 downto 0); - variable result_slv : UNSIGNED (rslv'range); - begin - if (l'length < 1 or r'length < 1 or - mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then - return NAUF; - end if; - lresize := resize (arg => l, - left_index => lresize'high, - right_index => lresize'low, - overflow_style => fixed_wrap, -- vector only grows - round_style => fixed_truncate); - lslv := to_uns (lresize); - rslv := to_uns (cleanvec(r)); - if (rslv = 0) then - report "FIXED_GENERIC_PKG.rem uFixed point Division by zero" severity error; - result := saturate (result'high, result'low); -- saturate - else - if (r'low <= l'high) then - result_slv := lslv rem rslv; - dresult := to_fixed (result_slv, dresult'high, dresult'low); - result := resize (arg => dresult, - left_index => result'high, - right_index => result'low, - overflow_style => fixed_wrap, - round_style => round_style); --- result(result'high downto r'low) := dresult(result'high downto r'low); - end if; - if l'low < r'low then - result(mins(r'low-1, l'high) downto l'low) := - cleanvec(l(mins(r'low-1, l'high) downto l'low)); - end if; - end if; - return result; - end function remainder; - - -- remainder - -- sfixed (a downto b) rem sfixed (c downto d) - -- = sfixed (min(a,c) downto min(b,d)) - function remainder ( - l, r : sfixed; -- fixed point input - constant round_style : BOOLEAN := fixed_round_style) - return sfixed is - variable l_abs : ufixed (l'range); - variable r_abs : ufixed (r'range); - variable result : sfixed (minimum(r'high, l'high) downto mine(r'low, l'low)); - variable neg_result : sfixed (minimum(r'high, l'high)+1 downto mins(r'low, l'low)); - begin - if (l'length < 1 or r'length < 1 or - mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then - return NASF; - end if; - l_abs := abs(l); - r_abs := abs(r); - result := sfixed(remainder (l => l_abs, - r => r_abs, - round_style => round_style)); - neg_result := -result; - if l(l'high) = '1' then - result := neg_result(result'range); - end if; - return result; - end function remainder; - - -- modulo - -- ufixed (a downto b) mod ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b, d)) - function "mod" ( - l, r : ufixed) -- fixed point input - return ufixed is - begin - return modulo (l => l, - r => r, - round_style => fixed_round_style); - end function "mod"; - - -- sfixed (a downto b) mod sfixed (c downto d) - -- = sfixed (c downto min(b, d)) - function "mod" ( - l, r : sfixed) -- fixed point input - return sfixed is - begin - return modulo(l => l, - r => r, - round_style => fixed_round_style); - end function "mod"; - - -- modulo - -- ufixed (a downto b) mod ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b, d)) - function modulo ( - l, r : ufixed; -- fixed point input - constant round_style : BOOLEAN := fixed_round_style) - return ufixed is - begin - return remainder(l => l, - r => r, - round_style => round_style); - end function modulo; - - -- sfixed (a downto b) mod sfixed (c downto d) - -- = sfixed (c downto min(b, d)) - function modulo ( - l, r : sfixed; -- fixed point input - constant overflow_style : BOOLEAN := fixed_overflow_style; - constant round_style : BOOLEAN := fixed_round_style) - return sfixed is - variable l_abs : ufixed (l'range); - variable r_abs : ufixed (r'range); - variable result : sfixed (r'high downto - mine(r'low, l'low)); - variable dresult : sfixed (minimum(r'high, l'high)+1 downto - mins(r'low, l'low)); - variable dresult_not_zero : BOOLEAN; - begin - if (l'length < 1 or r'length < 1 or - mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then - return NASF; - end if; - l_abs := abs(l); - r_abs := abs(r); - dresult := "0" & sfixed(remainder (l => l_abs, - r => r_abs, - round_style => round_style)); - if (to_s(dresult) = 0) then - dresult_not_zero := false; - else - dresult_not_zero := true; - end if; - if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0' - and dresult_not_zero then - result := resize (arg => r - dresult, - left_index => result'high, - right_index => result'low, - overflow_style => overflow_style, - round_style => round_style); - elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then - result := resize (arg => -dresult, - left_index => result'high, - right_index => result'low, - overflow_style => overflow_style, - round_style => round_style); - elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1' - and dresult_not_zero then - result := resize (arg => dresult + r, - left_index => result'high, - right_index => result'low, - overflow_style => overflow_style, - round_style => round_style); - else - result := resize (arg => dresult, - left_index => result'high, - right_index => result'low, - overflow_style => overflow_style, - round_style => round_style); - end if; - return result; - end function modulo; - - -- Procedure for those who need an "accumulator" function - procedure add_carry ( - L, R : in ufixed; - c_in : in STD_ULOGIC; - result : out ufixed; - c_out : out STD_ULOGIC) is - constant left_index : INTEGER := maximum(l'high, r'high)+1; - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (left_index-right_index - downto 0); - variable result_slv : UNSIGNED (left_index-right_index - downto 0); - variable cx : UNSIGNED (0 downto 0); -- Carry in - begin - if (l'length < 1 or r'length < 1) then - result := NAUF; - c_out := '0'; - else - cx (0) := c_in; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - result_slv := lslv + rslv + cx; - c_out := result_slv(left_index); - result := to_fixed(result_slv (left_index-right_index-1 downto 0), - left_index-1, right_index); - end if; - end procedure add_carry; - - procedure add_carry ( - L, R : in sfixed; - c_in : in STD_ULOGIC; - result : out sfixed; - c_out : out STD_ULOGIC) is - constant left_index : INTEGER := maximum(l'high, r'high)+1; - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (left_index-right_index - downto 0); - variable result_slv : SIGNED (left_index-right_index - downto 0); - variable cx : SIGNED (1 downto 0); -- Carry in - begin - if (l'length < 1 or r'length < 1) then - result := NASF; - c_out := '0'; - else - cx (1) := '0'; - cx (0) := c_in; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - result_slv := lslv + rslv + cx; - c_out := result_slv(left_index); - result := to_fixed(result_slv (left_index-right_index-1 downto 0), - left_index-1, right_index); - end if; - end procedure add_carry; - - -- Scales the result by a power of 2. Width of input = width of output with - -- the decimal point moved. - function scalb (y : ufixed; N : integer) return ufixed is - variable result : ufixed (y'high+N downto y'low+N); - begin - if y'length < 1 then - return NAUF; - else - result := y; - return result; - end if; - end function scalb; - - function scalb (y : ufixed; N : SIGNED) return ufixed is - begin - return scalb (y => y, - N => to_integer(N)); - end function scalb; - - function scalb (y : sfixed; N : integer) return sfixed is - variable result : sfixed (y'high+N downto y'low+N); - begin - if y'length < 1 then - return NASF; - else - result := y; - return result; - end if; - end function scalb; - - function scalb (y : sfixed; N : SIGNED) return sfixed is - begin - return scalb (y => y, - N => to_integer(N)); - end function scalb; - - function Is_Negative (arg : sfixed) return BOOLEAN is - begin - if to_X01(arg(arg'high)) = '1' then - return true; - else - return false; - end if; - end function Is_Negative; - - function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER is - begin - for_loop : for i in arg'low to arg'high loop - if arg(i) = y then - return i; - end if; - end loop; - return arg'high+1; -- return out of bounds 'high - end function find_lsb; - - function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER is - begin - for_loop : for i in arg'high downto arg'low loop - if arg(i) = y then - return i; - end if; - end loop; - return arg'low-1; -- return out of bounds 'low - end function find_msb; - - function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER is - begin - for_loop : for i in arg'low to arg'high loop - if arg(i) = y then - return i; - end if; - end loop; - return arg'high+1; -- return out of bounds 'high - end function find_lsb; - - function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER is - begin - for_loop : for i in arg'high downto arg'low loop - if arg(i) = y then - return i; - end if; - end loop; - return arg'low-1; -- return out of bounds 'low - end function find_msb; - - function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed is - variable argslv : UNSIGNED (arg'length-1 downto 0); - variable result : ufixed (arg'range); - begin - argslv := to_uns (arg); - argslv := argslv sll COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "sll"; - - function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed is - variable argslv : UNSIGNED (arg'length-1 downto 0); - variable result : ufixed (arg'range); - begin - argslv := to_uns (arg); - argslv := argslv srl COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "srl"; - - function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed is - variable argslv : UNSIGNED (arg'length-1 downto 0); - variable result : ufixed (arg'range); - begin - argslv := to_uns (arg); - argslv := argslv rol COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "rol"; - - function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed is - variable argslv : UNSIGNED (arg'length-1 downto 0); - variable result : ufixed (arg'range); - begin - argslv := to_uns (arg); - argslv := argslv ror COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "ror"; - - function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed is - variable argslv : UNSIGNED (arg'length-1 downto 0); - variable result : ufixed (arg'range); - begin - argslv := to_uns (arg); - -- Arithmetic shift on an unsigned is a logical shift - argslv := argslv sll COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "sla"; - - function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed is - variable argslv : UNSIGNED (arg'length-1 downto 0); - variable result : ufixed (arg'range); - begin - argslv := to_uns (arg); - -- Arithmetic shift on an unsigned is a logical shift - argslv := argslv srl COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "sra"; - - function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed is - variable argslv : SIGNED (arg'length-1 downto 0); - variable result : sfixed (arg'range); - begin - argslv := to_s (arg); - argslv := argslv sll COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "sll"; - - function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed is - variable argslv : SIGNED (arg'length-1 downto 0); - variable result : sfixed (arg'range); - begin - argslv := to_s (arg); - argslv := argslv srl COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "srl"; - - function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed is - variable argslv : SIGNED (arg'length-1 downto 0); - variable result : sfixed (arg'range); - begin - argslv := to_s (arg); - argslv := argslv rol COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "rol"; - - function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed is - variable argslv : SIGNED (arg'length-1 downto 0); - variable result : sfixed (arg'range); - begin - argslv := to_s (arg); - argslv := argslv ror COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "ror"; - - function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed is - variable argslv : SIGNED (arg'length-1 downto 0); - variable result : sfixed (arg'range); - begin - argslv := to_s (arg); - if COUNT > 0 then - -- Arithmetic shift left on a 2's complement number is a logic shift - argslv := argslv sll COUNT; - else - argslv := argslv sra -COUNT; - end if; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "sla"; - - function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed is - variable argslv : SIGNED (arg'length-1 downto 0); - variable result : sfixed (arg'range); - begin - argslv := to_s (arg); - if COUNT > 0 then - argslv := argslv sra COUNT; - else - -- Arithmetic shift left on a 2's complement number is a logic shift - argslv := argslv sll -COUNT; - end if; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "sra"; - - -- Because some people want the older functions. - function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed is - begin - if (ARG'length < 1) then - return NAUF; - end if; - return ARG sla COUNT; - end function SHIFT_LEFT; - function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed is - begin - if (ARG'length < 1) then - return NAUF; - end if; - return ARG sra COUNT; - end function SHIFT_RIGHT; - function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed is - begin - if (ARG'length < 1) then - return NASF; - end if; - return ARG sla COUNT; - end function SHIFT_LEFT; - function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed is - begin - if (ARG'length < 1) then - return NASF; - end if; - return ARG sra COUNT; - end function SHIFT_RIGHT; - - ---------------------------------------------------------------------------- - -- logical functions - ---------------------------------------------------------------------------- - function "not" (L : ufixed) return ufixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - RESULT := not to_slv(L); - return to_ufixed(RESULT, L'high, L'low); - end function "not"; - - function "and" (L, R : ufixed) return ufixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) and to_slv(R); - else - report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_ufixed(RESULT, L'high, L'low); - end function "and"; - - function "or" (L, R : ufixed) return ufixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) or to_slv(R); - else - report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_ufixed(RESULT, L'high, L'low); - end function "or"; - - function "nand" (L, R : ufixed) return ufixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) nand to_slv(R); - else - report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_ufixed(RESULT, L'high, L'low); - end function "nand"; - - function "nor" (L, R : ufixed) return ufixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) nor to_slv(R); - else - report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_ufixed(RESULT, L'high, L'low); - end function "nor"; - - function "xor" (L, R : ufixed) return ufixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) xor to_slv(R); - else - report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_ufixed(RESULT, L'high, L'low); - end function "xor"; - - function "xnor" (L, R : ufixed) return ufixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) xnor to_slv(R); - else - report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_ufixed(RESULT, L'high, L'low); - end function "xnor"; - - function "not" (L : sfixed) return sfixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - RESULT := not to_slv(L); - return to_sfixed(RESULT, L'high, L'low); - end function "not"; - - function "and" (L, R : sfixed) return sfixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) and to_slv(R); - else - report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_sfixed(RESULT, L'high, L'low); - end function "and"; - - function "or" (L, R : sfixed) return sfixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) or to_slv(R); - else - report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_sfixed(RESULT, L'high, L'low); - end function "or"; - - function "nand" (L, R : sfixed) return sfixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) nand to_slv(R); - else - report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_sfixed(RESULT, L'high, L'low); - end function "nand"; - - function "nor" (L, R : sfixed) return sfixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) nor to_slv(R); - else - report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_sfixed(RESULT, L'high, L'low); - end function "nor"; - - function "xor" (L, R : sfixed) return sfixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) xor to_slv(R); - else - report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_sfixed(RESULT, L'high, L'low); - end function "xor"; - - function "xnor" (L, R : sfixed) return sfixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) xnor to_slv(R); - else - report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_sfixed(RESULT, L'high, L'low); - end function "xnor"; - - -- Vector and std_ulogic functions, same as functions in numeric_std - function "and" (L : STD_ULOGIC; R : ufixed) return ufixed is - variable result : ufixed (R'range); - begin - for i in result'range loop - result(i) := L and R(i); - end loop; - return result; - end function "and"; - - function "and" (L : ufixed; R : STD_ULOGIC) return ufixed is - variable result : ufixed (L'range); - begin - for i in result'range loop - result(i) := L(i) and R; - end loop; - return result; - end function "and"; - - function "or" (L : STD_ULOGIC; R : ufixed) return ufixed is - variable result : ufixed (R'range); - begin - for i in result'range loop - result(i) := L or R(i); - end loop; - return result; - end function "or"; - - function "or" (L : ufixed; R : STD_ULOGIC) return ufixed is - variable result : ufixed (L'range); - begin - for i in result'range loop - result(i) := L(i) or R; - end loop; - return result; - end function "or"; - - function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed is - variable result : ufixed (R'range); - begin - for i in result'range loop - result(i) := L nand R(i); - end loop; - return result; - end function "nand"; - - function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed is - variable result : ufixed (L'range); - begin - for i in result'range loop - result(i) := L(i) nand R; - end loop; - return result; - end function "nand"; - - function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed is - variable result : ufixed (R'range); - begin - for i in result'range loop - result(i) := L nor R(i); - end loop; - return result; - end function "nor"; - - function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed is - variable result : ufixed (L'range); - begin - for i in result'range loop - result(i) := L(i) nor R; - end loop; - return result; - end function "nor"; - - function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed is - variable result : ufixed (R'range); - begin - for i in result'range loop - result(i) := L xor R(i); - end loop; - return result; - end function "xor"; - - function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed is - variable result : ufixed (L'range); - begin - for i in result'range loop - result(i) := L(i) xor R; - end loop; - return result; - end function "xor"; - - function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed is - variable result : ufixed (R'range); - begin - for i in result'range loop - result(i) := L xnor R(i); - end loop; - return result; - end function "xnor"; - - function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed is - variable result : ufixed (L'range); - begin - for i in result'range loop - result(i) := L(i) xnor R; - end loop; - return result; - end function "xnor"; - - function "and" (L : STD_ULOGIC; R : sfixed) return sfixed is - variable result : sfixed (R'range); - begin - for i in result'range loop - result(i) := L and R(i); - end loop; - return result; - end function "and"; - - function "and" (L : sfixed; R : STD_ULOGIC) return sfixed is - variable result : sfixed (L'range); - begin - for i in result'range loop - result(i) := L(i) and R; - end loop; - return result; - end function "and"; - - function "or" (L : STD_ULOGIC; R : sfixed) return sfixed is - variable result : sfixed (R'range); - begin - for i in result'range loop - result(i) := L or R(i); - end loop; - return result; - end function "or"; - - function "or" (L : sfixed; R : STD_ULOGIC) return sfixed is - variable result : sfixed (L'range); - begin - for i in result'range loop - result(i) := L(i) or R; - end loop; - return result; - end function "or"; - - function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed is - variable result : sfixed (R'range); - begin - for i in result'range loop - result(i) := L nand R(i); - end loop; - return result; - end function "nand"; - - function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed is - variable result : sfixed (L'range); - begin - for i in result'range loop - result(i) := L(i) nand R; - end loop; - return result; - end function "nand"; - - function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed is - variable result : sfixed (R'range); - begin - for i in result'range loop - result(i) := L nor R(i); - end loop; - return result; - end function "nor"; - - function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed is - variable result : sfixed (L'range); - begin - for i in result'range loop - result(i) := L(i) nor R; - end loop; - return result; - end function "nor"; - - function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed is - variable result : sfixed (R'range); - begin - for i in result'range loop - result(i) := L xor R(i); - end loop; - return result; - end function "xor"; - - function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed is - variable result : sfixed (L'range); - begin - for i in result'range loop - result(i) := L(i) xor R; - end loop; - return result; - end function "xor"; - - function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed is - variable result : sfixed (R'range); - begin - for i in result'range loop - result(i) := L xnor R(i); - end loop; - return result; - end function "xnor"; - - function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed is - variable result : sfixed (L'range); - begin - for i in result'range loop - result(i) := L(i) xnor R; - end loop; - return result; - end function "xnor"; - - -- Reduction operators, same as numeric_std functions - -- %%% remove 12 functions (old syntax) - function and_reduce(arg : ufixed) return STD_ULOGIC is - begin - return and_reducex (to_slv(arg)); - end function and_reduce; - - function nand_reduce(arg : ufixed) return STD_ULOGIC is - begin - return not and_reducex (to_slv(arg)); - end function nand_reduce; - - function or_reduce(arg : ufixed) return STD_ULOGIC is - begin - return or_reducex (to_slv(arg)); - end function or_reduce; - - function nor_reduce(arg : ufixed) return STD_ULOGIC is - begin - return not or_reducex (to_slv(arg)); - end function nor_reduce; - - function xor_reduce(arg : ufixed) return STD_ULOGIC is - begin - return xor_reducex (to_slv(arg)); - end function xor_reduce; - - function xnor_reduce(arg : ufixed) return STD_ULOGIC is - begin - return not xor_reducex (to_slv(arg)); - end function xnor_reduce; - - function and_reduce(arg : sfixed) return STD_ULOGIC is - begin - return and_reducex (to_slv(arg)); - end function and_reduce; - - function nand_reduce(arg : sfixed) return STD_ULOGIC is - begin - return not and_reducex (to_slv(arg)); - end function nand_reduce; - - function or_reduce(arg : sfixed) return STD_ULOGIC is - begin - return or_reducex (to_slv(arg)); - end function or_reduce; - - function nor_reduce(arg : sfixed) return STD_ULOGIC is - begin - return not or_reducex (to_slv(arg)); - end function nor_reduce; - - function xor_reduce(arg : sfixed) return STD_ULOGIC is - begin - return xor_reducex (to_slv(arg)); - end function xor_reduce; - - function xnor_reduce(arg : sfixed) return STD_ULOGIC is - begin - return not xor_reducex (to_slv(arg)); - end function xnor_reduce; - -- %%% Uncomment the following 12 functions (new syntax) - -- function "and" ( arg : ufixed ) RETURN std_ulogic is - -- begin - -- return and to_slv(arg); - -- end function "and"; - -- function "nand" ( arg : ufixed ) RETURN std_ulogic is - -- begin - -- return nand to_slv(arg); - -- end function "nand";; - -- function "or" ( arg : ufixed ) RETURN std_ulogic is - -- begin - -- return or to_slv(arg); - -- end function "or"; - -- function "nor" ( arg : ufixed ) RETURN std_ulogic is - -- begin - -- return nor to_slv(arg); - -- end function "nor"; - -- function "xor" ( arg : ufixed ) RETURN std_ulogic is - -- begin - -- return xor to_slv(arg); - -- end function "xor"; - -- function "xnor" ( arg : ufixed ) RETURN std_ulogic is - -- begin - -- return xnor to_slv(arg); - -- end function "xnor"; - -- function "and" ( arg : sfixed ) RETURN std_ulogic is - -- begin - -- return and to_slv(arg); - -- end function "and";; - -- function "nand" ( arg : sfixed ) RETURN std_ulogic is - -- begin - -- return nand to_slv(arg); - -- end function "nand";; - -- function "or" ( arg : sfixed ) RETURN std_ulogic is - -- begin - -- return or to_slv(arg); - -- end function "or"; - -- function "nor" ( arg : sfixed ) RETURN std_ulogic is - -- begin - -- return nor to_slv(arg); - -- end function "nor"; - -- function "xor" ( arg : sfixed ) RETURN std_ulogic is - -- begin - -- return xor to_slv(arg); - -- end function "xor"; - -- function "xnor" ( arg : sfixed ) RETURN std_ulogic is - -- begin - -- return xnor to_slv(arg); - -- end function "xnor"; - - -- %%% Replace with the following (new syntax) --- function "?=" (L, R : ufixed) return STD_ULOGIC is - function \?=\ (L, R : ufixed) return STD_ULOGIC is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable result, result1 : STD_ULOGIC; -- result - begin -- ?= - if ((L'LENGTH < 1) or (R'LENGTH < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?="": null detected, returning X" - severity warning; - return 'X'; - else - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - result := '1'; - for i in lresize'reverse_range loop - result1 := \?=\(lresize(i), rresize(i)); - if result1 = 'U' then - return 'U'; - elsif result1 = 'X' or result = 'X' then - result := 'X'; - else - result := result and result1; - end if; - end loop; - return result; - end if; - end function \?=\; --- end function "?="; - --- function "?/=" (L, R : ufixed) return STD_ULOGIC is - function \?/=\ (L, R : ufixed) return STD_ULOGIC is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable result, result1 : STD_ULOGIC; -- result - begin -- ?/= - if ((L'LENGTH < 1) or (R'LENGTH < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?/="": null detected, returning X" - severity warning; - return 'X'; - else - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - result := '0'; - for i in lresize'reverse_range loop - result1 := \?/=\ (lresize(i), rresize(i)); - if result1 = 'U' then - return 'U'; - elsif result1 = 'X' or result = 'X' then - result := 'X'; - else - result := result or result1; - end if; - end loop; - return result; - end if; - end function \?/=\; --- end function "?/="; - --- function "?>" (L, R : ufixed) return STD_ULOGIC is - function \?>\ (L, R : ufixed) return STD_ULOGIC is - begin -- ?> - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?>"": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l > r then - return '1'; - else - return '0'; - end if; - end if; - end function \?>\; --- end function "?>"; - --- function "?>=" (L, R : ufixed) return STD_ULOGIC is - function \?>=\ (L, R : ufixed) return STD_ULOGIC is - begin -- ?>= - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?>="": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l >= r then - return '1'; - else - return '0'; - end if; - end if; - end function \?>=\; --- end function "?>="; - --- function "?<" (L, R : ufixed) return STD_ULOGIC is - function \?<\ (L, R : ufixed) return STD_ULOGIC is - begin -- ?< - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?<"": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l < r then - return '1'; - else - return '0'; - end if; - end if; - end function \?<\; --- end function "?<"; - --- function "?<=" (L, R : ufixed) return STD_ULOGIC is - function \?<=\ (L, R : ufixed) return STD_ULOGIC is - begin -- ?<= - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?<="": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l <= r then - return '1'; - else - return '0'; - end if; - end if; - end function \?<=\; --- end function "?<="; - - -- function "?=" (L, R : sfixed) return STD_ULOGIC is - function \?=\ (L, R : sfixed) return STD_ULOGIC is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable result, result1 : STD_ULOGIC; -- result - begin -- ?= - if ((L'LENGTH < 1) or (R'LENGTH < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?="": null detected, returning X" - severity warning; - return 'X'; - else - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - result := '1'; - for i in lresize'reverse_range loop - result1 := \?=\ (lresize(i), rresize(i)); - if result1 = 'U' then - return 'U'; - elsif result1 = 'X' or result = 'X' then - result := 'X'; - else - result := result and result1; - end if; - end loop; - return result; - end if; - end function \?=\; --- end function "?="; - --- function "?/=" (L, R : sfixed) return STD_ULOGIC is - function \?/=\ (L, R : sfixed) return STD_ULOGIC is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable result, result1 : STD_ULOGIC; -- result - begin -- ?/= - if ((L'LENGTH < 1) or (R'LENGTH < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?/="": null detected, returning X" - severity warning; - return 'X'; - else - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - result := '0'; - for i in lresize'reverse_range loop - result1 := \?/=\ (lresize(i), rresize(i)); - if result1 = 'U' then - return 'U'; - elsif result1 = 'X' or result = 'X' then - result := 'X'; - else - result := result or result1; - end if; - end loop; - return result; - end if; - end function \?/=\; --- end function "?/="; - --- function "?>" (L, R : sfixed) return STD_ULOGIC is - function \?>\ (L, R : sfixed) return STD_ULOGIC is - begin -- ?> - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?>"": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l > r then - return '1'; - else - return '0'; - end if; - end if; - end function \?>\; --- end function "?>"; - --- function "?>=" (L, R : sfixed) return STD_ULOGIC is - function \?>=\ (L, R : sfixed) return STD_ULOGIC is - begin -- ?>= - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?>="": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l >= r then - return '1'; - else - return '0'; - end if; - end if; - end function \?>=\; --- end function "?>="; - --- function "?<" (L, R : sfixed) return STD_ULOGIC is - function \?<\ (L, R : sfixed) return STD_ULOGIC is - begin -- ?< - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?<"": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l < r then - return '1'; - else - return '0'; - end if; - end if; - end function \?<\; --- end function "?<"; - --- function "?<=" (L, R : sfixed) return STD_ULOGIC is - function \?<=\ (L, R : sfixed) return STD_ULOGIC is - begin -- ?<= - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?<="": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l <= r then - return '1'; - else - return '0'; - end if; - end if; - end function \?<=\; --- end function "?<="; - - -- %%% end replace - -- Match function, similar to "std_match" from numeric_std - function std_match (L, R : ufixed) return BOOLEAN is - begin - if (L'high = R'high and L'low = R'low) then - return std_match(to_slv(L), to_slv(R)); - else - report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE" - severity warning; - return false; - end if; - end function std_match; - - function std_match (L, R : sfixed) return BOOLEAN is - begin - if (L'high = R'high and L'low = R'low) then - return std_match(to_slv(L), to_slv(R)); - else - report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE" - severity warning; - return false; - end if; - end function std_match; - --%%% end remove - - -- compare functions - function "=" ( - l, r : ufixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - return lslv = rslv; - end function "="; - - function "=" ( - l, r : sfixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - return lslv = rslv; - end function "="; - - function "/=" ( - l, r : ufixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE" - severity warning; - return true; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE" - severity warning; - return true; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - return lslv /= rslv; - end function "/="; - - function "/=" ( - l, r : sfixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE" - severity warning; - return true; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE" - severity warning; - return true; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - return lslv /= rslv; - end function "/="; - - function ">" ( - l, r : ufixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - return lslv > rslv; - end function ">"; - - function ">" ( - l, r : sfixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - return lslv > rslv; - end function ">"; - - function "<" ( - l, r : ufixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - return lslv < rslv; - end function "<"; - - function "<" ( - l, r : sfixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - return lslv < rslv; - end function "<"; - - function ">=" ( - l, r : ufixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - return lslv >= rslv; - end function ">="; - - function ">=" ( - l, r : sfixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - return lslv >= rslv; - end function ">="; - - function "<=" ( - l, r : ufixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - return lslv <= rslv; - end function "<="; - - function "<=" ( - l, r : sfixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - return lslv <= rslv; - end function "<="; - - -- overloads of the default maximum and minimum functions - function maximum (l, r : ufixed) return ufixed is - begin - if l > r then return l; - else return r; - end if; - end function maximum; - - function maximum (l, r : sfixed) return sfixed is - begin - if l > r then return l; - else return r; - end if; - end function maximum; - - function minimum (l, r : ufixed) return ufixed is - begin - if l > r then return r; - else return l; - end if; - end function minimum; - - function minimum (l, r : sfixed) return sfixed is - begin - if l > r then return r; - else return l; - end if; - end function minimum; - - function to_ufixed ( - arg : NATURAL; -- integer - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default - return ufixed is - variable argx : INTEGER; - constant fw : INTEGER := mine (right_index, right_index); -- catch literals - variable result : ufixed (left_index downto fw) := (others => '0'); - variable sresult : UNSIGNED (left_index downto 0); -- integer portion - variable bound : NATURAL; -- find the numerical bounds - begin - if (left_index < fw) then - return NAUF; - end if; - if left_index >= 0 then - if (left_index < 30) then - bound := 2**(left_index+1); - else - bound := INTEGER'high; - end if; - end if; - if (arg /= 0) then - if arg >= bound or left_index < 0 then - assert NO_WARNING - report "FIXED_GENERIC_PKG.TO_UFIXED(NATURAL): vector truncated" - severity warning; - if (overflow_style = fixed_wrap) then -- wrap - if bound = 0 then - argx := 0; - else - argx := arg mod bound; - end if; - else -- saturate - return saturate (result'high, result'low); - end if; - else - argx := arg; - end if; - else - return result; -- return zero - end if; - sresult := to_unsigned (argx, sresult'high+1); - result := resize (arg => ufixed (sresult), - left_index => left_index, - right_index => right_index, - round_style => round_style, - overflow_style => overflow_style); - return result; - end function to_ufixed; - - function to_sfixed ( - arg : INTEGER; -- integer - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default - return sfixed is - variable argx : INTEGER; - constant fw : INTEGER := mine (right_index, right_index); -- catch literals - variable result : sfixed (left_index downto fw) := (others => '0'); - variable sresult : SIGNED (left_index+1 downto 0); -- integer portion - variable bound : NATURAL := 0; - begin - if (left_index < fw) then -- null range - return NASF; - end if; - if left_index >= 0 then - if (left_index < 30) then - bound := 2**(left_index); - else - bound := INTEGER'high; - end if; - end if; - if (arg /= 0) then - if (arg >= bound or arg < -bound or left_index < 0) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.TO_SFIXED(INTEGER): vector truncated" - severity warning; - if overflow_style = fixed_wrap then -- wrap - if bound = 0 then -- negative integer_range trap - argx := 0; - else -- shift off the top bits - argx := arg rem (bound*2); - end if; - else -- saturate - if arg < 0 then - result := not saturate (result'high, result'low); -- underflow - else - result := saturate (result'high, result'low); -- overflow - end if; - return result; - end if; - else - argx := arg; - end if; - else - return result; -- return zero - end if; - sresult := to_signed (argx, sresult'length); - result := resize (arg => sfixed (sresult), - left_index => left_index, - right_index => right_index, - round_style => round_style, - overflow_style => overflow_style); - return result; - end function to_sfixed; - - function to_ufixed ( - arg : REAL; -- real - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return ufixed is - constant fw : INTEGER := mine (right_index, right_index); -- catch literals - variable result : ufixed (left_index downto fw) := (others => '0'); - variable Xresult : ufixed (left_index downto fw-guard_bits) := (others => '0'); - variable presult : REAL; - variable overflow_needed : BOOLEAN; - begin - -- If negative or null range, return. - if (left_index < fw) then - return NAUF; - end if; - if (arg < 0.0) then - report "FIXED_GENERIC_PKG.TO_UFIXED: Negative argument passed " - & REAL'image(arg) severity error; - return result; - end if; - presult := arg; - if presult >= (2.0**(left_index+1)) then - assert NO_WARNING report "FIXED_GENERIC_PKG.TO_UFIXED(REAL): vector truncated" - severity warning; - overflow_needed := (overflow_style = fixed_saturate); - if overflow_style = fixed_wrap then - presult := presult mod (2.0**(left_index+1)); -- wrap - else - return saturate (result'high, result'low); - end if; - end if; - for i in Xresult'range loop - if presult >= 2.0**i then - Xresult(i) := '1'; - presult := presult - 2.0**i; - else - Xresult(i) := '0'; - end if; - end loop; - if guard_bits > 0 and round_style = fixed_round then - result := round_fixed (arg => Xresult (left_index - downto right_index), - remainder => Xresult (right_index-1 downto - right_index-guard_bits), - overflow_style => overflow_style); - else - result := Xresult (result'range); - end if; - return result; - end function to_ufixed; - - function to_sfixed ( - arg : REAL; -- real - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return sfixed is - constant fw : INTEGER := mine (right_index, right_index); -- catch literals - variable result : sfixed (left_index downto fw) := (others => '0'); - variable Xresult : sfixed (left_index+1 downto fw-guard_bits) := (others => '0'); - variable presult : REAL; - begin - if (left_index < fw) then -- null range - return NASF; - end if; - if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then - assert NO_WARNING report "FIXED_GENERIC_PKG.TO_SFIXED(REAL): vector truncated" - severity warning; - if overflow_style = fixed_saturate then - if arg < 0.0 then -- saturate - result := not saturate (result'high, result'low); -- underflow - else - result := saturate (result'high, result'low); -- overflow - end if; - return result; - else - presult := abs(arg) mod (2.0**(left_index+1)); -- wrap - end if; - else - presult := abs(arg); - end if; - for i in Xresult'range loop - if presult >= 2.0**i then - Xresult(i) := '1'; - presult := presult - 2.0**i; - else - Xresult(i) := '0'; - end if; - end loop; - if arg < 0.0 then - Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low); - end if; - if guard_bits > 0 and round_style then - result := round_fixed (arg => Xresult (left_index - downto right_index), - remainder => Xresult (right_index-1 downto - right_index-guard_bits), - overflow_style => overflow_style); - else - result := Xresult (result'range); - end if; - return result; - end function to_sfixed; - - function to_ufixed ( - arg : UNSIGNED; -- unsigned - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default - return ufixed is - constant ARG_LEFT : INTEGER := ARG'length-1; - alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG; - constant fw : INTEGER := mine (right_index, right_index); -- catch literals - variable result : ufixed (left_index downto fw); - begin - if arg'length < 1 or (left_index < fw) then - return NAUF; - end if; - result := resize (arg => ufixed (XARG), - left_index => left_index, - right_index => right_index, - round_style => round_style, - overflow_style => overflow_style); - return result; - end function to_ufixed; - - -- casted version - function to_ufixed ( - arg : UNSIGNED) -- unsigned - return ufixed is - constant ARG_LEFT : INTEGER := ARG'length-1; - alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG; - begin - if arg'length < 1 then - return NAUF; - end if; - return ufixed(xarg); - end function to_ufixed; - - function to_sfixed ( - arg : SIGNED; -- signed - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default - return sfixed is - constant ARG_LEFT : INTEGER := ARG'length-1; - alias XARG : SIGNED(ARG_LEFT downto 0) is ARG; - constant fw : INTEGER := mine (right_index, right_index); -- catch literals - variable result : sfixed (left_index downto fw); - begin - if arg'length < 1 or (left_index < fw) then - return NASF; - end if; - result := resize (arg => sfixed (XARG), - left_index => left_index, - right_index => right_index, - round_style => round_style, - overflow_style => overflow_style); - return result; - end function to_sfixed; - - -- casted version - function to_sfixed ( - arg : SIGNED) -- signed - return sfixed is - constant ARG_LEFT : INTEGER := ARG'length-1; - alias XARG : SIGNED(ARG_LEFT downto 0) is ARG; - begin - if arg'length < 1 then - return NASF; - end if; - return sfixed(xarg); - end function to_sfixed; - - function add_sign (arg : ufixed) return sfixed is - variable result : sfixed (arg'high+1 downto arg'low); - begin - if arg'length < 1 then - return NASF; - end if; - result (arg'high downto arg'low) := sfixed(cleanvec(arg)); - result (arg'high+1) := '0'; - return result; - end function add_sign; - - -- Because of the farily complicated sizing rules in the fixed point - -- packages these functions are provided to compute the result ranges - -- Example: - -- signal uf1 : ufixed (3 downto -3); - -- signal uf2 : ufixed (4 downto -2); - -- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto - -- ufixed_low (3, -3, '*', 4, -2)); - -- uf1multuf2 <= uf1 * uf2; - -- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod), - -- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed) - function ufixed_high (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER is - begin - case operation is - when '+'| '-' => return maximum (left_index, left_index2) + 1; - when '*' => return left_index + left_index2 + 1; - when '/' => return left_index - right_index2; - when '1' => return -right_index; -- reciprocal - when 'R'|'r' => return mins (left_index, left_index2); -- "rem" - when 'M'|'m' => return mins (left_index, left_index2); -- "mod" - when others => return left_index; -- For abs and default - end case; - end function ufixed_high; - - function ufixed_low (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER is - begin - case operation is - when '+'| '-' => return mins (right_index, right_index2); - when '*' => return right_index + right_index2; - when '/' => return right_index - left_index2 - 1; - when '1' => return -left_index - 1; -- reciprocal - when 'R'|'r' => return mins (right_index, right_index2); -- "rem" - when 'M'|'m' => return mins (right_index, right_index2); -- "mod" - when others => return right_index; -- for abs and default - end case; - end function ufixed_low; - - function sfixed_high (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER is - begin - case operation is - when '+'| '-' => return maximum (left_index, left_index2) + 1; - when '*' => return left_index + left_index2 + 1; - when '/' => return left_index - right_index2 + 1; - when '1' => return -right_index + 1; -- reciprocal - when 'R'|'r' => return mins (left_index, left_index2); -- "rem" - when 'M'|'m' => return left_index2; -- "mod" - when 'A'|'a' => return left_index + 1; -- "abs" - when 'N'|'n' => return left_index + 1; -- -sfixed - when others => return left_index; - end case; - end function sfixed_high; - - function sfixed_low (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER is - begin - case operation is - when '+'| '-' => return mins (right_index, right_index2); - when '*' => return right_index + right_index2; - when '/' => return right_index - left_index2; - when '1' => return -left_index; -- reciprocal - when 'R'|'r' => return mins (right_index, right_index2); -- "rem" - when 'M'|'m' => return mins (right_index, right_index2); -- "mod" - when others => return right_index; -- default for abs, neg and default - end case; - end function sfixed_low; - -- Same as above, but using the "size_res" input only for their ranges: - -- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto - -- ufixed_low (uf1, '*', uf2)); - -- uf1multuf2 <= uf1 * uf2; - function ufixed_high (size_res : ufixed; - operation : CHARACTER := 'X'; - size_res2 : ufixed) - return INTEGER is - begin - return ufixed_high (left_index => size_res'high, - right_index => size_res'low, - operation => operation, - left_index2 => size_res2'high, - right_index2 => size_res2'low); - end function ufixed_high; - function ufixed_low (size_res : ufixed; - operation : CHARACTER := 'X'; - size_res2 : ufixed) - return INTEGER is - begin - return ufixed_low (left_index => size_res'high, - right_index => size_res'low, - operation => operation, - left_index2 => size_res2'high, - right_index2 => size_res2'low); - end function ufixed_low; - function sfixed_high (size_res : sfixed; - operation : CHARACTER := 'X'; - size_res2 : sfixed) - return INTEGER is - begin - return sfixed_high (left_index => size_res'high, - right_index => size_res'low, - operation => operation, - left_index2 => size_res2'high, - right_index2 => size_res2'low); - end function sfixed_high; - function sfixed_low (size_res : sfixed; - operation : CHARACTER := 'X'; - size_res2 : sfixed) - return INTEGER is - begin - return sfixed_low (left_index => size_res'high, - right_index => size_res'low, - operation => operation, - left_index2 => size_res2'high, - right_index2 => size_res2'low); - end function sfixed_low; - - -- purpose: returns a saturated number - function saturate ( - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed is - constant sat : ufixed (left_index downto right_index) := (others => '1'); - begin - return sat; - end function saturate; - - -- purpose: returns a saturated number - function saturate ( - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed is - variable sat : sfixed (left_index downto right_index) := (others => '1'); - begin - -- saturate positive, to saturate negative, just do "not saturate()" - sat (left_index) := '0'; - return sat; - end function saturate; - - function saturate ( - size_res : ufixed) -- only the size of this is used - return ufixed is - begin - return saturate (size_res'high, size_res'low); - end function saturate; - - function saturate ( - size_res : sfixed) -- only the size of this is used - return sfixed is - begin - return saturate (size_res'high, size_res'low); - end function saturate; - - -- As a concession to those who use a graphical DSP environment, - -- these functions take parameters in those tools format and create - -- fixed point numbers. These functions are designed to convert from - -- a std_logic_vector to the VHDL fixed point format using the conventions - -- of these packages. In a pure VHDL environment you should use the - -- "to_ufixed" and "to_sfixed" routines. - -- Unsigned fixed point - function to_UFix ( - arg : STD_LOGIC_VECTOR; - width : NATURAL; -- width of vector - fraction : NATURAL) -- width of fraction - return ufixed is - variable result : ufixed (width-fraction-1 downto -fraction); - begin - if (arg'length /= result'length) then - report "FIXED_GENERIC_PKG.TO_UFIX (STD_LOGIC_VECTOR) " - & "Vector lengths do not match. Input length is " - & INTEGER'image(arg'length) & " and output will be " - & INTEGER'image(result'length) & " wide." - severity error; - return NAUF; - else - result := to_ufixed (arg, result'high, result'low); - return result; - end if; - end function to_UFix; - - -- signed fixed point - function to_SFix ( - arg : STD_LOGIC_VECTOR; - width : NATURAL; -- width of vector - fraction : NATURAL) -- width of fraction - return sfixed is - variable result : sfixed (width-fraction-1 downto -fraction); - begin - if (arg'length /= result'length) then - report "FIXED_GENERIC_PKG.TO_SFIX (STD_LOGIC_VECTOR) " - & "Vector lengths do not match. Input length is " - & INTEGER'image(arg'length) & " and output will be " - & INTEGER'image(result'length) & " wide." - severity error; - return NASF; - else - result := to_sfixed (arg, result'high, result'low); - return result; - end if; - end function to_SFix; - - -- finding the bounds of a number. These functions can be used like this: - -- signal xxx : ufixed (7 downto -3); - -- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))" - -- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3) - -- downto UFix_low(11, 3, "+", 11, 3)); - -- Where "11" is the width of xxx (xxx'length), - -- and 3 is the lower bound (abs (xxx'low)) - -- In a pure VHDL environment use "ufixed_high" and "ufixed_low" - function ufix_high ( - width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER is - begin - return ufixed_high (left_index => width - 1 - fraction, - right_index => -fraction, - operation => operation, - left_index2 => width2 - 1 - fraction2, - right_index2 => -fraction2); - end function ufix_high; - function ufix_low ( - width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER is - begin - return ufixed_low (left_index => width - 1 - fraction, - right_index => -fraction, - operation => operation, - left_index2 => width2 - 1 - fraction2, - right_index2 => -fraction2); - end function ufix_low; - function sfix_high ( - width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER is - begin - return sfixed_high (left_index => width - fraction, - right_index => -fraction, - operation => operation, - left_index2 => width2 - fraction2, - right_index2 => -fraction2); - end function sfix_high; - function sfix_low ( - width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER is - begin - return sfixed_low (left_index => width - fraction, - right_index => -fraction, - operation => operation, - left_index2 => width2 - fraction2, - right_index2 => -fraction2); - end function sfix_low; - - function to_unsigned ( - arg : ufixed; -- ufixed point input - constant size : NATURAL; -- length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return UNSIGNED is - begin - return to_uns(resize (arg => arg, - left_index => size-1, - right_index => 0, - round_style => round_style, - overflow_style => overflow_style)); - end function to_unsigned; - - function to_unsigned ( - arg : ufixed; -- ufixed point input - size_res : UNSIGNED; -- length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return UNSIGNED is - begin - return to_unsigned (arg => arg, - size => size_res'length, - round_style => round_style, - overflow_style => overflow_style); - end function to_unsigned; - - function to_signed ( - arg : sfixed; -- ufixed point input - constant size : NATURAL; -- length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return SIGNED is - begin - return to_s(resize (arg => arg, - left_index => size-1, - right_index => 0, - round_style => round_style, - overflow_style => overflow_style)); - end function to_signed; - - function to_signed ( - arg : sfixed; -- ufixed point input - size_res : SIGNED; -- used for length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return SIGNED is - begin - return to_signed (arg => arg, - size => size_res'length, - round_style => round_style, - overflow_style => overflow_style); - end function to_signed; - - function to_real ( - arg : ufixed) -- ufixed point input - return REAL is - constant left_index : INTEGER := arg'high; - constant right_index : INTEGER := arg'low; - variable result : REAL; -- result - variable arg_int : ufixed (left_index downto right_index); - begin - if (arg'length < 1) then - return 0.0; - end if; - arg_int := cleanvec(arg); - if (Is_X(arg_int)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0" - severity warning; - return 0.0; - end if; - result := 0.0; - for i in arg_int'range loop - if (arg_int(i) = '1') then - result := result + (2.0**i); - end if; - end loop; - return result; - end function to_real; - - function to_real ( - arg : sfixed) -- ufixed point input - return REAL is - constant left_index : INTEGER := arg'high; - constant right_index : INTEGER := arg'low; - variable result : REAL; -- result - variable arg_int : sfixed (left_index downto right_index); - -- unsigned version of argument - variable arg_uns : ufixed (left_index downto right_index); - -- absolute of argument - begin - if (arg'length < 1) then - return 0.0; - end if; - arg_int := cleanvec(arg); - if (Is_X(arg_int)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0" - severity warning; - return 0.0; - end if; - arg_uns := abs(arg_int); - result := to_real (arg_uns); - if (arg_int(arg_int'high) = '1') then - result := -result; - end if; - return result; - end function to_real; - - function to_integer ( - arg : ufixed; -- fixed point input - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return NATURAL is - constant left_index : INTEGER := arg'high; - variable arg_uns : UNSIGNED (minimum(31, left_index+1) downto 0) - := (others => '0'); - begin - if (arg'length < 1) then - return 0; - end if; - if (Is_X (arg)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0" - severity warning; - return 0; - end if; - if (left_index < -1) then - return 0; - end if; - arg_uns := to_uns(resize (arg => arg, - left_index => arg_uns'high, - right_index => 0, - round_style => round_style, - overflow_style => overflow_style)); - return to_integer (arg_uns); - end function to_integer; - - function to_integer ( - arg : sfixed; -- fixed point input - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return INTEGER is - constant left_index : INTEGER := arg'high; - constant right_index : INTEGER := arg'low; - variable arg_s : SIGNED (minimum(31, left_index+1) downto 0); - begin - if (arg'length < 1) then - return 0; - end if; - if (Is_X (arg)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0" - severity warning; - return 0; - end if; - if (left_index < -1) then - return 0; - end if; - arg_s := to_s(resize (arg => arg, - left_index => arg_s'high, - right_index => 0, - round_style => round_style, - overflow_style => overflow_style)); - return to_integer (arg_s); - end function to_integer; - - function to_01 ( - s : ufixed; -- ufixed point input - constant XMAP : STD_LOGIC := '0') -- Map x to - return ufixed is - variable result : ufixed (s'range); -- result - begin - for i in s'range loop - case s(i) is - when '0' | 'L' => result(i) := '0'; - when '1' | 'H' => result(i) := '1'; - when others => result(i) := XMAP; - end case; - end loop; - return result; - end function to_01; - - function to_01 ( - s : sfixed; -- ufixed point input - constant XMAP : STD_LOGIC := '0') -- Map x to - return sfixed is - variable result : sfixed (s'range); - begin - for i in s'range loop - case s(i) is - when '0' | 'L' => result(i) := '0'; - when '1' | 'H' => result(i) := '1'; - when others => result(i) := XMAP; - end case; - end loop; - return result; - end function to_01; - - function Is_X ( - arg : ufixed) - return BOOLEAN is - variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv - begin - argslv := to_slv(arg); - return Is_X(argslv); - end function Is_X; - - function Is_X ( - arg : sfixed) - return BOOLEAN is - variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv - begin - argslv := to_slv(arg); - return Is_X(argslv); - end function Is_X; - - function To_X01 ( - arg : ufixed) - return ufixed is - begin - return to_ufixed (To_X01(to_slv(arg)), arg'high, arg'low); - end function To_X01; - - function to_X01 ( - arg : sfixed) - return sfixed is - begin - return to_sfixed (To_X01(to_slv(arg)), arg'high, arg'low); - end function To_X01; - - function To_X01Z ( - arg : ufixed) - return ufixed is - begin - return to_ufixed (To_X01Z(to_slv(arg)), arg'high, arg'low); - end function To_X01Z; - - function to_X01Z ( - arg : sfixed) - return sfixed is - begin - return to_sfixed (To_X01Z(to_slv(arg)), arg'high, arg'low); - end function To_X01Z; - - function To_UX01 ( - arg : ufixed) - return ufixed is - begin - return to_ufixed (To_UX01(to_slv(arg)), arg'high, arg'low); - end function To_UX01; - - function to_UX01 ( - arg : sfixed) - return sfixed is - begin - return to_sfixed (To_UX01(to_slv(arg)), arg'high, arg'low); - end function To_UX01; - - - function resize ( - arg : ufixed; -- input - constant left_index : INTEGER; -- integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow - constant round_style : BOOLEAN := fixed_round_style) -- rounding - return ufixed is - constant arghigh : INTEGER := maximum (arg'high, arg'low); - constant arglow : INTEGER := mine (arg'high, arg'low); - variable invec : ufixed (arghigh downto arglow); - variable result : ufixed(left_index downto right_index) := - (others => '0'); - variable needs_rounding : BOOLEAN := false; - begin -- resize - if (arg'length < 1) or (result'length < 1) then - return NAUF; - elsif (invec'length < 1) then - return result; -- string literal value - else - invec := cleanvec(arg); - if (right_index > arghigh) then -- return top zeros - needs_rounding := (round_style = fixed_round) and - (right_index = arghigh+1); - elsif (left_index < arglow) then -- return overflow - if (overflow_style = fixed_saturate) and - (or_reducex(to_slv(invec)) = '1') then - result := saturate (result'high, result'low); -- saturate - end if; - elsif (arghigh > left_index) then - -- wrap or saturate? - if (overflow_style and - or_reducex(to_slv(invec(arghigh downto left_index+1))) = '1') - then - result := saturate (result'high, result'low); -- saturate - else - if (arglow >= right_index) then - result (left_index downto arglow) := - invec(left_index downto arglow); - else - result (left_index downto right_index) := - invec (left_index downto right_index); - needs_rounding := (round_style = fixed_round); -- round - end if; - end if; - else -- arghigh <= integer width - if (arglow >= right_index) then - result (arghigh downto arglow) := invec; - else - result (arghigh downto right_index) := - invec (arghigh downto right_index); - needs_rounding := (round_style = fixed_round); -- round - end if; - end if; - -- Round result - if needs_rounding then - result := round_fixed (arg => result, - remainder => invec (right_index-1 - downto arglow), - overflow_style => overflow_style); - end if; - return result; - end if; - end function resize; - - function resize ( - arg : sfixed; -- input - constant left_index : INTEGER; -- integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow - constant round_style : BOOLEAN := fixed_round_style) -- rounding - return sfixed is - constant arghigh : INTEGER := maximum (arg'high, arg'low); - constant arglow : INTEGER := mine (arg'high, arg'low); - variable invec : sfixed (arghigh downto arglow); - variable result : sfixed(left_index downto right_index) := - (others => '0'); - variable reduced : STD_ULOGIC; - variable needs_rounding : BOOLEAN := false; -- rounding - begin -- resize - if (arg'length < 1) or (result'length < 1) then - return NASF; - elsif (invec'length < 1) then - return result; -- string literal value - else - invec := cleanvec(arg); - if (right_index > arghigh) then -- return top zeros - if (arg'low /= INTEGER'low) then -- check for a literal - result := (others => arg(arghigh)); -- sign extend - end if; - needs_rounding := (round_style = fixed_round) and - (right_index = arghigh+1); - elsif (left_index < arglow) then -- return overflow - if (overflow_style) then - reduced := or_reducex(to_slv(invec)); - if (reduced = '1') then - if (invec(arghigh) = '0') then - -- saturate POSITIVE - result := saturate (result'high, result'low); - else - -- saturate negative - result := not saturate (result'high, result'low); - end if; - -- else return 0 (input was 0) - end if; - -- else return 0 (wrap) - end if; - elsif (arghigh > left_index) then - if (invec(arghigh) = '0') then - reduced := or_reducex(to_slv(invec(arghigh-1 downto - left_index))); - if overflow_style and reduced = '1' then - -- saturate positive - result := saturate (result'high, result'low); - else - if (right_index > arglow) then - result := invec (left_index downto right_index); - needs_rounding := (round_style = fixed_round); - else - result (left_index downto arglow) := - invec (left_index downto arglow); - end if; - end if; - else - reduced := and_reducex(to_slv(invec(arghigh-1 downto - left_index))); - if overflow_style and reduced = '0' then - result := not saturate (result'high, result'low); - else - if (right_index > arglow) then - result := invec (left_index downto right_index); - needs_rounding := (round_style = fixed_round); - else - result (left_index downto arglow) := - invec (left_index downto arglow); - end if; - end if; - end if; - else -- arghigh <= integer width - if (arglow >= right_index) then - result (arghigh downto arglow) := invec; - else - result (arghigh downto right_index) := - invec (arghigh downto right_index); - needs_rounding := (round_style = fixed_round); -- round - end if; - if (left_index > arghigh) then -- sign extend - result(left_index downto arghigh+1) := (others => invec(arghigh)); - end if; - end if; - -- Round result - if (needs_rounding) then - result := round_fixed (arg => result, - remainder => invec (right_index-1 - downto arglow), - overflow_style => overflow_style); - end if; - return result; - end if; - end function resize; - - -- size_res functions - -- These functions compute the size from a passed variable named "size_res" - -- The only part of this variable used it it's size, it is never passed - -- to a lower level routine. - function to_ufixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - size_res : ufixed) -- for size only - return ufixed is - variable result : ufixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_ufixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low); - return result; - end if; - end function to_ufixed; - - function to_sfixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - size_res : sfixed) -- for size only - return sfixed is - variable result : sfixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_sfixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low); - return result; - end if; - end function to_sfixed; - - function to_ufixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - size_res : ufixed) -- for size only - return ufixed is - variable result : ufixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_ufixed (arg => to_stdlogicvector(arg), - left_index => size_res'high, - right_index => size_res'low); - return result; - end if; - end function to_ufixed; - - function to_sfixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - size_res : sfixed) -- for size only - return sfixed is - variable result : sfixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_sfixed (arg => to_stdlogicvector(arg), - left_index => size_res'high, - right_index => size_res'low); - return result; - end if; - end function to_sfixed; - - function to_ufixed ( - arg : NATURAL; -- integer - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default - return ufixed is - variable result : ufixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_ufixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function to_ufixed; - - function to_sfixed ( - arg : INTEGER; -- integer - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default - return sfixed is - variable result : sfixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_sfixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function to_sfixed; - - function to_ufixed ( - arg : REAL; -- real - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return ufixed is - variable result : ufixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_ufixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - guard_bits => guard_bits, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function to_ufixed; - - function to_sfixed ( - arg : REAL; -- real - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return sfixed is - variable result : sfixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_sfixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - guard_bits => guard_bits, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function to_sfixed; - - function to_ufixed ( - arg : UNSIGNED; -- unsigned - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow - constant round_style : BOOLEAN := fixed_round_style) -- rounding - return ufixed is - variable result : ufixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_ufixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function to_ufixed; - - function to_sfixed ( - arg : SIGNED; -- signed - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default - return sfixed is - variable result : sfixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_sfixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function to_sfixed; - - function resize ( - arg : ufixed; -- input - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow - constant round_style : BOOLEAN := fixed_round_style) -- rounding - return ufixed is - variable result : ufixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := resize (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function resize; - - function resize ( - arg : sfixed; -- input - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow - constant round_style : BOOLEAN := fixed_round_style) -- rounding - return sfixed is - variable result : sfixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := resize (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function resize; - - -- Overloaded functions - function "+" ( - l : ufixed; -- fixed point input - r : REAL) - return ufixed is - begin - return (l + - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "+"; - - function "+" ( - l : REAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - + r); - end function "+"; - - function "+" ( - l : sfixed; -- fixed point input - r : REAL) - return sfixed is - begin - return (l + - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "+"; - - function "+" ( - l : REAL; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - + r); - end function "+"; - - -- Overloaded functions - function "-" ( - l : ufixed; -- fixed point input - r : REAL) - return ufixed is - begin - return (l - - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "-"; - - function "-" ( - l : REAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - - r); - end function "-"; - - function "-" ( - l : sfixed; -- fixed point input - r : REAL) - return sfixed is - begin - return (l - - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "-"; - - function "-" ( - l : REAL; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - - r); - end function "-"; - - -- Overloaded functions - function "*" ( - l : ufixed; -- fixed point input - r : REAL) - return ufixed is - begin - return (l * - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "*"; - - function "*" ( - l : REAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - * r); - end function "*"; - - function "*" ( - l : sfixed; -- fixed point input - r : REAL) - return sfixed is - begin - return (l * - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "*"; - - function "*" ( - l : REAL; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - * r); - end function "*"; - - -- Overloaded functions - function "/" ( - l : ufixed; -- fixed point input - r : REAL) - return ufixed is - begin - return (l / - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "/"; - - function "/" ( - l : REAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - / r); - end function "/"; - - function "/" ( - l : sfixed; -- fixed point input - r : REAL) - return sfixed is - begin - return (l / - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "/"; - - function "/" ( - l : REAL; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - / r); - end function "/"; - - -- Overloaded functions - function "rem" ( - l : ufixed; -- fixed point input - r : REAL) - return ufixed is - begin - return (l rem - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "rem"; - - function "rem" ( - l : REAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - rem r); - end function "rem"; - - function "rem" ( - l : sfixed; -- fixed point input - r : REAL) - return sfixed is - begin - return (l rem - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "rem"; - - function "rem" ( - l : REAL; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - rem r); - end function "rem"; - - function "mod" ( - l : ufixed; -- fixed point input - r : REAL) - return ufixed is - begin - return (l mod - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "mod"; - - function "mod" ( - l : REAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - mod r); - end function "mod"; - - function "mod" ( - l : sfixed; -- fixed point input - r : REAL) - return sfixed is - begin - return (l mod - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "mod"; - - function "mod" ( - l : REAL; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - mod r); - end function "mod"; - - -- Overloaded functions for integers - function "+" ( - l : ufixed; -- fixed point input - r : NATURAL) - return ufixed is - begin - return (l + to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); -- rounding not needed - end function "+"; - - function "+" ( - l : NATURAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - + r); - end function "+"; - - function "+" ( - l : sfixed; -- fixed point input - r : INTEGER) - return sfixed is - begin - return (l + to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "+"; - - function "+" ( - l : INTEGER; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - + r); - end function "+"; - - -- Overloaded functions - function "-" ( - l : ufixed; -- fixed point input - r : NATURAL) - return ufixed is - begin - return (l - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "-"; - - function "-" ( - l : NATURAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - - r); - end function "-"; - - function "-" ( - l : sfixed; -- fixed point input - r : INTEGER) - return sfixed is - begin - return (l - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "-"; - - function "-" ( - l : INTEGER; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - - r); - end function "-"; - - -- Overloaded functions - function "*" ( - l : ufixed; -- fixed point input - r : NATURAL) - return ufixed is - begin - return (l * to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "*"; - - function "*" ( - l : NATURAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - * r); - end function "*"; - - function "*" ( - l : sfixed; -- fixed point input - r : INTEGER) - return sfixed is - begin - return (l * to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "*"; - - function "*" ( - l : INTEGER; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - * r); - end function "*"; - - -- Overloaded functions - function "/" ( - l : ufixed; -- fixed point input - r : NATURAL) - return ufixed is - begin - return (l / to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "/"; - - function "/" ( - l : NATURAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - / r); - end function "/"; - - function "/" ( - l : sfixed; -- fixed point input - r : INTEGER) - return sfixed is - begin - return (l / to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "/"; - - function "/" ( - l : INTEGER; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - / r); - end function "/"; - - -- Overloaded functions - function "rem" ( - l : ufixed; -- fixed point input - r : NATURAL) - return ufixed is - begin - return (l rem to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "rem"; - - function "rem" ( - l : NATURAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - rem r); - end function "rem"; - - function "rem" ( - l : sfixed; -- fixed point input - r : INTEGER) - return sfixed is - begin - return (l rem to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "rem"; - - function "rem" ( - l : INTEGER; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - rem r); - end function "rem"; - - function "mod" ( - l : ufixed; -- fixed point input - r : NATURAL) - return ufixed is - begin - return (l mod to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "mod"; - - function "mod" ( - l : NATURAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - mod r); - end function "mod"; - - function "mod" ( - l : sfixed; -- fixed point input - r : INTEGER) - return sfixed is - begin - return (l mod to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "mod"; - - function "mod" ( - l : INTEGER; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - mod r); - end function "mod"; - - -- overloaded compare functions - function "=" ( - l : ufixed; - r : NATURAL) -- fixed point input - return BOOLEAN is - begin - return (l = to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "="; - - function "/=" ( - l : ufixed; - r : NATURAL) -- fixed point input - return BOOLEAN is - begin - return (l /= to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "/="; - - function ">=" ( - l : ufixed; - r : NATURAL) -- fixed point input - return BOOLEAN is - begin - return (l >= to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function ">="; - - function "<=" ( - l : ufixed; - r : NATURAL) -- fixed point input - return BOOLEAN is - begin - return (l <= to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "<="; - - function ">" ( - l : ufixed; - r : NATURAL) -- fixed point input - return BOOLEAN is - begin - return (l > to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function ">"; - - function "<" ( - l : ufixed; - r : NATURAL) -- fixed point input - return BOOLEAN is - begin - return (l < to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "<"; - - function "=" ( - l : NATURAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - = r); - end function "="; - - function "/=" ( - l : NATURAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - /= r); - end function "/="; - - function ">=" ( - l : NATURAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - >= r); - end function ">="; - - function "<=" ( - l : NATURAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - <= r); - end function "<="; - - function ">" ( - l : NATURAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - > r); - end function ">"; - - function "<" ( - l : NATURAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - < r); - end function "<"; - - function "=" ( - l : ufixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l = - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "="; - - function "/=" ( - l : ufixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l /= - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "/="; - - function ">=" ( - l : ufixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l >= - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function ">="; - - function "<=" ( - l : ufixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l <= - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "<="; - - function ">" ( - l : ufixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l > - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function ">"; - - function "<" ( - l : ufixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l < - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "<"; - - function "=" ( - l : REAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - = r); - end function "="; - - function "/=" ( - l : REAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - /= r); - end function "/="; - - function ">=" ( - l : REAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - >= r); - end function ">="; - - function "<=" ( - l : REAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - <= r); - end function "<="; - - function ">" ( - l : REAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - > r); - end function ">"; - - function "<" ( - l : REAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - < r); - end function "<"; - - function "=" ( - l : sfixed; - r : INTEGER) -- fixed point input - return BOOLEAN is - begin - return (l = to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "="; - - function "/=" ( - l : sfixed; - r : INTEGER) -- fixed point input - return BOOLEAN is - begin - return (l /= to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "/="; - - function ">=" ( - l : sfixed; - r : INTEGER) -- fixed point input - return BOOLEAN is - begin - return (l >= to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function ">="; - - function "<=" ( - l : sfixed; - r : INTEGER) -- fixed point input - return BOOLEAN is - begin - return (l <= to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "<="; - - function ">" ( - l : sfixed; - r : INTEGER) -- fixed point input - return BOOLEAN is - begin - return (l > to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function ">"; - - function "<" ( - l : sfixed; - r : INTEGER) -- fixed point input - return BOOLEAN is - begin - return (l < to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "<"; - - function "=" ( - l : INTEGER; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - = r); - end function "="; - - function "/=" ( - l : INTEGER; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - /= r); - end function "/="; - - function ">=" ( - l : INTEGER; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - >= r); - end function ">="; - - function "<=" ( - l : INTEGER; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - <= r); - end function "<="; - - function ">" ( - l : INTEGER; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - > r); - end function ">"; - - function "<" ( - l : INTEGER; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - < r); - end function "<"; - - function "=" ( - l : sfixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l = - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "="; - - function "/=" ( - l : sfixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l /= - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "/="; - - function ">=" ( - l : sfixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l >= - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function ">="; - - function "<=" ( - l : sfixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l <= - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "<="; - - function ">" ( - l : sfixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l > - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function ">"; - - function "<" ( - l : sfixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l < - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "<"; - - function "=" ( - l : REAL; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - = r); - end function "="; - - function "/=" ( - l : REAL; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - /= r); - end function "/="; - - function ">=" ( - l : REAL; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - >= r); - end function ">="; - - function "<=" ( - l : REAL; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - <= r); - end function "<="; - - function ">" ( - l : REAL; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - > r); - end function ">"; - - function "<" ( - l : REAL; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - < r); - end function "<"; - - -- rtl_synthesis off - -- synthesis translate_off - -- copied from std_logic_textio - type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error); - type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER; - type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC; - type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus; - - constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-"; - constant char_to_MVL9 : MVL9_indexed_by_char := - ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', - 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U'); - constant char_to_MVL9plus : MVL9plus_indexed_by_char := - ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', - 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error); - constant NBSP : CHARACTER := CHARACTER'val(160); -- space character - constant NUS : STRING(2 to 1) := (others => ' '); - - -- purpose: writes fixed point into a line - procedure write ( - L : inout LINE; -- input line - VALUE : in ufixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0) is - variable s : STRING(1 to value'length +1) := (others => ' '); - variable sindx : INTEGER; - begin -- function write Example: 0011.1100 - sindx := 1; - for i in value'high downto value'low loop - if i = -1 then - s(sindx) := '.'; - sindx := sindx +1; - end if; - s(sindx) := MVL9_to_char(STD_ULOGIC(value(i))); - sindx := sindx +1; - end loop; - write(l, s, justified, field); - end procedure write; - - -- purpose: writes fixed point into a line - procedure write ( - L : inout LINE; -- input line - VALUE : in sfixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0) is - variable s : STRING(1 to value'length +1); - variable sindx : INTEGER; - begin -- function write Example: 0011.1100 - sindx := 1; - for i in value'high downto value'low loop - if i = -1 then - s(sindx) := '.'; - sindx := sindx +1; - end if; - s(sindx) := MVL9_to_char(STD_ULOGIC(value(i))); - sindx := sindx +1; - end loop; - write(l, s, justified, field); - end procedure write; - - procedure READ(L : inout LINE; - VALUE : out ufixed) is - -- Possible data: 00000.0000000 - -- 000000000000 - variable c : CHARACTER; - variable s : STRING(1 to value'length-1); - variable readOk : BOOLEAN; - variable i : INTEGER; -- index variable - begin -- READ - VALUE (VALUE'range) := (others => 'U'); - loop -- skip white space - read(l, c, readOk); - exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - i := value'high; - readloop : loop - if readOk = false then -- Bail out if there was a bad read - report "FIXED_GENERIC_PKG.READ(ufixed) " - & "Error: end of string encountered" - severity error; - return; - elsif c = ' ' or c = NBSP or c = HT then -- reading done. - assert i = value'low - report "FIXED_GENERIC_PKG.READ(ufixed) " - & "Warning: Value truncated " severity warning; - return; - elsif c = '.' then -- separator, ignore - assert (i = -1) - report "FIXED_GENERIC_PKG.READ(ufixed) " - & "Warning: Decimal point does not match number format " - severity warning; - elsif (char_to_MVL9plus(c) = error) then - report "FIXED_GENERIC_PKG.READ(ufixed) " - & "Error: Character '" & c & "' read, expected STD_ULOGIC literal." - severity error; - return; - else - value (i) := char_to_MVL9(c); - i := i - 1; - if i < value'low then - return; - end if; - end if; - read(l, c, readOk); - end loop readloop; - end procedure READ; - - procedure READ(L : inout LINE; - VALUE : out ufixed; - GOOD : out BOOLEAN) is - -- Possible data: 00000.0000000 - -- 000000000000 - variable c : CHARACTER; - variable i : INTEGER; -- index variable - variable readOk : BOOLEAN; - begin -- READ - VALUE (VALUE'range) := (others => 'U'); - loop -- skip white space - read(l, c, readOk); - exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - i := value'high; - good := true; - readloop : loop - if readOk = false then -- Bail out if there was a bad read - good := false; - return; - elsif c = ' ' or c = NBSP or c = HT then -- reading done - good := false; - return; - elsif c = '.' then -- separator, ignore - good := (i = -1); - elsif (char_to_MVL9plus(c) = error) then - good := false; - return; - else - value (i) := char_to_MVL9(c); - i := i - 1; - if i < value'low then - return; - end if; - end if; - read(l, c, readOk); - end loop readloop; - end procedure READ; - - procedure READ(L : inout LINE; - VALUE : out sfixed) is - -- Possible data: 00000.0000000 - -- 000000000000 - variable c : CHARACTER; - variable readOk : BOOLEAN; - variable i : INTEGER; -- index variable - begin -- READ - VALUE (VALUE'range) := (others => 'U'); - loop -- skip white space - read(l, c, readOk); - exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - i := value'high; - readloop : loop - if readOk = false then -- Bail out if there was a bad read - report "FIXED_GENERIC_PKG.READ(sfixed) " - & "Error end of string encountered" - severity error; - return; - elsif c = ' ' or c = NBSP or c = HT then -- reading done. - assert i = value'low - report "FIXED_GENERIC_PKG.READ(sfixed) " - & "Warning: Value truncated " severity warning; - return; - elsif c = '.' then -- separator, ignore - assert (i = -1) - report "FIXED_GENERIC_PKG.READ(sfixed) " - & "Warning: Decimal point does not match number format " - severity warning; - elsif (char_to_MVL9plus(c) = error) then - report "FIXED_GENERIC_PKG.READ(sfixed) " - & "Error: Character '" & c & "' read, expected STD_ULOGIC literal." - severity error; - return; - else - value (i) := char_to_MVL9(c); - i := i - 1; - if i < value'low then - return; - end if; - end if; - read(l, c, readOk); - end loop readloop; - end procedure READ; - - procedure READ(L : inout LINE; - VALUE : out sfixed; - GOOD : out BOOLEAN) is - -- Possible data: 00000.0000000 - -- 000000000000 - variable c : CHARACTER; - variable i : INTEGER; -- index variable - variable readOk : BOOLEAN; - begin -- READ - VALUE (VALUE'range) := (others => 'U'); - loop -- skip white space - read(l, c, readOk); - exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - i := value'high; - good := true; - readloop : loop - if readOk = false then -- Bail out if there was a bad read - good := false; - return; - elsif c = ' ' or c = NBSP or c = HT then -- reading done - good := false; - return; - elsif c = '.' then -- separator, ignore - good := (i = -1); - elsif (char_to_MVL9plus(c) = error) then - good := false; - return; - else - value (i) := char_to_MVL9(c); - i := i - 1; - if i < value'low then - return; - end if; - end if; - read(l, c, readOk); - end loop readloop; - end procedure READ; - - -- octal read and write - procedure owrite ( - L : inout LINE; -- input line - VALUE : in ufixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0) is - begin -- Example 03.30 - write (L => L, - VALUE => to_ostring (VALUE), - JUSTIFIED => JUSTIFIED, - FIELD => FIELD); - end procedure owrite; - - procedure owrite ( - L : inout LINE; -- input line - VALUE : in sfixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0) is - begin -- Example 03.30 - write (L => L, - VALUE => to_ostring (VALUE), - JUSTIFIED => JUSTIFIED, - FIELD => FIELD); - end procedure owrite; - - procedure Char2TriBits (C : CHARACTER; - RESULT : out STD_LOGIC_VECTOR(2 downto 0); - GOOD : out BOOLEAN; - ISSUE_ERROR : in BOOLEAN) is - begin - case c is - when '0' => result := o"0"; good := true; - when '1' => result := o"1"; good := true; - when '2' => result := o"2"; good := true; - when '3' => result := o"3"; good := true; - when '4' => result := o"4"; good := true; - when '5' => result := o"5"; good := true; - when '6' => result := o"6"; good := true; - when '7' => result := o"7"; good := true; - when 'Z' => result := "ZZZ"; good := true; - when 'X' => result := "XXX"; good := true; - when others => - assert not ISSUE_ERROR - report - "FIXED_GENERIC_PKG.OREAD Error: Read a '" & c & - "', expected an Octal character (0-7)." - severity error; - result := "UUU"; - good := false; - end case; - end procedure Char2TriBits; - - -- Note that for Octal and Hex read, you can not start with a ".", - -- the read is for numbers formatted "A.BC". These routines go to - -- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3). - procedure OREAD(L : inout LINE; - VALUE : out ufixed) is - constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1; - constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : ufixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - report "FIXED_GENERIC_PKG.OREAD(ufixed): " - & "Error end of string encountered" - severity error; - return; - else - Char2triBits(c, nybble, igood, true); - i := hbv-lbv - 3; -- Top - 3 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood = false then - report "FIXED_GENERIC_PKG.OREAD(ufixed): " - & "Error end of string encountered" - severity error; - elsif (c = '.') then - if (i + 1 /= -lbv) then - igood := false; - report "FIXED_GENERIC_PKG.OREAD(ufixed): " - & "encountered ""."" at wrong index" - severity error; - end if; - else - Char2TriBits(c, nybble, igood, true); - slv (i downto i-2) := nybble; - i := i - 3; - end if; - end loop; - if igood then -- We did not get another error - assert (i = -1) and -- We read everything, and high bits 0 - (or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') - report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated." - severity error; - if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then - assert NO_WARNING - report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated" - severity warning; - end if; - end if; - valuex := to_ufixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure OREAD; - - procedure OREAD(L : inout LINE; - VALUE : out ufixed; - GOOD : out BOOLEAN) is - constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1; - constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : ufixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - return; - else - Char2triBits(c, nybble, igood, false); - i := hbv-lbv - 3; -- Top - 3 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood then - if (c = '.') then - igood := igood and (i + 1 = -lbv); - else - Char2TriBits(c, nybble, igood, false); - slv (i downto i-2) := nybble; - i := i - 3; - end if; - end if; - end loop; - good := igood and -- We did not get another error - (i = -1) and -- We read everything, and high bits 0 - (or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0'); - valuex := to_ufixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure OREAD; - - procedure OREAD(L : inout LINE; - VALUE : out sfixed) is - constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1; - constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : sfixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - report "FIXED_GENERIC_PKG.OREAD(sfixed): " - & "Error end of string encountered" - severity error; - return; - else - Char2triBits(c, nybble, igood, true); - i := hbv-lbv - 3; -- Top - 3 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood = false then - report "FIXED_GENERIC_PKG.OREAD(sfixed): " - & "Error end of string encountered" - severity error; - elsif (c = '.') then - if (i + 1 /= -lbv) then - igood := false; - report "FIXED_GENERIC_PKG.OREAD(sfixed): " - & "encountered ""."" at wrong index" - severity error; - end if; - else - Char2TriBits(c, nybble, igood, true); - slv (i downto i-2) := nybble; - i := i - 3; - end if; - end loop; - if igood then -- We did not get another error - assert (i = -1) and -- We read everything - ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits - or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or - (slv(VALUE'high-lbv) = '1' and - and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1')) - report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated." - severity error; - if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then - assert NO_WARNING - report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated" - severity warning; - end if; - end if; - valuex := to_sfixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure OREAD; - - procedure OREAD(L : inout LINE; - VALUE : out sfixed; - GOOD : out BOOLEAN) is - constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1; - constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : sfixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - return; - else - Char2triBits(c, nybble, igood, false); - i := hbv-lbv - 3; -- Top - 3 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood then - if (c = '.') then - igood := igood and (i + 1 = -lbv); - else - Char2TriBits(c, nybble, igood, false); - slv (i downto i-2) := nybble; - i := i - 3; - end if; - end if; - end loop; - good := igood -- We did not get another error - and (i = -1) -- We read everything - and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits - or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or - (slv(VALUE'high-lbv) = '1' and - and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1')); - valuex := to_sfixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure OREAD; - - -- hex read and write - procedure hwrite ( - L : inout LINE; -- input line - VALUE : in ufixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0) is - begin -- Example 03.30 - write (L => L, - VALUE => to_hstring (VALUE), - JUSTIFIED => JUSTIFIED, - FIELD => FIELD); - end procedure hwrite; - - -- purpose: writes fixed point into a line - procedure hwrite ( - L : inout LINE; -- input line - VALUE : in sfixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0) is - begin -- Example 03.30 - write (L => L, - VALUE => to_hstring (VALUE), - JUSTIFIED => JUSTIFIED, - FIELD => FIELD); - end procedure hwrite; - - -- Hex Read and Write procedures for STD_ULOGIC_VECTOR. - -- Modified from the original to be more forgiving. - - procedure Char2QuadBits (C : CHARACTER; - RESULT : out STD_LOGIC_VECTOR(3 downto 0); - GOOD : out BOOLEAN; - ISSUE_ERROR : in BOOLEAN) is - begin - case c is - when '0' => result := x"0"; good := true; - when '1' => result := x"1"; good := true; - when '2' => result := x"2"; good := true; - when '3' => result := x"3"; good := true; - when '4' => result := x"4"; good := true; - when '5' => result := x"5"; good := true; - when '6' => result := x"6"; good := true; - when '7' => result := x"7"; good := true; - when '8' => result := x"8"; good := true; - when '9' => result := x"9"; good := true; - when 'A' | 'a' => result := x"A"; good := true; - when 'B' | 'b' => result := x"B"; good := true; - when 'C' | 'c' => result := x"C"; good := true; - when 'D' | 'd' => result := x"D"; good := true; - when 'E' | 'e' => result := x"E"; good := true; - when 'F' | 'f' => result := x"F"; good := true; - when 'Z' => result := "ZZZZ"; good := true; - when 'X' => result := "XXXX"; good := true; - when others => - assert not ISSUE_ERROR - report - "FIXED_GENERIC_PKG.HREAD Error: Read a '" & c & - "', expected a Hex character (0-F)." - severity error; - result := "UUUU"; - good := false; - end case; - end procedure Char2QuadBits; - - procedure HREAD(L : inout LINE; - VALUE : out ufixed) is - constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1; - constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : ufixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - report "FIXED_GENERIC_PKG.HREAD(ufixed): " - & "Error end of string encountered" - severity error; - return; - else - Char2QuadBits(c, nybble, igood, true); - i := hbv-lbv - 4; -- Top - 4 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood = false then - report "FIXED_GENERIC_PKG.HREAD(ufixed): " - & "Error end of string encountered" - severity error; - elsif (c = '.') then - if (i + 1 /= -lbv) then - igood := false; - report "FIXED_GENERIC_PKG.HREAD(ufixed): " - & "encountered ""."" at wrong index" - severity error; - end if; - else - Char2QuadBits(c, nybble, igood, true); - slv (i downto i-3) := nybble; - i := i - 4; - end if; - end loop; - if igood then -- We did not get another error - assert (i = -1) and -- We read everything, and high bits 0 - (or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') - report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated." - severity error; - if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then - assert NO_WARNING - report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated" - severity warning; - end if; - end if; - valuex := to_ufixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure HREAD; - - procedure HREAD(L : inout LINE; - VALUE : out ufixed; - GOOD : out BOOLEAN) is - constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1; - constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : ufixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - return; - else - Char2QuadBits(c, nybble, igood, false); - i := hbv-lbv - 4; -- Top - 4 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood then - if (c = '.') then - igood := igood and (i + 1 = -lbv); - else - Char2QuadBits(c, nybble, igood, false); - slv (i downto i-3) := nybble; - i := i - 4; - end if; - end if; - end loop; - good := igood and -- We did not get another error - (i = -1) and -- We read everything, and high bits 0 - (or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0'); - valuex := to_ufixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure HREAD; - - procedure HREAD(L : inout LINE; - VALUE : out sfixed) is - constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1; - constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : sfixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - report "FIXED_GENERIC_PKG.HREAD(sfixed): " - & "Error end of string encountered" - severity error; - return; - else - Char2QuadBits(c, nybble, igood, true); - i := hbv-lbv - 4; -- Top - 4 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood = false then - report "FIXED_GENERIC_PKG.HREAD(sfixed): " - & "Error end of string encountered" - severity error; - elsif (c = '.') then - if (i + 1 /= -lbv) then - igood := false; - report "FIXED_GENERIC_PKG.HREAD(sfixed): " - & "encountered ""."" at wrong index" - severity error; - end if; - else - Char2QuadBits(c, nybble, igood, true); - slv (i downto i-3) := nybble; - i := i - 4; - end if; - end loop; - if igood then -- We did not get another error - assert (i = -1) -- We read everything - and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits - or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or - (slv(VALUE'high-lbv) = '1' and - and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1')) - report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated." - severity error; - if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then - assert NO_WARNING - report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated" - severity warning; - end if; - end if; - valuex := to_sfixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure HREAD; - - procedure HREAD(L : inout LINE; - VALUE : out sfixed; - GOOD : out BOOLEAN) is - constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1; - constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : sfixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - return; - else - Char2QuadBits(c, nybble, igood, false); - i := hbv-lbv - 4; -- Top - 4 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood then - if (c = '.') then - igood := igood and (i + 1 = -lbv); - else - Char2QuadBits(c, nybble, igood, false); - slv (i downto i-3) := nybble; - i := i - 4; - end if; - end if; - end loop; - good := igood and -- We did not get another error - (i = -1) and -- We read everything - ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits - or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or - (slv(VALUE'high-lbv) = '1' and - and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1')); - valuex := to_sfixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure HREAD; - - ----------------------------------------------------------------------------- - -- %%% Remove the following 3 functions. They are a duplicate needed for - -- testing - ----------------------------------------------------------------------------- - -- purpose: Justify a string to the right - function justify ( - value : STRING; - justified : SIDE := right; - field : width := 0) - return STRING is - constant VAL_LEN : INTEGER := value'length; - variable result : STRING (1 to field) := (others => ' '); - begin -- function justify - -- return value if field is too small - if VAL_LEN >= field then - return value; - end if; - if justified = left then - result(1 to VAL_LEN) := value; - elsif justified = right then - result(field - VAL_LEN + 1 to field) := value; - end if; - return result; - end function justify; - - function to_ostring ( - value : STD_LOGIC_VECTOR; - justified : SIDE := right; - field : width := 0 - ) return STRING is - constant ne : INTEGER := (value'length+2)/3; - variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1); - variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1); - variable result : STRING(1 to ne); - variable tri : STD_LOGIC_VECTOR(0 to 2); - begin - if value'length < 1 then - return NUS; - else - if value (value'left) = 'Z' then - pad := (others => 'Z'); - else - pad := (others => '0'); - end if; - ivalue := pad & value; - for i in 0 to ne-1 loop - tri := To_X01Z(ivalue(3*i to 3*i+2)); - case tri is - when o"0" => result(i+1) := '0'; - when o"1" => result(i+1) := '1'; - when o"2" => result(i+1) := '2'; - when o"3" => result(i+1) := '3'; - when o"4" => result(i+1) := '4'; - when o"5" => result(i+1) := '5'; - when o"6" => result(i+1) := '6'; - when o"7" => result(i+1) := '7'; - when "ZZZ" => result(i+1) := 'Z'; - when others => result(i+1) := 'X'; - end case; - end loop; - return justify(result, justified, field); - end if; - end function to_ostring; - ------------------------------------------------------------------- - function to_hstring ( - value : STD_LOGIC_VECTOR; - justified : SIDE := right; - field : width := 0 - ) return STRING is - constant ne : INTEGER := (value'length+3)/4; - variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1); - variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1); - variable result : STRING(1 to ne); - variable quad : STD_LOGIC_VECTOR(0 to 3); - begin - if value'length < 1 then - return NUS; - else - if value (value'left) = 'Z' then - pad := (others => 'Z'); - else - pad := (others => '0'); - end if; - ivalue := pad & value; - for i in 0 to ne-1 loop - quad := To_X01Z(ivalue(4*i to 4*i+3)); - case quad is - when x"0" => result(i+1) := '0'; - when x"1" => result(i+1) := '1'; - when x"2" => result(i+1) := '2'; - when x"3" => result(i+1) := '3'; - when x"4" => result(i+1) := '4'; - when x"5" => result(i+1) := '5'; - when x"6" => result(i+1) := '6'; - when x"7" => result(i+1) := '7'; - when x"8" => result(i+1) := '8'; - when x"9" => result(i+1) := '9'; - when x"A" => result(i+1) := 'A'; - when x"B" => result(i+1) := 'B'; - when x"C" => result(i+1) := 'C'; - when x"D" => result(i+1) := 'D'; - when x"E" => result(i+1) := 'E'; - when x"F" => result(i+1) := 'F'; - when "ZZZZ" => result(i+1) := 'Z'; - when others => result(i+1) := 'X'; - end case; - end loop; - return justify(result, justified, field); - end if; - end function to_hstring; - -- %%% End remove here - - function to_string ( - value : ufixed; - justified : SIDE := right; - field : width := 0 - ) return STRING is - variable s : STRING(1 to value'length +1) := (others => ' '); - variable sindx : INTEGER; - begin - if value'length < 1 then - return NUS; - else - if value'high < 0 then - return to_string (resize (value, 0, value'low), justified, field); - elsif value'low > 0 then - return to_string (resize (value, value'high, -1), justified, field); - else - sindx := 1; - for i in value'high downto value'low loop - if i = -1 then - s(sindx) := '.'; - sindx := sindx +1; - end if; - s(sindx) := MVL9_to_char(STD_ULOGIC(value(i))); - sindx := sindx +1; - end loop; - return justify(s, justified, field); - end if; - end if; - end function to_string; - - function to_string ( - value : sfixed; - justified : SIDE := right; - field : width := 0 - ) return STRING is - variable s : STRING(1 to value'length +1) := (others => ' '); - variable sindx : INTEGER; - begin - if value'length < 1 then - return NUS; - else - if value'high < 0 then - return to_string (resize (value, 0, value'low), justified, field); - elsif value'low > 0 then - return to_string (resize (value, value'high, -1), justified, field); - else - sindx := 1; - for i in value'high downto value'low loop - if i = -1 then - s(sindx) := '.'; - sindx := sindx +1; - end if; - s(sindx) := MVL9_to_char(STD_ULOGIC(value(i))); - sindx := sindx +1; - end loop; - return justify(s, justified, field); - end if; - end if; - end function to_string; - - function to_ostring ( - value : ufixed; - justified : SIDE := right; - field : width := 0 - ) return STRING is - constant lne : INTEGER := (-VALUE'low+2)/3; - constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) := - (others => '0'); - variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); - begin - if value'length < 1 then - return NUS; - else - if value'high < 0 then - return to_ostring (resize (value, 2, value'low), justified, field); - elsif value'low > 0 then - return to_ostring (resize (value, value'high, -3), justified, field); - else - slv := to_slv (value); - return justify(to_ostring(slv(slv'high downto slv'high-VALUE'high)) - & "." - & to_ostring(slv(slv'high-VALUE'high-1 downto 0)&lpad), - justified, field); - end if; - end if; - end function to_ostring; - - function to_hstring ( - value : ufixed; - justified : SIDE := right; - field : width := 0 - ) return STRING is - constant lne : INTEGER := (-VALUE'low+3)/4; - constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) := - (others => '0'); - variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); - begin - if value'length < 1 then - return NUS; - else - if value'high < 0 then - return to_hstring (resize (value, 3, value'low), justified, field); - elsif value'low > 0 then - return to_hstring (resize (value, value'high, -4), justified, field); - else - slv := to_slv (value); - return justify(to_hstring(slv(slv'high downto slv'high-VALUE'high)) - & "." - & to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad), - justified, field); - end if; - end if; - end function to_hstring; - - function to_ostring ( - value : sfixed; - justified : SIDE := right; - field : width := 0 - ) return STRING is - constant ne : INTEGER := ((value'high+1)+2)/3; - variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1); - constant lne : INTEGER := (-VALUE'low+2)/3; - constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) := - (others => '0'); - variable slv : STD_LOGIC_VECTOR (VALUE'high - VALUE'low downto 0); - begin - if value'length < 1 then - return NUS; - else - pad := (others => value(value'high)); - if value'high < 0 then - return to_ostring (resize (value, 2, value'low), justified, field); - elsif value'low > 0 then - return to_ostring (resize (value, value'high, -3), justified, field); - else - slv := to_slv (value); - return justify(to_ostring(pad - & slv(slv'high downto slv'high-VALUE'high)) - & "." - & to_ostring(slv(slv'high-VALUE'high-1 downto 0) - & lpad), - justified, field); - end if; - end if; - end function to_ostring; - - function to_hstring ( - value : sfixed; - justified : SIDE := right; - field : width := 0 - ) return STRING is - constant ne : INTEGER := ((value'high+1)+3)/4; - variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1); - constant lne : INTEGER := (-VALUE'low+3)/4; - constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) := - (others => '0'); - variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); - begin - if value'length < 1 then - return NUS; - else - pad := (others => value(value'high)); - if value'high < 0 then - return to_hstring (resize (value, 3, value'low), justified, field); - elsif value'low > 0 then - return to_hstring (resize (value, value'high, -4), justified, field); - else - slv := to_slv (value); - return justify(to_hstring(pad&slv(slv'high downto slv'high-VALUE'high)) - & "." - & to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad), - justified, field); - end if; - end if; - end function to_hstring; - - -- From string functions allow you to convert a string into a fixed - -- point number. Example: - -- signal uf1 : ufixed (3 downto -3); - -- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5 - -- The "." is optional in this syntax, however it exist and is - -- in the wrong location an error is produced. Overflow will - -- result in saturation. - function from_string ( - bstring : STRING; -- binary string - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed is - variable result : ufixed (left_index downto right_index); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(bstring); - read (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - return result; - end function from_string; - - -- Octal and hex conversions work as follows: - -- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped) - -- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped) - function from_ostring ( - ostring : STRING; -- Octal string - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed is - variable result : ufixed (left_index downto right_index); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(ostring); - oread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - return result; - end function from_ostring; - - function from_hstring ( - hstring : STRING; -- hex string - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed is - variable result : ufixed (left_index downto right_index); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(hstring); - hread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - return result; - end function from_hstring; - - function from_string ( - bstring : STRING; -- binary string - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed is - variable result : sfixed (left_index downto right_index); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(bstring); - read (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - return result; - end function from_string; - - function from_ostring ( - ostring : STRING; -- Octal string - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed is - variable result : sfixed (left_index downto right_index); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(ostring); - oread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - return result; - end function from_ostring; - - function from_hstring ( - hstring : STRING; -- hex string - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed is - variable result : sfixed (left_index downto right_index); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(hstring); - hread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - return result; - end function from_hstring; - - -- Same as above, "size_res" is used for it's range only. - function from_string ( - bstring : STRING; -- binary string - size_res : ufixed) - return ufixed is - variable result : ufixed (size_res'high downto size_res'low); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(bstring); - read (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - return result; - end function from_string; - - function from_ostring ( - ostring : STRING; -- Octal string - size_res : ufixed) - return ufixed is - variable result : ufixed (size_res'high downto size_res'low); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(ostring); - oread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - return result; - end function from_ostring; - - function from_hstring ( - hstring : STRING; -- hex string - size_res : ufixed) - return ufixed is - variable result : ufixed (size_res'high downto size_res'low); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(hstring); - hread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - return result; - end function from_hstring; - - function from_string ( - bstring : STRING; -- binary string - size_res : sfixed) - return sfixed is - variable result : sfixed (size_res'high downto size_res'low); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(bstring); - read (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - return result; - end function from_string; - - function from_ostring ( - ostring : STRING; -- Octal string - size_res : sfixed) - return sfixed is - variable result : sfixed (size_res'high downto size_res'low); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(ostring); - oread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - return result; - end function from_ostring; - - function from_hstring ( - hstring : STRING; -- hex string - size_res : sfixed) - return sfixed is - variable result : sfixed (size_res'high downto size_res'low); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(hstring); - hread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - return result; - end function from_hstring; - - -- purpose: find a dot in a string, return -1 if no dot (internal function) - function finddot ( - arg : STRING) - return INTEGER is - alias xarg : STRING (arg'length downto 1) is arg; -- make it a downto - begin - for i in xarg'reverse_range loop - if (xarg(i) = '.') then - return i-1; - end if; - end loop; - return -1; - end function finddot; - - -- Direct converstion functions. Example: - -- signal uf1 : ufixed (3 downto -3); - -- uf1 <= from_string ("0110.100"); -- 6.5 - -- In this case the "." is not optional, and the size of - -- the output must match exactly. - function from_string ( - bstring : STRING) -- binary string - return ufixed is - variable result : ufixed (bstring'length-2 downto 0); - variable result_nodot : ufixed (bstring'length-1 downto 0); - variable bstring_nodot : STRING (1 to bstring'length-1); - variable L : LINE; - variable good : BOOLEAN; - variable dot, i, j : INTEGER; - begin - dot := finddot(bstring); - if (dot = -1) then - L := new STRING'(bstring); - read (L, result_nodot, good); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - deallocate (L); - return result_nodot; - else - j := 1; - for i in 1 to bstring'high loop - if (bstring(i) /= '.') then - bstring_nodot(j) := bstring(i); -- get rid of the dot. - j := j + 1; - end if; - end loop; - L := new STRING'(bstring_nodot); - read (L, result, good); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - deallocate (L); - return to_ufixed(to_slv(result), bstring'length-dot-2, -dot); - end if; - end function from_string; - - -- Direct octal and hex converstion functions. In this case - -- the string lengths must match. Example: - -- signal sf1 := sfixed (5 downto -3); - -- sf1 <= from_ostring ("71.4") -- -6.5 - function from_ostring ( - ostring : STRING) -- Octal string - return ufixed is - variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0); - variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0); - variable ostring_nodot : STRING (1 to ostring'length-1); - variable L : LINE; - variable good : BOOLEAN; - variable dot, i, j : INTEGER; - begin - dot := finddot(ostring); - if (dot = -1) then - L := new STRING'(ostring); - oread (L, result_nodot, good); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - deallocate (L); - return to_ufixed(UNSIGNED(result_nodot)); - else - j := 1; - for i in 1 to ostring'high loop - if (ostring(i) /= '.') then - ostring_nodot(j) := ostring(i); -- get rid of the dot. - j := j + 1; - end if; - end loop; - L := new STRING'(ostring_nodot); - oread (L, result, good); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - deallocate (L); - return to_ufixed(result, (ostring'length-1-dot)*3-1, -dot*3); - end if; - end function from_ostring; - - function from_hstring ( - hstring : STRING) -- hex string - return ufixed is - variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0); - variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0); - variable hstring_nodot : STRING (1 to hstring'length-1); - variable L : LINE; - variable good : BOOLEAN; - variable dot, i, j : INTEGER; - begin - dot := finddot(hstring); - if (dot = -1) then - L := new STRING'(hstring); - hread (L, result_nodot, good); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - deallocate (L); - return to_ufixed(UNSIGNED(result_nodot)); - else - j := 1; - for i in 1 to hstring'high loop - if (hstring(i) /= '.') then - hstring_nodot(j) := hstring(i); -- get rid of the dot. - j := j + 1; - end if; - end loop; - L := new STRING'(hstring_nodot); - hread (L, result, good); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - deallocate (L); - return to_ufixed(result, (hstring'length-1-dot)*4-1, -dot*4); - end if; - end function from_hstring; - - function from_string ( - bstring : STRING) -- binary string - return sfixed is - variable result : sfixed (bstring'length-2 downto 0); - variable result_nodot : sfixed (bstring'length-1 downto 0); - variable bstring_nodot : STRING (1 to bstring'length-1); - variable L : LINE; - variable good : BOOLEAN; - variable dot, i, j : INTEGER; - begin - dot := finddot(bstring); - if (dot = -1) then - L := new STRING'(bstring); - read (L, result_nodot, good); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - deallocate (L); - return result_nodot; - else - j := 1; - for i in 1 to bstring'high loop - if (bstring(i) /= '.') then - bstring_nodot(j) := bstring(i); -- get rid of the dot. - j := j + 1; - end if; - end loop; - L := new STRING'(bstring_nodot); - read (L, result, good); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - deallocate (L); - return to_sfixed(to_slv(result), bstring'length-dot-2, -dot); - end if; - end function from_string; - - function from_ostring ( - ostring : STRING) -- Octal string - return sfixed is - variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0); - variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0); - variable ostring_nodot : STRING (1 to ostring'length-1); - variable L : LINE; - variable good : BOOLEAN; - variable dot, i, j : INTEGER; - begin - dot := finddot(ostring); - if (dot = -1) then - L := new STRING'(ostring); - oread (L, result_nodot, good); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - deallocate (L); - return to_sfixed(SIGNED(result_nodot)); - else - j := 1; - for i in 1 to ostring'high loop - if (ostring(i) /= '.') then - ostring_nodot(j) := ostring(i); -- get rid of the dot. - j := j + 1; - end if; - end loop; - L := new STRING'(ostring_nodot); - oread (L, result, good); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - deallocate (L); - return to_sfixed(result, (ostring'length-1-dot)*3-1, -dot*3); - end if; - end function from_ostring; - - function from_hstring ( - hstring : STRING) -- hex string - return sfixed is - variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0); - variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0); - variable hstring_nodot : STRING (1 to hstring'length-1); - variable L : LINE; - variable good : BOOLEAN; - variable dot, i, j : INTEGER; - begin - dot := finddot(hstring); - if (dot = -1) then - L := new STRING'(hstring); - hread (L, result_nodot, good); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - deallocate (L); - return sfixed(SIGNED(result_nodot)); - else - j := 1; - for i in 1 to hstring'high loop - if (hstring(i) /= '.') then - hstring_nodot(j) := hstring(i); -- get rid of the dot. - j := j + 1; - end if; - end loop; - L := new STRING'(hstring_nodot); - hread (L, result, good); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - deallocate (L); - return to_sfixed(result, (hstring'length-1-dot)*4-1, -dot*4); - end if; - end function from_hstring; - --- synthesis translate_on --- rtl_synthesis on - function to_StdLogicVector ( - arg : ufixed) -- fp vector - return STD_LOGIC_VECTOR is - begin - return to_slv (arg); - end function to_StdLogicVector; - function to_Std_Logic_Vector ( - arg : ufixed) -- fp vector - return STD_LOGIC_VECTOR is - begin - return to_slv (arg); - end function to_Std_Logic_Vector; - function to_StdLogicVector ( - arg : sfixed) -- fp vector - return STD_LOGIC_VECTOR is - begin - return to_slv (arg); - end function to_StdLogicVector; - function to_Std_Logic_Vector ( - arg : sfixed) -- fp vector - return STD_LOGIC_VECTOR is - begin - return to_slv (arg); - end function to_Std_Logic_Vector; - function to_StdULogicVector ( - arg : ufixed) -- fp vector - return STD_ULOGIC_VECTOR is - begin - return to_sulv (arg); - end function to_StdULogicVector; - function to_Std_ULogic_Vector ( - arg : ufixed) -- fp vector - return STD_ULOGIC_VECTOR is - begin - return to_sulv (arg); - end function to_Std_ULogic_Vector; - function to_StdULogicVector ( - arg : sfixed) -- fp vector - return STD_ULOGIC_VECTOR is - begin - return to_sulv (arg); - end function to_StdULogicVector; - function to_Std_ULogic_Vector ( - arg : sfixed) -- fp vector - return STD_ULOGIC_VECTOR is - begin - return to_sulv (arg); - end function to_Std_ULogic_Vector; -end package body fixed_pkg; diff --git a/lib/fixed_ja/fixed_ja.vhd b/lib/fixed_ja/fixed_ja.vhd deleted file mode 100644 index bcd2700..0000000 --- a/lib/fixed_ja/fixed_ja.vhd +++ /dev/null @@ -1,322 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; - -package fixed_ja is - - - type ufixed_t is array (integer range <>) of STD_LOGIC; - type sfixed_t is array (integer range <>) of STD_LOGIC; - type ufixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC; - type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC; - - type round_mode_t is (none, round_to_zero, round_pos_infinity, round_neg_infinity, round_half_up, round_half_down, round_nearest, round_convergent); - type saturate_mode_t is (none, saturate); - - -- Declare functions and procedure - - constant ASSERT_NO_WARN : boolean := false; - constant default_round_mode : round_mode_t := none; - constant default_saturate_mode : saturate_mode_t := none; - - -- null array constants - constant NAUF : ufixed_t (0 downto 1) := (others => '0'); - constant NASF : sfixed_t (0 downto 1) := (others => '0'); - constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0'); - - -- Constructor helpers - -- Use: variable v8u2 : ufixed_t(ufixed(8,2)'range); - function uproto (nbits : integer; nbits_int : integer) return ufixed_t; - - -- Use: variable v8s2 : sfixed_t(sfixed(8,2)'range); - function sproto (nbits : integer; nbits_int : integer) return sfixed_t; - - function uproto (a : ufixed_t; op : character; b : ufixed_t) return ufixed_t; - function sproto (a : sfixed_t; op : character; b : sfixed_t) return sfixed_t; - - -- Conversion Functions - function to_ufixed(src : ufixed_t) return ufixed_t; - function to_sfixed(src : sfixed_t) return sfixed_t; - function to_ufixed(src : sfixed_t) return ufixed_t; - function to_sfixed(src : ufixed_t) return sfixed_t; - - function to_ufixed - ( - src : ufixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t; - - function to_ufixed - ( - src : ufixed_t; - proto : ufixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t; - - function to_sfixed - ( - src : sfixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t; - - function to_sfixed - ( - src : sfixed_t; - proto : sfixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t; - - -- fixed <= integer - function to_ufixed (src : integer; nbits : integer; nbits_int : integer) return ufixed_t; - function to_ufixed (src : integer; proto : ufixed_t) return ufixed_t; - - -- fixed <= integer - function to_sfixed (src : integer; nbits : integer; nbits_int : integer) return sfixed_t; - function to_sfixed (src : integer; proto : sfixed_t) return sfixed_t; - - -- ufixed <= unsigned - function to_ufixed (src : unsigned; nbits : integer; nbits_int : integer) return ufixed_t; - function to_ufixed (src : unsigned; proto : ufixed_t) return ufixed_t; - - -- sfixed <= signed - function to_sfixed (src : signed; nbits : integer; nbits_int : integer) return sfixed_t; - function to_sfixed (src : signed; proto : sfixed_t) return sfixed_t; - - -- fixed <= slv - function to_ufixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return ufixed_t; - function to_ufixed (src : STD_LOGIC_VECTOR; proto : ufixed_t) return ufixed_t; - function to_sfixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return sfixed_t; - function to_sfixed (src : STD_LOGIC_VECTOR; proto : sfixed_t) return sfixed_t; - - -- ufixed <= real - function to_ufixed - ( - src : real; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t; - - function to_ufixed - ( - src : real; - proto : ufixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t; - - -- sfixed <= real - function to_sfixed - ( - src : real; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t; - - function to_sfixed - ( - src : real; - proto : sfixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t; - - -- Slicing functions for unconstrained array types - function to_ufixed(src : ufixed_array_t; index : integer) return ufixed_t; - function to_sfixed(src : sfixed_array_t; index : integer) return sfixed_t; - - -- ufixed <= string - function to_ufixed (src : string) return ufixed_t; - - -- sfixed <= string - function to_sfixed (src : string) return sfixed_t; - - -- real <= ufixed - function to_real(src : ufixed_t) return real; - - -- real <= sfixed - function to_real(src : sfixed_t) return real; - - -- slv <= ufixed - function to_slv(src : ufixed_t) return std_logic_vector; - - -- slv <= sfixed - function to_slv(src : sfixed_t) return std_logic_vector; - - -- UNSIGNED <= ufixed - function to_unsigned (src : ufixed_t) return UNSIGNED; - - -- SIGNED <= sfixed - function to_signed (src : sfixed_t) return SIGNED; - - -- integer <= ufixed - function to_integer (src : ufixed_t) return integer; - - -- integer <= sfixed - function to_integer (src : sfixed_t) return integer; - - function to_string(src : ufixed_t) return string; - function to_string(src : sfixed_t) return string; - function to_string(src : std_logic_vector) return string; - - ------------------------------------------------------------- - -- Arithmetic shift left - ------------------------------------------------------------- - function "sla" (src : ufixed_t; count : integer) return ufixed_t; - function "sla" (src : sfixed_t; count : integer) return sfixed_t; - - ------------------------------------------------------------- - -- Arithmetic shift right - ------------------------------------------------------------- - function "sra" (src : ufixed_t; count : integer) return ufixed_t; - function "sra" (src : sfixed_t; count : integer) return sfixed_t; - - ------------------------------------------------------------- - -- Multiplication - ------------------------------------------------------------- - function "*" (a : ufixed_t; b : ufixed_t) return ufixed_t; - function "*" (a : sfixed_t; b : sfixed_t) return sfixed_t; - function "*" (a : ufixed_t; b : sfixed_t) return sfixed_t; - function "*" (a : sfixed_t; b : ufixed_t) return sfixed_t; - - ------------------------------------------------------------- - -- Sum - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : integer) return ufixed_t; - function "+" (a : sfixed_t; b : integer) return sfixed_t; - function "+" (a : ufixed_t; b : unsigned) return ufixed_t; - function "+" (a : sfixed_t; b : signed) return sfixed_t; - function "+" (a : ufixed_t; b : ufixed_t) return ufixed_t; - function "+" (a : sfixed_t; b : sfixed_t) return sfixed_t; - function "+" (a : ufixed_t; b : sfixed_t) return sfixed_t; - function "+" (a : sfixed_t; b : ufixed_t) return sfixed_t; - function "+" (a : ufixed_t; b : std_logic) return ufixed_t; - function "+" (a : sfixed_t; b : std_logic) return sfixed_t; - - - ------------------------------------------------------------- - -- Difference - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : integer) return ufixed_t; - function "-" (a : sfixed_t; b : integer) return sfixed_t; - function "-" (a : ufixed_t; b : unsigned) return ufixed_t; - function "-" (a : sfixed_t; b : signed) return sfixed_t; - function "-" (a : ufixed_t; b : ufixed_t) return ufixed_t; - function "-" (a : sfixed_t; b : sfixed_t) return sfixed_t; - function "-" (a : ufixed_t; b : sfixed_t) return sfixed_t; - function "-" (a : sfixed_t; b : ufixed_t) return sfixed_t; - function "-" (a : ufixed_t; b : std_logic) return ufixed_t; - function "-" (a : sfixed_t; b : std_logic) return sfixed_t; - - ------------------------------------------------------------- - -- Equality - ------------------------------------------------------------- - function "=" (a : ufixed_t; b : ufixed_t) return boolean; - function "=" (a : sfixed_t; b : sfixed_t) return boolean; - function "=" (a : ufixed_t; b : sfixed_t) return boolean; - function "=" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Inequality - ------------------------------------------------------------- - function "/=" (a : ufixed_t; b : ufixed_t) return boolean; - function "/=" (a : sfixed_t; b : sfixed_t) return boolean; - function "/=" (a : ufixed_t; b : sfixed_t) return boolean; - function "/=" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Less than - ------------------------------------------------------------- - function "<" (a : ufixed_t; b : ufixed_t) return boolean; - function "<" (a : sfixed_t; b : sfixed_t) return boolean; - function "<" (a : ufixed_t; b : sfixed_t) return boolean; - function "<" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Greater than - ------------------------------------------------------------- - function ">" (a : ufixed_t; b : ufixed_t) return boolean; - function ">" (a : sfixed_t; b : sfixed_t) return boolean; - function ">" (a : ufixed_t; b : sfixed_t) return boolean; - function ">" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Less or equal than - ------------------------------------------------------------- - function "<=" (a : ufixed_t; b : ufixed_t) return boolean; - function "<=" (a : sfixed_t; b : sfixed_t) return boolean; - function "<=" (a : ufixed_t; b : sfixed_t) return boolean; - function "<=" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Greater or equal than - ------------------------------------------------------------- - function ">=" (a : ufixed_t; b : ufixed_t) return boolean; - function ">=" (a : sfixed_t; b : sfixed_t) return boolean; - function ">=" (a : ufixed_t; b : sfixed_t) return boolean; - function ">=" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Unary Arithmetic Operators - ------------------------------------------------------------- - function "abs" (src : sfixed_t) return sfixed_t; - function "-" (src : ufixed_t) return sfixed_t; - function "-" (src : sfixed_t) return sfixed_t; - - ------------------------------------------------------------- - -- Misc. Operators - ------------------------------------------------------------- - function ipart (src : ufixed_t) return ufixed_t; - function fpart (src : ufixed_t) return ufixed_t; - function ipart (src : sfixed_t) return sfixed_t; - function fpart (src : sfixed_t) return sfixed_t; - - ------------------------------------------------------------- - -- Print function - ------------------------------------------------------------- - procedure print_info(src : in ufixed_t; prefix : in string); - procedure print_info(src : in sfixed_t; prefix : in string); - procedure print_info(src : in string; prefix : in string); - - ------------------------------------------------------------- - -- Helpers - ------------------------------------------------------------- - function cmsb(src : ufixed_t) return integer; - function clsb(src : ufixed_t) return integer; - - function MIN (X, Y: INTEGER) return INTEGER; - function MAX (X, Y: INTEGER) return INTEGER; - - function "MOD" (X, Y: in REAL ) return REAL; - function ipart(src : real) return real; - function fpart(src : real) return real; - - function and_red(arg : ufixed_t) return STD_ULOGIC; - function nand_red(arg : ufixed_t) return STD_ULOGIC; - function or_red(arg : ufixed_t) return STD_ULOGIC; - function nor_red(arg : ufixed_t) return STD_ULOGIC; - function xor_red(arg : ufixed_t) return STD_ULOGIC; - function xnor_red(arg : ufixed_t) return STD_ULOGIC; - function and_red(arg : sfixed_t) return STD_ULOGIC; - function nand_red(arg : sfixed_t) return STD_ULOGIC; - function or_red(arg : sfixed_t) return STD_ULOGIC; - function nor_red(arg : sfixed_t) return STD_ULOGIC; - function xor_red(arg : sfixed_t) return STD_ULOGIC; - function xnor_red(arg : sfixed_t) return STD_ULOGIC; - - -------------------------------------------------------------- - -end; -- package fixed_ja; - diff --git a/lib/fixed_ja/fixed_ja_body.vhd b/lib/fixed_ja/fixed_ja_body.vhd deleted file mode 100644 index a85b626..0000000 --- a/lib/fixed_ja/fixed_ja_body.vhd +++ /dev/null @@ -1,1921 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use ieee.math_real.all; -use std.textio.all; - -package body fixed_ja is - - ------------------------------------------------------------- - -- Local Procedures - ------------------------------------------------------------- - -- adds 1 to the LSB of the number - procedure round_up - ( - src : in ufixed_t; - result : out ufixed_t; - overflowx : out BOOLEAN ) is - - variable srcuns, resuns : UNSIGNED (src'high-src'low+1 downto 0) := (others => '0'); - begin -- round_up - srcuns (srcuns'high-1 downto 0) := to_unsigned (src); - resuns := srcuns + 1; - - result := to_ufixed(resuns(src'high-src'low downto 0), src); - overflowx := (resuns(resuns'high) = '1'); - - end procedure round_up; - - ------------------------------------------------------------- - -- adds 1 to the LSB of the number - procedure round_up - ( - src : in sfixed_t; - result : out sfixed_t; - overflowx : out BOOLEAN ) is - - variable srcs, ress : SIGNED (src'high-src'low+1 downto 0); - begin -- round_up - srcs (srcs'high-1 downto 0) := to_signed (src); - srcs(srcs'high) := src(src'high); -- sign extend - ress := srcs + 1; - - result := to_sfixed(ress (ress'high-1 downto 0), src); - overflowx := ((src(src'high) /= ress(ress'high-1)) and (or_red (sfixed_t(ress)) /= '0')); - - end procedure round_up; - - ------------------------------------------------------------- - -- Local functions - ------------------------------------------------------------- - -- round_fixed() --- function round_fixed --- ( --- src : ufixed_t; --- remainder : ufixed_t; --- rnd_mode : round_mode_t := default_round_mode --- ) return ufixed_t is --- variable res : ufixed_t(src'range); --- begin --- return res; --- --- end round_fixed; - - ------------------------------------------------------------- --- function round_fixed --- ( --- src : sfixed_t; --- remainder : sfixed_t; --- rnd_mode : round_mode_t := default_round_mode --- ) return sfixed_t is --- variable res : signed(src'length-1 downto 0); --- begin --- return src; --- --- end round_fixed; - - ------------------------------------------------------------- - function reshape - ( - src : ufixed_t; - proto : ufixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - - variable RemainLow : ufixed_t (proto'low-1 downto src'low) := (others => '0'); - variable RemainHigh : ufixed_t (src'high downto proto'high+1) := (others => '0'); - variable dst, tmp : ufixed_t (proto'high downto proto'low) := (others => '0'); - variable ovf, isTruncLo, isTruncHi : boolean := false; - begin - - if proto'high < -1 then - assert false report "U: reshape: Bad dual point (Upper bound < (-1))" severity error; - end if; - - -- Check for high and low truncation - isTruncLo := (src'low < dst'low); - isTruncHi := (src'high > dst'high); - - -- Reshape - dst := (others => '0'); - dst(min(src'high, dst'high) downto max(src'low, dst'low)) := src(min(src'high, dst'high) downto max(src'low, dst'low)); - tmp := dst; - - -- Get low remainder - if isTruncLo then - RemainLow := src(RemainLow'range); - end if; - - -- Get high remainder - if isTruncHi then - RemainHigh := src(RemainHigh'range); - end if; - - ovf := false; - - -- Rounding - if isTruncLo then - - case rnd_mode is - - -- Round to positive infinity (round ceiling) - when round_pos_infinity => - if or_red(RemainLow) = '1' then - round_up(tmp, dst, ovf); - end if; - - -- Round Half-up - -- Round nearest - when round_half_up | round_nearest => - if (RemainLow(RemainLow'high) = '1') then - round_up(tmp, dst, ovf); - end if; - - -- Round convergent - when round_convergent => - if RemainLow(RemainLow'high) = '1' then - if or_red(RemainLow(RemainLow'high-1 downto RemainLow'low)) = '1' then - round_up(tmp, dst, ovf); - elsif tmp(dst'low) = '1' then - round_up(tmp, dst, ovf); - end if; - end if; - - -- Round to zero - when round_to_zero | none => null; - - when others => - assert false report "Reshape(U): Rounding mode (" & round_mode_t'image(rnd_mode) & ") not implemented!" severity error; - - end case; - end if; - - -- Saturating - if sat_mode = saturate then - - -- Check overflow - if isTruncHi then - ovf := ovf or or_red(RemainHigh) = '1'; - end if; - - -- Saturate - if ovf then - dst := (others => '1'); - end if; - - end if; - - return dst; - - end reshape; - - ------------------------------------------------------------- - function reshape - ( - src : ufixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - - begin - return reshape(src, uproto(nbits, nbits_int), rnd_mode, sat_mode); - - end reshape; - - ------------------------------------------------------------- - function reshape - ( - src : sfixed_t; - proto : sfixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - - variable RemainLow : sfixed_t (proto'low-1 downto src'low) := (others => '0'); - variable RemainHigh : sfixed_t (src'high-1 downto proto'high) := (others => '0'); - variable dst, tmp : sfixed_t (proto'high downto proto'low) := (others => '0'); - variable ovf, isTruncLo, isTruncHi : boolean := false; - variable sign : std_logic; - begin - - if proto'high < 0 then - assert false report "Reshape(S): Bad dual point (Upper bound < (0))" severity error; - end if; - - -- Check for high and low truncation - isTruncLo := (src'low < dst'low); - isTruncHi := (src'high > dst'high); - - -- Reshape - sign := src(src'high); - dst := (others => '0'); - dst(dst'high downto max(src'low, dst'low)) := (dst'high downto min(src'high, dst'high) => sign) & src(min(src'high, dst'high)-1 downto max(src'low, dst'low)); - tmp := dst; - - -- Get low remainder - if isTruncLo then - RemainLow := src(RemainLow'range); - end if; - - -- Get high remainder - if isTruncHi then - RemainHigh := src(RemainHigh'range); - end if; - - ovf := false; - - -- Rounding - if isTruncLo then - - case rnd_mode is - - -- Round to positive infinity (round ceiling) - when round_pos_infinity => - round_up(tmp, dst, ovf); - if ovf then - dst(dst'high) := '0'; - end if; - - -- Round Half-up - when round_half_up => - if RemainLow(RemainLow'high) = '1' then - round_up(tmp, dst, ovf); - end if; - - -- Round nearest - when round_nearest => - if RemainLow(RemainLow'high) = '1' then - if RemainLow'length = 1 then - if sign = '0' then - round_up(tmp, dst, ovf); - end if; - elsif sign = '0' or (sign and or_red(RemainLow(RemainLow'high-1 downto RemainLow'low))) = '1' then - round_up(tmp, dst, ovf); - end if; - end if; - - -- Round convergent - when round_convergent => - if RemainLow(RemainLow'high) = '1' then - if or_red(RemainLow(RemainLow'high-1 downto RemainLow'low)) = '1' then - round_up(tmp, dst, ovf); - elsif tmp(dst'low) = '1' then - round_up(tmp, dst, ovf); - end if; - end if; - - -- Round to zero - when round_to_zero => - if (or_red(RemainLow) = '1' and sign = '1') then - round_up(tmp, dst, ovf); - end if; - - -- No Round - when none => - -- Same as RoundToZero but overflow detection is omitted - dst := tmp + (or_red(RemainLow) and sign); - - when others => - assert false report "Reshape(S): Rounding mode (" & round_mode_t'image(rnd_mode) & ") not implemented!" severity error; - - end case; - - -- Check negative zero - if dst(dst'high) = '1' then - if or_red(dst(dst'high-1 downto dst'low)) = '0' then - dst(dst'high) := '0'; - -- assert false report "Reshape(S): -0 detected" severity note; - end if; - end if; - end if; - - -- Saturating - if sat_mode = saturate then - - -- Check overflow - if isTruncHi then - ovf := ovf or - (sign = '1' and src(dst'high) = '0' and or_red(tmp(dst'high-1 downto dst'low)) = '1') or - (sign = '1' and src(dst'high) = '1' and or_red(tmp(dst'high-1 downto dst'low)) = '0') or - (sign = '0' and or_red(RemainHigh) = '1'); - end if; - - -- Saturate - if ovf then - if (sign = '1') then - dst := '1' & (dst'high-1 downto dst'low+1 => '0') & '1'; - else - dst := '0' & (dst'high-1 downto dst'low => '1'); - end if; - end if; - - end if; - - return dst; - - end reshape; - - ------------------------------------------------------------- - function reshape - ( - src : sfixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - - begin - return reshape(src, sproto(nbits, nbits_int), rnd_mode, sat_mode); - - end reshape; - - ------------------------------------------------------------- - -- Constuctor helpers - ------------------------------------------------------------- - function uproto (nbits : integer; nbits_int : integer) return ufixed_t is - constant result : ufixed_t (nbits_int-1 downto nbits_int-nbits) := (others => '0'); - begin - return result(nbits_int-1 downto nbits_int-nbits); - end uproto; - - ------------------------------------------------------------- - function sproto (nbits : integer; nbits_int : integer) return sfixed_t is - constant result : sfixed_t (nbits_int downto nbits_int-nbits+1) := (others => '0'); - begin - return result(nbits_int downto nbits_int-nbits+1); - end sproto; - - ------------------------------------------------------------- - function uproto (a : ufixed_t; op : character; b : ufixed_t) return ufixed_t is - constant result : ufixed_t(a'high + b'high + 4 downto a'low + b'low - 4) := (others => '0'); - variable hi, lo : integer := 0; - - begin - - case op is - when '+' => - hi := max(a'high, b'high); - if a'high = b'high then - hi := hi + 1; - end if; - lo := min(a'low, b'low); - - when '-' => - hi := max(a'high, b'high); - lo := min(a'low, b'low); - - when '*' => - hi := a'high + b'high + 1; - if (a'high < 0 or b'high < 0) then - if (hi > -1) then - hi := hi-1; - end if; - end if; - lo := hi - a'length - b'length + 1; - - when others => null; - - end case; - - return result(hi downto lo); - end uproto; - - ------------------------------------------------------------- - function sproto (a : sfixed_t; op : character; b : sfixed_t) return sfixed_t is - constant result : sfixed_t(a'high + b'high + 4 downto a'low + b'low - 4) := (others => '0'); - variable hi, lo : integer := 0; - - begin - - case op is - when '+' => - hi := max(a'high, b'high); - if a'high = b'high then - hi := hi + 1; - end if; - lo := min(a'low, b'low); - - when '-' => - hi := max(a'high, b'high); - lo := min(a'low, b'low); - - when '*' => - hi := a'high + b'high; - if (a'high = 0 or b'high = 0) then - if (hi > 0) then - hi := hi-1; - end if; - end if; - lo := hi - a'length - b'length + 1; - - when others => null; - - end case; - - return result(hi downto lo); - end sproto; - - ------------------------------------------------------------- - -- Type conversions - ------------------------------------------------------------- - -- ufixed <= ufixed - function to_ufixed(src : ufixed_t) return ufixed_t is - begin - return to_ufixed(src, src); - - end to_ufixed; - - ------------------------------------------------------------- - -- ufixed <= sfixed - function to_ufixed(src : sfixed_t) return ufixed_t is - variable dst : ufixed_t(src'range) := (others => '0'); - begin - dst := ufixed_t(abs(src)); - return dst(src'high-1 downto src'low); - - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= sfixed - function to_sfixed(src : sfixed_t) return sfixed_t is - begin - return src; - - end to_sfixed; - - ------------------------------------------------------------- - -- sfixed <= ufixed - function to_sfixed(src : ufixed_t) return sfixed_t is - variable dst : sfixed_t(src'high+1 downto src'low) := (others => '0'); - begin - dst(src'range) := sfixed_t(src); - return dst; - - end to_sfixed; - - ------------------------------------------------------------- - -- ufixed <= ufixed - function to_ufixed - ( - src : ufixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - begin - return reshape(src, nbits, nbits_int, rnd_mode, sat_mode); - - end to_ufixed; - - ------------------------------------------------------------- - -- ufixed <= ufixed - function to_ufixed - ( - src : ufixed_t; - proto : ufixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - begin - return reshape(src, proto, rnd_mode, sat_mode); - - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= sfixed - function to_sfixed - ( - src : sfixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - begin - return reshape(src, nbits, nbits_int, rnd_mode, sat_mode); - - end to_sfixed; - - ------------------------------------------------------------- - -- sfixed <= sfixed - function to_sfixed - ( - src : sfixed_t; - proto : sfixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - begin - return reshape(src, proto, rnd_mode, sat_mode); - - end to_sfixed; - - ------------------------------------------------------------- - -- ufixed <= integer - function to_ufixed (src : integer; nbits : integer; nbits_int : integer) return ufixed_t is - begin - return to_ufixed(src, uproto(nbits, nbits_int)); - - end to_ufixed; - - function to_ufixed (src : integer; proto : ufixed_t) return ufixed_t is - begin - return to_ufixed(to_unsigned(src, proto'length), proto); - - end to_ufixed; - - ------------------------------------------------------------- - -- ufixed <= unsigned - function to_ufixed (src : unsigned; nbits : integer; nbits_int : integer) return ufixed_t is - begin - return to_ufixed(src, uproto(nbits, nbits_int)); - - end to_ufixed; - - ------------------------------------------------------------- - -- ufixed <= unsigned - function to_ufixed(src : unsigned; proto : ufixed_t) return ufixed_t is - variable dst : ufixed_t(proto'high downto proto'low) := (others => '0'); - begin - - dst(dst'low + min(dst'length, src'length)-1 downto dst'low) := ufixed_t(src(min(dst'length, src'length)-1 downto 0)); - - return dst; - - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= integer - function to_sfixed (src : integer; nbits : integer; nbits_int : integer) return sfixed_t is - begin - return to_sfixed(src, sproto(nbits, nbits_int)); - - end to_sfixed; - - function to_sfixed (src : integer; proto : sfixed_t) return sfixed_t is - begin - - return to_sfixed(to_signed(src, proto'length), proto); - - end to_sfixed; - - ------------------------------------------------------------- - -- sfixed <= signed - function to_sfixed (src : signed; nbits : integer; nbits_int : integer) return sfixed_t is - begin - return to_sfixed(src, sproto(nbits, nbits_int)); - - end to_sfixed; - - ------------------------------------------------------------- - -- sfixed <= signed - function to_sfixed(src : signed; proto : sfixed_t) return sfixed_t is - variable dst : sfixed_t(proto'high downto proto'low) := (others => '0'); - begin - - dst(dst'low + min(dst'length, src'length)-2 downto dst'low) := sfixed_t(src(min(dst'length, src'length)-2 downto 0)); - dst(dst'high) := src(src'high); - - return dst; - - end to_sfixed; - - ------------------------------------------------------------- - function to_ufixed (src : STD_LOGIC_VECTOR; proto : ufixed_t) return ufixed_t is - variable result : ufixed_t (proto'left downto proto'right); - begin - if (result'length < 1) then - return result; - else - result := to_ufixed (unsigned(src), proto); - return result; - end if; - - end function to_ufixed; - - ------------------------------------------------------------- - function to_ufixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return ufixed_t is - begin - return to_ufixed(src, uproto(nbits, nbits_int)); - - end function to_ufixed; - - ------------------------------------------------------------- - function to_sfixed (src : STD_LOGIC_VECTOR; proto : sfixed_t) return sfixed_t is - variable result : sfixed_t (proto'left downto proto'right); - begin - if (result'length < 1) then - return result; - else - result := to_sfixed (signed(src), proto); - return result; - end if; - - end function to_sfixed; - - ------------------------------------------------------------- - function to_sfixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return sfixed_t is - begin - return to_sfixed(src, sproto(nbits, nbits_int)); - - end to_sfixed; - ------------------------------------------------------------- - - -- ufixed <= real - function to_ufixed - ( - src : real; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - - constant nbits_ext : integer := nbits + 1; - constant fix_hi : integer := nbits_int - 1; - constant fix_lo : integer := nbits_int - nbits_ext; - - variable dst : ufixed_t (fix_hi downto fix_lo) := (others => '0'); - variable i : integer := 0; - variable remain : real := 0.0; - - begin - - if (nbits_int < 0) then - assert false report "to_ufixed: Bad dual point (N integer bits < 0)" severity error; - end if; - - if ((2.0**nbits_int - 1.0) < ipart(abs(src))) then --- assert ASSERT_NO_WARN report "to_ufixed: Overflow (" & REAL'image(src) & ") " severity warning; --- print_info(dst, "dst: "); - end if; - - remain := abs(src); - for i in dst'range loop - if remain >= 2.0**i then - dst(i) := '1'; - remain := remain - 2.0**i; - else - dst(i) := '0'; - end if; - end loop; - - return to_ufixed(dst, nbits, nbits_int, rnd_mode, sat_mode); - - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= real - function to_sfixed - ( - src : real; - proto : sfixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - - variable utmp : ufixed_t(proto'high-1 downto proto'low) := (others => '0'); - variable dst : sfixed_t(proto'high downto proto'low) := (others => '0'); - - begin - utmp := to_ufixed(src, utmp, rnd_mode, sat_mode); - if (src < 0.0) then - dst := -to_sfixed(utmp); - else - dst := to_sfixed(utmp); - end if; - - return dst; - end to_sfixed; - - ------------------------------------------------------------- - -- ufixed <= real - function to_ufixed - ( - src : real; - proto : ufixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - begin - return to_ufixed(src, proto'length, proto'high+1, rnd_mode, sat_mode); - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= real - function to_sfixed - ( - src : real; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - begin - return to_sfixed(src, sproto(nbits, nbits_int), rnd_mode, sat_mode); - end to_sfixed; - - ------------------------------------------------------------------------------- - -- ufixed <= ufixed_array(i) - function to_ufixed(src : ufixed_array_t; index : integer) return ufixed_t is - variable dst : ufixed_t(src'range(2)); - begin - for j in src'range(2) loop - dst(j) := src(index, j); - end loop; - - return dst; - - end to_ufixed; - - ------------------------------------------------------------------------------- - -- sfixed <= sfixed_array(i) - function to_sfixed(src : sfixed_array_t; index : integer) return sfixed_t is - variable dst : sfixed_t(src'range(2)); - begin - for j in src'range(2) loop - dst(j) := src(index, j); - end loop; - - return dst; - - end to_sfixed; - - ------------------------------------------------------------- - -- ufixed <= string - function to_ufixed (src : string) return ufixed_t is - - variable i, j, nbits, nbits_int, nbits_frac : integer := 0; - variable dst : unsigned(src'length downto 0) := (others => '0'); - variable dp_found : boolean := false; - begin - - for i in src'reverse_range loop - case src(i) is - when '.' => - if dp_found then - assert false report "More than one DP not found." severity error; - else - dp_found := true; - nbits_frac := j; - end if; - - when '0' => dst(nbits) := '0'; nbits := nbits + 1; j := j + 1; - when '1' => dst(nbits) := '1'; nbits := nbits + 1; j := j + 1; - when others => - assert false report "Illegal character in binary string." severity error; - - end case; - - end loop ; - if not dp_found then - assert ASSERT_NO_WARN report "DP not found. Using left alignment." severity warning; - end if; - - nbits_int := nbits - nbits_frac; - - return to_ufixed(dst(nbits-1 downto 0), nbits, nbits_int); - - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= string - function to_sfixed (src : string) return sfixed_t is - - variable i, j, nbits, nbits_int, nbits_frac : integer := 0; - variable dst : signed(src'length downto 0) := (others => '0'); - variable dp_found : boolean := false; - variable is_neg : boolean := false; - begin - - is_neg := src(src'left) = '-'; - - for i in src'reverse_range loop - case src(i) is - when '-' => null; - when '+' => null; - - when '.' => - if dp_found then - assert false report "More than one DP not found." severity error; - else - dp_found := true; - nbits_frac := j; - end if; - - when '0' => dst(nbits) := '0'; nbits := nbits + 1; j := j + 1; - when '1' => dst(nbits) := '1'; nbits := nbits + 1; j := j + 1; - when others => - assert false report "Illegal character in binary string." severity error; - end case; - end loop ; - nbits := nbits + 1; - - if not dp_found then - assert ASSERT_NO_WARN report "DP not found. Using left alignment." severity warning; - end if; - - nbits_int := nbits - nbits_frac-1; - - if is_neg then - dst(nbits-1 downto 0) := -dst(nbits-1 downto 0); - end if; - - return to_sfixed(dst(nbits-1 downto 0), nbits, nbits_int); - - end to_sfixed; - - ------------------------------------------------------------- - function to_unsigned (src : ufixed_t) return UNSIGNED is - subtype t is UNSIGNED(src'high - src'low downto 0); - variable slv : t; - begin - slv := t(src); - return UNSIGNED(to_X01(std_logic_vector(slv))); - - end function to_unsigned; - - ------------------------------------------------------------- - function to_signed (src : sfixed_t) return SIGNED is - subtype t is SIGNED(src'high - src'low downto 0); - variable slv : t; - begin - slv := t(src); - return SIGNED(to_X01(std_logic_vector(slv))); - - end function to_signed; - - ------------------------------------------------------------- - -- integer <= ufixed - function to_integer (src : ufixed_t) return integer is - begin - return to_integer(to_unsigned(src)); - end to_integer; - - ------------------------------------------------------------- - -- integer <= sfixed - function to_integer (src : sfixed_t) return integer is - begin - return to_integer(to_signed(src)); - end to_integer; - - ------------------------------------------------------------- - -- to_real - function to_real(src : ufixed_t) return real is - variable dst : real := 0.0; - begin - for i in src'range loop - if (src(i) = '1') then - dst := dst + real(2.0**i); - end if; - end loop; - return dst; - - end to_real; - - ------------------------------------------------------------- - function to_real(src : sfixed_t) return real is - variable dst : real := 0.0; - begin - dst := to_real(to_ufixed(src)); - - if (src(src'high) = '1') then - dst := -dst; - end if; - - return dst; - - end to_real; - - ------------------------------------------------------------- - -- to_slv - function to_slv (src : ufixed_t) return STD_LOGIC_VECTOR is - subtype t is STD_LOGIC_VECTOR (src'high - src'low downto 0); - variable slv : t; - begin - if src'length < 1 then - return NSLV; - end if; - slv := t (src); - return slv; - - end function to_slv; - - ------------------------------------------------------------- - -- to_slv - function to_slv (src : sfixed_t) return STD_LOGIC_VECTOR is - subtype t is STD_LOGIC_VECTOR (src'high - src'low downto 0); - variable slv : t; - begin - if src'length < 1 then - return NSLV; - end if; - slv := t (src); - return slv; - - end function to_slv; - - ------------------------------------------------------------- - function to_string(src : ufixed_t) return string is - variable str : string(src'length+1 downto 1) := (others => '0'); - variable i, j : integer := 0; - - begin - j := src'length+1; - for i in src'high downto 0 loop - if (src(i) = '1') then - str(j) := '1'; - end if; - j := j - 1; - end loop; - - str(j) := '.'; - j := j - 1; - - for i in -1 downto src'low loop - if (src(i) = '1') then - str(j) := '1'; - end if; - j := j - 1; - end loop; - - return str; - - end to_string; - - ------------------------------------------------------------- - function to_string(src : sfixed_t) return string is - variable str : string(src'length+1 downto 1) := (others => '0'); - variable i, j, start : integer := 0; - variable strlen : integer := 0; - variable src_abs : sfixed_t(src'range) := (others => '0'); - - begin - if (src'high < 0) then - assert false report "Illegal signed fix point number" severity error; - end if; - - start := src'high; - strlen := src'length; - - j := src'length+1; - if (src(start) = '1') then - str(j) := '-'; - j := j - 1; - start := start - 1; - strlen := strlen + 1; - end if; - - src_abs := abs(src); - - for i in start downto 0 loop - if (src_abs(i) = '1') then - str(j) := '1'; - end if; - j := j - 1; - end loop; - - str(j) := '.'; - j := j - 1; - - for i in -1 downto src'low loop - if (src_abs(i) = '1') then - str(j) := '1'; - end if; - j := j - 1; - end loop; - - return str(strlen downto 1); - - end to_string; - - ------------------------------------------------------------- - function to_string(src : std_logic_vector) return string is - variable str : string(src'length downto 1) := (others => '0'); - variable i : integer := 0; - - begin - for i in src'range loop - if (src(i) = '1') then - str(i+1) := '1'; - end if; - end loop; - - return str; - - end to_string; - - ------------------------------------------------------------- - -- Binary Operators - ------------------------------------------------------------- - function "sla" (src : ufixed_t; count : integer) return ufixed_t is - variable result : ufixed_t (src'high downto src'low) := (others => '0'); - - begin - if (count = 0) then - result := src; - elsif (count < 0) then - result := src sra -count; - elsif (count < src'length) then - result(src'high downto src'low) := src(src'high-count downto src'low) & (count-1 downto 0 => '0'); - end if; - return result; - - end "sla"; - - ------------------------------------------------------------- - function "sla" (src : sfixed_t; count : integer) return sfixed_t is - variable result : sfixed_t (src'high downto src'low) := (others => '0'); - variable sign : std_logic := '0'; - - begin - sign := src(src'high); - if (count = 0) then - result := src; - elsif (count < 0) then - result := src sra -count; - elsif (count < src'length-1) then - result(src'high downto src'low) := sign & src(src'high-count-1 downto src'low) & (count-1 downto 0 => '0'); - end if; - return result; - - end "sla"; - - ------------------------------------------------------------- - function "sra" (src : ufixed_t; count : integer) return ufixed_t is - variable result : ufixed_t (src'high downto src'low) := (others => '0'); - - begin - if (count = 0) then - result := src; - elsif (count < 0) then - result := src sla -count; - elsif (count < src'length) then - result(src'high downto src'low) := (count-1 downto 0 => '0') & src(src'high downto src'low + count); - end if; - return result; - - end "sra"; - - ------------------------------------------------------------- - function "sra" (src : sfixed_t; count : integer) return sfixed_t is - variable result : sfixed_t (src'high downto src'low) := (others => '0'); - variable res_slv, src_slv : signed (src'length-1 downto 0) := (others => '0'); - variable sign, do_sub : std_logic := '0'; - - begin - src_slv := to_signed(src); - sign := src(src'high); - do_sub := src(src'high) and src(src'low); - if (count = 0) then - result := src; - elsif (count < 0) then - result := src sla -count; - elsif (count < src'length-1) then - res_slv := (count downto 0 => sign) & src_slv(src'length-2 downto count); - if (do_sub = '1') then - result(src'high downto src'low) := to_sfixed(res_slv+1, result); - else - result(src'high downto src'low) := to_sfixed(res_slv, result); - end if; - end if; - return result; - - end "sra"; - - ------------------------------------------------------------- - function "*" (a : ufixed_t; b : ufixed_t) return ufixed_t is - variable result : ufixed_t (uproto(a,'*',b)'high downto uproto(a,'*',b)'low); - - begin - if (a'high < 0 and b'high >= 0) or (a'high >= 0 and b'high < 0) then - result := to_ufixed(to_unsigned(a) * to_unsigned(b), result) sla 1; - else - result := to_ufixed(to_unsigned(a) * to_unsigned(b), result); - end if; - return result; - - end "*"; - - ------------------------------------------------------------- - function "*" (a : sfixed_t; b : sfixed_t) return sfixed_t is - variable result : sfixed_t (sproto(a,'*',b)'high downto sproto(a,'*',b)'low); - - begin - if (a'high = 0 and b'high > 0) or (a'high > 0 and b'high = 0) then - result := to_sfixed(signed(a) * signed(b), result) sla 2; - else - result := to_sfixed(signed(a) * signed(b), result) sla 1; - end if; - return result; - - end "*"; - - ------------------------------------------------------------- - function "*" (a : ufixed_t; b : sfixed_t) return sfixed_t is - - begin - return to_sfixed(a) * b; - - end "*"; - - ------------------------------------------------------------- - function "*" (a : sfixed_t; b : ufixed_t) return sfixed_t is - - begin - return b * a; - - end "*"; - - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : ufixed_t) return ufixed_t is - variable result : ufixed_t (uproto(a,'+',b)'high downto uproto(a,'+',b)'low); - - begin - result := ufixed_t(unsigned(reshape(a, result)) + unsigned(reshape(b, result))); - return result; - - end "+"; - - ------------------------------------------------------------- - function "+" (a : sfixed_t; b : sfixed_t) return sfixed_t is - variable result : sfixed_t (sproto(a,'+',b)'high downto sproto(a,'+',b)'low); - - begin - result := to_sfixed(signed(reshape(a,result)) + signed(reshape(b,result)), result); --- result := to_sfixed(signed(a) + signed(b), result); - return result; - - end "+"; - - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : sfixed_t) return sfixed_t is - - begin - return to_sfixed(a) + b; - - end "+"; - - ------------------------------------------------------------- - function "+" (a : sfixed_t; b : ufixed_t) return sfixed_t is - - begin - return b + a; - - end "+"; - - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : unsigned) return ufixed_t is - - begin - - return ufixed_t(unsigned(a) + b); - - end "+"; - - ------------------------------------------------------------- - function "+" (a : sfixed_t; b : signed) return sfixed_t is - - begin - - return sfixed_t(signed(a) + b); - - end "+"; - - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : integer) return ufixed_t is - - begin - - return ufixed_t(unsigned(a) + to_unsigned(b, a'length)); - - end "+"; - - ------------------------------------------------------------- - function "+" (a : sfixed_t; b : integer) return sfixed_t is - - begin - - return sfixed_t(signed(a) + to_signed(b, a'length)); - - end "+"; - - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : std_logic) return ufixed_t is - variable result : ufixed_t (a'high downto a'low); - variable buns : unsigned(a'length-1 downto 0); - - begin - buns := (a'length-1 downto 1 => '0') & b; - result := ufixed_t(to_unsigned(a) + buns); - return result; - - end "+"; - - ------------------------------------------------------------- - function "+" (a : sfixed_t; b : std_logic) return sfixed_t is - variable result : sfixed_t (a'high downto a'low); - variable bs : signed(a'length-1 downto 0); - - begin - bs := (a'length-1 downto 1 => '0') & b; - result := sfixed_t(to_signed(a) + bs); - return result; - - end "+"; - - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : ufixed_t) return ufixed_t is - variable result : ufixed_t (uproto(a,'-',b)'high downto uproto(a,'-',b)'low); - begin - result := to_ufixed(to_sfixed(a) - to_sfixed(b)); - return result; - - end "-"; - - ------------------------------------------------------------- - function "-" (a : sfixed_t; b : sfixed_t) return sfixed_t is - variable result : sfixed_t (sproto(a,'-',b)'high downto sproto(a,'-',b)'low); - - begin - result := to_sfixed(signed(reshape(a,result)) - signed(reshape(b,result)), result); - return result; - - end "-"; - - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : sfixed_t) return sfixed_t is - begin - return to_sfixed(a) - b; - - end "-"; - - ------------------------------------------------------------- - function "-" (a : sfixed_t; b : ufixed_t) return sfixed_t is - - begin - return a - to_sfixed(b); - - end "-"; - - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : unsigned) return ufixed_t is - - begin - return ufixed_t(unsigned(a) - b); - - end "-"; - - ------------------------------------------------------------- - function "-" (a : sfixed_t; b : signed) return sfixed_t is - - begin - return sfixed_t(signed(a) - b); - - end "-"; - - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : integer) return ufixed_t is - - begin - - return ufixed_t(unsigned(a) - to_unsigned(b, a'length)); - - end "-"; - - ------------------------------------------------------------- - function "-" (a : sfixed_t; b : integer) return sfixed_t is - - begin - - return sfixed_t(signed(a) - to_signed(b, a'length)); - - end "-"; - - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : std_logic) return ufixed_t is - variable result : ufixed_t (a'high downto a'low); - variable buns : unsigned(a'length-1 downto 0); - - begin - buns := (a'length-1 downto 1 => '0') & b; - result := ufixed_t(unsigned(a) - buns); - return result; - - end "-"; - - ------------------------------------------------------------- - function "-" (a : sfixed_t; b : std_logic) return sfixed_t is - variable result : sfixed_t (a'high downto a'low); - variable bs : signed(a'length-1 downto 0); - - begin - bs := (a'length-1 downto 1 => '0') & b; - result := sfixed_t(signed(a) - bs); - return result; - - end "-"; - - ------------------------------------------------------------- - -- Unary Operators - ------------------------------------------------------------- - function "abs" (src : sfixed_t) return sfixed_t is - begin - return to_sfixed(abs(signed(src)), src); - - end "abs"; - - ------------------------------------------------------------- - function "-" (src : ufixed_t) return sfixed_t is - begin - return -to_sfixed(src); - - end "-"; - - ------------------------------------------------------------- - function "-" (src : sfixed_t) return sfixed_t is - begin - return to_sfixed(-signed(src), src); - - end "-"; - - ------------------------------------------------------------- - -- Binary Equality - ------------------------------------------------------------- - function "=" (a : ufixed_t; b : ufixed_t) return boolean is - variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_ufixed(a, ta); - tb := to_ufixed(b, tb); - return to_unsigned(ta) = to_unsigned(tb); - - end "="; - - ------------------------------------------------------------- - function "=" (a : sfixed_t; b : sfixed_t) return boolean is - variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_sfixed(a, ta); - tb := to_sfixed(b, tb); - return to_signed(ta) = to_signed(tb); - - end "="; - - ------------------------------------------------------------- - function "=" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return to_sfixed(a) = b; - end "="; - - ------------------------------------------------------------- - function "=" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return b = a; - end "="; - - ------------------------------------------------------------- - -- Binary Inequality - ------------------------------------------------------------- - function "/=" (a : ufixed_t; b : ufixed_t) return boolean is - begin - return not (a = b); - - end "/="; - - ------------------------------------------------------------- - function "/=" (a : sfixed_t; b : sfixed_t) return boolean is - begin - return not (a = b); - - end "/="; - - ------------------------------------------------------------- - function "/=" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return not (a = b); - end "/="; - - ------------------------------------------------------------- - function "/=" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return not (a = b); - end "/="; - - ------------------------------------------------------------- - -- Binary less than - ------------------------------------------------------------- - function "<" (a : ufixed_t; b : ufixed_t) return boolean is - variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_ufixed(a, ta); - tb := to_ufixed(b, tb); - return to_unsigned(ta) < to_unsigned(tb); - - end "<"; - - ------------------------------------------------------------- - function "<" (a : sfixed_t; b : sfixed_t) return boolean is - variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_sfixed(a, ta); - tb := to_sfixed(b, tb); - return to_signed(ta) < to_signed(tb); - - end "<"; - - ------------------------------------------------------------- - function "<" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return to_sfixed(a) < b; - - end "<"; - - ------------------------------------------------------------- - function "<" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return a < to_sfixed(b); - - end "<"; - - ------------------------------------------------------------- - -- Binary greater than - ------------------------------------------------------------- - function ">" (a : ufixed_t; b : ufixed_t) return boolean is - variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_ufixed(a, ta); - tb := to_ufixed(b, tb); - return to_unsigned(ta) > to_unsigned(tb); - - end ">"; - - ------------------------------------------------------------- - function ">" (a : sfixed_t; b : sfixed_t) return boolean is - variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_sfixed(a, ta); - tb := to_sfixed(b, tb); - return to_signed(ta) > to_signed(tb); - - end ">"; - - ------------------------------------------------------------- - function ">" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return to_sfixed(a) > b; - end ">"; - - ------------------------------------------------------------- - function ">" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return a > to_sfixed(b); - end ">"; - - ------------------------------------------------------------- - -- Binary less equal than - ------------------------------------------------------------- - function "<=" (a : ufixed_t; b : ufixed_t) return boolean is - begin - return not (a > b); - end "<="; - - function "<=" (a : sfixed_t; b : sfixed_t) return boolean is - begin - return not (a > b); - end "<="; - - function "<=" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return not (a > b); - end "<="; - - function "<=" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return not (a > b); - end "<="; - - ------------------------------------------------------------- - -- Binary greater or equal than - ------------------------------------------------------------- - function ">=" (a : ufixed_t; b : ufixed_t) return boolean is - begin - return not (a < b); - end ">="; - - function ">=" (a : sfixed_t; b : sfixed_t) return boolean is - begin - return not (a < b); - end ">="; - - function ">=" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return not (a < b); - end ">="; - - function ">=" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return not (a < b); - end ">="; - - ------------------------------------------------------------- - -- Misc. Operators - ------------------------------------------------------------- - function ipart (src : ufixed_t) return ufixed_t is - begin - return src(src'high downto 0); - end ipart; - - function fpart (src : ufixed_t) return ufixed_t is - begin - return src(-1 downto src'low); - end fpart; - - function ipart (src : sfixed_t) return sfixed_t is - begin - return src(src'high-1 downto 0); - end ipart; - - function fpart (src : sfixed_t) return sfixed_t is - begin - return src(-1 downto src'low); - end fpart; - - ------------------------------------------------------------- - -- Print functions - ------------------------------------------------------------- - procedure print_info(src : in ufixed_t; prefix : in string) is - variable L : line; - - begin - write (L, prefix & "'length = ");write (L, src'length); - writeline (output, L); - - write (L, prefix & "'high(left) = "); - write (L, src'high); - write (L, '('); - write (L, src'left); - write (L, ')'); - writeline (output, L); - - write (L, prefix & "'low(right) = "); - write (L, src'low); - write (L, '('); - write (L, src'right); - write (L, ')'); - writeline (output, L); - - write (L, prefix & "'value = B");write (L, to_string(src)); - writeline (output, L); - - write (L, prefix & "'value = ");write (L, to_real(src)); - writeline (output, L); - - -- write (L, prefix & "'cmsb = ");write (L, cmsb(src)); - -- writeline (output, L); - - -- write (L, prefix & "'clsb = ");write (L, clsb(src)); - -- writeline (output, L); - - writeline (output, L); - - end print_info; - - ------------------------------------------------------------- - procedure print_info(src : in sfixed_t; prefix : in string) is - variable L : line; - - begin - write (L, prefix & "'length = ");write (L, src'length); - writeline (output, L); - - write (L, prefix & "'high(left) = "); - write (L, src'high); - write (L, '('); - write (L, src'left); - write (L, ')'); - writeline (output, L); - - write (L, prefix & "'low(right) = "); - write (L, src'low); - write (L, '('); - write (L, src'right); - write (L, ')'); - writeline (output, L); - - write (L, prefix & "'value = B");write (L, to_string(src)); - writeline (output, L); - - write (L, prefix & "'value = ");write (L, to_real(src)); - writeline (output, L); - - -- write (L, prefix & "'cmsb = ");write (L, cmsb(src)); - -- writeline (output, L); - - -- write (L, prefix & "'clsb = ");write (L, clsb(src)); - -- writeline (output, L); - - writeline (output, L); - - end print_info; - - ------------------------------------------------------------- - procedure print_info(src : in string; prefix : in string) is - variable L : line; - - begin - write (L, prefix & "'length = ");write (L, src'length); - writeline (output, L); - - write (L, prefix & "'high(left) = "); - write (L, src'high); - write (L, '('); - write (L, src'left); - write (L, ')'); - writeline (output, L); - - write (L, prefix & "'low(right) = "); - write (L, src'low); - write (L, '('); - write (L, src'right); - write (L, ')'); - writeline (output, L); - - writeline (output, L); - - end print_info; - - ------------------------------------------------------------- - -- Helpers - ------------------------------------------------------------- - -- Count significant bits for integer part - function cmsb(src : ufixed_t) return integer is - variable j, i : integer := src'high; - begin - for i in src'range loop - if src(i) = '1' then - exit; - end if; - j := j - 1; - end loop; - - -- LRM nachlesen: hier is i=src'high re-initialisert - - return j; - - end cmsb; - - ------------------------------------------------------------- - -- Count significant bits for fractional part - function clsb(src : ufixed_t) return integer is - variable j, i : integer := src'low; - begin - for i in src'reverse_range loop - if src(i) = '1' then - exit; - end if; - j := j + 1; - end loop; - - -- LRM nachlesen: hier is i=src'low re-initialisert - - return j; - - end clsb; - - ------------------------------------------------------------- - function MIN (X, Y: INTEGER) return INTEGER is - variable res : integer := X; - begin - if Y < X then - res := Y; - end if; - - return res; - - end MIN; - - ------------------------------------------------------------- - function MAX (X, Y: INTEGER) return INTEGER is - variable res : integer := X; - begin - if Y > X then - res := Y; - end if; - - return res; - - end MAX; - - ------------------------------------------------------------- - function "MOD" (X, Y: in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - - variable XNEGATIVE : BOOLEAN := X < 0.0; - variable YNEGATIVE : BOOLEAN := Y < 0.0; - variable VALUE : REAL; - begin - -- Check validity of input arguments - if (Y = 0.0) then - assert FALSE - report "MOD(X, 0.0) is undefined" - severity ERROR; - return 0.0; - end if; - - -- Compute value - if ( XNEGATIVE ) then - if ( YNEGATIVE ) then - VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - end if; - else - if ( YNEGATIVE ) then - VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - end if; - end if; - - return VALUE; - - end "MOD"; - - ------------------------------------------------------------- - -- misc. conversion - function ipart(src : real) return real is - begin - return floor(src); - - end ipart; - - ------------------------------------------------------------- - function fpart(src : real) return real is - begin - return src - floor(src); - - end fpart; - - ------------------------------------------------------------- - function or_red (arg : STD_LOGIC_VECTOR) - return STD_LOGIC is - variable Upper, Lower : STD_LOGIC; - variable Half : INTEGER; - variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0); - variable Result : STD_LOGIC; - begin - if (arg'length < 1) then -- In the case of a NULL range - Result := '0'; - else - BUS_int := to_ux01 (arg); - if (BUS_int'length = 1) then - Result := BUS_int (BUS_int'left); - elsif (BUS_int'length = 2) then - Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left); - else - Half := (BUS_int'length + 1) / 2 + BUS_int'right; - Upper := or_red (BUS_int (BUS_int'left downto Half)); - Lower := or_red (BUS_int (Half - 1 downto BUS_int'right)); - Result := Upper or Lower; - end if; - end if; - return Result; - - end function or_red; - - ------------------------------------------------------------- - function and_red (arg : STD_LOGIC_VECTOR) - return STD_LOGIC is - variable Upper, Lower : STD_LOGIC; - variable Half : INTEGER; - variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0); - variable Result : STD_LOGIC; - begin - if (arg'length < 1) then -- In the case of a NULL range - Result := '1'; - else - BUS_int := to_ux01 (arg); - if (BUS_int'length = 1) then - Result := BUS_int (BUS_int'left); - elsif (BUS_int'length = 2) then - Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left); - else - Half := (BUS_int'length + 1) / 2 + BUS_int'right; - Upper := and_red (BUS_int (BUS_int'left downto Half)); - Lower := and_red (BUS_int (Half - 1 downto BUS_int'right)); - Result := Upper and Lower; - end if; - end if; - return Result; - - end function and_red; - - ------------------------------------------------------------- - function xor_red (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is - variable Upper, Lower : STD_ULOGIC; - variable Half : INTEGER; - variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0); - variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range - begin - if (arg'length >= 1) then - BUS_int := to_ux01 (arg); - if (BUS_int'length = 1) then - Result := BUS_int (BUS_int'left); - elsif (BUS_int'length = 2) then - Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left); - else - Half := (BUS_int'length + 1) / 2 + BUS_int'right; - Upper := xor_red (BUS_int (BUS_int'left downto Half)); - Lower := xor_red (BUS_int (Half - 1 downto BUS_int'right)); - Result := Upper xor Lower; - end if; - end if; - return Result; - - end function xor_red; - - ------------------------------------------------------------- - -- Reduction operators, same as numeric_std functions - function and_red(arg : ufixed_t) return STD_ULOGIC is - begin - return and_red (to_slv(arg)); - end function and_red; - - function nand_red(arg : ufixed_t) return STD_ULOGIC is - begin - return not and_red (to_slv(arg)); - end function nand_red; - - function or_red(arg : ufixed_t) return STD_ULOGIC is - begin - return or_red (to_slv(arg)); - end function or_red; - - function nor_red(arg : ufixed_t) return STD_ULOGIC is - begin - return not or_red (to_slv(arg)); - end function nor_red; - - function xor_red(arg : ufixed_t) return STD_ULOGIC is - begin - return xor_red (to_slv(arg)); - end function xor_red; - - function xnor_red(arg : ufixed_t) return STD_ULOGIC is - begin - return not xor_red (to_slv(arg)); - end function xnor_red; - - function and_red(arg : sfixed_t) return STD_ULOGIC is - begin - return and_red (to_slv(arg)); - end function and_red; - - function nand_red(arg : sfixed_t) return STD_ULOGIC is - begin - return not and_red (to_slv(arg)); - end function nand_red; - - function or_red(arg : sfixed_t) return STD_ULOGIC is - begin - return or_red (to_slv(arg)); - end function or_red; - - function nor_red(arg : sfixed_t) return STD_ULOGIC is - begin - return not or_red (to_slv(arg)); - end function nor_red; - - function xor_red(arg : sfixed_t) return STD_ULOGIC is - begin - return xor_red (to_slv(arg)); - end function xor_red; - - function xnor_red(arg : sfixed_t) return STD_ULOGIC is - begin - return not xor_red (to_slv(arg)); - end function xnor_red; - - ------------------------------------------------------------- - -end; -- package body fixed_ja; diff --git a/lib/jasm/cg.inc.jsm b/lib/jasm/cg.inc.jsm deleted file mode 100644 index 01c36c4..0000000 --- a/lib/jasm/cg.inc.jsm +++ /dev/null @@ -1,72 +0,0 @@ -; ------------------------------------------------- -; lcd.inc.jsm -; ------------------------------------------------- -; needs xio-address equates for -; reg_cg_char_addr: equ 0xXX ; RW -; reg_cg_line_addr: equ 0xXX ; RW -; reg_cg_data: equ 0xXX ; RW -; reg_cg_ctrl: equ 0xXX ; WO - -; needs delay.inc.jsm - -; ------------------------------------------------- -cg_clr_line: push R0 - mov R0, 2 - xout (reg_cg_ctrl), R0 - pop R0 - ret - -; ------------------------------------------------- -cg_clr_screen: push R0 - mov R0, 1 - xout (reg_cg_ctrl), R0 - pop R0 - ret - -; ------------------------------------------------- -; R0 : char address -; R1 : line address -cg_set_addr: call cg_wait_rdy - xout (reg_cg_line_addr), R1 - xout (reg_cg_char_addr), R0 - ret - -; ------------------------------------------------- -; R0 : character -cg_putchar: call cg_wait_rdy - xout (reg_cg_data), R0 - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_puts: push R0 -cg_p_lp: movx R0, (R1) - inc R1 - tst R0 - jz ex_cgp - call cg_putchar - jmp cg_p_lp -ex_cgp: pop R0 - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_clr_puts: call cg_clr_line - call cg_puts - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_puts_clr: call cg_puts - call cg_clr_line - ret - -; ------------------------------------------------- -cg_wait_rdy: push R0 -cg_wr_lp: xin R0, (reg_hwstat) - and R0, 0x02 - jz cg_wr_lp - pop R0 - ret - -; ------------------------------------------------- diff --git a/lib/jasm/cregs.inc.jsm b/lib/jasm/cregs.inc.jsm deleted file mode 100644 index 06d39d9..0000000 --- a/lib/jasm/cregs.inc.jsm +++ /dev/null @@ -1,7 +0,0 @@ -; JCPU On-Chip register -cpu_revision: equ 0x00 ; RO -cpu_control: equ 0x01 ; R/W -cpu_status: equ 0x02 ; RO -cpu_int_ctrl: equ 0x03 ; RW -cpu_cmem_high: equ 0x04 ; RW -cpu_stack_high: equ 0x05 ; RW diff --git a/lib/jasm/delays.inc.jsm b/lib/jasm/delays.inc.jsm deleted file mode 100644 index 6f002ee..0000000 --- a/lib/jasm/delays.inc.jsm +++ /dev/null @@ -1,64 +0,0 @@ -; ------------------------------------------------- -; Delays -; ------------------------------------------------- -delay1s: push R15 - mov R15, 10 -loop1s: call delay100ms - dec R15 - jnz loop1s - pop R15 - ret - -delay100ms: push R15 - mov R15, 10 -loop100ms: call delay10ms - dec R15 - jnz loop100ms - pop R15 - ret - -delay10ms: push R15 - mov R15, 10 -loop10ms: call delay1ms - dec R15 - jnz loop10ms - pop R15 - ret - -delay1ms: push R15 - mov R15, 10 -loop1ms: call delay100us - dec R15 - jnz loop1ms - pop R15 - ret - -delay100us: push R15 - mov R15, 10 -loop100us: call delay10us - dec R15 - jnz loop100us - pop R15 - ret - -delay10us: push R15 - mov R15, 99 -loop10us: nop - nop - nop - dec R15 - jnz loop10us - pop R15 - ret - -delay1us: push R15 - mov R15, 9 -loop1us: nop - nop - nop - dec R15 - jnz loop1us - pop R15 - ret - -; ------------------------------------------------- diff --git a/lib/jasm/lcd.inc.jsm b/lib/jasm/lcd.inc.jsm deleted file mode 100644 index d2883fa..0000000 --- a/lib/jasm/lcd.inc.jsm +++ /dev/null @@ -1,208 +0,0 @@ -; ------------------------------------------------- -; lcd.inc.jsm -; ------------------------------------------------- -; needs xmem-address definition for -; - lcd_port (LCD-Base) - -; needs delay.inc.jsm - -; ------------------------------------------------- -lcd_cmd: equ 0x00 -lcd_rd: equ 0x20 -lcd_data: equ 0x40 -lcd_enable: equ 0x80 - -LCD_CMD_Z1: equ 0x80 -LCD_CMD_Z2: equ 0xC0 -LCD_CMD_CLEAR: equ 0x01 - -; ------------------------------------------------- -; Init LCD -; ------------------------------------------------- -LCD_init: mov R2, 0x00 - mov R0, 0x03 - call _write_lcd - call delay10ms - mov R2, 0x00 - mov R0, 0x03 - call _write_lcd - call delay10ms - - mov R2, 0x00 - mov R0, 0x02 - call _write_lcd - call delay1ms - - ; 1. Function set: 4-Bit mode, two display lines - mov R0, 0x28 - call LCD_writecmd - - ; 2. Display on, no cursor - mov R0, 0x0C - call LCD_writecmd - - ; 3. Cursor shift during write - mov R0, 0x06 - call LCD_writecmd - - ; 4. Display clear - mov R0, 0x01 - call LCD_writecmd - - ret - -; ------------------------------------------------- -; LCD_waitbsy -; ------------------------------------------------- -LCD_waitbsy: push R0 -bsy_loop: call LCD_readstat - and R0, 0x80 - jz ex_bsy - call delay1us - jmp bsy_loop -ex_bsy: pop R0 - ret - -; ------------------------------------------------- -; LCD_writecmd -; ------------------------------------------------- -; R0 = cmd -LCD_writeaddr: -LCD_writecmd: push R2 - mov R2, lcd_cmd - call LCD_write - pop R2 - ret - -; ------------------------------------------------- -; LCD_putsx -; ------------------------------------------------- -; R1 = address of null-terminated string in XMEM -LCD_putsx: push R0 -putsx_loop: movx R0, (R1) - inc R1 - tst R0 - jz putsx_ex - call LCD_writechar - jmp putsx_loop -putsx_ex: pop R0 - ret - -; ------------------------------------------------- -; LCD_putsc -; ------------------------------------------------- -; R1 = address of null-terminated string in CMEM -LCD_putsc: push R0 -putsc_loop: movc R0, (R1) - inc R1 - tst R0 - jz putsc_ex - call LCD_writechar - jmp putsc_loop -putsc_ex: pop R0 - ret - -; ------------------------------------------------- -; LCD_writechar -; ------------------------------------------------- -; R0 = char -LCD_writedata: -LCD_writechar: push R2 - mov R2, lcd_data - call LCD_write - pop R2 - ret - -; ------------------------------------------------- -; LCD_write -; ------------------------------------------------- -; R0 = input -; R2 = register -LCD_write: call LCD_waitbsy - push R0 - swap R0 - call _write_lcd - pop R0 - call _write_lcd - ret - -; ------------------------------------------------- -; LCD_readstat -; ------------------------------------------------- -; R0 = status -LCD_readstat: push R2 - mov R2, lcd_cmd - call LCD_read - pop R2 - ret - -; ------------------------------------------------- -; LCD_read -; ------------------------------------------------- -; R0 = output -; R2 = register -LCD_read: call _read_lcd - swap R0 - push R0 - call _read_lcd - pop R2 - or R0, R2 - ret - -; ------------------------------------------------- -; _write -; ------------------------------------------------- -; R0 = input -_write_lcd: push R1 - - and R0, 0x0F - mov R1, R0 - or R1, R2 - xout (lcd_port), R1 - call delay1us - - mov R1, R0 - or R1, R2 - or R1, lcd_enable - xout (lcd_port), R1 - call delay1us - - mov R1, R0 - or R1, R2 - xout (lcd_port), R1 - call delay1us - - or R1, lcd_rd - xout (lcd_port), R1 - - pop R1 - ret - -; ------------------------------------------------- -; _read -; ------------------------------------------------- -; R0 = output -_read_lcd: push R1 - - mov R1, lcd_rd - or R1, R2 - xout (lcd_port), R1 - call delay1us - - mov R1, lcd_rd - or R1, R2 - or R1, lcd_enable - xout (lcd_port), R1 - call delay1us - xin R0, (lcd_port) - and R0, 0x0F - - mov R1, lcd_rd - or R1, R2 - xout (lcd_port), R1 - call delay1us - - pop R1 - ret - - \ No newline at end of file diff --git a/lib/jasm/mul8x8.inc.jsm b/lib/jasm/mul8x8.inc.jsm deleted file mode 100644 index 2f66e2a..0000000 --- a/lib/jasm/mul8x8.inc.jsm +++ /dev/null @@ -1,42 +0,0 @@ -; ------------------------------------------------- -; mul8x8.inc.jsm -; ------------------------------------------------- - -; ------------------------------------------------- -; Parameter: -; R0 : operand 1 -; R1 : operand 2 -; Return: -; R0 : product low -; R1 : product high -mul8x8: push R2 - push R3 - push R4 - - mov R4, R1 - mov R1, 0 - mov R2, 0 - mov R3, 0 - -loop1: cmp R4, 0x01 - jeq ende1 - - shr R4 - jnc next1 - - add R2, R0 - addc R3, R1 - -next1: shl R0 - rolc R1 - jmp loop1 - -ende1: add R0, R2 - addc R1, R3 - - pop R4 - pop R3 - pop R2 - ret - -; ------------------------------------------------- diff --git a/lib/jasm/uart.inc.jsm b/lib/jasm/uart.inc.jsm deleted file mode 100644 index df557b1..0000000 --- a/lib/jasm/uart.inc.jsm +++ /dev/null @@ -1,32 +0,0 @@ -; ------------------------------------------------- -; uart.inc.jsm -; ------------------------------------------------- -; needs xmem-address definition for -; - uart_status (Status register) -; - uart_data (Data register) - -; ------------------------------------------------- -; sout -; ------------------------------------------------- -; R0 = input -sout: push R1 -sout1: xin R1, (uart_status) - and R1, 0x02 - jnz sout1 - xout (uart_data), R0 - pop R1 - ret - -; ------------------------------------------------- -; sin -; ------------------------------------------------- -; R0 = output -sin: push R1 -sin1: xin R1, (uart_status) - and R1, 0x10 - jz sin1 - xin R0, (uart_data) - pop R1 - ret - -; ------------------------------------------------- diff --git a/lib/jasm/utils.inc.jsm b/lib/jasm/utils.inc.jsm deleted file mode 100644 index f354d7c..0000000 --- a/lib/jasm/utils.inc.jsm +++ /dev/null @@ -1,32 +0,0 @@ -; ------------------------------------------------- -; utils.inc.jsm -; ------------------------------------------------- - - -; ------------------------------------------------- -; Parameter -; R0 : Bin value in lower nibble -; Return -; R0 : Hex character representing lower nibble -nibble2hex: and R0, 0x0F - cmp R0, 0x0A - jlt isNum1 - add R0, 0x07 -isNum1: add R0, 0x30 - ret - -; ------------------------------------------------- -; Parameter -; R0 : Bin value -; Return -; R0 : Hex character high -; R1 : Hex character low -bin2hex: push R0 - call nibble2hex - mov R1, R0 - pop R0 - swap R0 - call nibble2hex - ret - -; ------------------------------------------------- diff --git a/lib/misc/debounce.vhd b/lib/misc/debounce.vhd deleted file mode 100644 index 79317a5..0000000 --- a/lib/misc/debounce.vhd +++ /dev/null @@ -1,91 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 19:34:24 10/23/05 --- Design Name: --- Module Name: debounce - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity debounce is - Generic ( ncyc_latency : integer := 100); - Port ( rst : in std_logic; - clk : in std_logic; - input : in std_logic; - output : out std_logic); -end debounce; - -architecture Behavioral of debounce is - -type debounce_state_t is (init_st, wait_st, rel_st); -signal debounce_cs : debounce_state_t; -signal debounce_ns : debounce_state_t; -signal count : integer range 0 to ncyc_latency; -signal input_last : std_logic; - -begin - - debounce_clk: process(rst, clk, debounce_ns, debounce_cs, input) - begin - if (rst = '1') then - count <= 0; - output <= input; - input_last <= input; - else - if rising_edge(clk) then - debounce_cs <= debounce_ns; - if (debounce_cs = wait_st) then - if (count /= 0) then - count <= count - 1; - end if; - else - count <= ncyc_latency; - if (debounce_cs = rel_st) then - output <= input; - input_last <= input; - end if; - end if; - end if; - end if; - end process; - - debounce_in: process(rst, clk, input, input_last, debounce_cs, count) - begin - debounce_ns <= debounce_cs; - case debounce_cs is - when init_st => - if (input /= input_last) then - debounce_ns <= wait_st; - end if; - when wait_st => - if (count = 0) then - debounce_ns <= rel_st; - end if; - when others => - debounce_ns <= init_st; - end case; - end process; - -end Behavioral; diff --git a/lib/misc/debounce2.vhd b/lib/misc/debounce2.vhd deleted file mode 100644 index 206a61c..0000000 --- a/lib/misc/debounce2.vhd +++ /dev/null @@ -1,142 +0,0 @@ -------------------------------------------------- --- Signal Debouncer --- Jeff Bazinet --- February 14, 2002 ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ - - -library ieee; -use ieee.std_logic_1164.all; -library lpm; -use lpm.lpm_components.lpm_counter; - - -entity debounce is - generic(BUFFER_WIDTH: positive:= 30; - CLOCK_DIV: positive:= 15 - ); - port( clock: in std_logic; - reset: in std_logic; - signal_in: in std_logic; - signal_out: out std_logic - ); -end entity debounce; - - -architecture rtl of debounce is - - --------------------------------------------------------------- - -- SIGNAL DECLARATION - --------------------------------------------------------------- - - -- General - signal reset_n: std_logic; - - -- SLOW CLOCK GENERATION - signal clock_reg: std_logic_vector(CLOCK_DIV-1 downto 0); - signal clock_reg_high: std_logic_vector(CLOCK_DIV-1 downto 1); - signal clock_slow: std_logic; - signal clock_slow_wire: std_logic; - - -- DATA BUFFER FILL - signal counter_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0); - signal data_buffer_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0); - - -- CHECK FOR DEBOUNCE STABILITY - signal stable: std_logic; - signal stable_old: std_logic; - signal stable_state_reg:std_logic_vector(BUFFER_WIDTH-1 downto 0); - - -- PUSH BUTTON ENABLE - signal button_pushed: std_logic; - - begin - - --------------------------------------------------------------- - -- SLOW CLOCK GENERATION - --------------------------------------------------------------- - - COUNTER_1: lpm_counter - generic map (lpm_width => CLOCK_DIV) - port map ( - clock => clock, - sclr => reset_n, - cout => clock_slow_wire - ); - - process (clock) is - begin - - clock_slow <= clock_slow_wire; - - end process; - - --------------------------------------------------------------- - -- DATA BUFFER FILL - --------------------------------------------------------------- - - process (clock) is - begin - - if (reset = '0') then - -- Initialization - data_buffer_reg <= (others => '1'); - elsif rising_edge(clock_slow) then - data_buffer_reg <= data_buffer_reg(BUFFER_WIDTH-2 downto 0) & signal_in; - end if; - - end process; - - --------------------------------------------------------------- - -- CHECK FOR DEBOUNCE STABILITY - --------------------------------------------------------------- - - process (clock) is - begin - - if (reset = '0') then - -- Initialization - stable <= '0'; - stable_old <= '0'; - stable_state_reg <= (others => '0'); - elsif rising_edge(clock) then - if (data_buffer_reg = stable_state_reg) then - stable <= '1'; - stable_state_reg <= (others => '0'); - else - stable <= '0'; - end if; - stable_old <= stable; - end if; - - end process; - - --------------------------------------------------------------- - -- PUSH BUTTON ENABLE - --------------------------------------------------------------- - - process (clock) is - begin - - if (reset = '0') then - -- Initialization - button_pushed <= '0'; - elsif rising_edge(clock) then - if (stable_old = '0' and stable = '1') then - button_pushed <= '1'; - else - button_pushed <= '0'; - end if; - end if; - - end process; - - --------------------------------------------------------------- - --------------------------------------------------------------- - - signal_out <= button_pushed; - reset_n <= not reset; - -end rtl; diff --git a/lib/misc/dpram_1w1r.vhd b/lib/misc/dpram_1w1r.vhd deleted file mode 100644 index dee0972..0000000 --- a/lib/misc/dpram_1w1r.vhd +++ /dev/null @@ -1,79 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -entity dpram_1w1r is - Generic ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram_1w1r; - -architecture Behavioral of dpram_1w1r is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal RAM : RAMtype; - -begin - -process (clka) -begin -if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) <= din_a; - end if; - end if; -end if; -end process; - -process (clkb) -begin -if clkb'event and clkb = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); - end if; -end if; -end process; - - -end Behavioral; - diff --git a/lib/misc/dpram_1w1r_dist.vhd b/lib/misc/dpram_1w1r_dist.vhd deleted file mode 100644 index e07555c..0000000 --- a/lib/misc/dpram_1w1r_dist.vhd +++ /dev/null @@ -1,84 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r_dist.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -entity dpram_1w1r_dist is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram_1w1r_dist; - -architecture Behavioral of dpram_1w1r_dist is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal RAM : RAMtype; - - attribute ram_style : string; - attribute ram_style of RAM: signal is "distributed"; - -begin - -process (clka) - begin - if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) <= din_a; - end if; - end if; - end if; -end process; - -process (clkb) - begin - if clkb'event and clkb = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); - end if; - end if; -end process; - - -end Behavioral; - diff --git a/lib/misc/dpram_2w2r.vhd b/lib/misc/dpram_2w2r.vhd deleted file mode 100644 index 33152f3..0000000 --- a/lib/misc/dpram_2w2r.vhd +++ /dev/null @@ -1,88 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -entity dpram_2w2r is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram_2w2r; - -architecture Behavioral of dpram_2w2r is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - shared variable RAM : RAMtype; - -begin - -process (clk_a) -begin -if clk_a'event and clk_a = '1' then - if en_a = '1' then - dout_a <= RAM(to_integer(addr_a)); - if we_a = '1' then - RAM(to_integer(addr_a)) := din_a; - end if; - end if; -end if; -end process; - -process (clk_b) -begin -if clk_b'event and clk_b = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); - if we_b = '1' then - RAM(to_integer(addr_b)) := din_b; - end if; - end if; -end if; -end process; - - -end Behavioral; - diff --git a/lib/misc/dpram_2w2r_virtex4.vhd b/lib/misc/dpram_2w2r_virtex4.vhd deleted file mode 100644 index 6d8bc83..0000000 --- a/lib/misc/dpram_2w2r_virtex4.vhd +++ /dev/null @@ -1,211 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r_virtex4.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity dpram_2w2r is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram_2w2r; - -architecture Structure of dpram_2w2r is - - signal do_a : std_logic_vector(31 downto 0); - signal do_b : std_logic_vector(31 downto 0); - signal di_a : std_logic_vector(31 downto 0); - signal di_b : std_logic_vector(31 downto 0); - signal ad_a : std_logic_vector(14 downto 0); - signal ad_b : std_logic_vector(14 downto 0); - signal wr_a : std_logic_vector(3 downto 0); - signal wr_b : std_logic_vector(3 downto 0); - -begin - --- RAMB16: 16k+2k Parity Paramatizable block RAM --- Virtex-4 --- Xilinx HDL Libraries Guide, version 9.1i -RAMB16_inst : RAMB16 -generic map -( - DOA_REG => 0, -- Optional output registers on the A port (0 or 1) - DOB_REG => 0, -- Optional output registers on the B port (0 or 1) - INIT_A => X"000000000", -- Initial values on A output port - INIT_B => X"000000000", -- Initial values on B output port - INVERT_CLK_DOA_REG => FALSE, -- Invert clock on A port output registers (TRUE or FALSE) - INVERT_CLK_DOB_REG => FALSE, -- Invert clock on B port output registers (TRUE or FALSE) - RAM_EXTENSION_A => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded - RAM_EXTENSION_B => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded - READ_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36 - READ_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36 - SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY", - - -- "GENERATE_X_ONLY" or "NONE" - SRVAL_A => X"000000000", -- Port A output value upon SSR assertion - SRVAL_B => X"000000000", -- Port B output value upon SSR assertion - WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36 - WRITE_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36 - - -- The following INIT_xx declarations specify the initial contents of the RAM - INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", - - -- The next set of INITP_xx are for the parity bits - INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000" -) -port map -( - CASCADEOUTA => open, -- 1-bit cascade output - CASCADEOUTB => open, -- 1-bit cascade output - DOA => do_a, -- 32-bit A port Data Output - DOB => do_b, -- 32-bit B port Data Output - DOPA => open, -- 4-bit A port Parity Output - DOPB => open, -- 4-bit B port Parity Output - ADDRA => ad_a, -- 15-bit A Port Address Input - ADDRB => ad_b, -- 15-bit B Port Address Input - CASCADEINA => '0', -- 1-bit cascade A input - CASCADEINB => '0', -- 1-bit cascade B input - CLKA => clk_a, -- Port A Clock - CLKB => clk_b, -- Port B Clock - DIA => di_a, -- 32-bit A port Data Input - DIB => di_b, -- 32-bit B port Data Input - DIPA => "0000", -- 4-bit A port parity Input - DIPB => "0000", -- 4-bit B port parity Input - ENA => en_a, -- 1-bit A port Enable Input - ENB => en_b, -- 1-bit B port Enable Input - REGCEA => '0', -- 1-bit A port register enable input - REGCEB => '0', -- 1-bit B port register enable input - SSRA => '0', -- 1-bit A port Synchronous Set/Reset Input - SSRB => '0', -- 1-bit B port Synchronous Set/Reset Input - WEA => wr_a, -- 4-bit A port Write Enable Input - WEB => wr_b -- 4-bit B port Write Enable Input -); --- End of RAMB16_inst instantiation - - dout_a <= unsigned(do_a(7 downto 0)); - dout_b <= unsigned(do_b(7 downto 0)); - di_a <= X"000000" & std_logic_vector(din_a); - di_b <= X"000000" & std_logic_vector(din_b); - ad_a <= '0' & std_logic_vector(addr_a) & "000"; - ad_b <= '0' & std_logic_vector(addr_b) & "000"; - wr_a <= (3 downto 0 => we_a); - wr_b <= (3 downto 0 => we_b); - -end Structure; - diff --git a/lib/misc/lcd_port.vhd b/lib/misc/lcd_port.vhd deleted file mode 100644 index 11f97eb..0000000 --- a/lib/misc/lcd_port.vhd +++ /dev/null @@ -1,69 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - - ------------------------------------------------------------------ -entity lcd_port is - Port ( - rst : in std_logic; - clk : in std_logic; - we : in std_logic; - din : in unsigned(7 downto 0); - dout : out unsigned(7 downto 0); - lcd_d : inout unsigned(3 downto 0); - lcd_e : out std_logic; - lcd_rs : out std_logic; - lcd_rw : out std_logic - ); - end lcd_port; - -architecture Behavioral of lcd_port is - - constant clcd_e : integer := 7; - constant clcd_rs : integer := 6; - constant clcd_rw : integer := 5; - - type lcd_t is record - d : unsigned(3 downto 0); - e : std_logic; - rs : std_logic; - rw : std_logic; - end record; - - ------------------------------------------------------------------ - begin - - proc_lcd_port: - process(rst, clk) - variable vlcd : lcd_t; - begin - if (rst = '1') then - dout <= (others => '0'); - vlcd.d := (others => '0'); - vlcd.e := '0'; - vlcd.rw := '1'; - vlcd.rs := '0'; - elsif rising_edge(clk) then - dout <= unsigned("0000" & lcd_d); - if we = '1' then - vlcd.d := din(3 downto 0); - vlcd.e := din(clcd_e); - vlcd.rs := din(clcd_rs); - vlcd.rw := din(clcd_rw); - end if; - end if; - if vlcd.rw = '0' then - lcd_d <= unsigned(vlcd.d); - else - lcd_d <= (others => 'Z'); - end if; - lcd_e <= vlcd.e; - lcd_rs <= vlcd.rs; - lcd_rw <= vlcd.rw; - end process; - ------------------------------------------------------------------ - -end Behavioral; diff --git a/lib/misc/oneshot.vhd b/lib/misc/oneshot.vhd deleted file mode 100644 index 2f5d8bd..0000000 --- a/lib/misc/oneshot.vhd +++ /dev/null @@ -1,223 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 21:52:19 10/22/05 --- Design Name: --- Module Name: oneshot - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/oneshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ --- Component Template --- --- COMPONENT oneshot --- GENERIC (mode : integer); --- PORT( --- rst : IN std_logic; --- clk : IN std_logic; --- input : IN std_logic; --- output : OUT std_logic --- ); --- END COMPONENT; --- --- Instantation Template --- --- oneshot_int: oneshot --- GENERIC MAP ( --- mode => 1) --- PORT MAP( --- rst => , --- clk => , --- input => , --- output => --- ); --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity oneshot is - Generic ( mode : integer range 0 to 2 := 1); - Port ( rst : in std_logic; - clk : in std_logic; - input : in std_logic; - output : out std_logic); -end oneshot; - -architecture Behavioral of oneshot is - -type shot_state_t is (shot_pos_st, shot_neg_st, release_pos_st, release_neg_st); - -signal shot_cs : shot_state_t; -signal shot_ns : shot_state_t; - -begin - -mode_0: -if mode = 0 generate -begin - shot_clk: process(rst, clk, shot_ns, input) - begin - if (rst = '1') then - if (input = '1') then - shot_cs <= release_pos_st; - else - shot_cs <= release_neg_st; - end if; - else - if rising_edge(clk) then - shot_cs <= shot_ns; - end if; - end if; - end process; - - shot_in: process(rst, clk, input, shot_cs) - begin - shot_ns <= shot_cs; - case shot_cs is - when release_pos_st => - if (input = '0') then - shot_ns <= shot_neg_st; - end if; - when shot_neg_st => - shot_ns <= release_neg_st; - when release_neg_st => - if (input = '1') then - shot_ns <= release_pos_st; - end if; - when others => null; - end case; - end process; - - shot_out: process(shot_cs) - begin - output <= '0'; - case shot_cs is - when shot_pos_st => - output <= '1'; - when shot_neg_st => - output <= '1'; - when others => null; - end case; - end process; -end generate; - -mode_1: -if mode = 1 generate -begin - shot_clk: process(rst, clk, shot_ns, input) - begin - if (rst = '1') then - if (input = '1') then - shot_cs <= release_pos_st; - else - shot_cs <= release_neg_st; - end if; - else - if rising_edge(clk) then - shot_cs <= shot_ns; - end if; - end if; - end process; - - shot_in: process(rst, clk, input, shot_cs) - begin - shot_ns <= shot_cs; - case shot_cs is - when shot_pos_st => - shot_ns <= release_pos_st; - when release_pos_st => - if (input = '0') then - shot_ns <= release_neg_st; - end if; - when release_neg_st => - if (input = '1') then - shot_ns <= shot_pos_st; - end if; - when others => null; - end case; - end process; - - shot_out: process(shot_cs) - begin - output <= '0'; - case shot_cs is - when shot_pos_st => - output <= '1'; - when shot_neg_st => - output <= '1'; - when others => null; - end case; - end process; -end generate; - -mode_2: -if mode = 2 generate -begin - shot_clk: process(rst, clk, shot_ns, input) - begin - if (rst = '1') then - if (input = '1') then - shot_cs <= release_pos_st; - else - shot_cs <= release_neg_st; - end if; - else - if rising_edge(clk) then - shot_cs <= shot_ns; - end if; - end if; - end process; - - shot_in: process(rst, clk, input, shot_cs) - begin - shot_ns <= shot_cs; - case shot_cs is - when shot_pos_st => - shot_ns <= release_pos_st; - when release_pos_st => - if (input = '0') then - shot_ns <= shot_neg_st; - end if; - when shot_neg_st => - shot_ns <= release_neg_st; - when release_neg_st => - if (input = '1') then - shot_ns <= shot_pos_st; - end if; - end case; - end process; - - shot_out: process(shot_cs) - begin - output <= '0'; - case shot_cs is - when shot_pos_st => - output <= '1'; - when shot_neg_st => - output <= '1'; - when others => null; - end case; - end process; -end generate; - - - -end Behavioral; diff --git a/lib/misc/singleshot.vhd b/lib/misc/singleshot.vhd deleted file mode 100644 index 25f7013..0000000 --- a/lib/misc/singleshot.vhd +++ /dev/null @@ -1,155 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 21:52:19 10/22/05 --- Design Name: --- Module Name: singleshot - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ --- Component Template --- --- COMPONENT singleshot --- GENERIC (mode : integer); --- PORT( --- rst : IN std_logic; --- clk : IN std_logic; --- input : IN std_logic; --- output : OUT std_logic --- ); --- END COMPONENT; --- --- Instantation Template --- --- singleshot_int: oneshot --- GENERIC MAP ( --- mode => 1) --- PORT MAP( --- rst => , --- clk => , --- input => , --- output => --- ); --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity singleshot is - Generic ( mode : integer range 0 to 2 := 1); - Port ( rst : in std_logic; - clk : in std_logic; - input : in std_logic; - output : out std_logic); -end singleshot; - -architecture Behavioral of singleshot is - -type s_t is (idle, shot_in, active, shot_out); -signal s, sn : s_t; - -begin - -process (rst, clk, sn) -begin - if rising_edge(clk) then - if rst = '1' then - s <= idle; - else - s <= sn; - end if; - end if; -end process; - -mode_1: -if mode = 1 generate -begin - process (input, s) - begin - output <= '0'; - sn <= s; - case s is - when idle => - if input = '1' then - sn <= shot_in; - end if; - when shot_in => - output <= '1'; - sn <= active; - when active => - if input = '0' then - sn <= shot_out; - end if; - when shot_out => - sn <= idle; - when others => null; - end case; - end process; -end generate; - -mode_0: -if mode = 0 generate -begin - process (input, s) - begin - output <= '0'; - sn <= s; - case s is - when idle => - if input = '1' then - sn <= shot_in; - end if; - when shot_in => - sn <= active; - when active => - if input = '0' then - sn <= shot_out; - end if; - when shot_out => - output <= '1'; - sn <= idle; - when others => null; - end case; - end process; -end generate; - -mode_2: -if mode = 2 generate -begin - process (input, s) - begin - output <= '0'; - sn <= s; - case s is - when idle => - if input = '1' then - sn <= shot_in; - end if; - when shot_in => - output <= '1'; - sn <= active; - when active => - if input = '0' then - sn <= shot_out; - end if; - when shot_out => - output <= '1'; - sn <= idle; - when others => null; - end case; - end process; -end generate; - -end Behavioral; diff --git a/lib/misc/tb_template.vhd b/lib/misc/tb_template.vhd deleted file mode 100644 index f96f294..0000000 --- a/lib/misc/tb_template.vhd +++ /dev/null @@ -1,63 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE STD.TEXTIO.ALL; - --- LIBRARY WORK; --- USE.YOURLIB.WHATELSE - -ENTITY tb_template IS -END tb_template; - -ARCHITECTURE behavior OF tb_template IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT your_comp - GENERIC - ( - ); - PORT - ( - ); - END COMPONENT; - - --Constants - constant PERIOD : time := 10 ns; - - --Inputs - signal clk : STD_LOGIC := '0'; - - --Outputs - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: your_comp - GENERIC MAP - ( - ) - PORT MAP - ( - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - - assert false report "Test finished" severity error; - wait; - - END PROCESS; - -END tb_template; diff --git a/lib/misc/utils_pkg.vhd b/lib/misc/utils_pkg.vhd deleted file mode 100644 index 2fcaec6..0000000 --- a/lib/misc/utils_pkg.vhd +++ /dev/null @@ -1,63 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - -package utils_pkg is - - -- Constants - - -- Functions - function NextPowerOfTwo(x : natural) return natural; - function NextExpBaseTwo(x : natural) return natural; - function GCD(a, b : natural) return natural; - function LCM(a, b : natural) return natural; - -end utils_pkg; - - -package body utils_pkg is - - function NextExpBaseTwo(x : natural) return natural is - begin - return natural(ceil(log2(real(x)))); - end NextExpBaseTwo; - - function NextPowerOfTwo(x : natural) return natural is - begin - - return 2**NextExpBaseTwo(x); - end NextPowerOfTwo; - - function GCD(a, b : natural) return natural is - variable aa : natural; - variable bb : natural; - begin - aa := a; - bb := b; - while bb /= 0 loop - if aa > bb then - aa := aa - bb; - else - bb := bb - aa; - end if; - end loop; - - return aa; - - end GCD; - - function LCM(a, b : natural) return natural is - begin - - return (a * b)/GCD(a, b); - - end LCM; - -end utils_pkg; - - diff --git a/lib/radio/mix/sim/tb_mix_cpx.fdo b/lib/radio/mix/sim/tb_mix_cpx.fdo deleted file mode 100644 index 14d9422..0000000 --- a/lib/radio/mix/sim/tb_mix_cpx.fdo +++ /dev/null @@ -1,13 +0,0 @@ -vlib work -vcom -explicit -93 "../../../../lib/fixed/fixed_pkg_c.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/mix_pkg.vhd" -vcom -explicit -93 "../src/mix_cpx.vhd" -vcom -explicit -93 "../src/tb_mix_cpx.vhd" -vsim -t 1ps -lib work tb_mix_cpx -do {tb_mix_cpx.wdo} -view wave -view structure -view signals -run 500ns diff --git a/lib/radio/mix/sim/tb_mix_cpx.wdo b/lib/radio/mix/sim/tb_mix_cpx.wdo deleted file mode 100644 index c84c651..0000000 --- a/lib/radio/mix/sim/tb_mix_cpx.wdo +++ /dev/null @@ -1,42 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mix_cpx/clk -add wave -noupdate -format Logic /tb_mix_cpx/srst -add wave -noupdate -divider {Fixed In} -add wave -noupdate -format Logic /tb_mix_cpx/in_valid -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/x_re_in -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/x_im_in -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/y_re_in -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/y_im_in -add wave -noupdate -divider {Fixed OUT} -add wave -noupdate -format Logic /tb_mix_cpx/out_valid -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/z_re_out -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/z_im_out -add wave -noupdate -divider {Convenient real out} -add wave -noupdate -format Literal /tb_mix_cpx/x_re -add wave -noupdate -format Literal /tb_mix_cpx/x_im -add wave -noupdate -format Literal /tb_mix_cpx/y_re -add wave -noupdate -format Literal /tb_mix_cpx/y_im -add wave -noupdate -format Literal /tb_mix_cpx/z_re -add wave -noupdate -format Literal /tb_mix_cpx/z_im -add wave -noupdate -format Logic /tb_mix_cpx/fileout_enable -add wave -noupdate -format Literal /tb_mix_cpx/uut/p_re_left -add wave -noupdate -format Literal /tb_mix_cpx/uut/p_re_right -add wave -noupdate -format Literal /tb_mix_cpx/uut/p_im_left -add wave -noupdate -format Literal /tb_mix_cpx/uut/p_im_right -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {90000 ps} 0} -configure wave -namecolwidth 193 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {348406 ps} diff --git a/lib/radio/mix/sim/tb_mix_real.fdo b/lib/radio/mix/sim/tb_mix_real.fdo deleted file mode 100644 index cbf7dd0..0000000 --- a/lib/radio/mix/sim/tb_mix_real.fdo +++ /dev/null @@ -1,13 +0,0 @@ -vlib work -vcom -explicit -93 "../../../../lib/fixed/fixed_pkg_c.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/mix_pkg.vhd" -vcom -explicit -93 "../src/mix_real.vhd" -vcom -explicit -93 "../src/tb_mix_real.vhd" -vsim -t 1ps -lib work tb_mix_real -do {tb_mix_real.wdo} -view wave -view structure -view signals -run 500ns diff --git a/lib/radio/mix/sim/tb_mix_real.wdo b/lib/radio/mix/sim/tb_mix_real.wdo deleted file mode 100644 index 6643ce3..0000000 --- a/lib/radio/mix/sim/tb_mix_real.wdo +++ /dev/null @@ -1,36 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mix_real/clk -add wave -noupdate -format Logic /tb_mix_real/srst -add wave -noupdate -divider {Fixed In} -add wave -noupdate -format Logic /tb_mix_real/in_valid -add wave -noupdate -format Literal -radix decimal /tb_mix_real/x_re_din -add wave -noupdate -format Literal -radix decimal /tb_mix_real/y_re_din -add wave -noupdate -format Literal -radix decimal /tb_mix_real/y_im_din -add wave -noupdate -divider {Fixed OUT} -add wave -noupdate -format Logic /tb_mix_real/out_valid -add wave -noupdate -format Literal -radix decimal /tb_mix_real/z_re_dout -add wave -noupdate -format Literal -radix decimal /tb_mix_real/z_im_dout -add wave -noupdate -divider {Convenient real out} -add wave -noupdate -format Literal /tb_mix_real/x_re -add wave -noupdate -format Literal /tb_mix_real/y_re -add wave -noupdate -format Literal /tb_mix_real/y_im -add wave -noupdate -format Literal /tb_mix_real/z_re -add wave -noupdate -format Literal /tb_mix_real/z_im -add wave -noupdate -format Logic /tb_mix_real/fileout_enable -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {120000 ps} 0} -configure wave -namecolwidth 193 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {348406 ps} diff --git a/lib/radio/mix/sim/tb_undc_real.fdo b/lib/radio/mix/sim/tb_undc_real.fdo deleted file mode 100644 index f7d989f..0000000 --- a/lib/radio/mix/sim/tb_undc_real.fdo +++ /dev/null @@ -1,13 +0,0 @@ -vlib work -vcom -explicit -93 "../../../../lib/fixed/fixed_pkg_c.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/mix_pkg.vhd" -vcom -explicit -93 "../src/undc_real.vhd" -vcom -explicit -93 "../src/tb_undc_real.vhd" -vsim -t 1ps -lib work tb_undc_real -do {tb_undc_real.wdo} -view wave -view structure -view signals -run 500us diff --git a/lib/radio/mix/sim/tb_undc_real.wdo b/lib/radio/mix/sim/tb_undc_real.wdo deleted file mode 100644 index f965905..0000000 --- a/lib/radio/mix/sim/tb_undc_real.wdo +++ /dev/null @@ -1,38 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_undc_real/clk -add wave -noupdate -format Logic /tb_undc_real/srst -add wave -noupdate -format Logic /tb_undc_real/din_valid -add wave -noupdate -format Logic /tb_undc_real/kin_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/din -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/kin -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/dout -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/dc_out -add wave -noupdate -format Logic /tb_undc_real/dout_valid -add wave -noupdate -format Literal /tb_undc_real/k -add wave -noupdate -format Literal /tb_undc_real/x -add wave -noupdate -format Literal /tb_undc_real/y -add wave -noupdate -format Literal /tb_undc_real/dc -add wave -noupdate -divider UUT -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/k -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/x -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y1 -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y2 -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/dc -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {97905405 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {157500 ns} diff --git a/lib/radio/mix/src/mix_cpx.vhd b/lib/radio/mix/src/mix_cpx.vhd deleted file mode 100644 index f77a312..0000000 --- a/lib/radio/mix/src/mix_cpx.vhd +++ /dev/null @@ -1,166 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: mix_cpx - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.mix_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity mix_cpx is -Generic -( - nbits_in : integer := 12; - nbits_in_frac : integer := 12; - nbits_out : integer := 12; - nbits_out_frac : integer := 12; - nbits_scale_z : integer := 0; - has_in_reg : boolean := false; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false; - rounding : boolean := true; - saturating : boolean := true -); -Port -( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_re_in : in sfixed; - x_im_in : in sfixed; - y_re_in : in sfixed; - y_im_in : in sfixed; - out_valid : out std_logic; - z_re_out : out sfixed; - z_im_out : out sfixed -); -end mix_cpx; - -architecture Behavioral of mix_cpx is -constant nbits_prod : integer := nbits_out + nbits_scale_z; -constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z; - -signal x_re, x_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal p_re_left, p_re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); -signal p_im_left, p_im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); -signal valid, p_valid : std_logic; ------------------------------------------------------------- -begin - - ------------------------------------------------------------- - proc_in_reg: process(srst, clk, in_valid, x_re_in, x_im_in, y_re_in, y_im_in) - begin - if has_in_reg = true then - if rising_edge(clk) then - if srst = '1' then - x_re <= to_sfixed(0, x_re); - x_im <= to_sfixed(0, x_im); - y_re <= to_sfixed(0, y_re); - y_im <= to_sfixed(0, y_im); - valid <= '0'; - else - valid <= in_valid; - if in_valid = '1' then - x_re <= x_re_in; - x_im <= x_im_in; - y_re <= y_re_in; - y_im <= y_im_in; - end if; - end if; - end if; - else - x_re <= x_re_in; - x_im <= x_im_in; - y_re <= y_re_in; - y_im <= y_im_in; - valid <= in_valid; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(srst, clk, valid, x_re, x_im, y_re, y_im) - variable re_left, re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low); - variable im_left, im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low); - - begin - re_left := resize(x_re * y_re, re_left); - re_right := resize(x_im * y_im, re_right); - im_left := resize(x_re * y_im, im_left); - im_right := resize(x_im * y_re, im_right); - if has_pipe_reg = true then - if rising_edge(clk) then - if srst = '1' then - p_re_left <= to_sfixed(0, p_re_left); - p_re_right <= to_sfixed(0, p_re_right); - p_im_left <= to_sfixed(0, p_im_left); - p_im_right <= to_sfixed(0, p_im_right); - p_valid <= '0'; - else - p_re_left <= re_left; - p_re_right <= re_right; - p_im_left <= im_left; - p_im_right <= im_right; - p_valid <= valid; - end if; - end if; - else - p_re_left <= re_left; - p_re_right <= re_right; - p_im_left <= im_left; - p_im_right <= im_right; - p_valid <= valid; - end if; - end process; - ------------------------------------------------------------- - proc_out_reg: process(srst, clk, p_valid, p_re_left, p_re_right, p_im_left, p_im_right) - variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - begin - sum_re := resize(scalb(p_re_left - p_re_right, nbits_scale_z), re, rounding, saturating); - sum_im := resize(scalb(p_im_left + p_im_right, nbits_scale_z), im, rounding, saturating); - if has_out_reg = true then - if rising_edge(clk) then - if srst = '1' then - z_re_out <= to_sfixed(0, re); - z_im_out <= to_sfixed(0, im); - out_valid <= '0'; - else - z_re_out <= sum_re; - z_im_out <= sum_im; - out_valid <= p_valid; - end if; - end if; - else - z_re_out <= re; - z_im_out <= im; - out_valid <= p_valid; - end if; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/mix/src/mix_pkg.vhd b/lib/radio/mix/src/mix_pkg.vhd deleted file mode 100644 index 9e6dcbf..0000000 --- a/lib/radio/mix/src/mix_pkg.vhd +++ /dev/null @@ -1,62 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use work.fixed_pkg.all; - -package mix_pkg is - - ------------------------------------------------------------- - -- Constructor helpers - -- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range); - function uproto (nbits : integer; nbits_frac : integer) return ufixed; - - -- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range); - function sproto (nbits : integer; nbits_frac : integer) return sfixed; - - function to_unsigned (src : ufixed) return UNSIGNED; - function to_signed (src : sfixed) return SIGNED; - -------------------------------------------------------------------------------- -end; -- package mix_cpx_pkg; - -package body mix_pkg is - - ------------------------------------------------------------- - -- Constuctor helpers - function uproto (nbits : integer; nbits_frac : integer) return ufixed is - constant result : ufixed (nbits-nbits_frac-1 downto -nbits_frac) := (others => '0'); - begin - return result(nbits-nbits_frac-1 downto -nbits_frac); - end uproto; - - ------------------------------------------------------------- - function sproto (nbits : integer; nbits_frac : integer) return sfixed is - constant result : sfixed (nbits-nbits_frac downto -nbits_frac+1) := (others => '0'); - begin - return result(nbits-nbits_frac downto -nbits_frac+1); - end sproto; - - ------------------------------------------------------------- - function to_unsigned (src : ufixed) return UNSIGNED is - subtype t is UNSIGNED(src'high - src'low downto 0); - variable slv : t; - begin - slv := t(src); - return UNSIGNED(to_X01(std_logic_vector(slv))); - - end function to_unsigned; - - ------------------------------------------------------------- - function to_signed (src : sfixed) return SIGNED is - subtype t is SIGNED(src'high - src'low downto 0); - variable slv : t; - begin - slv := t(src); - return SIGNED(to_X01(std_logic_vector(slv))); - - end function to_signed; - - -------------------------------------------------------------------------------- -end; -- package mix_pkg; diff --git a/lib/radio/mix/src/mix_real.vhd b/lib/radio/mix/src/mix_real.vhd deleted file mode 100644 index 3dfe3cc..0000000 --- a/lib/radio/mix/src/mix_real.vhd +++ /dev/null @@ -1,155 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: mix_cpx - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.mix_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity mix_real is -Generic -( - nbits_in : integer := 12; - nbits_in_frac : integer := 12; - nbits_out : integer := 12; - nbits_out_frac : integer := 12; - nbits_scale_z : integer := 0; - has_in_reg : boolean := false; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false; - rounding : boolean := true; - saturating : boolean := true -); -Port -( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_re_din : in sfixed; - y_re_din : in sfixed; - y_im_din : in sfixed; - out_valid : out std_logic; - z_re_dout : out sfixed; - z_im_dout : out sfixed -); -end mix_real; - -architecture Behavioral of mix_real is - -constant nbits_prod : integer := nbits_out + nbits_scale_z; -constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z; - -signal x_re : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal p_re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); -signal p_im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); -signal valid, p_valid : std_logic; ------------------------------------------------------------- -begin - - ------------------------------------------------------------- - proc_in_reg: process(srst, clk, in_valid, x_re_din, y_re_din, y_im_din) - begin - if has_in_reg = true then - if rising_edge(clk) then - if srst = '1' then - x_re <= to_sfixed(0, x_re); - y_re <= to_sfixed(0, y_re); - y_im <= to_sfixed(0, y_im); - valid <= '0'; - else - valid <= in_valid; - if in_valid = '1' then - x_re <= x_re_din; - y_re <= y_re_din; - y_im <= y_im_din; - end if; - end if; - end if; - else - x_re <= x_re_din; - y_re <= y_re_din; - y_im <= y_im_din; - valid <= in_valid; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(srst, clk, valid, x_re, y_re, y_im) - variable re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); - variable im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); - - begin - re_left := resize(x_re * y_re, re_left); - im_left := resize(x_re * y_im, im_left); - if has_pipe_reg = true then - if rising_edge(clk) then - if srst = '1' then - p_re_left <= to_sfixed(0, p_re_left); - p_im_left <= to_sfixed(0, p_im_left); - p_valid <= '0'; - else - p_re_left <= re_left; - p_im_left <= im_left; - p_valid <= valid; - end if; - end if; - else - p_re_left <= re_left; - p_im_left <= im_left; - p_valid <= valid; - end if; - end process; - ------------------------------------------------------------- - proc_out_reg: process(srst, clk, p_valid, p_re_left, p_im_left) - variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - begin - sum_re := resize(scalb(p_re_left, nbits_scale_z), re, rounding, saturating); - sum_im := resize(scalb(p_im_left, nbits_scale_z), im, rounding, saturating); - if has_out_reg = true then - if rising_edge(clk) then - if srst = '1' then - z_re_dout <= to_sfixed(0, re); - z_im_dout <= to_sfixed(0, im); - out_valid <= '0'; - else - z_re_dout <= sum_re; - z_im_dout <= sum_im; - out_valid <= p_valid; - end if; - end if; - else - z_re_dout <= re; - z_im_dout <= im; - out_valid <= p_valid; - end if; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/mix/src/tb_mix_cpx.vhd b/lib/radio/mix/src/tb_mix_cpx.vhd deleted file mode 100644 index 7882185..0000000 --- a/lib/radio/mix/src/tb_mix_cpx.vhd +++ /dev/null @@ -1,208 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_mix_cpx --- Module Name: tb_mix_cpx.vhd --- Project Name: mix_cpx --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.fixed_pkg.all; -use work.mix_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_mix_cpx IS - Generic ( - nbits_in : integer := 24; - nbits_in_frac : integer := 24; - nbits_out : integer := 24; - nbits_out_frac : integer := 24; - nbits_scale_z : integer := 0; - has_in_reg : boolean := true; - has_pipe_reg : boolean := true; - has_out_reg : boolean := true; - rounding : boolean := true; - saturating : boolean := true - ); -END tb_mix_cpx; - -ARCHITECTURE behavior OF tb_mix_cpx IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT mix_cpx - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - nbits_scale_z : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - has_out_reg : boolean; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_re_in : in sfixed; - x_im_in : in sfixed; - y_re_in : in sfixed; - y_im_in : in sfixed; - out_valid : out std_logic; - z_re_out : out sfixed; - z_im_out : out sfixed - ); - END COMPONENT; - - --Constants - constant PERIOD : time := 10 ns; - - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL in_valid : std_logic := '0'; - SIGNAL x_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - SIGNAL x_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - SIGNAL y_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - SIGNAL y_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - - --Outputs - SIGNAL z_re_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL z_im_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL out_valid : std_logic; - - SIGNAL fileout_enable : std_logic := '0'; - SIGNAL x_re : real := 0.0; - SIGNAL x_im : real := 0.0; - SIGNAL y_re : real := 0.0; - SIGNAL y_im : real := 0.0; - SIGNAL z_re : real := 0.0; - SIGNAL z_im : real := 0.0; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: mix_cpx - GENERIC MAP - ( - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - nbits_scale_z => nbits_scale_z, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_re_in => x_re_in, - x_im_in => x_im_in, - y_re_in => y_re_in, - y_im_in => y_im_in, - out_valid => out_valid, - z_re_out => z_re_out, - z_im_out => z_im_out - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.5, x_re_in); - x_im_in <= to_sfixed(0.5, x_im_in); - y_re_in <= to_sfixed(0.5, y_re_in); - y_im_in <= to_sfixed(0.5, y_im_in); - in_valid <= '1'; - wait until rising_edge(clk); - in_valid <= '0'; - wait for 5*PERIOD; - ------------------------------------------ - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.125, x_re_in); - x_im_in <= to_sfixed(0.25, x_im_in); - y_re_in <= to_sfixed(0.25, y_re_in); - y_im_in <= to_sfixed(0.125, y_im_in); - in_valid <= '1'; - wait until rising_edge(clk); - in_valid <= '0'; - wait for 5*PERIOD; - ------------------------------------------ - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.125, x_re_in); - x_im_in <= to_sfixed(-0.25, x_im_in); - y_re_in <= to_sfixed(0.25, y_re_in); - y_im_in <= to_sfixed(0.125, y_im_in); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.125, x_re_in); - x_im_in <= to_sfixed(-0.25, x_im_in); - y_re_in <= to_sfixed(0.25, y_re_in); - y_im_in <= to_sfixed(0.125, y_im_in); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.3, x_re_in); - x_im_in <= to_sfixed(0.0, x_im_in); - y_re_in <= to_sfixed(-0.5, y_re_in); - y_im_in <= to_sfixed(0.5, y_im_in); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.0, x_re_in); - x_im_in <= to_sfixed(-0.7071, x_im_in); - y_re_in <= to_sfixed(0.0, y_re_in); - y_im_in <= to_sfixed(-0.7071, y_im_in); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - in_valid <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - x_re <= to_real(x_re_in); - x_im <= to_real(x_im_in); - y_re <= to_real(y_re_in); - y_im <= to_real(y_im_in); - z_re <= to_real(z_re_out); - z_im <= to_real(z_im_out); - -END; diff --git a/lib/radio/mix/src/tb_mix_real.vhd b/lib/radio/mix/src/tb_mix_real.vhd deleted file mode 100644 index a9e458e..0000000 --- a/lib/radio/mix/src/tb_mix_real.vhd +++ /dev/null @@ -1,197 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_mix_cpx --- Module Name: tb_mix_cpx.vhd --- Project Name: mix_cpx --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.fixed_pkg.all; -use work.mix_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_mix_real IS - Generic ( - nbits_in : integer := 24; - nbits_in_frac : integer := 24; - nbits_out : integer := 24; - nbits_out_frac : integer := 24; - nbits_scale_z : integer := 0; - has_in_reg : boolean := true; - has_pipe_reg : boolean := true; - has_out_reg : boolean := true; - rounding : boolean := true; - saturating : boolean := true - ); -END tb_mix_real; - -ARCHITECTURE behavior OF tb_mix_real IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT mix_real - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - nbits_scale_z : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - has_out_reg : boolean; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_re_din : in sfixed; - y_re_din : in sfixed; - y_im_din : in sfixed; - out_valid : out std_logic; - z_re_dout : out sfixed; - z_im_dout : out sfixed - ); - END COMPONENT; - - --Constants - constant PERIOD : time := 10 ns; - - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL in_valid : std_logic := '0'; - SIGNAL x_re_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - SIGNAL y_re_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - SIGNAL y_im_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - - --Outputs - SIGNAL z_re_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL z_im_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL out_valid : std_logic; - - SIGNAL fileout_enable : std_logic := '0'; - SIGNAL x_re : real := 0.0; - SIGNAL y_re : real := 0.0; - SIGNAL y_im : real := 0.0; - SIGNAL z_re : real := 0.0; - SIGNAL z_im : real := 0.0; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: mix_real - GENERIC MAP - ( - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - nbits_scale_z => nbits_scale_z, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_re_din => x_re_din, - y_re_din => y_re_din, - y_im_din => y_im_din, - out_valid => out_valid, - z_re_dout => z_re_dout, - z_im_dout => z_im_dout - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.5, x_re_din); - y_re_din <= to_sfixed(0.5, y_re_din); - y_im_din <= to_sfixed(0.5, y_im_din); - in_valid <= '1'; - wait until rising_edge(clk); - in_valid <= '0'; - wait for 5*PERIOD; - ------------------------------------------ - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.125, x_re_din); - y_re_din <= to_sfixed(0.25, y_re_din); - y_im_din <= to_sfixed(0.125, y_im_din); - in_valid <= '1'; - wait until rising_edge(clk); - in_valid <= '0'; - wait for 5*PERIOD; - ------------------------------------------ - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.125, x_re_din); - y_re_din <= to_sfixed(0.25, y_re_din); - y_im_din <= to_sfixed(0.125, y_im_din); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.125, x_re_din); - y_re_din <= to_sfixed(0.25, y_re_din); - y_im_din <= to_sfixed(0.125, y_im_din); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.3, x_re_din); - y_re_din <= to_sfixed(-0.5, y_re_din); - y_im_din <= to_sfixed(0.5, y_im_din); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.0, x_re_din); - y_re_din <= to_sfixed(0.0, y_re_din); - y_im_din <= to_sfixed(-0.7071, y_im_din); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - in_valid <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - x_re <= to_real(x_re_din); - y_re <= to_real(y_re_din); - y_im <= to_real(y_im_din); - z_re <= to_real(z_re_dout); - z_im <= to_real(z_im_dout); - -END; diff --git a/lib/radio/mix/src/tb_undc_real.vhd b/lib/radio/mix/src/tb_undc_real.vhd deleted file mode 100644 index 3c7a52f..0000000 --- a/lib/radio/mix/src/tb_undc_real.vhd +++ /dev/null @@ -1,158 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_mix_cpx --- Module Name: tb_mix_cpx.vhd --- Project Name: mix_cpx --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.fixed_pkg.all; -use work.mix_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_undc_real IS - Generic ( - nbits_data : integer := 24; - nbits_data_frac : integer := 24; - nbits_k : integer := 24; - nbits_k_frac : integer := 24; - has_in_reg : boolean := true; - rounding : boolean := true; - saturating : boolean := true - ); -END tb_undc_real; - -ARCHITECTURE behavior OF tb_undc_real IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT undc_real - Generic - ( - nbits_data : integer; - nbits_data_frac : integer; - nbits_k : integer; - nbits_k_frac : integer; - has_in_reg : boolean; - rounding : boolean; - saturating : boolean - ); - Port - ( - srst : in std_logic; - clk : in std_logic; - din_valid : in std_logic; - din : in sfixed; - kin_valid : in std_logic; - kin : in sfixed; - dout_valid : out std_logic; - dout : out sfixed; - dc_out : out sfixed - ); - END COMPONENT; - - --Constants - constant PERIOD : time := 10 ns; - - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL din_valid : std_logic := '0'; - SIGNAL kin_valid : std_logic := '0'; - SIGNAL din : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low); - SIGNAL kin : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low); - - --Outputs - SIGNAL dout : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low); - SIGNAL dc_out : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low); - SIGNAL dout_valid : std_logic; - - SIGNAL k : real := 0.0; - SIGNAL x : real := 0.0; - SIGNAL y : real := 0.0; - SIGNAL dc : real := 0.0; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: undc_real - GENERIC MAP - ( - nbits_data => nbits_data, - nbits_data_frac => nbits_data_frac, - nbits_k => nbits_k, - nbits_k_frac => nbits_k_frac, - has_in_reg => has_in_reg, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - din_valid => din_valid, - din => din, - kin_valid => kin_valid, - kin => kin, - dout_valid => dout_valid, - dout => dout, - dc_out => dc_out - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - -- Load k - ------------------------------------------ - wait for 2*PERIOD; - wait until rising_edge(clk); - kin <= to_sfixed(0.0005, kin); - kin_valid <= '1'; - wait until rising_edge(clk); - kin_valid <= '1'; - ------------------------------------------ - -- Process - ------------------------------------------ - wait for 2*PERIOD; - wait until rising_edge(clk); - din <= to_sfixed(0.5, din); - din_valid <= '1'; - wait until rising_edge(clk); - din_valid <= '1'; - wait for 5*PERIOD; - - wait for 200*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - k <= to_real(kin); - x <= to_real(din); - y <= to_real(dout); - dc <= to_real(dc_out); - -END; diff --git a/lib/radio/mix/src/undc_real.vhd b/lib/radio/mix/src/undc_real.vhd deleted file mode 100644 index be6df6e..0000000 --- a/lib/radio/mix/src/undc_real.vhd +++ /dev/null @@ -1,139 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: mix_cpx - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.mix_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity undc_real is -Generic -( - nbits_data : integer := 12; - nbits_data_frac : integer := 12; - nbits_k : integer := 12; - nbits_k_frac : integer := 12; - has_in_reg : boolean := false; - rounding : boolean := true; - saturating : boolean := true -); -Port -( - srst : in std_logic; - clk : in std_logic; - din_valid : in std_logic; - din : in sfixed; - kin_valid : in std_logic; - kin : in sfixed; - dout_valid : out std_logic; - dout : out sfixed; - dc_out : out sfixed -); -end undc_real; - -architecture Behavioral of undc_real is - -constant nbits_internal : integer := nbits_data + nbits_data; -constant nbits_internal_frac : integer := nbits_data_frac + nbits_data_frac; - -signal x : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low); -signal k : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low); -signal dc : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low); -signal y : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low); -signal y1 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low); -signal y2 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low); - -begin - -dout <= resize(y, sproto(nbits_data, nbits_data_frac), rounding, saturating); -dc_out <= resize(dc, sproto(nbits_data, nbits_data_frac), false, false); - ------------------------------------------------------------- - proc_din_reg: process(clk, din_valid, din) - begin - if has_in_reg = true then - if rising_edge(clk) then - if srst = '1' then - x <= to_sfixed(0, x); - else - if din_valid = '1' then - x <= din; - end if; - end if; - end if; - else - x <= din; - end if; - end process; - ------------------------------------------------------------- - proc_valid_reg: process(clk, din_valid) - begin - if has_in_reg = true then - if rising_edge(clk) then - if srst = '1' then - dout_valid <= '0'; - else - dout_valid <= din_valid; - end if; - end if; - else - dout_valid <= din_valid; - end if; - end process; - ------------------------------------------------------------- - proc_kin_reg: process(clk, kin_valid, kin) - begin - if rising_edge(clk) then - if srst = '1' then - k <= to_sfixed(0, k); - else - if kin_valid = '1' then - k <= kin; - end if; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_y: process(clk, x, dc) - begin - y <= resize(x - dc, y, false, false); - if rising_edge(clk) then - if srst = '1' then - y1 <= to_sfixed(0, y1); - y2 <= to_sfixed(0, y2); - dc <= to_sfixed(0, dc); - else - y1 <= y; - y2 <= resize(y1 * k, y2, false, false); - dc <= resize(y2 + dc, dc, false, false); - end if; - end if; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/sim/tb_nco.fdo b/lib/radio/nco/sim/tb_nco.fdo deleted file mode 100644 index ae31dbf..0000000 --- a/lib/radio/nco/sim/tb_nco.fdo +++ /dev/null @@ -1,15 +0,0 @@ -vlib work -vcom -explicit -93 "../../../fixed/fixed_pkg_c.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/nco_pkg.vhd" -vcom -explicit -93 "../src/waverom_dual.vhd" -vcom -explicit -93 "../src/wavelut.vhd" -vcom -explicit -93 "../src/nco_dbg.vhd" -vcom -explicit -93 "../src/tb_nco.vhd" -vsim -t 1ps -lib work tb_nco -do {tb_nco.wdo} -view wave -view structure -view signals -run 250us diff --git a/lib/radio/nco/sim/tb_nco.wdo b/lib/radio/nco/sim/tb_nco.wdo deleted file mode 100644 index 0fd0917..0000000 --- a/lib/radio/nco/sim/tb_nco.wdo +++ /dev/null @@ -1,46 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_nco/uut/srst -add wave -noupdate -format Logic /tb_nco/uut/clk -add wave -noupdate -format Logic /tb_nco/uut/pacc_clr -add wave -noupdate -format Logic /tb_nco/uut/pacc_inc -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in -add wave -noupdate -format Logic /tb_nco/uut/freq_load -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in -add wave -noupdate -format Logic /tb_nco/uut/phase_load -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_out -add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_i -add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_q -add wave -noupdate -format Logic /tb_nco/uut/out_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/debug_out -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in_r -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in_r -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_ud -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_d -add wave -noupdate -format Literal /tb_nco/uut/wave_i_d -add wave -noupdate -format Literal /tb_nco/uut/wave_q_d -add wave -noupdate -format Literal /tb_nco/uut/wave_i_ud -add wave -noupdate -format Literal /tb_nco/uut/wave_q_ud -add wave -noupdate -format Literal /tb_nco/uut/lfsr -add wave -noupdate -format Literal /tb_nco/uut/lfsr_out -add wave -noupdate -format Logic /tb_nco/uut/lut_addr_valid -add wave -noupdate -format Logic /tb_nco/uut/lfsr_valid -add wave -noupdate -format Logic /tb_nco/uut/wave_d_valid -add wave -noupdate -format Logic /tb_nco/uut/wave_ud_valid -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {249141632 ps} 0} -configure wave -namecolwidth 193 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {249024188 ps} {250051359 ps} diff --git a/lib/radio/nco/sim/tb_nco_results.m b/lib/radio/nco/sim/tb_nco_results.m deleted file mode 100644 index 4147cea..0000000 --- a/lib/radio/nco/sim/tb_nco_results.m +++ /dev/null @@ -1,61 +0,0 @@ -% Read data -function tb_nco_results(nbins) -fa = 100.0; -f = TEXTREAD('freq.txt')*1E-6 - -I_ud = TEXTREAD('q_ud.txt')'; -I_d = TEXTREAD('q_d.txt')'; -LFSR = TEXTREAD('lfsr.txt'); - -N= length(I_ud); -N_fft = min(16384, N); -N_fft2 = N_fft/2; - -fft_y2 = 2/N_fft*abs(fft(I_ud(1:N_fft).*hann(N_fft)')); -fft_y3 = 2/N_fft*abs(fft(I_d(1:N_fft).*hann(N_fft)')); - -[i, v] = get_maxpur(fft_y2, fa, f); -max_spur_freq = (i*fa/N_fft); -max_spur_value = 20*log10(v); - -[i, v] = get_maxpur(fft_y3, fa, f); -max_ditherd_spur_freq = (i*fa/N_fft); -max_ditherd_spur_value = 20*log10(v); - -% Output -close all; - -subplot(2,1,1) -plot(fa/N_fft*(0:N_fft2),20*log10(1E-6+fft_y2(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_spur_value*ones(1,N_fft2+1), 'r-', [max_spur_freq], [max_spur_value], 'ro'); grid; -spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_spur_value, max_spur_freq); -legend('With dithering', spur_legend); -legend('No dithering', spur_legend); -title('Table'); -ylabel('dB'); -xlabel('f/MHz'); -axis([0 fa/2 -120 0]); -subplot(2,1,2) -plot(fa/N_fft*(0:N_fft2),20*log10(1E-6+fft_y3(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_ditherd_spur_value*ones(1,N_fft2+1), 'r-', [max_ditherd_spur_freq], [max_ditherd_spur_value], 'ro'); grid; -spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_ditherd_spur_value, max_ditherd_spur_freq); -legend('With dithering', spur_legend); -title('Table'); -ylabel('dB'); -xlabel('f/MHz'); -axis([0 fa/2 -120 0]); - -figure; -hist(LFSR, nbins) - -function [max_i, max_v] = get_maxpur(spec, fa, f) -max_v = 0; -max_i = 0; -for ii=1:fix(length(spec)/2+1), - fi = ii*fa/length(spec); - dfi = fi - f; - if abs(dfi) > 0.05*f - if spec(ii) > max_v - max_v = spec(ii); - max_i = ii; - end - end; -end; diff --git a/lib/radio/nco/src/nco.vhd b/lib/radio/nco/src/nco.vhd deleted file mode 100644 index 25b7f1d..0000000 --- a/lib/radio/nco/src/nco.vhd +++ /dev/null @@ -1,223 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity nco is -Generic -( - nbits_wave : integer := 18; - nbits_phase : integer := 16; - nbits_lut_depth : integer := 12; - nbits_dither : integer := 4; - nbits_lfsr : integer := 12; - q_phase : phase_relation_t := phase_90deg; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false -); -Port -( - srst : in std_logic; - clk : in std_logic; - pacc_clr : in std_logic; - pacc_inc : in std_logic; - freq_in : in unsigned(nbits_phase-1 downto 0); - freq_load : in std_logic; - phase_in : in unsigned(nbits_phase-1 downto 0); - phase_load : in std_logic; - phase_out : out unsigned(nbits_phase-1 downto 0); - wave_out_i : out sfixed; - wave_out_q : out sfixed; - out_valid : out std_logic -); -end nco; - -architecture Behavioral of nco is - - COMPONENT wavelut - Generic - ( - nbits_wave : integer; - nbits_wave_frac : integer; - nbits_lut_depth : integer; - q_phase : phase_relation_t; - has_out_reg : boolean - ); - Port - ( - clk : in std_logic; - rst : in std_logic; - addr_valid : in std_logic; - addr : in unsigned(nbits_lut_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed; - valid_out : out std_logic - ); - END COMPONENT; - -------------------------------------------------------------------------------- - constant nbits_wave_frac : integer := nbits_wave; - -------------------------------------------------------------------------------- - constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24 - - signal phase : unsigned(nbits_phase-1 downto 0); - signal freq_in_r : unsigned(nbits_phase-1 downto 0); - signal phase_in_r : unsigned(nbits_phase-1 downto 0); - signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0); - signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - - type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0); - signal lfsr : lfsr_t; - signal lfsr_out : unsigned(nbits_dither-1 downto 0); - signal lut_addr_valid, lfsr_valid, wave_d_valid : std_logic; - -------------------------------------------------------------------------------- -begin - - wave_out_i <= wave_i_d; - wave_out_q <= wave_q_d; - out_valid <= wave_d_valid; - ------------------------------------------------------------- - proc_lfsr: process(srst, clk, lfsr, pacc_inc) - variable lo : unsigned(nbits_dither-1 downto 0); - begin - if rising_edge(clk) then - if srst = '1' then - lfsr_valid <= '0'; - lfsr_out <= (others => '0'); - for i in lfsr'range loop - lfsr(i) <= to_unsigned(2**i, nbits_lfsr); - end loop; - else - lfsr_valid <= '0'; - if pacc_inc ='1' then - lfsr_valid <= '1'; - lo := (others => '0'); - for i in lfsr'range loop - if lfsr(i)(lfsr(i)'left) = '1' then - lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly; - else - lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left); - end if; - end loop; - for i in lfsr'range loop - lo := lo + lfsr(i)(nbits_dither-1 downto 0); - end loop; - -- lo := lfsr(0)(nbits_dither downto 0); - lfsr_out <= lo(nbits_dither-1 downto 0); - end if; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_phase_accu: process(clk, phase) - variable phase_accu : unsigned(nbits_phase-1 downto 0); - - begin - if rising_edge(clk) then - if srst = '1' then - phase_accu := (others => '0'); - else - phase <= phase_accu + phase_in_r; - if pacc_clr = '1' then - phase_accu := (others => '0'); - elsif pacc_inc = '1' then - phase_accu := phase_accu + freq_in_r; - end if; - end if; - end if; - phase_out <= phase; - end process; - ------------------------------------------------------------- - freq_in_reg: process(srst, clk, freq_load, freq_in) - begin - if rising_edge(clk) then - if srst = '1' then - freq_in_r <= (others => '0'); - elsif freq_load = '1' then - freq_in_r <= freq_in; - end if; - end if; - end process; - ------------------------------------------------------------- - phase_in_reg: process(srst, clk, phase_load, phase_in) - begin - if rising_edge(clk) then - if srst = '1' then - phase_in_r <= (others => '0'); - elsif phase_load = '1' then - phase_in_r <= phase_in; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(clk) - variable lfsr_sum : unsigned(nbits_phase-1 downto 0); - begin - if rising_edge(clk) then - lut_addr_valid <= '0'; - if srst = '1' then - lfsr_sum := (others => '0'); - elsif lfsr_valid = '1' then - lut_addr_valid <= '1'; - lfsr_sum := lfsr_out + phase; - end if; - end if; - lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth); - end process; - ------------------------------------------------------------- - inst_wavelut_d: wavelut - GENERIC MAP - ( - nbits_wave => nbits_wave, - nbits_wave_frac => nbits_wave_frac, - nbits_lut_depth => nbits_lut_depth, - q_phase => q_phase, - has_out_reg => has_out_reg - ) - PORT MAP - ( - rst => srst, - clk => clk, - addr_valid => lut_addr_valid, - addr => lut_addr_d, - wave_i_out => wave_i_d, - wave_q_out => wave_q_d, - valid_out => wave_d_valid - ); - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/src/nco.vhd.bak b/lib/radio/nco/src/nco.vhd.bak deleted file mode 100644 index 657b97a..0000000 --- a/lib/radio/nco/src/nco.vhd.bak +++ /dev/null @@ -1,240 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity nco is -Generic -( - nbits_wave : integer := 12; - nbits_phase : integer := 16; - nbits_lut_depth : integer := 12; - nbits_dither : integer := 4; - nbits_lfsr : integer := 12; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false -); -Port -( - srst : in std_logic; - clk : in std_logic; - pacc_clr : in std_logic; - pacc_inc : in std_logic; - freq_in : in unsigned(nbits_phase-1 downto 0); - freq_load : in std_logic; - phase_in : in unsigned(nbits_phase-1 downto 0); - phase_load : in std_logic; - phase_out : out unsigned(nbits_phase-1 downto 0); - wave_out_i : out sfixed; - wave_out_q : out sfixed; - out_valid : out std_logic -); -end nco; - -architecture Behavioral of nco is - - COMPONENT wavelut - Generic - ( - nbits_wave : integer; - nbits_wave_frac : integer; - nbits_lut_depth : integer; - has_out_reg : boolean - ); - Port - ( - clk : in std_logic; - addr_valid : in std_logic; - addr : in unsigned(nbits_lut_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed - ); - END COMPONENT; - -------------------------------------------------------------------------------- - constant nbits_wave_frac : integer := nbits_wave; - -------------------------------------------------------------------------------- - constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24 - - signal valid : std_logic_vector(3 downto 0); - signal phase : unsigned(nbits_phase-1 downto 0); - signal freq_in_r : unsigned(nbits_phase-1 downto 0); - signal phase_in_r : unsigned(nbits_phase-1 downto 0); - signal lsfr_sum : unsigned(nbits_phase-1 downto 0); - signal lut_addr : unsigned(nbits_lut_depth-1 downto 0); - signal wave_i, wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0); - signal lfsr : lfsr_t; - signal lfsr_out : unsigned(nbits_dither-1 downto 0); - signal lut_addr_valid _ std_logic; - -------------------------------------------------------------------------------- -begin - - wave_out_i <= wave_i; - wave_out_q <= wave_q; - ------------------------------------------------------------- - proc_ctrl: process(srst, clk, pacc_inc, pacc_clr) - begin - if rising_edge(clk) then - if srst = '1' then - valid <= (others => '0'); - else - valid <= valid(valid'left-1 downto valid'right) & (pacc_inc or pacc_clr); - end if; - end if; - end process; - ------------------------------------------------------------- - proc_lfsr: process(srst, clk, lfsr, pacc_inc) - variable lo : unsigned(nbits_dither downto 0); - begin - if rising_edge(clk) then - if srst = '1' then - for i in lfsr'range loop - lfsr(i) <= to_unsigned(1234+2**i, nbits_lfsr); - end loop; - elsif pacc_inc ='1' then - lo := (others => '0'); - for i in lfsr'range loop - if lfsr(i)(lfsr(i)'left) = '1' then - lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly; - else - lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left); - end if; - end loop; - for i in lfsr'range loop - lo := lo + lfsr(i)(nbits_dither-1 downto 0); - end loop; --- lo := lfsr(0)(nbits_dither downto 0); - lfsr_out <= lo(nbits_dither-1 downto 0); - end if; - end if; - end process; - ------------------------------------------------------------- - proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r) - variable phase_accu : unsigned(nbits_phase-1 downto 0); - - begin - if rising_edge(clk) then - if srst = '1' then - phase_accu := (others => '0'); - else - phase <= phase_accu + phase_in_r; - if pacc_clr = '1' then - phase_accu := (others => '0'); - elsif pacc_inc = '1' then - phase_accu := phase_accu + freq_in_r; - end if; - end if; - end if; - end process; - ------------------------------------------------------------- - freq_in_reg: process(srst, clk, freq_load, freq_in) - begin - if rising_edge(clk) then - if srst = '1' then - freq_in_r <= (others => '0'); - elsif freq_load = '1' then - freq_in_r <= freq_in; - end if; - end if; - end process; - ------------------------------------------------------------- - phase_in_reg: process(srst, clk, phase_load, phase_in) - begin - if rising_edge(clk) then - if srst = '1' then - phase_in_r <= (others => '0'); - elsif phase_load = '1' then - phase_in_r <= phase_in; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(clk) - begin - if rising_edge(clk) then - lsfr_sum <= lfsr_out + phase; - lut_addr <= lsfr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth); - end if; - end process; - ------------------------------------------------------------- - proc_out_reg: process(clk, phase) - begin - if has_out_reg = true then - if rising_edge(clk) then - phase_out <= phase; - end if; - else - phase_out <= phase; - end if; - end process; - ------------------------------------------------------------- - proc_valid_reg: process(clk, valid) - begin - out_valid <= valid(valid'right+1); - if has_out_reg = true then - out_valid <= valid(valid'right+2); - if has_pipe_reg = true then - out_valid <= valid(valid'right+3); - end if; - elsif has_pipe_reg = true then - out_valid <= valid(valid'right+2); - end if; - end process; - ------------------------------------------------------------- - inst_wavelut_d: wavelut - GENERIC MAP - ( - nbits_wave => nbits_wave, - nbits_wave_frac => nbits_wave_frac, - nbits_lut_depth => nbits_lut_depth, - has_out_reg => has_out_reg - ) - PORT MAP - ( - clk => clk, - addr => lut_addr, - addr_valid => lut_addr_valid, - wave_i_out => wave_i, - wave_q_out => wave_q - ); - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/src/nco_dbg.vhd b/lib/radio/nco/src/nco_dbg.vhd deleted file mode 100644 index c0038a9..0000000 --- a/lib/radio/nco/src/nco_dbg.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity nco is -Generic -( - nbits_wave : integer := 18; - nbits_phase : integer := 16; - nbits_lut_depth : integer := 12; - nbits_dither : integer := 4; - nbits_lfsr : integer := 12; - q_phase : phase_relation_t := phase_90deg; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false -); -Port -( - srst : in std_logic; - clk : in std_logic; - pacc_clr : in std_logic; - pacc_inc : in std_logic; - freq_in : in unsigned(nbits_phase-1 downto 0); - freq_load : in std_logic; - phase_in : in unsigned(nbits_phase-1 downto 0); - phase_load : in std_logic; - phase_out : out unsigned(nbits_phase-1 downto 0); - wave_out_i : out sfixed; - wave_out_q : out sfixed; - out_valid : out std_logic; - debug_out : out debug_out_t -); -end nco; - -architecture Behavioral of nco is - - COMPONENT wavelut - Generic - ( - nbits_wave : integer; - nbits_wave_frac : integer; - nbits_lut_depth : integer; - q_phase : phase_relation_t; - has_out_reg : boolean - ); - Port - ( - clk : in std_logic; - rst : in std_logic; - addr_valid : in std_logic; - addr : in unsigned(nbits_lut_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed; - valid_out : out std_logic - ); - END COMPONENT; - -------------------------------------------------------------------------------- - constant nbits_wave_frac : integer := nbits_wave; - -------------------------------------------------------------------------------- - constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24 - - signal phase : unsigned(nbits_phase-1 downto 0); - signal freq_in_r : unsigned(nbits_phase-1 downto 0); - signal phase_in_r : unsigned(nbits_phase-1 downto 0); - signal lut_addr_ud : unsigned(nbits_lut_depth-1 downto 0); - signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0); - signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - signal wave_i_ud, wave_q_ud : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - - type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0); - signal lfsr : lfsr_t; - signal lfsr_out : unsigned(nbits_dither-1 downto 0); - signal lut_addr_valid, lfsr_valid, wave_d_valid, wave_ud_valid : std_logic; - -------------------------------------------------------------------------------- -begin - - wave_out_i <= wave_i_d; - wave_out_q <= wave_q_d; - out_valid <= wave_d_valid; - - debug_out.lfsr <= (debug_out.lfsr'left downto (debug_out.lfsr'right+lfsr_out'left+1) => '0') & lfsr_out; - debug_out.i_d <= to_real(wave_i_d); - debug_out.q_d <= to_real(wave_q_d); - debug_out.i_ud <= to_real(wave_i_ud); - debug_out.q_ud <= to_real(wave_q_ud); - ------------------------------------------------------------- - proc_lfsr: process(srst, clk, lfsr, pacc_inc) - variable lo : unsigned(nbits_dither-1 downto 0); - begin - if rising_edge(clk) then - if srst = '1' then - lfsr_valid <= '0'; - lfsr_out <= (others => '0'); - for i in lfsr'range loop - lfsr(i) <= to_unsigned(2**i, nbits_lfsr); - end loop; - else - lfsr_valid <= '0'; - if pacc_inc ='1' then - lfsr_valid <= '1'; - lo := (others => '0'); - for i in lfsr'range loop - if lfsr(i)(lfsr(i)'left) = '1' then - lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly; - else - lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left); - end if; - end loop; - for i in lfsr'range loop - lo := lo + lfsr(i)(nbits_dither-1 downto 0); - end loop; - -- lo := lfsr(0)(nbits_dither downto 0); - lfsr_out <= lo(nbits_dither-1 downto 0); - end if; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r) - variable phase_accu : unsigned(nbits_phase-1 downto 0); - - begin - if rising_edge(clk) then - if srst = '1' then - phase_accu := (others => '0'); - else - phase <= phase_accu + phase_in_r; - if pacc_clr = '1' then - phase_accu := (others => '0'); - elsif pacc_inc = '1' then - phase_accu := phase_accu + freq_in_r; - end if; - end if; - end if; - phase_out <= phase; - end process; - ------------------------------------------------------------- - freq_in_reg: process(srst, clk, freq_load, freq_in) - begin - if rising_edge(clk) then - if srst = '1' then - freq_in_r <= (others => '0'); - elsif freq_load = '1' then - freq_in_r <= freq_in; - end if; - end if; - end process; - ------------------------------------------------------------- - phase_in_reg: process(srst, clk, phase_load, phase_in) - begin - if rising_edge(clk) then - if srst = '1' then - phase_in_r <= (others => '0'); - elsif phase_load = '1' then - phase_in_r <= phase_in; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(clk) - variable lfsr_sum : unsigned(nbits_phase-1 downto 0); - begin - if rising_edge(clk) then - lut_addr_valid <= '0'; - if srst = '1' then - lfsr_sum := (others => '0'); - elsif lfsr_valid = '1' then - lut_addr_valid <= '1'; - lfsr_sum := lfsr_out + phase; - end if; - end if; - lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth); - lut_addr_ud <= phase(nbits_phase-1 downto nbits_phase-nbits_lut_depth); - end process; - ------------------------------------------------------------- - inst_wavelut_ud: wavelut - GENERIC MAP - ( - nbits_wave => nbits_wave, - nbits_wave_frac => nbits_wave_frac, - nbits_lut_depth => nbits_lut_depth, - q_phase => q_phase, - has_out_reg => has_out_reg - ) - PORT MAP - ( - rst => srst, - clk => clk, - addr_valid => lut_addr_valid, - addr => lut_addr_ud, - wave_i_out => wave_i_ud, - wave_q_out => wave_q_ud, - valid_out => wave_ud_valid - ); - - inst_wavelut_d: wavelut - GENERIC MAP - ( - nbits_wave => nbits_wave, - nbits_wave_frac => nbits_wave_frac, - nbits_lut_depth => nbits_lut_depth, - q_phase => q_phase, - has_out_reg => has_out_reg - ) - PORT MAP - ( - rst => srst, - clk => clk, - addr_valid => lut_addr_valid, - addr => lut_addr_d, - wave_i_out => wave_i_d, - wave_q_out => wave_q_d, - valid_out => wave_d_valid - ); - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/src/nco_pkg.vhd b/lib/radio/nco/src/nco_pkg.vhd deleted file mode 100644 index 0bb9cef..0000000 --- a/lib/radio/nco/src/nco_pkg.vhd +++ /dev/null @@ -1,117 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use IEEE.MATH_REAL.ALL; -use work.fixed_pkg.all; - -------------------------------------------------------------------------------- -package nco_pkg is - - constant tpd : time := 0 ns; - - -- Global set arithmetic rounding mode - constant pi : real := 3.141592653589793e+000; - constant sqrt2 : real := 1.414213562373095e+000; - constant sqrt2_inv : real := 7.071067811865475e-001; - - type real_array_t is array (natural range <>) of real; - type natural_array_t is array (natural range <>) of natural; - type phase_relation_t is (phase_90deg, phase_270deg); - - type debug_out_t is record - lfsr : unsigned(31 downto 0); - i_ud : real; - q_ud : real; - i_d : real; - q_d : real; - end record; - - constant lfsr_poly : natural_array_t(3 to 24) := - ( - 12, -- 3 - 24, -- 4 - 58, -- 5 - 114, -- 6 - 210, -- 7 - 500, -- 8 - 1000, -- 9 - 1824, -- 10 - 3712, -- 11 - 7184, -- 12 - 14592, -- 13 - 28674, -- 14 - 59392, -- 15 - 106512, -- 16 - 245760, -- 17 - 466944, -- 18 - 933888, -- 19 - 1654784, -- 20 - 3735552, -- 21 - 7342080, -- 22 - 14745600, -- 23 - 14811138 -- 24 - ); - - function sin_tbl(nsamples : integer; omega, phi_in : real) return real_array_t; - function cos_tbl(nsamples : integer; omega, phi_in : real) return real_array_t; - - ------------------------------------------------------------- - -- Constructor helpers - -- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range); - function uproto (nbits : integer; nbits_frac : integer) return ufixed; - - -- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range); - function sproto (nbits : integer; nbits_frac : integer) return sfixed; - -end; -- package nco_pkg; - -------------------------------------------------------------------------------- -package body nco_pkg is - - function sin_tbl(nsamples : integer; omega, phi_in : real) return real_array_t is - variable tbl : real_array_t (0 to nsamples-1); - variable phi : real := phi_in; - variable dphi : real := 2.0*pi*omega; - - begin - for i in 0 to nsamples-1 loop - tbl(i) := sin(phi); - phi := phi + dphi; - end loop; - - return tbl; - end sin_tbl; - - ------------------------------------------------------------- - function cos_tbl(nsamples : integer; omega, phi_in : real) return real_array_t is - variable tbl : real_array_t (0 to nsamples-1); - variable phi : real := phi_in; - variable dphi : real := 2.0*pi*omega; - - begin - for i in 0 to nsamples-1 loop - tbl(i) := cos(phi); - phi := phi + dphi; - end loop; - - return tbl; - end cos_tbl; - - ------------------------------------------------------------- - -- Constuctor helpers - function uproto (nbits : integer; nbits_frac : integer) return ufixed is - constant result : ufixed (nbits-nbits_frac-1 downto -nbits_frac) := (others => '0'); - begin - return result(nbits-nbits_frac-1 downto -nbits_frac); - end uproto; - - ------------------------------------------------------------- - function sproto (nbits : integer; nbits_frac : integer) return sfixed is - constant result : sfixed (nbits-nbits_frac downto -nbits_frac+1) := (others => '0'); - begin - return result(nbits-nbits_frac downto -nbits_frac+1); - end sproto; - -------------------------------------------------------------------------------- -end; -- package nco_pkg; diff --git a/lib/radio/nco/src/tb_nco.vhd b/lib/radio/nco/src/tb_nco.vhd deleted file mode 100644 index f2d930a..0000000 --- a/lib/radio/nco/src/tb_nco.vhd +++ /dev/null @@ -1,299 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_nco --- Module Name: tb_nco.vhd --- Project Name: nco --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.fixed_pkg.all; -use work.nco_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_nco IS - Generic ( - nbits_wave : integer := 18; - nbits_phase : integer := 16; - nbits_lut_depth : integer := 12; - nbits_dither : integer := 4; - nbits_lfsr : integer := 12; - q_phase : phase_relation_t := phase_270deg; - has_pipe_reg : boolean := true; - has_out_reg : boolean := true - ); -END tb_nco; - -ARCHITECTURE behavior OF tb_nco IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT nco - GENERIC ( - nbits_wave : integer; - nbits_phase : integer; - nbits_lut_depth : integer; - nbits_dither : integer; - nbits_lfsr : integer; - q_phase : phase_relation_t; - has_pipe_reg : boolean; - has_out_reg : boolean - ); - PORT( - srst : in std_logic; - clk : in std_logic; --- ce : in std_logic; - pacc_clr : in std_logic; - pacc_inc : in std_logic; - freq_in : in unsigned(nbits_phase-1 downto 0); - freq_load : in std_logic; - phase_in : in unsigned(nbits_phase-1 downto 0); - phase_load : in std_logic; - phase_out : out unsigned(nbits_phase-1 downto 0); - wave_out_i : out sfixed; - wave_out_q : out sfixed; - out_valid : out std_logic; - debug_out : out debug_out_t - ); - END COMPONENT; - - --Constants - constant f : REAL := 4.1667E6; - constant df : REAL := 10.0E3; - constant fa : REAL := 100.0E6; - constant PERIOD : time := 10 ns; - constant nbits_wave_frac : integer := nbits_wave; - - SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase); - SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase); - - --Inputs - SIGNAL clk : std_logic := '0'; --- SIGNAL ce : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL pacc_clr : std_logic := '0'; - SIGNAL pacc_inc : std_logic := '0'; - SIGNAL phase_load : std_logic := '0'; - SIGNAL freq_load : std_logic := '0'; - SIGNAL freq_in : unsigned(nbits_phase-1 downto 0); - SIGNAL phase_in : unsigned(nbits_phase-1 downto 0); - - --Outputs - SIGNAL wave_out_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - SIGNAL wave_out_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - SIGNAL out_valid : std_logic; - SIGNAL phase_out : unsigned(nbits_phase-1 downto 0); - SIGNAL debug_out : debug_out_t; - - SIGNAL fileout_enable : std_logic := '0'; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: nco - GENERIC MAP ( - nbits_wave => nbits_wave, - nbits_phase => nbits_phase, - nbits_lut_depth => nbits_lut_depth, - nbits_dither => nbits_dither, - nbits_lfsr => nbits_lfsr, - q_phase => q_phase, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg - ) - PORT MAP( - srst => srst, - clk => clk, --- ce => ce, - pacc_clr => pacc_clr, - pacc_inc => pacc_inc, - freq_in => freq_in, - freq_load => freq_load, - phase_in => phase_in, - phase_load => phase_load, - phase_out => phase_out, - wave_out_i => wave_out_i, - wave_out_q => wave_out_q, - out_valid => out_valid, - debug_out => debug_out - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - file RESULT_FREQ: text open write_mode is "freq.txt"; - variable L: line; - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - - fprint(RESULT_FREQ, L,"%s\n", REAL'image(f)); - - wait for 2*PERIOD; --- ce <= '1'; - ------------------------------------------- - -- 1 - phase_in <= to_unsigned(0,nbits_phase); - wait until rising_edge(clk); - phase_load <= '1'; - wait until rising_edge(clk); - phase_load <= '0'; - - freq_in <= to_unsigned(1411,nbits_phase); - wait until rising_edge(clk); - freq_load <= '1'; - wait until rising_edge(clk); - freq_load <= '0'; - - wait for 2*PERIOD; - pacc_inc <= '1'; - - wait for 2*PERIOD; - wait until rising_edge(clk); - - wait for 40*PERIOD; - ------------------------------------------- - freq_in <= to_unsigned(643,nbits_phase); - wait until rising_edge(clk); - freq_load <= '1'; - wait until rising_edge(clk); - freq_load <= '0'; - - wait for 40*PERIOD; - ------------------------------------------- - phase_in <= to_unsigned(800,nbits_phase); - wait until rising_edge(clk); - phase_load <= '1'; - wait until rising_edge(clk); - phase_load <= '0'; - - wait for 20*PERIOD; - ------------------------------------------- - phase_in <= to_unsigned(45072,nbits_phase); - wait until rising_edge(clk); - phase_load <= '1'; - wait until rising_edge(clk); - phase_load <= '0'; - - wait for 20*PERIOD; - ------------------------------------------- - phase_in <= to_unsigned(20593,nbits_phase); - wait until rising_edge(clk); - phase_load <= '1'; - wait until rising_edge(clk); - phase_load <= '0'; - - ------------------------------------------- - freq_in <= to_unsigned(freq_word,nbits_phase); - wait until rising_edge(clk); - freq_load <= '1'; - wait until rising_edge(clk); - freq_load <= '0'; - - wait for 20*PERIOD; - fileout_enable <= '1'; - - wait for 20000*PERIOD; - fileout_enable <= '0'; - - ------------------------------------------- - -- Sweep - freq_word <= 100; - for i in 1 to 200 loop - wait for 20*PERIOD; - freq_word <= freq_word + dfreq_word; - - freq_in <= to_unsigned(freq_word,nbits_phase); - wait until rising_edge(clk); - freq_load <= '1'; - wait until rising_edge(clk); - freq_load <= '0'; - - end loop; - - pacc_inc <= '0'; - wait for 20*PERIOD; - fileout_enable <= '0'; - wait until rising_edge(clk); - pacc_clr <= '1'; - wait until rising_edge(clk); - pacc_clr <= '0'; - wait for 20*PERIOD; - pacc_inc <= '1'; - wait for 20*PERIOD; - wait until rising_edge(clk); - pacc_clr <= '1'; - wait until rising_edge(clk); - pacc_clr <= '0'; - wait for 20*PERIOD; - pacc_inc <= '0'; - wait for 20*PERIOD; - wait until rising_edge(clk); - pacc_inc <= '1'; - wait until rising_edge(clk); - pacc_inc <= '0'; - wait for 20*PERIOD; - wait until rising_edge(clk); - srst <= '1'; - wait until rising_edge(clk); - srst <= '0'; - freq_in <= to_unsigned(freq_word,nbits_phase); - wait until rising_edge(clk); - freq_load <= '1'; - wait until rising_edge(clk); - freq_load <= '0'; - - wait for 20*PERIOD; - pacc_inc <= '1'; - wait for 20*PERIOD; - wait until rising_edge(clk); - srst <= '1'; - wait until rising_edge(clk); - srst <= '0'; - wait for 20*PERIOD; - pacc_inc <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - tb_fo : PROCESS(clk, fileout_enable, out_valid) - file RESULT_I: text open write_mode is "i_ud.txt"; - file RESULT_Q: text open write_mode is "q_ud.txt"; - file RESULT_ID: text open write_mode is "i_d.txt"; - file RESULT_QD: text open write_mode is "q_d.txt"; - file RESULT_LFSR: text open write_mode is "lfsr.txt"; - variable L: line; - - BEGIN - if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then - fprint(RESULT_I, L,"%s\n", REAL'image(debug_out.i_ud)); - fprint(RESULT_Q, L,"%s\n", REAL'image(debug_out.q_ud)); - fprint(RESULT_ID, L,"%s\n", REAL'image(debug_out.i_d)); - fprint(RESULT_QD, L,"%s\n", REAL'image(debug_out.q_d)); - fprint(RESULT_LFSR, L,"%s\n", INTEGER'image(to_integer(debug_out.lfsr))); - end if; - - END PROCESS; - - -END; diff --git a/lib/radio/nco/src/wavelut.vhd b/lib/radio/nco/src/wavelut.vhd deleted file mode 100644 index 4b0f02e..0000000 --- a/lib/radio/nco/src/wavelut.vhd +++ /dev/null @@ -1,239 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity wavelut is -Generic -( - nbits_wave : integer := 12; - nbits_wave_frac : integer := 12; - nbits_lut_depth : integer := 12; - q_phase : phase_relation_t := phase_90deg; - has_out_reg : boolean := false -); -Port -( - rst : in std_logic; - clk : in std_logic; - addr_valid : in std_logic; - addr : in unsigned(nbits_lut_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed; - valid_out : out std_logic -); -end wavelut; - -architecture Behavioral of wavelut is - - COMPONENT waverom_dual - Generic - ( - nbits_wave : integer; - nbits_wave_frac : integer; - nbits_rom_depth : integer - ); - Port - ( - clk : in std_logic; - addr_i : in unsigned(nbits_rom_depth-1 downto 0); - addr_q : in unsigned(nbits_rom_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed - ); - END COMPONENT; - -------------------------------------------------------------------------------- -constant nbits_rom_depth : integer := nbits_lut_depth-2; - -------------------------------------------------------------------------------- -signal wave_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); -signal wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); -signal inv_i : std_logic; -signal inv_q : std_logic; -signal addr_i : unsigned(nbits_rom_depth-1 downto 0); -signal addr_q : unsigned(nbits_rom_depth-1 downto 0); -signal zero_i : std_logic; -signal zero_q : std_logic; - -------------------------------------------------------------------------------- -begin - - inst_waverom_dual: waverom_dual - GENERIC MAP - ( - nbits_wave => nbits_wave, - nbits_wave_frac => nbits_wave_frac, - nbits_rom_depth => nbits_rom_depth - ) - PORT MAP - ( - clk => clk, - addr_i => addr_i, - addr_q => addr_q, - wave_i_out => wave_i, - wave_q_out => wave_q - ); - ------------------------------------------------------------- -proc_valid: process(clk) - variable v : unsigned(0 to 1); - begin - if rising_edge(clk) then - if rst = '1' then - v := (others => '0'); - valid_out <= '0'; - else - valid_out <= v(1); - v(1) := v(0); - v(0) := addr_valid; - end if; - end if; - end process; - ------------------------------------------------------------- -proc_tbl_addr_i: process(clk, addr) - variable index : unsigned(addr'left downto addr'right); - variable n2 : integer; - constant N_2 : integer := 2**(nbits_lut_depth-1); - constant N_4 : integer := 2**(nbits_lut_depth-2); - begin - n2 := to_integer(addr(addr'left-1 downto addr'right)); - if n2 > N_4 then - index := to_unsigned(N_2 - n2, index'length); - else - index := to_unsigned(n2, index'length); - end if; - - if rising_edge(clk) then - if rst = '1' then - addr_i <= (others => '0'); - zero_i <= '0'; - inv_i <= '0'; - elsif addr_valid = '1' then - addr_i <= index(addr'left-2 downto addr'right); - zero_i <= index(addr'left-1); - inv_i <= addr(addr'left) xor addr(addr'left-1); - end if; - end if; - - end process; - -------------------------------------------------------------------------------- -proc_tbl_addr_q: process(clk, addr) - variable index : unsigned(addr'left downto addr'right); - variable n2 : integer; - constant N_4 : integer := 2**(nbits_lut_depth-2); - - begin - n2 := to_integer(addr(addr'left-1 downto addr'right)); - if n2 > N_4 then - index := to_unsigned(n2 - N_4, index'length); - else - index := to_unsigned(N_4 - n2, index'length); - end if; - - if rising_edge(clk) then - if rst = '1' then - addr_q <= (others => '0'); - zero_q <= '0'; - inv_q <= '0'; - elsif addr_valid = '1' then - addr_q <= index(addr'left-2 downto addr'right); - zero_q <= index(addr'left-1); - if q_phase = phase_90deg then - inv_q <= addr(addr'left); - elsif q_phase = phase_270deg then - inv_q <= not addr(addr'left); - end if; - end if; - end if; - - end process; - ------------------------------------------------------------- -proc_out_i: process(clk, wave_i, inv_i, zero_i) - variable w : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - variable z, inv : std_logic; - begin - - w := to_sfixed(0.0, w); - if z = '0' then - w := wave_i; - if inv = '1' then - w := resize(-wave_i, w, fixed_truncate, fixed_wrap); - end if; - end if; - - if has_out_reg = true then - if rising_edge(clk) then - wave_i_out <= w; - end if; - else - wave_i_out <= w; - end if; - - if rising_edge(clk) then - z := zero_i; - inv := inv_i; - end if; - - end process; - ------------------------------------------------------------- -proc_out_q: process(clk, wave_q, inv_q, zero_q) - variable w : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - variable z, inv : std_logic; - begin - - w := to_sfixed(0.0, w); - if z = '0' then - w := wave_q; - if inv = '1' then - w := resize(-wave_q, w, fixed_truncate, fixed_wrap); - end if; - end if; - - if has_out_reg = true then - if rising_edge(clk) then - wave_q_out <= w; - end if; - else - wave_q_out <= w; - end if; - - if rising_edge(clk) then - z := zero_q; - inv := inv_q; - end if; - - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/src/waverom_dual.vhd b/lib/radio/nco/src/waverom_dual.vhd deleted file mode 100644 index 4824eb0..0000000 --- a/lib/radio/nco/src/waverom_dual.vhd +++ /dev/null @@ -1,86 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity waverom_dual is -Generic -( - nbits_wave : integer := 12; - nbits_wave_frac : integer := 12; - nbits_rom_depth : integer := 12 -); -Port -( - clk : in std_logic; - addr_i : in unsigned(nbits_rom_depth-1 downto 0); - addr_q : in unsigned(nbits_rom_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed -); -end waverom_dual; - -architecture Behavioral of waverom_dual is - -------------------------------------------------------------------------------- -constant rom_depth : integer := 2**nbits_rom_depth; -type wave_mem_t is array (0 to rom_depth-1) of sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - -constant sfixed_proto : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low) := (others => '0'); - -------------------------------------------------------------------------------- -function to_wave_mem(wave_real : real_array_t; len : integer; proto : sfixed) return wave_mem_t is -variable res : wave_mem_t; -begin - for i in 0 to len-1 loop - res(i) := to_sfixed(wave_real(i), proto, fixed_round, fixed_saturate); - end loop; - - return res; -end to_wave_mem; - -------------------------------------------------------------------------------- --- Create ROM -constant real_wave_tbl : real_array_t(0 to rom_depth-1) := cos_tbl(rom_depth, 0.25/real(rom_depth), 0.0); -constant wave_tbl : wave_mem_t := to_wave_mem(real_wave_tbl, rom_depth, sfixed_proto); - -------------------------------------------------------------------------------- -begin - -------------------------------------------------------------------------------- -proc_wave: process(clk) - begin - if rising_edge(clk) then - wave_i_out <= wave_tbl(to_integer(addr_i)); - wave_q_out <= wave_tbl(to_integer(addr_q)); - end if; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/uart/bbfifo_16x8.vhd b/lib/uart/bbfifo_16x8.vhd deleted file mode 100644 index d6604a6..0000000 --- a/lib/uart/bbfifo_16x8.vhd +++ /dev/null @@ -1,281 +0,0 @@ --- 'Bucket Brigade' FIFO --- 16 deep --- 8-bit data --- --- Version : 1.10 --- Version Date : 3rd December 2003 --- Reason : '--translate' directives changed to '--synthesis translate' directives --- --- Version : 1.00 --- Version Date : 14th October 2002 --- --- Start of design entry : 14th October 2002 --- --- Ken Chapman --- Xilinx Ltd --- Benchmark House --- 203 Brooklands Road --- Weybridge --- Surrey KT13 ORH --- United Kingdom --- --- chapman@xilinx.com --- ------------------------------------------------------------------------------------- --- --- NOTICE: --- --- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other --- third parties. By providing this core as one possible implementation of a standard, --- Xilinx is making no representation that the provided implementation of this standard --- is free from any claims of infringement by any third party. Xilinx expressly --- disclaims any warranty with respect to the adequacy of the implementation, including --- but not limited to any warranty or representation that the implementation is free --- from claims of any third party. Futhermore, Xilinx is providing this core as a --- courtesy to you and suggests that you contact all third parties to obtain the --- necessary rights to use this implementation. --- ------------------------------------------------------------------------------------- --- --- Library declarations --- --- The Unisim Library is used to define Xilinx primitives. It is also used during --- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use unisim.vcomponents.all; --- ------------------------------------------------------------------------------------- --- --- Main Entity for BBFIFO_16x8 --- -entity bbfifo_16x8 is - Port ( data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - reset : in std_logic; - write : in std_logic; - read : in std_logic; - full : out std_logic; - half_full : out std_logic; - data_present : out std_logic; - clk : in std_logic); - end bbfifo_16x8; --- ------------------------------------------------------------------------------------- --- --- Start of Main Architecture for BBFIFO_16x8 --- -architecture low_level_definition of bbfifo_16x8 is --- ------------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------------- --- --- Signals used in BBFIFO_16x8 --- ------------------------------------------------------------------------------------- --- -signal pointer : std_logic_vector(3 downto 0); -signal next_count : std_logic_vector(3 downto 0); -signal half_count : std_logic_vector(3 downto 0); -signal count_carry : std_logic_vector(2 downto 0); - -signal pointer_zero : std_logic; -signal pointer_full : std_logic; -signal decode_data_present : std_logic; -signal data_present_int : std_logic; -signal valid_write : std_logic; --- --- ------------------------------------------------------------------------------------- --- --- Attributes to define LUT contents during implementation --- The information is repeated in the generic map for functional simulation-- --- ------------------------------------------------------------------------------------- --- -attribute INIT : string; -attribute INIT of zero_lut : label is "0001"; -attribute INIT of full_lut : label is "8000"; -attribute INIT of dp_lut : label is "BFA0"; -attribute INIT of valid_lut : label is "C4"; --- ------------------------------------------------------------------------------------- --- --- Start of BBFIFO_16x8 circuit description --- ------------------------------------------------------------------------------------- --- -begin - - -- SRL16E data storage - - data_width_loop: for i in 0 to 7 generate - -- - attribute INIT : string; - attribute INIT of data_srl : label is "0000"; - -- - begin - - data_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => data_in(i), - CE => valid_write, - CLK => clk, - A0 => pointer(0), - A1 => pointer(1), - A2 => pointer(2), - A3 => pointer(3), - Q => data_out(i) ); - - end generate data_width_loop; - - -- 4-bit counter to act as data pointer - -- Counter is clock enabled by 'data_present' - -- Counter will be reset when 'reset' is active - -- Counter will increment when 'valid_write' is active - - count_width_loop: for i in 0 to 3 generate - -- - attribute INIT : string; - attribute INIT of count_lut : label is "6606"; - -- - begin - - register_bit: FDRE - port map ( D => next_count(i), - Q => pointer(i), - CE => data_present_int, - R => reset, - C => clk); - - count_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"6606") - --synthesis translate_on - port map( I0 => pointer(i), - I1 => read, - I2 => pointer_zero, - I3 => write, - O => half_count(i)); - - lsb_count: if i=0 generate - begin - - count_muxcy: MUXCY - port map( DI => pointer(i), - CI => valid_write, - S => half_count(i), - O => count_carry(i)); - - count_xor: XORCY - port map( LI => half_count(i), - CI => valid_write, - O => next_count(i)); - - end generate lsb_count; - - mid_count: if i>0 and i<3 generate - begin - - count_muxcy: MUXCY - port map( DI => pointer(i), - CI => count_carry(i-1), - S => half_count(i), - O => count_carry(i)); - - count_xor: XORCY - port map( LI => half_count(i), - CI => count_carry(i-1), - O => next_count(i)); - - end generate mid_count; - - upper_count: if i=3 generate - begin - - count_xor: XORCY - port map( LI => half_count(i), - CI => count_carry(i-1), - O => next_count(i)); - - end generate upper_count; - - end generate count_width_loop; - - - -- Detect when pointer is zero and maximum - - zero_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"0001") - --synthesis translate_on - port map( I0 => pointer(0), - I1 => pointer(1), - I2 => pointer(2), - I3 => pointer(3), - O => pointer_zero ); - - - full_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"8000") - --synthesis translate_on - port map( I0 => pointer(0), - I1 => pointer(1), - I2 => pointer(2), - I3 => pointer(3), - O => pointer_full ); - - - -- Data Present status - - dp_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"BFA0") - --synthesis translate_on - port map( I0 => write, - I1 => read, - I2 => pointer_zero, - I3 => data_present_int, - O => decode_data_present ); - - dp_flop: FDR - port map ( D => decode_data_present, - Q => data_present_int, - R => reset, - C => clk); - - -- Valid write signal - - valid_lut: LUT3 - --synthesis translate_off - generic map (INIT => X"C4") - --synthesis translate_on - port map( I0 => pointer_full, - I1 => write, - I2 => read, - O => valid_write ); - - - -- assign internal signals to outputs - - full <= pointer_full; - half_full <= pointer(3); - data_present <= data_present_int; - -end low_level_definition; - ------------------------------------------------------------------------------------- --- --- END OF FILE BBFIFO_16x8.VHD --- ------------------------------------------------------------------------------------- - - diff --git a/lib/uart/kcuart_rx.vhd b/lib/uart/kcuart_rx.vhd deleted file mode 100644 index a7ac1a2..0000000 --- a/lib/uart/kcuart_rx.vhd +++ /dev/null @@ -1,352 +0,0 @@ --- Constant (K) Compact UART Receiver --- --- Version : 1.10 --- Version Date : 3rd December 2003 --- Reason : '--translate' directives changed to '--synthesis translate' directives --- --- Version : 1.00 --- Version Date : 16th October 2002 --- --- Start of design entry : 16th October 2002 --- --- Ken Chapman --- Xilinx Ltd --- Benchmark House --- 203 Brooklands Road --- Weybridge --- Surrey KT13 ORH --- United Kingdom --- --- chapman@xilinx.com --- ------------------------------------------------------------------------------------- --- --- NOTICE: --- --- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other --- third parties. By providing this core as one possible implementation of a standard, --- Xilinx is making no representation that the provided implementation of this standard --- is free from any claims of infringement by any third party. Xilinx expressly --- disclaims any warranty with respect to the adequacy of the implementation, including --- but not limited to any warranty or representation that the implementation is free --- from claims of any third party. Futhermore, Xilinx is providing this core as a --- courtesy to you and suggests that you contact all third parties to obtain the --- necessary rights to use this implementation. --- ------------------------------------------------------------------------------------- --- --- Library declarations --- --- The Unisim Library is used to define Xilinx primitives. It is also used during --- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use unisim.vcomponents.all; --- ------------------------------------------------------------------------------------- --- --- Main Entity for KCUART_RX --- -entity kcuart_rx is - Port ( serial_in : in std_logic; - data_out : out std_logic_vector(7 downto 0); - data_strobe : out std_logic; - en_16_x_baud : in std_logic; - clk : in std_logic); - end kcuart_rx; --- ------------------------------------------------------------------------------------- --- --- Start of Main Architecture for KCUART_RX --- -architecture low_level_definition of kcuart_rx is --- ------------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------------- --- --- Signals used in KCUART_RX --- ------------------------------------------------------------------------------------- --- -signal sync_serial : std_logic; -signal stop_bit : std_logic; -signal data_int : std_logic_vector(7 downto 0); -signal data_delay : std_logic_vector(7 downto 0); -signal start_delay : std_logic; -signal start_bit : std_logic; -signal edge_delay : std_logic; -signal start_edge : std_logic; -signal decode_valid_char : std_logic; -signal valid_char : std_logic; -signal decode_purge : std_logic; -signal purge : std_logic; -signal valid_srl_delay : std_logic_vector(8 downto 0); -signal valid_reg_delay : std_logic_vector(8 downto 0); -signal decode_data_strobe : std_logic; --- --- ------------------------------------------------------------------------------------- --- --- Attributes to define LUT contents during implementation --- The information is repeated in the generic map for functional simulation-- --- ------------------------------------------------------------------------------------- --- -attribute INIT : string; -attribute INIT of start_srl : label is "0000"; -attribute INIT of edge_srl : label is "0000"; -attribute INIT of valid_lut : label is "0040"; -attribute INIT of purge_lut : label is "54"; -attribute INIT of strobe_lut : label is "8"; --- ------------------------------------------------------------------------------------- --- --- Start of KCUART_RX circuit description --- ------------------------------------------------------------------------------------- --- -begin - - -- Synchronise input serial data to system clock - - sync_reg: FD - port map ( D => serial_in, - Q => sync_serial, - C => clk); - - stop_reg: FD - port map ( D => sync_serial, - Q => stop_bit, - C => clk); - - - -- Data delays to capture data at 16 time baud rate - -- Each SRL16E is followed by a flip-flop for best timing - - data_loop: for i in 0 to 7 generate - begin - - lsbs: if i<7 generate - -- - attribute INIT : string; - attribute INIT of delay15_srl : label is "0000"; - -- - begin - - delay15_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => data_int(i+1), - CE => en_16_x_baud, - CLK => clk, - A0 => '0', - A1 => '1', - A2 => '1', - A3 => '1', - Q => data_delay(i) ); - - end generate lsbs; - - msb: if i=7 generate - -- - attribute INIT : string; - attribute INIT of delay15_srl : label is "0000"; - -- - begin - - delay15_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => stop_bit, - CE => en_16_x_baud, - CLK => clk, - A0 => '0', - A1 => '1', - A2 => '1', - A3 => '1', - Q => data_delay(i) ); - - end generate msb; - - data_reg: FDE - port map ( D => data_delay(i), - Q => data_int(i), - CE => en_16_x_baud, - C => clk); - - end generate data_loop; - - -- Assign internal signals to outputs - - data_out <= data_int; - - -- Data delays to capture start bit at 16 time baud rate - - start_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => data_int(0), - CE => en_16_x_baud, - CLK => clk, - A0 => '0', - A1 => '1', - A2 => '1', - A3 => '1', - Q => start_delay ); - - start_reg: FDE - port map ( D => start_delay, - Q => start_bit, - CE => en_16_x_baud, - C => clk); - - - -- Data delays to capture start bit leading edge at 16 time baud rate - -- Delay ensures data is captured at mid-bit position - - edge_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => start_bit, - CE => en_16_x_baud, - CLK => clk, - A0 => '1', - A1 => '0', - A2 => '1', - A3 => '0', - Q => edge_delay ); - - edge_reg: FDE - port map ( D => edge_delay, - Q => start_edge, - CE => en_16_x_baud, - C => clk); - - -- Detect a valid character - - valid_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"0040") - --synthesis translate_on - port map( I0 => purge, - I1 => stop_bit, - I2 => start_edge, - I3 => edge_delay, - O => decode_valid_char ); - - valid_reg: FDE - port map ( D => decode_valid_char, - Q => valid_char, - CE => en_16_x_baud, - C => clk); - - -- Purge of data status - - purge_lut: LUT3 - --synthesis translate_off - generic map (INIT => X"54") - --synthesis translate_on - port map( I0 => valid_reg_delay(8), - I1 => valid_char, - I2 => purge, - O => decode_purge ); - - purge_reg: FDE - port map ( D => decode_purge, - Q => purge, - CE => en_16_x_baud, - C => clk); - - -- Delay of valid_char pulse of length equivalent to the time taken - -- to purge data shift register of all data which has been used. - -- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with - -- up to 16 delays and utilising the dedicated flip flop in each stage. - - valid_loop: for i in 0 to 8 generate - begin - - lsb: if i=0 generate - -- - attribute INIT : string; - attribute INIT of delay15_srl : label is "0000"; - -- - begin - - delay15_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => valid_char, - CE => en_16_x_baud, - CLK => clk, - A0 => '0', - A1 => '1', - A2 => '1', - A3 => '1', - Q => valid_srl_delay(i) ); - - end generate lsb; - - msbs: if i>0 generate - -- - attribute INIT : string; - attribute INIT of delay16_srl : label is "0000"; - -- - begin - - delay16_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => valid_reg_delay(i-1), - CE => en_16_x_baud, - CLK => clk, - A0 => '1', - A1 => '1', - A2 => '1', - A3 => '1', - Q => valid_srl_delay(i) ); - - end generate msbs; - - data_reg: FDE - port map ( D => valid_srl_delay(i), - Q => valid_reg_delay(i), - CE => en_16_x_baud, - C => clk); - - end generate valid_loop; - - -- Form data strobe - - strobe_lut: LUT2 - --synthesis translate_off - generic map (INIT => X"8") - --synthesis translate_on - port map( I0 => valid_char, - I1 => en_16_x_baud, - O => decode_data_strobe ); - - strobe_reg: FD - port map ( D => decode_data_strobe, - Q => data_strobe, - C => clk); - -end low_level_definition; - ------------------------------------------------------------------------------------- --- --- END OF FILE KCUART_RX.VHD --- ------------------------------------------------------------------------------------- - - diff --git a/lib/uart/kcuart_tx.vhd b/lib/uart/kcuart_tx.vhd deleted file mode 100644 index 556ac58..0000000 --- a/lib/uart/kcuart_tx.vhd +++ /dev/null @@ -1,394 +0,0 @@ --- Constant (K) Compact UART Transmitter --- --- Version : 1.10 --- Version Date : 3rd December 2003 --- Reason : '--translate' directives changed to '--synthesis translate' directives --- --- Version : 1.00 --- Version Date : 14th October 2002 --- --- Start of design entry : 2nd October 2002 --- --- Ken Chapman --- Xilinx Ltd --- Benchmark House --- 203 Brooklands Road --- Weybridge --- Surrey KT13 ORH --- United Kingdom --- --- chapman@xilinx.com --- ------------------------------------------------------------------------------------- --- --- NOTICE: --- --- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other --- third parties. By providing this core as one possible implementation of a standard, --- Xilinx is making no representation that the provided implementation of this standard --- is free from any claims of infringement by any third party. Xilinx expressly --- disclaims any warranty with respect to the adequacy of the implementation, including --- but not limited to any warranty or representation that the implementation is free --- from claims of any third party. Futhermore, Xilinx is providing this core as a --- courtesy to you and suggests that you contact all third parties to obtain the --- necessary rights to use this implementation. --- ------------------------------------------------------------------------------------- --- --- Library declarations --- --- The Unisim Library is used to define Xilinx primitives. It is also used during --- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use unisim.vcomponents.all; --- ------------------------------------------------------------------------------------- --- --- Main Entity for KCUART_TX --- -entity kcuart_tx is - Port ( data_in : in std_logic_vector(7 downto 0); - send_character : in std_logic; - en_16_x_baud : in std_logic; - serial_out : out std_logic; - Tx_complete : out std_logic; - clk : in std_logic); - end kcuart_tx; --- ------------------------------------------------------------------------------------- --- --- Start of Main Architecture for KCUART_TX --- -architecture low_level_definition of kcuart_tx is --- ------------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------------- --- --- Signals used in KCUART_TX --- ------------------------------------------------------------------------------------- --- -signal data_01 : std_logic; -signal data_23 : std_logic; -signal data_45 : std_logic; -signal data_67 : std_logic; -signal data_0123 : std_logic; -signal data_4567 : std_logic; -signal data_01234567 : std_logic; -signal bit_select : std_logic_vector(2 downto 0); -signal next_count : std_logic_vector(2 downto 0); -signal mask_count : std_logic_vector(2 downto 0); -signal mask_count_carry : std_logic_vector(2 downto 0); -signal count_carry : std_logic_vector(2 downto 0); -signal ready_to_start : std_logic; -signal decode_Tx_start : std_logic; -signal Tx_start : std_logic; -signal decode_Tx_run : std_logic; -signal Tx_run : std_logic; -signal decode_hot_state : std_logic; -signal hot_state : std_logic; -signal hot_delay : std_logic; -signal Tx_bit : std_logic; -signal decode_Tx_stop : std_logic; -signal Tx_stop : std_logic; -signal decode_Tx_complete : std_logic; --- --- ------------------------------------------------------------------------------------- --- --- Attributes to define LUT contents during implementation --- The information is repeated in the generic map for functional simulation-- --- ------------------------------------------------------------------------------------- --- -attribute INIT : string; -attribute INIT of mux1_lut : label is "E4FF"; -attribute INIT of mux2_lut : label is "E4FF"; -attribute INIT of mux3_lut : label is "E4FF"; -attribute INIT of mux4_lut : label is "E4FF"; -attribute INIT of ready_lut : label is "10"; -attribute INIT of start_lut : label is "0190"; -attribute INIT of run_lut : label is "1540"; -attribute INIT of hot_state_lut : label is "94"; -attribute INIT of delay14_srl : label is "0000"; -attribute INIT of stop_lut : label is "0180"; -attribute INIT of complete_lut : label is "8"; --- ------------------------------------------------------------------------------------- --- --- Start of KCUART_TX circuit description --- ------------------------------------------------------------------------------------- --- -begin - - -- 8 to 1 multiplexer to convert parallel data to serial - - mux1_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"E4FF") - --synthesis translate_on - port map( I0 => bit_select(0), - I1 => data_in(0), - I2 => data_in(1), - I3 => Tx_run, - O => data_01 ); - - mux2_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"E4FF") - --synthesis translate_on - port map( I0 => bit_select(0), - I1 => data_in(2), - I2 => data_in(3), - I3 => Tx_run, - O => data_23 ); - - mux3_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"E4FF") - --synthesis translate_on - port map( I0 => bit_select(0), - I1 => data_in(4), - I2 => data_in(5), - I3 => Tx_run, - O => data_45 ); - - mux4_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"E4FF") - --synthesis translate_on - port map( I0 => bit_select(0), - I1 => data_in(6), - I2 => data_in(7), - I3 => Tx_run, - O => data_67 ); - - mux5_muxf5: MUXF5 - port map( I1 => data_23, - I0 => data_01, - S => bit_select(1), - O => data_0123 ); - - mux6_muxf5: MUXF5 - port map( I1 => data_67, - I0 => data_45, - S => bit_select(1), - O => data_4567 ); - - mux7_muxf6: MUXF6 - port map( I1 => data_4567, - I0 => data_0123, - S => bit_select(2), - O => data_01234567 ); - - -- Register serial output and force start and stop bits - - pipeline_serial: FDRS - port map ( D => data_01234567, - Q => serial_out, - R => Tx_start, - S => Tx_stop, - C => clk); - - -- 3-bit counter - -- Counter is clock enabled by en_16_x_baud - -- Counter will be reset when 'Tx_start' is active - -- Counter will increment when Tx_bit is active - -- Tx_run must be active to count - -- count_carry(2) indicates when terminal count (7) is reached and Tx_bit=1 (ie overflow) - - count_width_loop: for i in 0 to 2 generate - -- - attribute INIT : string; - attribute INIT of count_lut : label is "8"; - -- - begin - - register_bit: FDRE - port map ( D => next_count(i), - Q => bit_select(i), - CE => en_16_x_baud, - R => Tx_start, - C => clk); - - count_lut: LUT2 - --synthesis translate_off - generic map (INIT => X"8") - --synthesis translate_on - port map( I0 => bit_select(i), - I1 => Tx_run, - O => mask_count(i)); - - mask_and: MULT_AND - port map( I0 => bit_select(i), - I1 => Tx_run, - LO => mask_count_carry(i)); - - lsb_count: if i=0 generate - begin - - count_muxcy: MUXCY - port map( DI => mask_count_carry(i), - CI => Tx_bit, - S => mask_count(i), - O => count_carry(i)); - - count_xor: XORCY - port map( LI => mask_count(i), - CI => Tx_bit, - O => next_count(i)); - - end generate lsb_count; - - upper_count: if i>0 generate - begin - - count_muxcy: MUXCY - port map( DI => mask_count_carry(i), - CI => count_carry(i-1), - S => mask_count(i), - O => count_carry(i)); - - count_xor: XORCY - port map( LI => mask_count(i), - CI => count_carry(i-1), - O => next_count(i)); - - end generate upper_count; - - end generate count_width_loop; - - -- Ready to start decode - - ready_lut: LUT3 - --synthesis translate_off - generic map (INIT => X"10") - --synthesis translate_on - port map( I0 => Tx_run, - I1 => Tx_start, - I2 => send_character, - O => ready_to_start ); - - -- Start bit enable - - start_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"0190") - --synthesis translate_on - port map( I0 => Tx_bit, - I1 => Tx_stop, - I2 => ready_to_start, - I3 => Tx_start, - O => decode_Tx_start ); - - Tx_start_reg: FDE - port map ( D => decode_Tx_start, - Q => Tx_start, - CE => en_16_x_baud, - C => clk); - - - -- Run bit enable - - run_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"1540") - --synthesis translate_on - port map( I0 => count_carry(2), - I1 => Tx_bit, - I2 => Tx_start, - I3 => Tx_run, - O => decode_Tx_run ); - - Tx_run_reg: FDE - port map ( D => decode_Tx_run, - Q => Tx_run, - CE => en_16_x_baud, - C => clk); - - -- Bit rate enable - - hot_state_lut: LUT3 - --synthesis translate_off - generic map (INIT => X"94") - --synthesis translate_on - port map( I0 => Tx_stop, - I1 => ready_to_start, - I2 => Tx_bit, - O => decode_hot_state ); - - hot_state_reg: FDE - port map ( D => decode_hot_state, - Q => hot_state, - CE => en_16_x_baud, - C => clk); - - delay14_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => hot_state, - CE => en_16_x_baud, - CLK => clk, - A0 => '1', - A1 => '0', - A2 => '1', - A3 => '1', - Q => hot_delay ); - - Tx_bit_reg: FDE - port map ( D => hot_delay, - Q => Tx_bit, - CE => en_16_x_baud, - C => clk); - - -- Stop bit enable - - stop_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"0180") - --synthesis translate_on - port map( I0 => Tx_bit, - I1 => Tx_run, - I2 => count_carry(2), - I3 => Tx_stop, - O => decode_Tx_stop ); - - Tx_stop_reg: FDE - port map ( D => decode_Tx_stop, - Q => Tx_stop, - CE => en_16_x_baud, - C => clk); - - -- Tx_complete strobe - - complete_lut: LUT2 - --synthesis translate_off - generic map (INIT => X"8") - --synthesis translate_on - port map( I0 => count_carry(2), - I1 => en_16_x_baud, - O => decode_Tx_complete ); - - Tx_complete_reg: FD - port map ( D => decode_Tx_complete, - Q => Tx_complete, - C => clk); - - -end low_level_definition; - ------------------------------------------------------------------------------------- --- --- END OF FILE KCUART_TX.VHD --- ------------------------------------------------------------------------------------- - - diff --git a/lib/uart/uart_rx.vhd b/lib/uart/uart_rx.vhd deleted file mode 100644 index 69eb70e..0000000 --- a/lib/uart/uart_rx.vhd +++ /dev/null @@ -1,146 +0,0 @@ --- UART Receiver with integral 16 byte FIFO buffer --- --- 8 bit, no parity, 1 stop bit --- --- Version : 1.00 --- Version Date : 16th October 2002 --- --- Start of design entry : 16th October 2002 --- --- Ken Chapman --- Xilinx Ltd --- Benchmark House --- 203 Brooklands Road --- Weybridge --- Surrey KT13 ORH --- United Kingdom --- --- chapman@xilinx.com --- ------------------------------------------------------------------------------------- --- --- NOTICE: --- --- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other --- third parties. By providing this core as one possible implementation of a standard, --- Xilinx is making no representation that the provided implementation of this standard --- is free from any claims of infringement by any third party. Xilinx expressly --- disclaims any warranty with respect to the adequacy of the implementation, including --- but not limited to any warranty or representation that the implementation is free --- from claims of any third party. Futhermore, Xilinx is providing this core as a --- courtesy to you and suggests that you contact all third parties to obtain the --- necessary rights to use this implementation. --- ------------------------------------------------------------------------------------- --- --- Library declarations --- --- The Unisim Library is used to define Xilinx primitives. It is also used during --- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use unisim.vcomponents.all; --- ------------------------------------------------------------------------------------- --- --- Main Entity for UART_RX --- -entity uart_rx is - Port ( serial_in : in std_logic; - data_out : out std_logic_vector(7 downto 0); - read_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - buffer_data_present : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - clk : in std_logic); - end uart_rx; --- ------------------------------------------------------------------------------------- --- --- Start of Main Architecture for UART_RX --- -architecture macro_level_definition of uart_rx is --- ------------------------------------------------------------------------------------- --- --- Components used in UART_RX and defined in subsequent entities. --- ------------------------------------------------------------------------------------- --- --- Constant (K) Compact UART Receiver --- -component kcuart_rx - Port ( serial_in : in std_logic; - data_out : out std_logic_vector(7 downto 0); - data_strobe : out std_logic; - en_16_x_baud : in std_logic; - clk : in std_logic); - end component; --- --- 'Bucket Brigade' FIFO --- -component bbfifo_16x8 - Port ( data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - reset : in std_logic; - write : in std_logic; - read : in std_logic; - full : out std_logic; - half_full : out std_logic; - data_present : out std_logic; - clk : in std_logic); - end component; --- ------------------------------------------------------------------------------------- --- --- Signals used in UART_RX --- ------------------------------------------------------------------------------------- --- -signal uart_data_out : std_logic_vector(7 downto 0); -signal fifo_write : std_logic; --- ------------------------------------------------------------------------------------- --- --- Start of UART_RX circuit description --- ------------------------------------------------------------------------------------- --- -begin - - -- 8 to 1 multiplexer to convert parallel data to serial - - kcuart: kcuart_rx - port map ( serial_in => serial_in, - data_out => uart_data_out, - data_strobe => fifo_write, - en_16_x_baud => en_16_x_baud, - clk => clk ); - - - buf: bbfifo_16x8 - port map ( data_in => uart_data_out, - data_out => data_out, - reset => reset_buffer, - write => fifo_write, - read => read_buffer, - full => buffer_full, - half_full => buffer_half_full, - data_present => buffer_data_present, - clk => clk); - -end macro_level_definition; - ------------------------------------------------------------------------------------- --- --- END OF FILE UART_RX.VHD --- ------------------------------------------------------------------------------------- - - diff --git a/lib/uart/uart_tx.vhd b/lib/uart/uart_tx.vhd deleted file mode 100644 index 8c4e63d..0000000 --- a/lib/uart/uart_tx.vhd +++ /dev/null @@ -1,148 +0,0 @@ --- UART Transmitter with integral 16 byte FIFO buffer --- --- 8 bit, no parity, 1 stop bit --- --- Version : 1.00 --- Version Date : 14th October 2002 --- --- Start of design entry : 14th October 2002 --- --- Ken Chapman --- Xilinx Ltd --- Benchmark House --- 203 Brooklands Road --- Weybridge --- Surrey KT13 ORH --- United Kingdom --- --- chapman@xilinx.com --- ------------------------------------------------------------------------------------- --- --- NOTICE: --- --- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other --- third parties. By providing this core as one possible implementation of a standard, --- Xilinx is making no representation that the provided implementation of this standard --- is free from any claims of infringement by any third party. Xilinx expressly --- disclaims any warranty with respect to the adequacy of the implementation, including --- but not limited to any warranty or representation that the implementation is free --- from claims of any third party. Futhermore, Xilinx is providing this core as a --- courtesy to you and suggests that you contact all third parties to obtain the --- necessary rights to use this implementation. --- ------------------------------------------------------------------------------------- --- --- Library declarations --- --- The Unisim Library is used to define Xilinx primitives. It is also used during --- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use unisim.vcomponents.all; --- ------------------------------------------------------------------------------------- --- --- Main Entity for UART_TX --- -entity uart_tx is - Port ( data_in : in std_logic_vector(7 downto 0); - write_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - serial_out : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - clk : in std_logic); - end uart_tx; --- ------------------------------------------------------------------------------------- --- --- Start of Main Architecture for UART_TX --- -architecture macro_level_definition of uart_tx is --- ------------------------------------------------------------------------------------- --- --- Components used in UART_TX and defined in subsequent entities. --- ------------------------------------------------------------------------------------- --- --- Constant (K) Compact UART Transmitter --- -component kcuart_tx - Port ( data_in : in std_logic_vector(7 downto 0); - send_character : in std_logic; - en_16_x_baud : in std_logic; - serial_out : out std_logic; - Tx_complete : out std_logic; - clk : in std_logic); - end component; --- --- 'Bucket Brigade' FIFO --- -component bbfifo_16x8 - Port ( data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - reset : in std_logic; - write : in std_logic; - read : in std_logic; - full : out std_logic; - half_full : out std_logic; - data_present : out std_logic; - clk : in std_logic); - end component; --- ------------------------------------------------------------------------------------- --- --- Signals used in UART_TX --- ------------------------------------------------------------------------------------- --- -signal fifo_data_out : std_logic_vector(7 downto 0); -signal fifo_data_present : std_logic; -signal fifo_read : std_logic; --- ------------------------------------------------------------------------------------- --- --- Start of UART_TX circuit description --- ------------------------------------------------------------------------------------- --- -begin - - -- 8 to 1 multiplexer to convert parallel data to serial - - kcuart: kcuart_tx - port map ( data_in => fifo_data_out, - send_character => fifo_data_present, - en_16_x_baud => en_16_x_baud, - serial_out => serial_out, - Tx_complete => fifo_read, - clk => clk); - - - buf: bbfifo_16x8 - port map ( data_in => data_in, - data_out => fifo_data_out, - reset => reset_buffer, - write => write_buffer, - read => fifo_read, - full => buffer_full, - half_full => buffer_half_full, - data_present => fifo_data_present, - clk => clk); - -end macro_level_definition; - ------------------------------------------------------------------------------------- --- --- END OF FILE UART_TX.VHD --- ------------------------------------------------------------------------------------- - -