- fixed ise.mk

- cleaned up project/vga_ctrl

git-svn-id: http://moon:8086/svn/vhdl/trunk@1580 cc03376c-175c-47c8-b038-4cd826a8556b

projects/vga_ctrl/syn/ise/project/bitgen.ut

@@ -1,34 +0,0 @@
- 
--w
--g DebugBitstream:No
--g Binary:no
--g CRC:Enable
--g ConfigRate:4
--g CclkPin:PullUp
--g M0Pin:PullUp
--g M1Pin:PullUp
--g M2Pin:PullUp
--g ProgPin:PullUp
--g DonePin:PullUp
--g InitPin:Pullup
--g CsPin:Pullup
--g DinPin:Pullup
--g BusyPin:Pullup
--g RdWrPin:Pullup
--g TckPin:PullUp
--g TdiPin:PullUp
--g TdoPin:PullUp
--g TmsPin:PullUp
--g UnusedPin:PullDown
--g UserID:0xFFFFFFFF
--g DCMShutDown:Disable
--g DCIUpdateMode:AsRequired
--g StartUpClk:JtagClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:None
--g DonePipe:No
--g DriveDone:No
--g Encrypt:No

projects/vga_ctrl/syn/ise/project/pepExtractor.prj

@@ -1,4 +0,0 @@
-work "fsm_scan.vhd"
-work "sdcwr.vhd"
-work "vga_ctrl_core.vhd"
-work "vga_types.vhd"

projects/vga_ctrl/syn/ise/project/prjname.lso

@@ -1 +0,0 @@
-work

projects/vga_ctrl/syn/ise/project/tb_vga_ctrl.do

@@ -1,17 +0,0 @@
-## NOTE:  Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
-##
-vlib work
-vcom -explicit  -93 "vga_types.vhd"
-vcom -explicit  -93 "sdcwr.vhd"
-vcom -explicit  -93 "fsm_scan.vhd"
-vcom -explicit  -93 "vga_ctrl_core.vhd"
-vcom -explicit  -93 "vga_ctrl_top.vhd"
-vcom -explicit  -93 "tb_vga_ctrl.vhd"
-vsim -t 1ps   -lib work tb_vga_ctrl_vhd
-view wave
-do {wave_vga_ctrl.do}
-view structure
-view signals
-
-run 10us

projects/vga_ctrl/syn/ise/project/tb_vga_ctrl_vhd.udo

@@ -1,4 +0,0 @@
--- ProjNav VHDL simulation template: tb_vga_ctrl_vhd.udo
--- You may edit this file after the line that starts with
--- '-- START' to customize your simulation
--- START user-defined simulation commands

projects/vga_ctrl/syn/ise/project/vga_ctrl_core.lso

@@ -1 +0,0 @@
-work

projects/vga_ctrl/syn/ise/project/vga_ctrl_core.prj

@@ -1,4 +0,0 @@
-vhdl work "sdcwr.vhd"
-vhdl work "vga_types.vhd"
-vhdl work "fsm_scan.vhd"
-vhdl work "vga_ctrl_core.vhd"

projects/vga_ctrl/syn/ise/project/vga_ctrl_top.prj

@@ -1,17 +1,28 @@
-vhdl work "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
-vhdl work "../../../lib/VGA_ctrl/src/vga_types.vhd"
-vhdl work "../src/cpu_pkg.vhd"
-vhdl work "../../../lib/FIFO/src/gray_counter.vhd"
-vhdl work "../../../lib/VGA_ctrl/src/vga_sync.vhd"
-vhdl work "../../../lib/VGA_ctrl/src/dpram.vhd"
-vhdl work "../../../lib/FIFO/src/async_fifo_ctrl.vhd"
-vhdl work "../src/main_irom_ld.vhdl"
-vhdl work "../../../lib/VGA_ctrl/src/vga_timing.vhd"
-vhdl work "../../../lib/VGA_ctrl/src/linefifo.vhd"
-vhdl work "../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
-vhdl work "../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
-vhdl work "../src/main_xrom_ld.vhdl"
-vhdl work "../src/cpu_embedded.vhd"
-vhdl work "../../../lib/VGA_ctrl/src/vga_backend.vhd"
-vhdl work "../../../lib/VGA_ctrl/src/char_gen.vhd"
-vhdl work "../src/vga_ctrl_top.vhd"
+vhdl work "../../../../lib/rams/sim/src/dpram_1w1r2c_ro.vhd"
+vhdl work "../../../../lib/misc/utils_pkg.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
+vhdl work "../../../../lib/rams/sim/src/dpram_1w1r2c_ra.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
+vhdl work "../../../../lib/CPUs/JCpu/src/core/cpu_pkg.vhd"
+vhdl work "../../../../lib/CPUs/JCpu/src/core/cpu.vhd"
+vhdl work "../../../../lib/CPUs/JCpu/src/core/alu.vhd"
+vhdl work "../../../../lib/CPUs/JCpu/src/core/chipram.vhd"
+vhdl work "../../../../lib/CPUs/JCpu/src/core/chipreg.vhd"
+vhdl work "../../../../lib/CPUs/JCpu/src/core/dpath_ctrl.vhd"
+vhdl work "../../../../lib/CPUs/JCpu/src/core/int_ctrl.vhd"
+vhdl work "../../../../lib/CPUs/JCpu/src/core/pc.vhd"
+vhdl work "../../../../lib/CPUs/JCpu/src/core/reg_dual.vhd"
+vhdl work "../../../../lib/CPUs/JCpu/src/core/stack_ctrl.vhd"
+vhdl work "../../src/main_xrom.vhdl"
+vhdl work "../../src/main_irom.vhdl"
+vhdl work "../../src/cpu_embedded.vhd"
+vhdl work "../../src/vga_ctrl_top.vhd"
+

projects/vga_ctrl/syn/ise/project/vga_ctrl_top.xst

@@ -1,7 +1,7 @@
-set -tmpdir "./xst/projnav.tmp"
+set -tmpdir "./xst/tmp"
 set -xsthdpdir "./xst"
 run
--ifn vga_ctrl_top.prj
+-ifn ./project/vga_ctrl_top.prj
 -ifmt mixed
 -ofn vga_ctrl_top
 -ofmt NGC
@@ -11,7 +11,7 @@ run
 -opt_level 1
 -power NO
 -iuc NO
--lso vga_ctrl_top.lso
+-lso ./project/vga_ctrl_top.lso
 -keep_hierarchy NO
 -rtlview Yes
 -glob_opt AllClockNets

projects/vga_ctrl/syn/ise/project/vga_ctrl_top_vhdl.prj

@@ -1,17 +0,0 @@
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
-vhdl work "W:\vhdl\projects\vga_ctrl\src\cpu_pkg.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\dpram.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
-vhdl work "W:\vhdl\projects\vga_ctrl\src\main_irom_ld.vhdl"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\linefifo.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
-vhdl work "W:\vhdl\projects\vga_ctrl\src\main_xrom_ld.vhdl"
-vhdl work "W:\vhdl\projects\vga_ctrl\src\cpu_embedded.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
-vhdl work "W:\vhdl\projects\vga_ctrl\src\vga_ctrl_top.vhd"

projects/vga_ctrl/syn/ise/project/vga_types_vhdl.prj

@@ -1 +0,0 @@
-work "vga_types.vhd"

projects/vga_ctrl/syn/ise/project/wave_vga_ctrl.do

@@ -1,35 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_vga_ctrl_vhd/sys_rstn_in
-add wave -noupdate -format Logic /tb_vga_ctrl_vhd/sys_clk_in
-add wave -noupdate -format Logic /tb_vga_ctrl_vhd/sys_vga_clk
-add wave -noupdate -format Logic /tb_vga_ctrl_vhd/uut/hsync_i
-add wave -noupdate -format Logic /tb_vga_ctrl_vhd/uut/vsync_i
-add wave -noupdate -format Literal /tb_vga_ctrl_vhd/sys_vga_red
-add wave -noupdate -format Literal /tb_vga_ctrl_vhd/sys_vga_green
-add wave -noupdate -format Literal /tb_vga_ctrl_vhd/sys_vga_blue
-add wave -noupdate -format Logic /tb_vga_ctrl_vhd/sys_vga_clk
-add wave -noupdate -format Logic /tb_vga_ctrl_vhd/sys_vga_hsync
-add wave -noupdate -format Logic /tb_vga_ctrl_vhd/sys_vga_vsync
-add wave -noupdate -format Logic /tb_vga_ctrl_vhd/uut/is_scan_h
-add wave -noupdate -format Logic /tb_vga_ctrl_vhd/uut/is_scan_v
-add wave -noupdate -format Logic /tb_vga_ctrl_vhd/uut/h_scan_rdy
-add wave -noupdate -format Logic /tb_vga_ctrl_vhd/uut/v_scan_rdy
-add wave -noupdate -format Logic /tb_vga_ctrl_vhd/sys_dcm_locked
-add wave -noupdate -format Logic /tb_vga_ctrl_vhd/uut/clk_scan_rdy
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1908400 ps} 0}
-configure wave -namecolwidth 212
-configure wave -valuecolwidth 68
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {993377 ps} {2954189 ps}