From 1c7fd9022e117a2c86692131a2fb6d9af1b3b801 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Sat, 25 Oct 2008 17:20:15 +0000
Subject: [PATCH] - Intital revision

git-svn-id: http://moon:8086/svn/vhdl/trunk@117 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/CPUs/MIPS/syn/ise101/mips_top.prj      | 20 ++++++++++++++++++++
 lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj | 20 ++++++++++++++++++++
 2 files changed, 40 insertions(+)
 create mode 100644 lib/CPUs/MIPS/syn/ise101/mips_top.prj
 create mode 100644 lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj

diff --git a/lib/CPUs/MIPS/syn/ise101/mips_top.prj b/lib/CPUs/MIPS/syn/ise101/mips_top.prj
new file mode 100644
index 0000000..7b70379
--- /dev/null
+++ b/lib/CPUs/MIPS/syn/ise101/mips_top.prj
@@ -0,0 +1,20 @@
+vhdl work "../../src/core/mips_types.vhd"
+vhdl work "../../../../misc/dpram_2w2r.vhd"
+vhdl work "../../../../misc/dpram_1w1r_dist.vhd"
+vhdl work "../../../../misc/dpram_1w1r.vhd"
+vhdl work "../../../../FIFO/src/sync_fifo_ctrl.vhd"
+vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../src/core/mips_instr.vhd"
+vhdl work "../../../../FIFO/src/fifo_sync_dist.vhd"
+vhdl work "../../src/core/mips_shifter.vhd"
+vhdl work "../../src/core/mips_reg.vhd"
+vhdl work "../../src/core/mips_muldiv.vhd"
+vhdl work "../../src/core/mips_idecode_rom.vhd"
+vhdl work "../../src/core/mips_cop.vhd"
+vhdl work "../../src/core/mips_bcu.vhd"
+vhdl work "../../src/core/mips_alu.vhd"
+vhdl work "../../src/core/icache.vhd"
+vhdl work "../../src/core/dcache.vhd"
+vhdl work "../../src/core/mips_pipeline.vhd"
+vhdl work "../../src/core/mips_bui.vhd"
+vhdl work "../../src/core/mips_top.vhd"
diff --git a/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj b/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
new file mode 100644
index 0000000..9077a07
--- /dev/null
+++ b/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
@@ -0,0 +1,20 @@
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_dist.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_idecode_rom.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\icache.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\dcache.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"