diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd
index 56b69dc..cca3a3e 100644
--- a/projects/mips_sys/src/mips_sys.vhd
+++ b/projects/mips_sys/src/mips_sys.vhd
@@ -272,22 +272,33 @@ ARCHITECTURE behavior OF mips_sys IS
 	PORT
 	(
 		-- System signals
-		CLK_I			: in  STD_LOGIC;
 		RST_I			: in  STD_LOGIC;
+		CLK_I			: in  STD_LOGIC;
 
+		-- JBUS Master signals
+		CYC_O			: out STD_LOGIC;
+		STB_O			: out STD_LOGIC;
+		WE_O			: out STD_LOGIC;
+		SEL_O			: out unsigned(3 downto 0);
+		ACK_I			: in  STD_LOGIC;
+		SRDY_I			: in  STD_LOGIC;
+		MRDY_O			: out STD_LOGIC;
+		ADDR_O			: out unsigned(31 downto 0);
+		MDAT_I			: in  unsigned(31 downto 0);
+		MDAT_O			: out unsigned(31 downto 0);
+		
 		-- JBUS Slave signals
 		CYC_I			: in  STD_LOGIC;
 		STB_I			: in  STD_LOGIC;
 		WE_I			: in  STD_LOGIC;
+		SEL_I			: in  unsigned(3 downto 0);
 		ACK_O			: out STD_LOGIC;
 		SRDY_O			: out STD_LOGIC;
 		MRDY_I			: in  STD_LOGIC;
 		ADDR_I			: in  unsigned(31 downto 0);
+		SDAT_I			: in  unsigned(31 downto 0);
+		SDAT_O			: out unsigned(31 downto 0);
 		
-		-- JBUS common signals
-		DAT_I			: in  unsigned(31 downto 0);
-		DAT_O			: out unsigned(31 downto 0);
-
 		-- VGA signals
 		vga_clk_out		: out std_logic;
 		vga_red			: out unsigned(7 downto 0);
@@ -310,10 +321,16 @@ ARCHITECTURE behavior OF mips_sys IS
 	signal usb_addr 	: unsigned(31 downto 0);
 	signal flash_addr	: unsigned(31 downto 0);
 
+	-- Arbiter
+	constant ARB_MAX_MASTER	: natural := 2;
+	signal	arb_idx		: natural range 0 to ARB_MAX_MASTER-1;
+	signal	arb_req		: unsigned (ARB_MAX_MASTER-1 downto 0);
+	signal	arb_gnt		: unsigned (ARB_MAX_MASTER-1 downto 0);
+	
 	-- J-Bus signals
 	signal INT	 		: unsigned(5 downto 0);
-	signal DAT_I		: word_t;
-	signal DAT_O 		: word_t;
+	signal MDAT_I		: word_t;
+	signal MDAT_O 		: word_t;
 	signal ADDR_O 		: word_t;
 	signal SEL_O 		: unsigned(3 downto 0);
 	signal WE_O 		: std_logic;
@@ -323,50 +340,73 @@ ARCHITECTURE behavior OF mips_sys IS
 	signal SRDY_I		: std_logic;
 	signal MRDY_O		: std_logic;
 
-	signal CYC_O_flash	: std_logic;
-	signal ACK_I_flash	: std_logic;
-	signal SRDY_I_flash	: std_logic;
-	signal DAT_I_flash	: unsigned(31 downto 0);
-
-	signal CYC_O_usb	: std_logic;
-	signal ACK_I_usb	: std_logic;
-	signal SRDY_I_usb	: std_logic;
-	signal DAT_I_usb	: unsigned(31 downto 0);
-
-	signal CYC_O_sdram	: std_logic;
-	signal ACK_I_sdram	: std_logic;
-	signal SRDY_I_sdram	: std_logic;
-	signal DAT_I_sdram	: unsigned(31 downto 0);
-
-	signal CYC_O_ram	: std_logic;
-	signal ACK_I_ram	: std_logic;
-	signal SRDY_I_ram	: std_logic;
-	signal DAT_I_ram	: unsigned(31 downto 0);
-
-	signal CYC_O_rom	: std_logic;
-	signal ACK_I_rom	: std_logic;
-	signal SRDY_I_rom	: std_logic;
-	signal DAT_I_rom	: unsigned(31 downto 0);
-
-	signal CYC_O_gpio	: std_logic;
-	signal ACK_I_gpio	: std_logic;
-	signal SRDY_I_gpio	: std_logic;
-	signal DAT_I_gpio	: unsigned(31 downto 0);
-
-	signal CYC_O_urom	: std_logic;
-	signal ACK_I_urom	: std_logic;
-	signal SRDY_I_urom	: std_logic;
-	signal DAT_I_urom	: unsigned(31 downto 0);
-
-	signal CYC_O_uart	: std_logic;
-	signal ACK_I_uart	: std_logic;
-	signal SRDY_I_uart	: std_logic;
-	signal DAT_I_uart	: unsigned(31 downto 0);
+	-- CPU Master
+	signal MRDY_O_cpu	: std_logic;
+	signal MDAT_O_cpu	: word_t;
+	signal ADDR_O_cpu	: word_t;
+	signal SEL_O_cpu	: unsigned(3 downto 0);
+	signal WE_O_cpu		: std_logic;
+	signal CYC_O_cpu	: std_logic;
+	signal STB_O_cpu	: std_logic;
+	signal SRDY_I_cpu	: std_logic;
+	signal ACK_I_cpu	: std_logic;
 
+	-- VGA Master
+	signal MRDY_O_vga	: std_logic;
+	signal MDAT_O_vga	: word_t;
+	signal ADDR_O_vga	: word_t;
+	signal SEL_O_vga	: unsigned(3 downto 0);
+	signal WE_O_vga		: std_logic;
 	signal CYC_O_vga	: std_logic;
-	signal ACK_I_vga	: std_logic;
+	signal STB_O_vga	: std_logic;
 	signal SRDY_I_vga	: std_logic;
-	signal DAT_I_vga	: unsigned(31 downto 0);
+	signal ACK_I_vga	: std_logic;
+
+	-- Slaves
+	signal CYC_I_flash	: std_logic;
+	signal ACK_O_flash	: std_logic;
+	signal SRDY_O_flash	: std_logic;
+	signal SDAT_O_flash	: unsigned(31 downto 0);
+
+	signal CYC_I_usb	: std_logic;
+	signal ACK_O_usb	: std_logic;
+	signal SRDY_O_usb	: std_logic;
+	signal SDAT_O_usb	: unsigned(31 downto 0);
+
+	signal CYC_I_sdram	: std_logic;
+	signal ACK_O_sdram	: std_logic;
+	signal SRDY_O_sdram	: std_logic;
+	signal SDAT_O_sdram	: unsigned(31 downto 0);
+
+	signal CYC_I_ram	: std_logic;
+	signal ACK_O_ram	: std_logic;
+	signal SRDY_O_ram	: std_logic;
+	signal SDAT_O_ram	: unsigned(31 downto 0);
+
+	signal CYC_I_rom	: std_logic;
+	signal ACK_O_rom	: std_logic;
+	signal SRDY_O_rom	: std_logic;
+	signal SDAT_O_rom	: unsigned(31 downto 0);
+
+	signal CYC_I_gpio	: std_logic;
+	signal ACK_O_gpio	: std_logic;
+	signal SRDY_O_gpio	: std_logic;
+	signal SDAT_O_gpio	: unsigned(31 downto 0);
+
+	signal CYC_I_urom	: std_logic;
+	signal ACK_O_urom	: std_logic;
+	signal SRDY_O_urom	: std_logic;
+	signal SDAT_O_urom	: unsigned(31 downto 0);
+
+	signal CYC_I_uart	: std_logic;
+	signal ACK_O_uart	: std_logic;
+	signal SRDY_O_uart	: std_logic;
+	signal SDAT_O_uart	: unsigned(31 downto 0);
+
+	signal CYC_I_vga	: std_logic;
+	signal ACK_O_vga	: std_logic;
+	signal SRDY_O_vga	: std_logic;
+	signal SDAT_O_vga	: unsigned(31 downto 0);
 
 	signal gpo0			: unsigned(31 downto 0);
 	signal gpo1			: unsigned(31 downto 0);
@@ -400,6 +440,45 @@ BEGIN
 	usb_addr			<= X"0000000" & "00" & ADDR_O(3 downto 2);
 	flash_addr			<= "0000000" & ADDR_O(25 downto 2) & '0';
 
+
+	---------------------------------------------------------------
+	-- Arbiter
+	MRDY_O		<= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
+	MDAT_O		<= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga when arb_gnt(1) = '1' else (others => '0');
+	ADDR_O		<= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0');
+	SEL_O		<= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga when arb_gnt(1) = '1' else (others => '0');
+	WE_O		<= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0';
+	CYC_O		<= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0';
+	STB_O		<= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0';
+	SRDY_I_cpu	<= SRDY_I and arb_gnt(0);
+	SRDY_I_vga	<= SRDY_I and arb_gnt(1);
+	ACK_I_cpu	<= ACK_I and arb_gnt(0);
+	ACK_I_vga	<= ACK_I and arb_gnt(1);
+	
+	arb_req(0)	<= CYC_O_cpu;
+	arb_req(1)	<= CYC_O_vga;
+	
+	
+arbiter_proc:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				arb_gnt	<= (others => '0');
+				arb_idx	<= 0;
+			elsif arb_req(arb_idx) = '0' then
+				if arb_idx /= ARB_MAX_MASTER-1 then
+					arb_idx	<= arb_idx + 1;
+				else
+					arb_idx	<= 0;
+				end if;
+			else	
+				arb_gnt	<= (others => '0');
+				arb_gnt(arb_idx)	<= '1';
+			end if;	
+		end if;
+	end process;
+	
 int_sample:
 	process(clk)
 	begin
@@ -439,44 +518,44 @@ signal_mux:
 	process(mem_area, CYC_O)
 	begin
 	
-		CYC_O_urom		<= '0';
-		CYC_O_uart		<= '0';
-		CYC_O_gpio		<= '0';
-		CYC_O_flash		<= '0';
-		CYC_O_usb		<= '0';
-		CYC_O_rom		<= '0';
-		CYC_O_ram		<= '0';
-		CYC_O_sdram		<= '0';
-		CYC_O_vga		<= '0';
+		CYC_I_urom		<= '0';
+		CYC_I_uart		<= '0';
+		CYC_I_gpio		<= '0';
+		CYC_I_flash		<= '0';
+		CYC_I_usb		<= '0';
+		CYC_I_rom		<= '0';
+		CYC_I_ram		<= '0';
+		CYC_I_sdram		<= '0';
+		CYC_I_vga		<= '0';
 		
 		case mem_area is
 
 		when mem_urom =>
-			CYC_O_urom		<= CYC_O;
+			CYC_I_urom		<= CYC_O;
 			
 		when mem_gpio =>
-			CYC_O_gpio		<= CYC_O;
+			CYC_I_gpio		<= CYC_O;
 
 		when mem_uart =>
-			CYC_O_uart		<= CYC_O;
+			CYC_I_uart		<= CYC_O;
 
 		when mem_flash =>
-			CYC_O_flash		<= CYC_O;
+			CYC_I_flash		<= CYC_O;
 
 		when mem_usb =>
-			CYC_O_usb		<= CYC_O;
+			CYC_I_usb		<= CYC_O;
 
 		when mem_rom =>
-			CYC_O_rom		<= CYC_O;
+			CYC_I_rom		<= CYC_O;
 
 		when mem_ram =>
-			CYC_O_ram		<= CYC_O;
+			CYC_I_ram		<= CYC_O;
 
 		when mem_sdram =>
-			CYC_O_sdram		<= CYC_O;
+			CYC_I_sdram		<= CYC_O;
 		
 		when mem_vga =>
-			CYC_O_vga		<= CYC_O;
+			CYC_I_vga		<= CYC_O;
 
 		when others => null;
 		
@@ -486,30 +565,30 @@ signal_mux:
 
 --	sys_user_rom_addr	<= ADDR_O;
 --	sys_user_rom_clk	<= clk;
---	sys_user_rom_en		<= CYC_O_urom and STB_O;
---	DAT_I_urom			<= sys_user_rom_din;
-	SRDY_I_urom			<= CYC_O_urom;
+--	sys_user_rom_en		<= CYC_I_urom and STB_O;
+--	SDAT_O_urom			<= sys_user_rom_din;
+	SRDY_O_urom			<= CYC_I_urom;
 	
 urom_ack_register:
 	process(clk)
 	begin
 		if rising_edge(clk) then
-			ACK_I_urom	<= CYC_O_urom and STB_O;
+			ACK_O_urom	<= CYC_I_urom and STB_O;
 		end if;
 	end process;
 	
 ------------------------------------------------------------------
- 	SRDY_I		<=	SRDY_I_flash or SRDY_I_usb or SRDY_I_sdram or SRDY_I_ram or SRDY_I_rom or SRDY_I_urom or SRDY_I_uart or SRDY_I_gpio or SRDY_I_vga;
- 	ACK_I		<=	ACK_I_flash or ACK_I_usb or ACK_I_sdram or ACK_I_ram or ACK_I_rom or ACK_I_urom or ACK_I_uart or ACK_I_gpio or ACK_I_vga;
- 	DAT_I		<=	DAT_I_sdram when CYC_O_sdram = '1' else
-					DAT_I_ram when CYC_O_ram = '1' else
-					DAT_I_rom when CYC_O_rom = '1' else
-					DAT_I_urom when CYC_O_urom = '1' else
-					DAT_I_flash when CYC_O_flash = '1' else
-					DAT_I_usb when CYC_O_usb = '1' else
-					DAT_I_uart when CYC_O_uart = '1' else
-					DAT_I_vga when CYC_O_vga = '1' else
-					DAT_I_gpio when CYC_O_gpio = '1' else X"DEADBEEF";
+ 	SRDY_I		<=	SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_urom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga;
+ 	ACK_I		<=	ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ram or ACK_O_rom or ACK_O_urom or ACK_O_uart or ACK_O_gpio or ACK_O_vga;
+ 	MDAT_I		<=	SDAT_O_sdram when CYC_I_sdram = '1' else
+					SDAT_O_ram when CYC_I_ram = '1' else
+					SDAT_O_rom when CYC_I_rom = '1' else
+					SDAT_O_urom when CYC_I_urom = '1' else
+					SDAT_O_flash when CYC_I_flash = '1' else
+					SDAT_O_usb when CYC_I_usb = '1' else
+					SDAT_O_uart when CYC_I_uart = '1' else
+					SDAT_O_vga when CYC_I_vga = '1' else
+					SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
 
 ------------------------------------------------------------------
 inst_mips_top: mips_top
@@ -518,16 +597,16 @@ inst_mips_top: mips_top
 		debug			=> debug,
 		RST_I			=> rst,
 		CLK_I			=> clk,
-		ACK_I			=> ACK_I,
-		SRDY_I			=> SRDY_I,
-		MRDY_O			=> MRDY_O,
-		CYC_O			=> CYC_O,
-		STB_O			=> STB_O,
-		WE_O			=> WE_O,
-		SEL_O			=> SEL_O,
-		DAT_I			=> DAT_I,
-		DAT_O			=> DAT_O,
-		ADDR_O			=> ADDR_O,
+		ACK_I			=> ACK_I_cpu,
+		SRDY_I			=> SRDY_I_cpu,
+		MRDY_O			=> MRDY_O_cpu,
+		CYC_O			=> CYC_O_cpu,
+		STB_O			=> STB_O_cpu,
+		WE_O			=> WE_O_cpu,
+		SEL_O			=> SEL_O_cpu,
+		DAT_I			=> MDAT_I,
+		DAT_O			=> MDAT_O_cpu,
+		ADDR_O			=> ADDR_O_cpu,
 		INT				=> INT
 	);
 
@@ -536,16 +615,16 @@ inst_ram_wb : ram_wb
 	(
 		CLK_I	=> clk,
 		RST_I	=> rst,
-		CYC_I	=> CYC_O_ram,
+		CYC_I	=> CYC_I_ram,
 		STB_I	=> STB_O,
 		SEL_I	=> SEL_O,
 		WE_I	=> WE_O,
-		ACK_O	=> ACK_I_ram,
-		SRDY_O	=> SRDY_I_ram,
+		ACK_O	=> ACK_O_ram,
+		SRDY_O	=> SRDY_O_ram,
 		MRDY_I	=> MRDY_O,
 		ADDR_I	=> ADDR_O,
-		DAT_I	=> DAT_O,
-		DAT_O	=> DAT_I_ram
+		DAT_I	=> MDAT_O,
+		DAT_O	=> SDAT_O_ram
 	);
 
 inst_rom_wb : rom_wb
@@ -553,13 +632,13 @@ inst_rom_wb : rom_wb
 	(
 		CLK_I	=> clk,
 		RST_I	=> rst,
-		CYC_I	=> CYC_O_rom,
+		CYC_I	=> CYC_I_rom,
 		STB_I	=> STB_O,
-		ACK_O	=> ACK_I_rom,
+		ACK_O	=> ACK_O_rom,
 		MRDY_I	=> MRDY_O,
-		SRDY_O	=> SRDY_I_rom,
+		SRDY_O	=> SRDY_O_rom,
 		ADDR_I	=> ADDR_O,
-		DAT_O	=> DAT_I_rom
+		DAT_O	=> SDAT_O_rom
 	);
 
 
@@ -582,16 +661,16 @@ inst_gpio_wb : gpio_wb
 	(
 		CLK_I		=> clk,
 		RST_I		=> rst,
-		CYC_I		=> CYC_O_gpio,
+		CYC_I		=> CYC_I_gpio,
 		STB_I		=> STB_O,
 		SEL_I		=> SEL_O,
 		WE_I		=> WE_O,
-		ACK_O		=> ACK_I_gpio,
-		SRDY_O		=> SRDY_I_gpio,
+		ACK_O		=> ACK_O_gpio,
+		SRDY_O		=> SRDY_O_gpio,
 		MRDY_I		=> MRDY_O,
 		ADDR_I		=> ADDR_O,
-		DAT_I		=> DAT_O,
-		DAT_O		=> DAT_I_gpio,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_gpio,
 
 		sys_gpo0	=> gpo0,
 		sys_gpo1	=> gpo1,
@@ -611,15 +690,15 @@ inst_flash_port : async_port_wb
 	(
 		CLK_I		=> clk,
 		RST_I		=> rst,
-		CYC_I		=> CYC_O_flash,
+		CYC_I		=> CYC_I_flash,
 		STB_I		=> STB_O,
 		WE_I		=> WE_O,
-		ACK_O		=> ACK_I_flash,
-		SRDY_O		=> SRDY_I_flash,
+		ACK_O		=> ACK_O_flash,
+		SRDY_O		=> SRDY_O_flash,
 		MRDY_I		=> MRDY_O,
 		ADDR_I		=> flash_addr,
-		DAT_I		=> DAT_O,
-		DAT_O		=> DAT_I_flash,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_flash,
 		async_a		=> sys_flash_a,
 		async_d		=> sys_flash_d,
 		async_cs	=> sys_flash_ce,
@@ -639,15 +718,15 @@ inst_usb_port : async_port_wb
 	(
 		CLK_I		=> clk,
 		RST_I		=> rst,
-		CYC_I		=> CYC_O_usb,
+		CYC_I		=> CYC_I_usb,
 		STB_I		=> STB_O,
 		WE_I		=> WE_O,
-		ACK_O		=> ACK_I_usb,
-		SRDY_O		=> SRDY_I_usb,
+		ACK_O		=> ACK_O_usb,
+		SRDY_O		=> SRDY_O_usb,
 		MRDY_I		=> MRDY_O,
 		ADDR_I		=> usb_addr,
-		DAT_I		=> DAT_O,
-		DAT_O		=> DAT_I_usb,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_usb,
 		async_a		=> sys_usb_a,
 		async_d		=> sys_usb_d,
 		async_cs	=> sys_usb_csn,
@@ -661,16 +740,16 @@ inst_uart_wb : uart_wb
 	(
 		CLK_I		=> clk,
 		RST_I		=> rst,
-		CYC_I		=> CYC_O_uart,
+		CYC_I		=> CYC_I_uart,
 		STB_I		=> STB_O,
 		SEL_I		=> SEL_O,
 		WE_I		=> WE_O,
-		ACK_O		=> ACK_I_uart,
-		SRDY_O		=> SRDY_I_uart,
+		ACK_O		=> ACK_O_uart,
+		SRDY_O		=> SRDY_O_uart,
 		MRDY_I		=> MRDY_O,
 		ADDR_I		=> ADDR_O,
-		DAT_I		=> DAT_O,
-		DAT_O		=> DAT_I_uart,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_uart,
 		INT_RX_O	=> int_uart_rx,
 		INT_TX_O	=> open,
 		ser_rx		=> sys_rx,
@@ -683,7 +762,7 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb
 	(
 		BL			=> BURST_LEN,
 		f_sysclk	=> ddr_frequency_hz,
-		fifo_depth	=> 4
+		fifo_depth	=> 6
 	)
 	PORT MAP
 	(
@@ -692,16 +771,16 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb
 		CLK270_I		=> clk270,
 		CLK270VAR_I		=> clk270var,
 		
-		CYC_I			=> CYC_O_sdram,
+		CYC_I			=> CYC_I_sdram,
 		STB_I			=> STB_O,
 		SEL_I			=> SEL_O,
 		WE_I			=> WE_O,
-		ACK_O			=> ACK_I_sdram,
+		ACK_O			=> ACK_O_sdram,
 		MRDY_I			=> MRDY_O,
-		SRDY_O			=> SRDY_I_sdram,
+		SRDY_O			=> SRDY_O_sdram,
 		ADDR_I			=> ADDR_O,
-		DAT_I			=> DAT_O,
-		DAT_O			=> DAT_I_sdram,
+		DAT_I			=> MDAT_O,
+		DAT_O			=> SDAT_O_sdram,
 
 		-- SDRAM signals
 		sd_clk_p		=> sys_sdr_clk_p,
@@ -744,8 +823,8 @@ inst_vga_frontend : vga_frontend
 	(
 		sys_freq					=> 100E6,
 		fifo_depth					=> 2048,
-		fifo_almost_full_thresh		=> 2000,
-		fifo_almost_empty_thresh	=> 48,
+		fifo_almost_full_thresh		=> 1860,
+		fifo_almost_empty_thresh	=> 256,
 		tsvga						=> ts_vga_800_600_72
 	)
 	PORT MAP
@@ -754,19 +833,30 @@ inst_vga_frontend : vga_frontend
 		RST_I			=> rst,
 		CLK_I			=> clk,
 
+		-- JBUS Master signals
+		CYC_O			=> CYC_O_vga,
+		STB_O			=> STB_O_vga,
+		WE_O			=> WE_O_vga,
+		SEL_O			=> SEL_O_vga,
+		ACK_I			=> ACK_I_vga,
+		SRDY_I			=> SRDY_I_vga,
+		MRDY_O			=> MRDY_O_vga,
+		ADDR_O			=> ADDR_O_vga,
+		MDAT_I			=> MDAT_I,
+		MDAT_O			=> MDAT_O_vga,
+
 		-- JBUS Slave signals
-		CYC_I			=> CYC_O_vga,
+		CYC_I			=> CYC_I_vga,
 		STB_I			=> STB_O,
 		WE_I			=> WE_O,
-		ACK_O			=> ACK_I_vga,
-		SRDY_O			=> SRDY_I_vga,
+		SEL_I			=> SEL_O,
+		ACK_O			=> ACK_O_vga,
+		SRDY_O			=> SRDY_O_vga,
 		MRDY_I			=> MRDY_O,
 		ADDR_I			=> ADDR_O,
+		SDAT_I			=> MDAT_O,
+		SDAT_O			=> SDAT_O_vga,
 		
-		-- JBUS common signals
-		DAT_I			=> DAT_O,
-		DAT_O			=> DAT_I_vga,
-
 		-- VGA signals
 		vga_clk_out		=> sys_vga_clk,
 		vga_red			=> sys_vga_red,
diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd
index 5f88c3b..2090a07 100644
--- a/projects/mips_sys/src/mips_sys_sim.vhd
+++ b/projects/mips_sys/src/mips_sys_sim.vhd
@@ -35,6 +35,7 @@ use work.mips_types.all;
 --use work.fifo_ctrl_pkg.all;
 use work.sdram_config.all;
 use work.sdram_types.all;
+use work.vga_types.all;
 use work.sys_types.all;
 
 
@@ -87,14 +88,14 @@ PORT
 	sys_sdr_clk_fb		: in std_logic;
 	
 	-- VGA
---	sys_vga_red			: out unsigned(7 downto 0);
---	sys_vga_green		: out unsigned(7 downto 0);
---	sys_vga_blue		: out unsigned(7 downto 0);
---	sys_vga_blank_n		: out std_logic;
---	sys_vga_sync_n		: out std_logic;
---	sys_vga_hsync		: out std_logic;
---	sys_vga_vsync		: out std_logic;
---	sys_vga_clk			: out std_logic;
+	sys_vga_clk			: out std_logic;
+	sys_vga_red			: out unsigned(7 downto 0);
+	sys_vga_green		: out unsigned(7 downto 0);
+	sys_vga_blue		: out unsigned(7 downto 0);
+	sys_vga_blank_n		: out std_logic;
+	sys_vga_sync_n		: out std_logic;
+	sys_vga_hsync		: out std_logic;
+	sys_vga_vsync		: out std_logic;
 
 	sys_usb_d			: inout unsigned(15 downto 0);
 	sys_usb_a			: out unsigned(1 downto 0);
@@ -265,6 +266,57 @@ ARCHITECTURE behavior OF mips_sys IS
 	);
 	END COMPONENT;
 
+	COMPONENT vga_frontend
+	GENERIC
+	(
+		sys_freq					: integer;
+		fifo_depth					: integer;
+		fifo_almost_full_thresh		: natural;
+		fifo_almost_empty_thresh	: natural;
+		tsvga						: vga_timespec_t
+	);
+	PORT
+	(
+		-- System signals
+		RST_I			: in  STD_LOGIC;
+		CLK_I			: in  STD_LOGIC;
+
+		-- JBUS Master signals
+		CYC_O			: out STD_LOGIC;
+		STB_O			: out STD_LOGIC;
+		WE_O			: out STD_LOGIC;
+		SEL_O			: out unsigned(3 downto 0);
+		ACK_I			: in  STD_LOGIC;
+		SRDY_I			: in  STD_LOGIC;
+		MRDY_O			: out STD_LOGIC;
+		ADDR_O			: out unsigned(31 downto 0);
+		MDAT_I			: in  unsigned(31 downto 0);
+		MDAT_O			: out unsigned(31 downto 0);
+
+		-- JBUS Slave signals
+		CYC_I			: in  STD_LOGIC;
+		STB_I			: in  STD_LOGIC;
+		WE_I			: in  STD_LOGIC;
+		SEL_I			: in  unsigned(3 downto 0);
+		ACK_O			: out STD_LOGIC;
+		SRDY_O			: out STD_LOGIC;
+		MRDY_I			: in  STD_LOGIC;
+		ADDR_I			: in  unsigned(31 downto 0);
+		SDAT_I			: in  unsigned(31 downto 0);
+		SDAT_O			: out unsigned(31 downto 0);
+		
+		-- VGA signals
+		vga_clk_out		: out std_logic;
+		vga_red			: out unsigned(7 downto 0);
+		vga_green		: out unsigned(7 downto 0);
+		vga_blue		: out unsigned(7 downto 0);
+		vga_blank_n		: out std_logic;
+		vga_sync_n		: out std_logic;
+		vga_hsync		: out std_logic;
+		vga_vsync		: out std_logic
+	);
+	END COMPONENT;
+
 	signal rst			: std_logic;
 	signal clk			: std_logic;
 	signal clk270		: std_logic;
@@ -275,10 +327,16 @@ ARCHITECTURE behavior OF mips_sys IS
 	signal usb_addr 	: unsigned(31 downto 0);
 	signal flash_addr	: unsigned(31 downto 0);
 
+	-- Arbiter
+	constant ARB_MAX_MASTER	: natural := 2;
+	signal	arb_idx		: natural range 0 to ARB_MAX_MASTER-1;
+	signal	arb_req		: unsigned (ARB_MAX_MASTER-1 downto 0);
+	signal	arb_gnt		: unsigned (ARB_MAX_MASTER-1 downto 0);
+	
 	-- J-Bus signals
 	signal INT	 		: unsigned(5 downto 0);
-	signal DAT_I		: word_t;
-	signal DAT_O 		: word_t;
+	signal MDAT_I		: word_t;
+	signal MDAT_O 		: word_t;
 	signal ADDR_O 		: word_t;
 	signal SEL_O 		: unsigned(3 downto 0);
 	signal WE_O 		: std_logic;
@@ -288,45 +346,73 @@ ARCHITECTURE behavior OF mips_sys IS
 	signal SRDY_I		: std_logic;
 	signal MRDY_O		: std_logic;
 
-	signal CYC_O_flash	: std_logic;
-	signal ACK_I_flash	: std_logic;
-	signal SRDY_I_flash	: std_logic;
-	signal DAT_I_flash	: unsigned(31 downto 0);
+	-- CPU Master
+	signal MRDY_O_cpu	: std_logic;
+	signal MDAT_O_cpu	: word_t;
+	signal ADDR_O_cpu	: word_t;
+	signal SEL_O_cpu	: unsigned(3 downto 0);
+	signal WE_O_cpu		: std_logic;
+	signal CYC_O_cpu	: std_logic;
+	signal STB_O_cpu	: std_logic;
+	signal SRDY_I_cpu	: std_logic;
+	signal ACK_I_cpu	: std_logic;
 
-	signal CYC_O_usb	: std_logic;
-	signal ACK_I_usb	: std_logic;
-	signal SRDY_I_usb	: std_logic;
-	signal DAT_I_usb	: unsigned(31 downto 0);
+	-- VGA Master
+	signal MRDY_O_vga	: std_logic;
+	signal MDAT_O_vga	: word_t;
+	signal ADDR_O_vga	: word_t;
+	signal SEL_O_vga	: unsigned(3 downto 0);
+	signal WE_O_vga		: std_logic;
+	signal CYC_O_vga	: std_logic;
+	signal STB_O_vga	: std_logic;
+	signal SRDY_I_vga	: std_logic;
+	signal ACK_I_vga	: std_logic;
 
-	signal CYC_O_sdram	: std_logic;
-	signal ACK_I_sdram	: std_logic;
-	signal SRDY_I_sdram	: std_logic;
-	signal DAT_I_sdram	: unsigned(31 downto 0);
+	-- Slaves
+	signal CYC_I_flash	: std_logic;
+	signal ACK_O_flash	: std_logic;
+	signal SRDY_O_flash	: std_logic;
+	signal SDAT_O_flash	: unsigned(31 downto 0);
 
-	signal CYC_O_ram	: std_logic;
-	signal ACK_I_ram	: std_logic;
-	signal SRDY_I_ram	: std_logic;
-	signal DAT_I_ram	: unsigned(31 downto 0);
+	signal CYC_I_usb	: std_logic;
+	signal ACK_O_usb	: std_logic;
+	signal SRDY_O_usb	: std_logic;
+	signal SDAT_O_usb	: unsigned(31 downto 0);
 
-	signal CYC_O_rom	: std_logic;
-	signal ACK_I_rom	: std_logic;
-	signal SRDY_I_rom	: std_logic;
-	signal DAT_I_rom	: unsigned(31 downto 0);
+	signal CYC_I_sdram	: std_logic;
+	signal ACK_O_sdram	: std_logic;
+	signal SRDY_O_sdram	: std_logic;
+	signal SDAT_O_sdram	: unsigned(31 downto 0);
 
-	signal CYC_O_gpio	: std_logic;
-	signal ACK_I_gpio	: std_logic;
-	signal SRDY_I_gpio	: std_logic;
-	signal DAT_I_gpio	: unsigned(31 downto 0);
+	signal CYC_I_ram	: std_logic;
+	signal ACK_O_ram	: std_logic;
+	signal SRDY_O_ram	: std_logic;
+	signal SDAT_O_ram	: unsigned(31 downto 0);
 
-	signal CYC_O_urom	: std_logic;
-	signal ACK_I_urom	: std_logic;
-	signal SRDY_I_urom	: std_logic;
-	signal DAT_I_urom	: unsigned(31 downto 0);
+	signal CYC_I_rom	: std_logic;
+	signal ACK_O_rom	: std_logic;
+	signal SRDY_O_rom	: std_logic;
+	signal SDAT_O_rom	: unsigned(31 downto 0);
 
-	signal CYC_O_uart	: std_logic;
-	signal ACK_I_uart	: std_logic;
-	signal SRDY_I_uart	: std_logic;
-	signal DAT_I_uart	: unsigned(31 downto 0);
+	signal CYC_I_gpio	: std_logic;
+	signal ACK_O_gpio	: std_logic;
+	signal SRDY_O_gpio	: std_logic;
+	signal SDAT_O_gpio	: unsigned(31 downto 0);
+
+	signal CYC_I_urom	: std_logic;
+	signal ACK_O_urom	: std_logic;
+	signal SRDY_O_urom	: std_logic;
+	signal SDAT_O_urom	: unsigned(31 downto 0);
+
+	signal CYC_I_uart	: std_logic;
+	signal ACK_O_uart	: std_logic;
+	signal SRDY_O_uart	: std_logic;
+	signal SDAT_O_uart	: unsigned(31 downto 0);
+
+	signal CYC_I_vga	: std_logic;
+	signal ACK_O_vga	: std_logic;
+	signal SRDY_O_vga	: std_logic;
+	signal SDAT_O_vga	: unsigned(31 downto 0);
 
 	signal gpo0			: unsigned(31 downto 0);
 	signal gpo1			: unsigned(31 downto 0);
@@ -344,7 +430,7 @@ ARCHITECTURE behavior OF mips_sys IS
 --	attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
 --	attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
 
-	type mem_area_t is (mem_dead, mem_urom, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram);
+	type mem_area_t is (mem_dead, mem_urom, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga);
 	signal mem_area : mem_area_t;
 
 BEGIN
@@ -360,6 +446,45 @@ BEGIN
 	usb_addr			<= X"0000000" & "00" & ADDR_O(3 downto 2);
 	flash_addr			<= "0000000" & ADDR_O(25 downto 2) & '0';
 
+
+	---------------------------------------------------------------
+	-- Arbiter
+	MRDY_O		<= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
+	MDAT_O		<= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga when arb_gnt(1) = '1' else (others => '0');
+	ADDR_O		<= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0');
+	SEL_O		<= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga when arb_gnt(1) = '1' else (others => '0');
+	WE_O		<= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0';
+	CYC_O		<= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0';
+	STB_O		<= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0';
+	SRDY_I_cpu	<= SRDY_I and arb_gnt(0);
+	SRDY_I_vga	<= SRDY_I and arb_gnt(1);
+	ACK_I_cpu	<= ACK_I and arb_gnt(0);
+	ACK_I_vga	<= ACK_I and arb_gnt(1);
+	
+	arb_req(0)	<= CYC_O_cpu;
+	arb_req(1)	<= CYC_O_vga;
+	
+	
+arbiter_proc:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				arb_gnt	<= (others => '0');
+				arb_idx	<= 0;
+			elsif arb_req(arb_idx) = '0' then
+				if arb_idx /= ARB_MAX_MASTER-1 then
+					arb_idx	<= arb_idx + 1;
+				else
+					arb_idx	<= 0;
+				end if;
+			else	
+				arb_gnt	<= (others => '0');
+				arb_gnt(arb_idx)	<= '1';
+			end if;	
+		end if;
+	end process;
+	
 int_sample:
 	process(clk)
 	begin
@@ -383,6 +508,8 @@ mem_mux:
 				mem_area	<= mem_uart;
 			elsif ADDR_O(17 downto 16) = "10" then
 				mem_area	<= mem_usb;
+			elsif ADDR_O(17 downto 16) = "11" then
+				mem_area	<= mem_vga;
 			end if;	
 		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
 			mem_area	<= mem_rom;
@@ -397,41 +524,45 @@ signal_mux:
 	process(mem_area, CYC_O)
 	begin
 	
-		CYC_O_urom		<= '0';
-		CYC_O_uart		<= '0';
-		CYC_O_gpio		<= '0';
-		CYC_O_flash		<= '0';
-		CYC_O_usb		<= '0';
-		CYC_O_rom		<= '0';
-		CYC_O_ram		<= '0';
-		CYC_O_sdram		<= '0';
+		CYC_I_urom		<= '0';
+		CYC_I_uart		<= '0';
+		CYC_I_gpio		<= '0';
+		CYC_I_flash		<= '0';
+		CYC_I_usb		<= '0';
+		CYC_I_rom		<= '0';
+		CYC_I_ram		<= '0';
+		CYC_I_sdram		<= '0';
+		CYC_I_vga		<= '0';
 		
 		case mem_area is
 
 		when mem_urom =>
-			CYC_O_urom		<= CYC_O;
+			CYC_I_urom		<= CYC_O;
 			
 		when mem_gpio =>
-			CYC_O_gpio		<= CYC_O;
+			CYC_I_gpio		<= CYC_O;
 
 		when mem_uart =>
-			CYC_O_uart		<= CYC_O;
+			CYC_I_uart		<= CYC_O;
 
 		when mem_flash =>
-			CYC_O_flash		<= CYC_O;
+			CYC_I_flash		<= CYC_O;
 
 		when mem_usb =>
-			CYC_O_usb		<= CYC_O;
+			CYC_I_usb		<= CYC_O;
 
 		when mem_rom =>
-			CYC_O_rom		<= CYC_O;
+			CYC_I_rom		<= CYC_O;
 
 		when mem_ram =>
-			CYC_O_ram		<= CYC_O;
+			CYC_I_ram		<= CYC_O;
 
 		when mem_sdram =>
-			CYC_O_sdram		<= CYC_O;
+			CYC_I_sdram		<= CYC_O;
 		
+		when mem_vga =>
+			CYC_I_vga		<= CYC_O;
+
 		when others => null;
 		
 		end case;
@@ -440,29 +571,30 @@ signal_mux:
 
 	sys_user_rom_addr	<= ADDR_O;
 	sys_user_rom_clk	<= clk;
-	sys_user_rom_en		<= CYC_O_urom and STB_O;
-	DAT_I_urom			<= sys_user_rom_din;
-	SRDY_I_urom			<= CYC_O_urom;
+	sys_user_rom_en		<= CYC_I_urom and STB_O;
+	SDAT_O_urom			<= sys_user_rom_din;
+	SRDY_O_urom			<= CYC_I_urom;
 	
 urom_ack_register:
 	process(clk)
 	begin
 		if rising_edge(clk) then
-			ACK_I_urom	<= CYC_O_urom and STB_O;
+			ACK_O_urom	<= CYC_I_urom and STB_O;
 		end if;
 	end process;
 	
 ------------------------------------------------------------------
- 	SRDY_I		<=	SRDY_I_flash or SRDY_I_usb or SRDY_I_sdram or SRDY_I_ram or SRDY_I_rom or SRDY_I_urom or SRDY_I_uart or SRDY_I_gpio;
- 	ACK_I		<=	ACK_I_flash or ACK_I_usb or ACK_I_sdram or ACK_I_ram or ACK_I_rom or ACK_I_urom or ACK_I_uart or ACK_I_gpio;
- 	DAT_I		<=	DAT_I_sdram when CYC_O_sdram = '1' else
-					DAT_I_ram when CYC_O_ram = '1' else
-					DAT_I_rom when CYC_O_rom = '1' else
-					DAT_I_urom when CYC_O_urom = '1' else
-					DAT_I_flash when CYC_O_flash = '1' else
-					DAT_I_usb when CYC_O_usb = '1' else
-					DAT_I_uart when CYC_O_uart = '1' else
-					DAT_I_gpio when CYC_O_gpio = '1' else X"DEADBEEF";
+ 	SRDY_I		<=	SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_urom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga;
+ 	ACK_I		<=	ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ram or ACK_O_rom or ACK_O_urom or ACK_O_uart or ACK_O_gpio or ACK_O_vga;
+ 	MDAT_I		<=	SDAT_O_sdram when CYC_I_sdram = '1' else
+					SDAT_O_ram when CYC_I_ram = '1' else
+					SDAT_O_rom when CYC_I_rom = '1' else
+					SDAT_O_urom when CYC_I_urom = '1' else
+					SDAT_O_flash when CYC_I_flash = '1' else
+					SDAT_O_usb when CYC_I_usb = '1' else
+					SDAT_O_uart when CYC_I_uart = '1' else
+					SDAT_O_vga when CYC_I_vga = '1' else
+					SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
 
 ------------------------------------------------------------------
 inst_mips_top: mips_top
@@ -471,16 +603,16 @@ inst_mips_top: mips_top
 		debug			=> debug,
 		RST_I			=> rst,
 		CLK_I			=> clk,
-		ACK_I			=> ACK_I,
-		SRDY_I			=> SRDY_I,
-		MRDY_O			=> MRDY_O,
-		CYC_O			=> CYC_O,
-		STB_O			=> STB_O,
-		WE_O			=> WE_O,
-		SEL_O			=> SEL_O,
-		DAT_I			=> DAT_I,
-		DAT_O			=> DAT_O,
-		ADDR_O			=> ADDR_O,
+		ACK_I			=> ACK_I_cpu,
+		SRDY_I			=> SRDY_I_cpu,
+		MRDY_O			=> MRDY_O_cpu,
+		CYC_O			=> CYC_O_cpu,
+		STB_O			=> STB_O_cpu,
+		WE_O			=> WE_O_cpu,
+		SEL_O			=> SEL_O_cpu,
+		DAT_I			=> MDAT_I,
+		DAT_O			=> MDAT_O_cpu,
+		ADDR_O			=> ADDR_O_cpu,
 		INT				=> INT
 	);
 
@@ -489,16 +621,16 @@ inst_ram_wb : ram_wb
 	(
 		CLK_I	=> clk,
 		RST_I	=> rst,
-		CYC_I	=> CYC_O_ram,
+		CYC_I	=> CYC_I_ram,
 		STB_I	=> STB_O,
 		SEL_I	=> SEL_O,
 		WE_I	=> WE_O,
-		ACK_O	=> ACK_I_ram,
-		SRDY_O	=> SRDY_I_ram,
+		ACK_O	=> ACK_O_ram,
+		SRDY_O	=> SRDY_O_ram,
 		MRDY_I	=> MRDY_O,
 		ADDR_I	=> ADDR_O,
-		DAT_I	=> DAT_O,
-		DAT_O	=> DAT_I_ram
+		DAT_I	=> MDAT_O,
+		DAT_O	=> SDAT_O_ram
 	);
 
 inst_rom_wb : rom_wb
@@ -506,13 +638,13 @@ inst_rom_wb : rom_wb
 	(
 		CLK_I	=> clk,
 		RST_I	=> rst,
-		CYC_I	=> CYC_O_rom,
+		CYC_I	=> CYC_I_rom,
 		STB_I	=> STB_O,
-		ACK_O	=> ACK_I_rom,
+		ACK_O	=> ACK_O_rom,
 		MRDY_I	=> MRDY_O,
-		SRDY_O	=> SRDY_I_rom,
+		SRDY_O	=> SRDY_O_rom,
 		ADDR_I	=> ADDR_O,
-		DAT_O	=> DAT_I_rom
+		DAT_O	=> SDAT_O_rom
 	);
 
 
@@ -535,16 +667,16 @@ inst_gpio_wb : gpio_wb
 	(
 		CLK_I		=> clk,
 		RST_I		=> rst,
-		CYC_I		=> CYC_O_gpio,
+		CYC_I		=> CYC_I_gpio,
 		STB_I		=> STB_O,
 		SEL_I		=> SEL_O,
 		WE_I		=> WE_O,
-		ACK_O		=> ACK_I_gpio,
-		SRDY_O		=> SRDY_I_gpio,
+		ACK_O		=> ACK_O_gpio,
+		SRDY_O		=> SRDY_O_gpio,
 		MRDY_I		=> MRDY_O,
 		ADDR_I		=> ADDR_O,
-		DAT_I		=> DAT_O,
-		DAT_O		=> DAT_I_gpio,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_gpio,
 
 		sys_gpo0	=> gpo0,
 		sys_gpo1	=> gpo1,
@@ -564,15 +696,15 @@ inst_flash_port : async_port_wb
 	(
 		CLK_I		=> clk,
 		RST_I		=> rst,
-		CYC_I		=> CYC_O_flash,
+		CYC_I		=> CYC_I_flash,
 		STB_I		=> STB_O,
 		WE_I		=> WE_O,
-		ACK_O		=> ACK_I_flash,
-		SRDY_O		=> SRDY_I_flash,
+		ACK_O		=> ACK_O_flash,
+		SRDY_O		=> SRDY_O_flash,
 		MRDY_I		=> MRDY_O,
 		ADDR_I		=> flash_addr,
-		DAT_I		=> DAT_O,
-		DAT_O		=> DAT_I_flash,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_flash,
 		async_a		=> sys_flash_a,
 		async_d		=> sys_flash_d,
 		async_cs	=> sys_flash_ce,
@@ -592,15 +724,15 @@ inst_usb_port : async_port_wb
 	(
 		CLK_I		=> clk,
 		RST_I		=> rst,
-		CYC_I		=> CYC_O_usb,
+		CYC_I		=> CYC_I_usb,
 		STB_I		=> STB_O,
 		WE_I		=> WE_O,
-		ACK_O		=> ACK_I_usb,
-		SRDY_O		=> SRDY_I_usb,
+		ACK_O		=> ACK_O_usb,
+		SRDY_O		=> SRDY_O_usb,
 		MRDY_I		=> MRDY_O,
 		ADDR_I		=> usb_addr,
-		DAT_I		=> DAT_O,
-		DAT_O		=> DAT_I_usb,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_usb,
 		async_a		=> sys_usb_a,
 		async_d		=> sys_usb_d,
 		async_cs	=> sys_usb_csn,
@@ -614,16 +746,16 @@ inst_uart_wb : uart_wb
 	(
 		CLK_I		=> clk,
 		RST_I		=> rst,
-		CYC_I		=> CYC_O_uart,
+		CYC_I		=> CYC_I_uart,
 		STB_I		=> STB_O,
 		SEL_I		=> SEL_O,
 		WE_I		=> WE_O,
-		ACK_O		=> ACK_I_uart,
-		SRDY_O		=> SRDY_I_uart,
+		ACK_O		=> ACK_O_uart,
+		SRDY_O		=> SRDY_O_uart,
 		MRDY_I		=> MRDY_O,
 		ADDR_I		=> ADDR_O,
-		DAT_I		=> DAT_O,
-		DAT_O		=> DAT_I_uart,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_uart,
 		INT_RX_O	=> int_uart_rx,
 		INT_TX_O	=> open,
 		ser_rx		=> sys_rx,
@@ -636,7 +768,7 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb
 	(
 		BL			=> BURST_LEN,
 		f_sysclk	=> ddr_frequency_hz,
-		fifo_depth	=> 4
+		fifo_depth	=> 6
 	)
 	PORT MAP
 	(
@@ -645,16 +777,16 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb
 		CLK270_I		=> clk270,
 		CLK270VAR_I		=> clk270var,
 		
-		CYC_I			=> CYC_O_sdram,
+		CYC_I			=> CYC_I_sdram,
 		STB_I			=> STB_O,
 		SEL_I			=> SEL_O,
 		WE_I			=> WE_O,
-		ACK_O			=> ACK_I_sdram,
+		ACK_O			=> ACK_O_sdram,
 		MRDY_I			=> MRDY_O,
-		SRDY_O			=> SRDY_I_sdram,
+		SRDY_O			=> SRDY_O_sdram,
 		ADDR_I			=> ADDR_O,
-		DAT_I			=> DAT_O,
-		DAT_O			=> DAT_I_sdram,
+		DAT_I			=> MDAT_O,
+		DAT_O			=> SDAT_O_sdram,
 
 		-- SDRAM signals
 		sd_clk_p		=> sys_sdr_clk_p,
@@ -692,5 +824,55 @@ inst_clockgen : entity work.clockgen
 		error_out		=> open
 	);
 
+inst_vga_frontend : vga_frontend
+	GENERIC MAP
+	(
+		sys_freq					=> 100E6,
+		fifo_depth					=> 2048,
+		fifo_almost_full_thresh		=> 2000,
+		fifo_almost_empty_thresh	=> 1600,
+		tsvga						=> ts_vga_800_600_72
+	)
+	PORT MAP
+	(
+		-- System signals
+		RST_I			=> rst,
+		CLK_I			=> clk,
+
+		-- JBUS Master signals
+		CYC_O			=> CYC_O_vga,
+		STB_O			=> STB_O_vga,
+		WE_O			=> WE_O_vga,
+		SEL_O			=> SEL_O_vga,
+		ACK_I			=> ACK_I_vga,
+		SRDY_I			=> SRDY_I_vga,
+		MRDY_O			=> MRDY_O_vga,
+		ADDR_O			=> ADDR_O_vga,
+		MDAT_I			=> MDAT_I,
+		MDAT_O			=> MDAT_O_vga,
+
+		-- JBUS Slave signals
+		CYC_I			=> CYC_I_vga,
+		STB_I			=> STB_O,
+		WE_I			=> WE_O,
+		SEL_I			=> SEL_O,
+		ACK_O			=> ACK_O_vga,
+		SRDY_O			=> SRDY_O_vga,
+		MRDY_I			=> MRDY_O,
+		ADDR_I			=> ADDR_O,
+		SDAT_I			=> MDAT_O,
+		SDAT_O			=> SDAT_O_vga,
+
+		-- VGA signals
+		vga_clk_out		=> sys_vga_clk,
+		vga_red			=> sys_vga_red,
+		vga_green		=> sys_vga_green,
+		vga_blue		=> sys_vga_blue,
+		vga_blank_n		=> sys_vga_blank_n,
+		vga_sync_n		=> sys_vga_sync_n,
+		vga_hsync		=> sys_vga_hsync,
+		vga_vsync		=> sys_vga_vsync	
+	);
+
 	------------------------------------------------------------------
 END;
diff --git a/projects/mips_sys/src/tb_mips_sys.vhd b/projects/mips_sys/src/tb_mips_sys.vhd
index 092a632..446816e 100644
--- a/projects/mips_sys/src/tb_mips_sys.vhd
+++ b/projects/mips_sys/src/tb_mips_sys.vhd
@@ -203,7 +203,7 @@ CLK_GEN: process
 
 UROM_READ: process(sys_rst_n_in, sys_user_rom_clk)
 	type file_t is file of integer;
-	file load_urom : file_t open read_mode is "test_dcache.bin";
+	file load_urom : file_t open read_mode is "test_bui.bin";
 	variable instr : integer;
 	variable index : natural;
 	variable temp : signed(31 downto 0);