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- generate CKE from SDRAM CMD fsm. Simplified interfaces

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1233 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-25 12:13:27 +00:00
parent ce79902c62
commit 1bc700a041
3 changed files with 22 additions and 23 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+19 -14
View File
@@ -38,7 +38,6 @@ entity sdram_cmd is
( (
rst : in STD_LOGIC; rst : in STD_LOGIC;
clk : in STD_LOGIC; clk : in STD_LOGIC;
enable : in STD_LOGIC;
tag : in user_tag_t; tag : in user_tag_t;
col_addr : in col_addr_t; col_addr : in col_addr_t;
mode_word : in mode_word_t; mode_word : in mode_word_t;
@@ -84,11 +83,11 @@ begin
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
fsm_sdr_state: fsm_sdr_state:
process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr, tag) process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, col_addr, tag)
begin begin
st_sdr_next <= st_sdr; st_sdr_next <= st_sdr;
phy_ctrl.part.cmd <= COMMAND(SD_NOP); phy_ctrl.part.cmd <= COMMAND(SD_NOP);
phy_ctrl.part.cke <= enable; phy_ctrl.part.cke <= '1';
phy_ctrl.u_tag <= tag; phy_ctrl.u_tag <= tag;
cc_load_en <= '0'; cc_load_en <= '0';
burst_load_en <= '0'; burst_load_en <= '0';
@@ -101,21 +100,18 @@ fsm_sdr_state:
phy_ctrl.part.ba <= mode_word(mode_word_t'left downto mode_word_t'left-1); phy_ctrl.part.ba <= mode_word(mode_word_t'left downto mode_word_t'left-1);
case st_sdr is case st_sdr is
when PWR_DOWN => when PWR_DOWN =>
phy_ctrl.part.cke <= '0';
phy_ctrl.part.cmd <= COMMAND(SD_DESELECT); phy_ctrl.part.cmd <= COMMAND(SD_DESELECT);
if enable = '1' then if cmd_we = '1' then
st_sdr_next <= IDLE; cmd_ack <= '1';
cc_load_en <= '1';
if cmd = SD_NOP then
st_sdr_next <= IDLE_WAIT;
end if;
end if; end if;
when PRECHARGE =>
st_sdr_next <= IDLE_WAIT;
when MODE =>
st_sdr_next <= IDLE_WAIT;
when ROW_ACT =>
st_sdr_next <= IDLE_WAIT;
when IDLE_WAIT => when IDLE_WAIT =>
if cycle_finished = '1' then if cycle_finished = '1' then
st_sdr_next <= IDLE; st_sdr_next <= IDLE;
@@ -183,6 +179,15 @@ fsm_sdr_state:
st_sdr_next <= IDLE_WAIT; st_sdr_next <= IDLE_WAIT;
end if; end if;
when PRECHARGE =>
st_sdr_next <= IDLE_WAIT;
when MODE =>
st_sdr_next <= IDLE_WAIT;
when ROW_ACT =>
st_sdr_next <= IDLE_WAIT;
when WRITE_A => -- not implemented yet when WRITE_A => -- not implemented yet
st_sdr_next <= IDLE_WAIT; st_sdr_next <= IDLE_WAIT;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+1 -5
View File
@@ -48,8 +48,7 @@ entity sdram_ctrl is
sdr_cmd_busy : in STD_LOGIC; sdr_cmd_busy : in STD_LOGIC;
sdr_cmd : out sdr_cmd_t; sdr_cmd : out sdr_cmd_t;
sdr_cmd_we : out STD_LOGIC; sdr_cmd_we : out STD_LOGIC;
sdr_mode : out mode_word_t; sdr_mode : out mode_word_t
sdr_cke : out STD_LOGIC
); );
end sdram_ctrl; end sdram_ctrl;
@@ -198,7 +197,6 @@ fsm_ctrl_state:
sdr_cmd_we <= '0'; sdr_cmd_we <= '0';
sdr_mode <= bank_addr_reg & row_addr_reg; sdr_mode <= bank_addr_reg & row_addr_reg;
col_addr <= col_addr_reg; col_addr <= col_addr_reg;
sdr_cke <= '1';
seq_cnt_en <= '0'; seq_cnt_en <= '0';
seq_rst_en <= '0'; seq_rst_en <= '0';
addr_reg_load_en <= '0'; addr_reg_load_en <= '0';
@@ -210,12 +208,10 @@ fsm_ctrl_state:
st_ctrl_next <= st_ctrl; st_ctrl_next <= st_ctrl;
case st_ctrl is case st_ctrl is
when RESET => when RESET =>
sdr_cke <= '0';
pwr_up_cnt_rst <= '1'; pwr_up_cnt_rst <= '1';
st_ctrl_next <= POWER_WAIT; st_ctrl_next <= POWER_WAIT;
when POWER_WAIT => when POWER_WAIT =>
sdr_cke <= '0';
if pwr_up_finished = '1' then if pwr_up_finished = '1' then
seq_rst_en <= '1'; seq_rst_en <= '1';
st_ctrl_next <= INIT; st_ctrl_next <= INIT;
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+1 -3
View File
@@ -112,8 +112,7 @@ begin
sdr_cmd => sd_cmd_in, sdr_cmd => sd_cmd_in,
sdr_cmd_we => cmd_fifo_we, sdr_cmd_we => cmd_fifo_we,
col_addr => col_fifo_in, col_addr => col_fifo_in,
sdr_mode => mode_fifo_in, sdr_mode => mode_fifo_in
sdr_cke => cke
); );
-- Instantiate synchronous FIFO -- Instantiate synchronous FIFO
@@ -148,7 +147,6 @@ begin
( (
rst => sdram_rst0, rst => sdram_rst0,
clk => sdram_clk0, clk => sdram_clk0,
enable => cke,
tag => sd_tag_fifo_out, tag => sd_tag_fifo_out,
col_addr => sd_col_fifo_out, col_addr => sd_col_fifo_out,
mode_word => sd_mode_fifo_out, mode_word => sd_mode_fifo_out,