From 1b8dd208710d0fa5fc2d961a6737b65f07ba91c0 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 24 May 2015 11:28:03 +0000 Subject: [PATCH] - removed hard coded constants git-svn-id: http://moon:8086/svn/vhdl/trunk@1206 cc03376c-175c-47c8-b038-4cd826a8556b --- .../ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd index e860176..782169a 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd @@ -80,8 +80,8 @@ architecture struct of sdram_ctrl_frontend_wb32 is signal cat_fifo_full : std_logic; signal cat_fifo_empty : std_logic; - signal write_fifo_din : unsigned(35 downto 0); - signal write_fifo_dout : unsigned(35 downto 0); + signal write_fifo_din : unsigned(32 + PART_DM_WIDTH-1 downto 0); + signal write_fifo_dout : unsigned(32 + PART_DM_WIDTH-1 downto 0); signal write_fifo_re : std_logic; signal write_fifo_we : std_logic; signal write_fifo_full : std_logic; @@ -102,9 +102,9 @@ architecture struct of sdram_ctrl_frontend_wb32 is alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0); alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-1 downto 4); - alias write_fifo_dm_in is write_fifo_din(3 downto 0); + alias write_fifo_dm_in is write_fifo_din(PART_DM_WIDTH-1 downto 0); alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-1 downto 4); - alias write_fifo_dm_out is write_fifo_dout(3 downto 0); + alias write_fifo_dm_out is write_fifo_dout(PART_DM_WIDTH-1 downto 0); alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-1 downto 0); alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-1 downto 0); @@ -222,7 +222,7 @@ begin u_cmd_we <= (not cat_fifo_empty) and (not u_busy); u_cmd <= cmd_fifo_out; u_addr <= addr_fifo_out; - phy_in.wr_dm <= ("1111" & write_fifo_dm_out) when phy_out.tag_wr(0) = '0' else (write_fifo_dm_out & "1111"); + phy_in.wr_dm <= ((PART_DM_WIDTH-1 downto 0 => '1') & write_fifo_dm_out) when phy_out.tag_wr(0) = '0' else (write_fifo_dm_out & (PART_DM_WIDTH-1 downto 0 => '1')); u_tag_in <= tag_fifo_out; phy_in.wr_data <= write_fifo_data_out & write_fifo_data_out;