From 1abe64b3b4f86a180e5d948dc7e308dedbcbc063 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Thu, 8 Apr 2010 15:44:55 +0000 Subject: [PATCH] Inital version Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@882 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/emac/src/crc32.vhd | 59 +++++++++++++++++++++ lib/emac/src/tb_crc32.vhd | 106 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 165 insertions(+) create mode 100644 lib/emac/src/crc32.vhd create mode 100644 lib/emac/src/tb_crc32.vhd diff --git a/lib/emac/src/crc32.vhd b/lib/emac/src/crc32.vhd new file mode 100644 index 0000000..5a8cb22 --- /dev/null +++ b/lib/emac/src/crc32.vhd @@ -0,0 +1,59 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +use std.textio.all; -- Imports the standard textio package. + +use work.utils_pkg.all; -- Imports the standard textio package. + +ENTITY crc32 IS + Port + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + din_vld : in STD_LOGIC; + din : in unsigned(7 downto 0); + crc32_vld : out STD_LOGIC; + crc32_out : out unsigned(31 downto 0) + + ); +END crc32; + +ARCHITECTURE behavior OF crc32 IS + + type crc_table_t is array (0 to 15) of unsigned(31 downto 0); + + constant crc_table : crc_table_t := + ( + X"4DBDF21C", X"500AE278", X"76D3D2D4", X"6B64C2B0", + X"3B61B38C", X"26D6A3E8", X"000F9344", X"1DB88320", + X"A005713C", X"BDB26158", X"9B6B51F4", X"86DC4190", + X"D6D930AC", X"CB6E20C8", X"EDB71064", X"F0000000" + ); + + signal crc0 : unsigned(31 downto 0); + signal crc1 : unsigned(31 downto 0); + signal crc2 : unsigned(31 downto 0); + +-------------------------------------------------------------------------- +begin + + crc1 <= X"0" & crc0(31 downto 4) xor crc_table(to_integer(crc0(3 downto 0) xor din(3 downto 0))); + crc2 <= X"0" & crc1(31 downto 4) xor crc_table(to_integer(crc1(3 downto 0) xor din(7 downto 4))); + + crc32_out <= crc0; + +-------------------------------------------------------------------------- +process(clk) +begin + if rising_edge(clk) then + crc32_vld <= not rst and din_vld; + if rst = '1' then + crc0 <= (others => '0'); + elsif din_vld = '1' then + crc0 <= crc2; + end if; + end if; +end process; + +-------------------------------------------------------------------------- +end behavior; diff --git a/lib/emac/src/tb_crc32.vhd b/lib/emac/src/tb_crc32.vhd new file mode 100644 index 0000000..ad49ca3 --- /dev/null +++ b/lib/emac/src/tb_crc32.vhd @@ -0,0 +1,106 @@ +------------------------------------------------------------------------- +-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL +-- This file: testbench for system test using Xilinx ML-402 + +-- Copyright (C) 2007 J. Ahrensfeld + +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. + +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. + +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +-- For questions and ideas, please contact the author at jens@jayfield.org + +----------------------------------------------------------------------- + +LIBRARY ieee; +use IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY tb_crc32 IS +END tb_crc32; + +ARCHITECTURE behavior OF tb_crc32 IS + + constant CLK_PERIOD : time := 10 ns; + + signal CLK : std_logic := '1'; + signal RST : std_logic := '1'; + + signal din_vld : std_logic := '0'; + signal din : unsigned(7 downto 0) := (others => '-'); + signal crc32 : unsigned(31 downto 0); + signal crc32_vld : std_logic; + + + type byte_array_t is array (0 to 61) of unsigned(7 downto 0); + + signal test_data : byte_array_t := + ( + X"00", X"0A", X"E6", X"F0", X"05", X"A3", X"00", X"12", + X"34", X"56", X"78", X"90", X"08", X"00", X"45", X"00", + X"00", X"30", X"B3", X"FE", X"00", X"00", X"80", X"11", + X"72", X"BA", X"0A", X"00", X"00", X"03", X"0A", X"00", + X"00", X"02", X"04", X"00", X"04", X"00", X"00", X"1C", + X"89", X"4D", X"00", X"01", X"02", X"03", X"04", X"05", + X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", + X"0E", X"0F", X"10", X"11", X"12", X"13" + ); + +BEGIN + +inst_crc32: entity work.crc32 + PORT MAP + ( + rst => RST, + clk => CLK, + din_vld => din_vld, + din => din, + crc32_vld => crc32_vld, + crc32_out => crc32 + + ); + + +CLK_GEN: process + begin + wait for CLK_PERIOD/2; + CLK <= not CLK; + end process; + + +-- Master +STIMULUS: process + + + begin + + wait for 6*CLK_PERIOD; + RST <= '0'; + wait for 6*CLK_PERIOD; + + wait until rising_edge(CLK); + + for i in 0 to 61 loop + din_vld <= '1'; + din <= test_data(i); + wait until rising_edge(CLK); + end loop; + + din <= (others => '-'); + din_vld <= '0'; + + wait; + + end process; + +END;