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- fixed paths after refactoring

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1533 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2021-03-24 20:18:09 +00:00
parent 4943c43e32
commit 1a346c73d9
21 changed files with 23 additions and 25 deletions
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lib/rams/sim/src/dpram_1w1r1c_ra.vhd
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-------------------------------------------------------------------------
-- Project: Dual-Port RAM with 1 clock latency for simulation
-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r1c_ra is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk : in STD_LOGIC;
we_a : in STD_LOGIC;
re_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r1c_ra;
architecture Behavioral of dpram_1w1r1c_ra is
TYPE MEM IS ARRAY(0 TO 2**addr_width-1) OF unsigned(data_width-1 DOWNTO 0);
SIGNAL ram_block: MEM;
BEGIN
PROCESS (clk)
BEGIN
IF (clk'event AND clk = '1') THEN
IF (we_a = '1') THEN
ram_block(to_integer(addr_a)) <= din_a;
END IF;
IF (re_b = '1') THEN
dout_b <= ram_block(to_integer(addr_b));
END IF;
-- VHDL semantics imply that q doesn't get data
-- in this clock cycle
END IF;
END PROCESS;
end Behavioral;
lib/rams/sim/src/dpram_1w1r2c_ra.vhd
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-------------------------------------------------------------------------
-- Project: Dual-Port RAM with 1 clock latency for simulation
-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r2c_ra is
Generic (
addr_width : integer := 3;
data_width : integer := 8
);
Port (
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
we_a : in STD_LOGIC;
re_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r2c_ra;
architecture Behavioral of dpram_1w1r2c_ra is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
signal addr_b_r : unsigned (addr_width-1 downto 0);
begin
dout_b <= RAM(to_integer(addr_b_r));
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if re_b = '1' then
addr_b_r <= addr_b;
end if;
end if;
end process;
end Behavioral;
lib/rams/sim/src/dpram_1w1r2c_ro.vhd
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-------------------------------------------------------------------------
-- Project: Dual-Port RAM with 1 clock latency for simulation
-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered output
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity dpram_1w1r2c_ro is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
we_a : in STD_LOGIC;
re_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_1w1r2c_ro;
architecture Behavioral of dpram_1w1r2c_ro is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
begin
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if re_b = '1' then
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;
end Behavioral;
lib/rams/sim/src/dpram_2w2r2c_ra.vhd
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-------------------------------------------------------------------------
-- Project: Dual-Port RAM with 1 clock latency for simulation
-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered address
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_2w2r2c_ra is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
re_a : in STD_LOGIC;
re_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_2w2r2c_ra;
architecture Behavioral of dpram_2w2r2c_ra is
constant depth : integer := 2**addr_width;
signal addr_a_r : unsigned (addr_width-1 downto 0);
signal addr_b_r : unsigned (addr_width-1 downto 0);
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
signal RAM : RAMtype;
begin
dout_a <= RAM(to_integer(addr_a_r));
dout_b <= RAM(to_integer(addr_b_r));
process (clk_a, clk_b)
begin
if clk_a'event and clk_a = '1' and we_a = '1' then
RAM(to_integer(addr_a)) <= din_a;
elsif clk_b'event and clk_b = '1' and we_b = '1' then
RAM(to_integer(addr_b)) <= din_b;
end if;
end process;
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if re_a = '1' then
addr_a_r <= addr_a;
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if re_b = '1' then
addr_b_r <= addr_b;
end if;
end if;
end process;
end Behavioral;
lib/rams/sim/src/dpram_2w2r2c_ro.vhd
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-------------------------------------------------------------------------
-- Project: Dual-Port RAM with 1 clock latency for simulation
-- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered output
-- Copyright (C) 2007 J. Ahrensfeld
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-- For questions and ideas, please contact the author at jens@jayfield.org
-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_2w2r2c_ro_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity dpram_2w2r2c_ro is
Generic
(
addr_width : integer := 3;
data_width : integer := 8
);
Port
(
clk_a : in STD_LOGIC;
clk_b : in STD_LOGIC;
re_a : in STD_LOGIC;
re_b : in STD_LOGIC;
we_a : in STD_LOGIC;
we_b : in STD_LOGIC;
addr_a : in unsigned (addr_width-1 downto 0);
addr_b : in unsigned (addr_width-1 downto 0);
din_a : in unsigned (data_width-1 downto 0);
din_b : in unsigned (data_width-1 downto 0);
dout_a : out unsigned (data_width-1 downto 0);
dout_b : out unsigned (data_width-1 downto 0)
);
end dpram_2w2r2c_ro;
architecture Behavioral of dpram_2w2r2c_ro is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable RAM : RAMtype;
begin
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
end if;
if re_a = '1' then
dout_a <= RAM(to_integer(addr_a));
end if;
end if;
end process;
process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
end if;
if re_b = '1' then
dout_b <= RAM(to_integer(addr_b));
end if;
end if;
end process;
end Behavioral;