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- fixed paths after refactoring

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1533 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-24 20:18:09 +00:00
parent 4943c43e32
commit 1a346c73d9
21 changed files with 23 additions and 25 deletions
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lib/CPUs/MIPS/ghdl/mips_core.inc
+17 -15
View File
@@ -3,29 +3,31 @@ PKG_NAME := MIPS_CORE
ROOT_PATH := ../../../..
LIB_PATH := $(ROOT_PATH)/lib
CUR_PATH := $(shell dirname $(lastword $(MAKEFILE_LIST)))
SRC_PATH := $(LIB_PATH)/CPUs/MIPS/src/core
MOD_PATH := $(LIB_PATH)/CPUs/MIPS/src/core
# -----------------------------------------------------------
SRCS := $(SRC_PATH)/mips_types.vhd
SRCS += $(SRC_PATH)/mips_instr.vhd
SRCS += $(SRC_PATH)/mips_alu.vhd
SRCS += $(SRC_PATH)/mips_bcu.vhd
SRCS += $(SRC_PATH)/mips_biu.vhd
SRCS += $(SRC_PATH)/mips_cop.vhd
SRCS += $(SRC_PATH)/mips_dcache.vhd
SRCS += $(SRC_PATH)/mips_icache.vhd
SRCS += $(SRC_PATH)/mips_muldiv.vhd
SRCS += $(SRC_PATH)/mips_pipeline.vhd
SRCS += $(SRC_PATH)/mips_reg.vhd
SRCS += $(SRC_PATH)/mips_shifter.vhd
SRCS += $(SRC_PATH)/mips_top.vhd
SRCS += $(LIB_PATH)/rams/sim/src/dpram_2w2r2c_ra.vhd
SRCS += $(LIB_PATH)/rams/sim/src/dpram_1w1r2c_ra.vhd
SRCS += $(MOD_PATH)/mips_types.vhd
SRCS += $(MOD_PATH)/mips_instr.vhd
SRCS += $(MOD_PATH)/mips_alu.vhd
SRCS += $(MOD_PATH)/mips_bcu.vhd
SRCS += $(MOD_PATH)/mips_biu.vhd
SRCS += $(MOD_PATH)/mips_cop.vhd
SRCS += $(MOD_PATH)/mips_dcache.vhd
SRCS += $(MOD_PATH)/mips_icache.vhd
SRCS += $(MOD_PATH)/mips_muldiv.vhd
SRCS += $(MOD_PATH)/mips_pipeline.vhd
SRCS += $(MOD_PATH)/mips_reg.vhd
SRCS += $(MOD_PATH)/mips_shifter.vhd
SRCS += $(MOD_PATH)/mips_top.vhd
# -----------------------------------------------------------
$(PKG_NAME)_SRCS := $(addprefix $(CUR_PATH)/,$(SRCS))
SRCS :=
CUR_PATH :=
SRC_PATH :=
MOD_PATH :=
ROOT_PATH :=
LIB_PATH :=
lib/CPUs/MIPS/ghdl/tb_mips_top.make
-4
View File
@@ -2,10 +2,6 @@ include mips_core.inc
include ../../../../lib/FIFO/ghdl/fifo_sync.inc
include ../../../../lib/FIFO/ghdl/fifo_async.inc
# RAMS
SRCS += ../../../rams/sim/dpram_2w2r2c_ra.vhd
SRCS += ../../../rams/sim/dpram_1w1r2c_ra.vhd
# FIFOS
SRCS += $(FIFO_SYNC_SRCS)
SRCS += $(FIFO_ASYNC_SRCS)