From 1a26f8176a1849c9879fd303ad150320b80a68a7 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 18 Jan 2009 14:39:23 +0000 Subject: [PATCH] - Minor changes Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@253 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/tools/src/ramgen.c | 262 ++++++++++++++++++++++++++++++- lib/CPUs/MIPS/tools/src/romgen.c | 2 +- 2 files changed, 262 insertions(+), 2 deletions(-) diff --git a/lib/CPUs/MIPS/tools/src/ramgen.c b/lib/CPUs/MIPS/tools/src/ramgen.c index a266e35..8f61118 100644 --- a/lib/CPUs/MIPS/tools/src/ramgen.c +++ b/lib/CPUs/MIPS/tools/src/ramgen.c @@ -24,6 +24,260 @@ void basename(char *pSrc, char *pDst) } +int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) +{ + FILE *pFileIn, *pFileOut; + long start, end; + int i, word, filesize, romsize; + + pFileIn = fopen(pFilenameIn, "rb"); + if (!pFileIn) + { + fprintf(stderr, "Error opening file %s\n", pFilenameIn); + return 1; + } + + pFileOut = fopen(pFilenameOut, "wb"); + if (!pFileOut) + { + fprintf(stderr, "Error opening file %s\n", pFilenameOut); + return 1; + } + + fseek(pFileIn, 0, SEEK_SET); + start = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_END); + end = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_SET); + + filesize = (end-start); + romsize = (int)pow(2, nbits_addr+2); + + // ------------------------------------------------------------------------- + // Header + + // ------------------------------------------------------------------------- + fprintf(pFileOut, "LIBRARY IEEE;\n"); + fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); + fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); + fprintf(pFileOut, "\tPort\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1); + fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "END %s;\n", ENT_NAME); + fprintf(pFileOut, "\n"); + + + fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4); + fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); + + fprintf(pFileOut, "\tsignal sram : word_array_t :=\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // ROM part + // ------------------------------------------------------------------------- + for (i=0; i < filesize; i += sizeof(int)) + { + fread(&word, 1, sizeof(int), pFileIn); + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + word = 0; + for (; i < romsize; i += sizeof(int)) + { + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // Trailer + // ------------------------------------------------------------------------- + fprintf(pFileOut, "begin\n", ARCH_NAME); + fprintf(pFileOut, "\n"); + fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME); + fprintf(pFileOut, "\tprocess(clk)\n"); + fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n"); + fprintf(pFileOut, "\tbegin\n"); + fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); + fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1); + fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n"); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n"); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n"); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n"); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\t\tdout <= sram(index);\n"); + fprintf(pFileOut, "\t\tend if;\n"); + fprintf(pFileOut, "\tend process;\n"); + fprintf(pFileOut, "\n"); + fprintf(pFileOut, "end %s;\n", ARCH_NAME); + + return 0; +} + +int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) +{ + FILE *pFileIn, *pFileOut; + long start, end; + int i, word, filesize, romsize; + + char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; + + pFileIn = fopen(pFilenameIn, "rb"); + if (!pFileIn) + { + fprintf(stderr, "Error opening file %s\n", pFilenameIn); + return 1; + } + + pFileOut = fopen(pFilenameOut, "wb"); + if (!pFileOut) + { + fprintf(stderr, "Error opening file %s\n", pFilenameOut); + return 1; + } + + fseek(pFileIn, 0, SEEK_SET); + start = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_END); + end = ftell(pFileIn); + fseek(pFileIn, 0, SEEK_SET); + + filesize = (end-start); + romsize = (int)pow(2, nbits_addr+2); + + // ------------------------------------------------------------------------- + // Header + + // ------------------------------------------------------------------------- + fprintf(pFileOut, "LIBRARY IEEE;\n"); + fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); + fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "library UNISIM;\n"); + fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); + fprintf(pFileOut, "\tPort\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); + fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "END %s;\n", ENT_NAME); + fprintf(pFileOut, "\n"); + + + fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); + + fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); + fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); + fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); + fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); + fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); + fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); + fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); + fprintf(pFileOut, "\t(\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // ROM part + // ------------------------------------------------------------------------- + for (i=0; i < filesize; i += sizeof(int)) + { + fread(&word, 1, sizeof(int), pFileIn); + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + word = 0; + for (; i < romsize; i += sizeof(int)) + { + fprintf(pFileOut, "\t\tX\"%8.8X\"", word); + if (i < (romsize-sizeof(int))) + fprintf(pFileOut, ", -- %8.8X\n", i); + else + fprintf(pFileOut, " -- %8.8X\n", i); + } + fprintf(pFileOut, "\t);\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "begin\n", ARCH_NAME); + + fprintf(pFileOut, "\n"); + fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); + fprintf(pFileOut, "\tprocess(clk)\n"); + fprintf(pFileOut, "\tbegin\n"); + fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); + fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); + fprintf(pFileOut, "\t\tend if;\n"); + fprintf(pFileOut, "\tend process;\n"); + fprintf(pFileOut, "\n"); + + // ------------------------------------------------------------------------- + // Trailer + // ------------------------------------------------------------------------- + fprintf(pFileOut, "\n"); + fputs(tpl, pFileOut); + + fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); + fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); + fprintf(pFileOut, "\tbegin\n"); + fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); + fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); + fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); + fprintf(pFileOut, "\t\t\telse\n"); + fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); + fprintf(pFileOut, "\t\t\tend if;\n"); + fprintf(pFileOut, "\t\tend if;\n"); + fprintf(pFileOut, "\tend process;\n"); + fprintf(pFileOut, "\n"); + + fprintf(pFileOut, "end %s;\n", ARCH_NAME); + return 0; +} + int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) { FILE *pFileIn, *pFileOut; @@ -97,6 +351,8 @@ int main(int argc, char *argv[]) char *pFilenameIn; char name_prj[1024]; char name_rom_tcl[1024]; + char name_rom[1024]; + char name_rom_v4ld[1024]; FILE *pFileIn; int filesize, romsize, nbits_addr, nbits_data; @@ -105,7 +361,7 @@ int main(int argc, char *argv[]) if (argc < 2) { - fprintf(stderr, "Usage: romgen \n"); + fprintf(stderr, "Usage: ramgen \n"); return 1; } @@ -115,8 +371,12 @@ int main(int argc, char *argv[]) basename(pFilenameIn, name_prj); + sprintf(name_rom, "%s.vhd", name_prj); + sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); sprintf(name_rom_tcl, "%s.tcl", name_prj); + SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); +// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); diff --git a/lib/CPUs/MIPS/tools/src/romgen.c b/lib/CPUs/MIPS/tools/src/romgen.c index 6d1ec5f..a59e705 100644 --- a/lib/CPUs/MIPS/tools/src/romgen.c +++ b/lib/CPUs/MIPS/tools/src/romgen.c @@ -4,7 +4,7 @@ #include #define ARCH_NAME "data" -#define ENT_NAME "icache" +#define ENT_NAME "rom" #define JTAG_ADDR_WIDTH 16 // --------------------------------------------------------------