diff --git a/lib/FIFO/ghdl/tb_reg_stage.gtkw b/lib/FIFO/ghdl/tb_reg_stage.gtkw new file mode 100644 index 0000000..e69de29 diff --git a/lib/FIFO/ghdl/tb_reg_stage.make b/lib/FIFO/ghdl/tb_reg_stage.make new file mode 100644 index 0000000..6e7b09f --- /dev/null +++ b/lib/FIFO/ghdl/tb_reg_stage.make @@ -0,0 +1,12 @@ +include $(VHDL_HOME)/make/defs.mk + +SRCS += $(LIB_PATH)/FIFO/src/reg_stage.vhd +SRCS += $(LIB_PATH)/FIFO/src/tb_reg_stage.vhd + +# Compile +TARGET := tb_reg_stage +ENTITY := tb_reg_stage +RUN_TIME := 1us + +include $(VHDL_HOME)/make/ghdl.mk + diff --git a/lib/FIFO/src/reg_stage.vhd b/lib/FIFO/src/reg_stage.vhd new file mode 100644 index 0000000..b2b5574 --- /dev/null +++ b/lib/FIFO/src/reg_stage.vhd @@ -0,0 +1,82 @@ +------------------------------------------------------------------------- +-- Project: FIFO, generic FIFOs written in VHDL +-- Release 1 +-- +-- Copyright (C) 2007 J. Ahrensfeld +-- +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. +-- +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. +-- +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +----------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +entity reg_stage is + Generic + ( + num_regs : natural := 1; + data_width : natural := 8 + ); + Port + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + we : in STD_LOGIC; + re : in STD_LOGIC; + full : out STD_LOGIC; + dvld_r : out STD_LOGIC; + data_w : in unsigned (data_width-1 downto 0); + data_r : out unsigned (data_width-1 downto 0) + ); +end reg_stage; + +architecture Behavioral of reg_stage is + + signal dvld : std_logic; + signal d : std_logic; + +begin + + full <= dvld and not re; + dvld_r <= dvld; + d <= we or (dvld and not re); + +proc_dvld_reg: + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + dvld <= '0'; + else + dvld <= d; + end if; + end if; + end process; + +proc_data_reg: + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + data_r <= data_w; + end if; + end if; + end process; + +end Behavioral; + diff --git a/lib/FIFO/src/tb_reg_stage.vhd b/lib/FIFO/src/tb_reg_stage.vhd new file mode 100644 index 0000000..04fba84 --- /dev/null +++ b/lib/FIFO/src/tb_reg_stage.vhd @@ -0,0 +1,198 @@ +------------------------------------------------------------------------- +-- Project: FIFO, generic FIFOs written in VHDL +-- Release 1 +-- +-- Copyright (C) 2007 J. Ahrensfeld +-- +-- This library is free software; you can redistribute it and/or +-- modify it under the terms of the GNU Lesser General Public +-- License as published by the Free Software Foundation; either +-- version 2.1 of the License, or (at your option) any later version. +-- +-- This library is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +-- Lesser General Public License for more details. +-- +-- You should have received a copy of the GNU Lesser General Public +-- License along with this library; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +-- +-- For questions and ideas, please contact the author at jens@jayfield.org +-- +----------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE STD.TEXTIO.ALL; + +-- LIBRARY WORK; +-- USE.YOURLIB.WHATELSE + +ENTITY tb_reg_stage IS +END tb_reg_stage; + +ARCHITECTURE behavior OF tb_reg_stage IS + + --Constants + constant PERIOD : time := 10 ns; + constant ADDR_WIDTH : integer := 3; + constant DATA_WIDTH : integer := 8; + + --Inputs + signal rst : STD_LOGIC := '1'; + signal clk : STD_LOGIC := '0'; + signal we : STD_LOGIC := '0'; + signal re : STD_LOGIC := '0'; + signal din : unsigned (7 downto 0); + --Outputs + + signal dout : unsigned (7 downto 0); + signal full : STD_LOGIC; + signal dvld_r : STD_LOGIC; + + signal write_en : STD_LOGIC := '0'; + signal read_en : STD_LOGIC := '0'; + + signal ref_r : unsigned (7 downto 0) := (others => '0'); + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: entity work.reg_stage + GENERIC MAP + ( + data_width => DATA_WIDTH + ) + PORT MAP + ( + rst => rst, + clk => clk, + we => we, + re => re, + data_w => din, + data_r => dout, + full => full, + dvld_r => dvld_r + ); + + tb_clk : PROCESS + BEGIN + clk <= not clk; + wait for PERIOD/2; + END PROCESS; + + tb_write : PROCESS + BEGIN + + -- Wait 100 ns for global reset to finish + wait for 5*PERIOD; + rst <= '0'; + wait for 7*PERIOD; + write_en <= '1'; + wait for 25*PERIOD; + write_en <= '0'; + wait for 7*PERIOD; + write_en <= '1'; + wait for 25*PERIOD; + write_en <= '0'; + wait for 7*PERIOD; + write_en <= '1'; + wait for 1*PERIOD; + write_en <= '0'; + wait for 1*PERIOD; + write_en <= '1'; + wait for 1*PERIOD; + write_en <= '0'; + wait for 3*PERIOD; + write_en <= '1'; + wait for 4*PERIOD; + write_en <= '0'; + wait for 17*PERIOD; + write_en <= '1'; + wait for 25*PERIOD; + write_en <= '0'; + + wait; + + END PROCESS; + + tb_read : PROCESS + BEGIN + + -- Wait 100 ns for global reset to finish + wait for 25*PERIOD; + read_en <= '1'; + wait for 25*PERIOD; + read_en <= '0'; + wait for 25*PERIOD; + read_en <= '1'; + wait for 1*PERIOD; + read_en <= '0'; + wait for 5*PERIOD; + read_en <= '1'; + wait for 1*PERIOD; + read_en <= '0'; + wait for 5*PERIOD; + read_en <= '1'; + wait for 1*PERIOD; + read_en <= '0'; + wait for 5*PERIOD; + read_en <= '1'; + wait for 1*PERIOD; + read_en <= '0'; + wait for 5*PERIOD; + read_en <= '1'; + wait for 1*PERIOD; + read_en <= '0'; + wait for 5*PERIOD; + read_en <= '1'; + wait for 1*PERIOD; + read_en <= '0'; + wait for 5*PERIOD; + read_en <= '1'; + wait for 1*PERIOD; + read_en <= '0'; + wait for 7*PERIOD; + read_en <= '1'; + wait for 20*PERIOD; + read_en <= '0'; + + wait; + + END PROCESS; + + we <= write_en and not full; + + tb_w : PROCESS(rst, clk) + BEGIN + + if rst = '1' then + din <= (others => '0'); + elsif rising_edge(clk) then + if we = '1' then + din <= din + 1; + end if; + end if; + + END PROCESS; + + re <= read_en and dvld_r; + + tb_r : PROCESS(rst, clk) + BEGIN + + if rst = '1' then + ref_r <= (others => '0'); + elsif rising_edge(clk) then + if re = '1' then + assert ref_r = dout report "FIFO read error!" severity failure; + ref_r <= ref_r + 1; + end if; + end if; + + END PROCESS; + +END behavior;