diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb16.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb16.vhd
index 6b02c49..ee5bd62 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb16.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb16.vhd
@@ -96,6 +96,8 @@ architecture struct of sdram_ctrl_frontend_wb16 is
 
 	signal write_fifo_data_avail	: std_logic;
 	signal read_fifo_rdy			: std_logic;
+	signal write_piso_data_dout		: unsigned(PART_DATA_WIDTH-1 downto 0);
+	signal write_piso_dm_dout		: unsigned(PART_DM_WIDTH-1 downto 0);
 	
 	alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
 	alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
@@ -175,7 +177,7 @@ begin
 		din			=> write_fifo_data_out,
 		dout_vld	=> open,
 		shift_en	=> phy_out.wr_data_re,
-		dout		=> phy_in.wr_data
+		dout		=> write_piso_data_dout
 		
 	);
 
@@ -195,7 +197,7 @@ begin
 		din			=> write_fifo_dm_out,
 		dout_vld	=> open,
 		shift_en	=> phy_out.wr_data_re,
-		dout		=> phy_in.wr_dm
+		dout		=> write_piso_dm_dout
 		
 	);
 
@@ -282,7 +284,7 @@ begin
 	cat_fifo_we			<= STB_I and rdy;
 	cmd_fifo_in			<= UCMD_WRITE when WE_I = '1' else UCMD_READ;
 	addr_fifo_in		<= "00" & ADDR_I(22 downto 1);
-	tag_fifo_in			<= "000" & ADDR_I(2);
+	tag_fifo_in			<= "000" & ADDR_I(0);
 	
 	cat_fifo_re			<= u_cmd_we and (not u_busy);
 	u_cmd_we			<= (not cat_fifo_empty);
@@ -291,6 +293,9 @@ begin
 	u_tag_in			<= tag_fifo_out;
 --	phy_in.wr_dm		<= write_fifo_dm_out;
 --	phy_in.wr_data		<= write_fifo_data_out;
+	phy_in.wr_data		<= write_piso_data_dout when phy_out.tag_wr(0) = '0' else (write_piso_data_dout(PART_DATA_WIDTH/2-1 downto 0) & write_piso_data_dout(PART_DATA_WIDTH-1 downto PART_DATA_WIDTH/2));
+	phy_in.wr_dm		<= write_piso_dm_dout when phy_out.tag_wr(0) = '0' else (write_piso_dm_dout(PART_DM_WIDTH/2-1 downto 0) & write_piso_dm_dout(PART_DM_WIDTH-1 downto PART_DM_WIDTH/2));
+
 --	write_fifo_re		<= phy_out.wr_data_re and (not write_fifo_empty);
 	read_fifo_re 		<= (not read_fifo_empty) and MRDY_I;
 --	read_fifo_we		<= phy_out.rd_data_we;