jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- removed half-cycle register for pc.branch_take

Browse Source 
- refactored

git-svn-id: http://moon:8086/svn/vhdl/trunk@1616 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-31 14:04:22 +00:00
parent 8af5e1a8a5
commit 1864b98e55
1 changed files with 72 additions and 79 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+72 -79
View File
@@ -146,13 +146,11 @@ architecture Behavioral of pipeline is
signal EX_stage : EX_t; signal EX_stage : EX_t;
signal MEM_stage : MEM_t; signal MEM_stage : MEM_t;
signal WB_stage : WB_t; signal WB_stage : WB_t;
signal clk_2, clk_1 : STD_LOGIC;
signal hdu : hdu_t; signal hdu : hdu_t;
signal sdu : sdu_t; signal sdu : sdu_t;
signal reg_a : word_t; signal reg_a : word_t;
signal reg_b : word_t; signal reg_b : word_t;
signal branch_ce : STD_LOGIC; signal branch_ce : STD_LOGIC;
signal cpu_run : STD_LOGIC;
signal alu_result : word_t; signal alu_result : word_t;
signal mul_result : word_t; signal mul_result : word_t;
signal mul_busy : STD_LOGIC; signal mul_busy : STD_LOGIC;
@@ -174,10 +172,6 @@ architecture Behavioral of pipeline is
-------------------------------------------------------------------------- --------------------------------------------------------------------------
begin begin
clk_1 <= clk;
clk_2 <= not clk;
cpu_run <= ce;
-- Stall Detection Unit --------------------------------------------------- -- Stall Detection Unit ---------------------------------------------------
sdu.ID_nop <= sdu.imem_dep or c0_ctrl_in.exc_pending or ID_stage.exc or EX_stage.exc or MEM_stage.exc; sdu.ID_nop <= sdu.imem_dep or c0_ctrl_in.exc_pending or ID_stage.exc or EX_stage.exc or MEM_stage.exc;
sdu.EX_nop <= sdu.mul_dep or ID_stage.nop or ID_stage.exc; sdu.EX_nop <= sdu.mul_dep or ID_stage.nop or ID_stage.exc;
@@ -194,7 +188,7 @@ begin
sdu.imem_dep <= not imem_rdy; sdu.imem_dep <= not imem_rdy;
sdu.dmem_dep <= not dmem_rdy and MEM_stage.ctrl.dmem_en; sdu.dmem_dep <= not dmem_rdy and MEM_stage.ctrl.dmem_en;
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
imem_en <= cpu_run and not (sdu.mul_dep or sdu.dmem_dep or c0_ctrl_in.exc_commit); imem_en <= ce and not (sdu.mul_dep or sdu.dmem_dep or c0_ctrl_in.exc_commit);
-------------------------------------------------------------------------- --------------------------------------------------------------------------
-- Coprocessor assignments -- Coprocessor assignments
@@ -239,9 +233,9 @@ inst_muldiv: muldiv
pipe_rst <= stage_rst(0); pipe_rst <= stage_rst(0);
proc_stage_reset: proc_stage_reset:
process(clk_1) process(clk)
begin begin
if rising_edge(clk_1) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
stage_rst <= (others => '1'); stage_rst <= (others => '1');
else else
@@ -250,45 +244,10 @@ proc_stage_reset:
end if; end if;
end process; end process;
proc_stage_pc:
process(pc)
begin
if pc.branch_take = '1' then
pc.curr <= pc.pc_branch;
else
pc.curr <= pc.nxt;
end if;
end process;
proc_stage_pc_branch:
process(clk_1)
begin
if rising_edge(clk_1) then
if sdu.ID_stall = '0' then
pc.pc_branch <= pc.curr + ID_stage.bimm18;
end if;
end if;
end process;
proc_stage_branch_ce:
process(clk_1)
begin
if rising_edge(clk_1) then
if pipe_rst = '1' then
branch_ce <= '1';
else
branch_ce <= c0_ctrl_in.exc_pending;
if sdu.ID_stall = '0' and c0_ctrl_in.exc_inject = '0' then
branch_ce <= '1';
end if;
end if;
end if;
end process;
proc_stage_pc_next: proc_stage_pc_next:
process(clk_1) process(clk)
begin begin
if rising_edge(clk_1) then if rising_edge(clk) then
if c0_ctrl_in.exc_inject = '1' then if c0_ctrl_in.exc_inject = '1' then
pc.nxt <= c0_ctrl_in.exc_vec; pc.nxt <= c0_ctrl_in.exc_vec;
elsif sdu.ID_stall = '0' then elsif sdu.ID_stall = '0' then
@@ -304,32 +263,66 @@ proc_stage_pc_next:
end if; end if;
end process; end process;
proc_stage_branch: proc_stage_branch_ce:
process(clk_2) process(clk)
begin begin
if rising_edge(clk_2) then if rising_edge(clk) then
if branch_ce = '1' then if pipe_rst = '1' then
pc.branch_take <= '0'; branch_ce <= '1';
if EX_stage.ctrl.branch = '1' then else
branch_ce <= c0_ctrl_in.exc_pending;
if sdu.ID_stall = '0' and c0_ctrl_in.exc_inject = '0' then
branch_ce <= '1';
end if;
end if;
end if;
end process;
case EX_stage.ctrl.bc_src is proc_stage_branch:
process(EX_stage, bcu_flags, branch_ce)
begin
if branch_ce = '1' then
pc.branch_take <= '0';
if EX_stage.ctrl.branch = '1' then
when bc_eq_ne => case EX_stage.ctrl.bc_src is
pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.eq;
when bc_lez_gtz => when bc_eq_ne =>
pc.branch_take <= EX_stage.ctrl.bc_not xor (bcu_flags.eq or bcu_flags.ltz); pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.eq;
when bc_ltz_gez => when bc_lez_gtz =>
pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.ltz; pc.branch_take <= EX_stage.ctrl.bc_not xor (bcu_flags.eq or bcu_flags.ltz);
when others => null; when bc_ltz_gez =>
end case; pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.ltz;
end if;
when others => null;
end case;
end if; end if;
end if; end if;
end process; end process;
proc_stage_pc_branch:
process(clk)
begin
if rising_edge(clk) then
if sdu.ID_stall = '0' then
pc.pc_branch <= pc.curr + ID_stage.bimm18;
end if;
end if;
end process;
proc_stage_pc:
process(pc)
begin
if pc.branch_take = '1' then
pc.curr <= pc.pc_branch;
else
pc.curr <= pc.nxt;
end if;
end process;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
-- ID stage -- ID stage
-------------------------------------------------------------------------- --------------------------------------------------------------------------
@@ -462,7 +455,7 @@ inst_reg_dual: reg_dual
) )
PORT MAP PORT MAP
( (
clk_w => clk_1, clk_w => clk,
we => WB_stage.wreg_we, we => WB_stage.wreg_we,
en => '1', en => '1',
wptr => WB_stage.reg_wptr, wptr => WB_stage.reg_wptr,
@@ -481,9 +474,9 @@ inst_reg_dual: reg_dual
EX_stage.result <= alu_result when EX_stage.ctrl.mul_access = '0' else mul_result; EX_stage.result <= alu_result when EX_stage.ctrl.mul_access = '0' else mul_result;
proc_stage_ID_EX_1: proc_stage_ID_EX_1:
process(clk_1) process(clk)
begin begin
if rising_edge(clk_1) then if rising_edge(clk) then
if stage_rst(1) = '1' then if stage_rst(1) = '1' then
EX_stage.nop <= '1'; EX_stage.nop <= '1';
EX_stage.op <= op_nop; EX_stage.op <= op_nop;
@@ -543,9 +536,9 @@ proc_stage_EX_alu_except:
vaddr <= ID_stage.reg_a + extract_simm32(ID_stage.IR); vaddr <= ID_stage.reg_a + extract_simm32(ID_stage.IR);
proc_stage_EX_mem_except: proc_stage_EX_mem_except:
process(clk_1) process(clk)
begin begin
if rising_edge(clk_1) then if rising_edge(clk) then
if pipe_rst = '1' then if pipe_rst = '1' then
dmem_en <= '0'; dmem_en <= '0';
elsif sdu.EX_stall = '0' then elsif sdu.EX_stall = '0' then
@@ -572,9 +565,9 @@ proc_stage_EX_mem_except:
end process; end process;
proc_stage_DMEM_ADDR: proc_stage_DMEM_ADDR:
process(clk_1) process(clk)
begin begin
if rising_edge(clk_1) then if rising_edge(clk) then
if sdu.EX_stall = '0' then if sdu.EX_stall = '0' then
if c0_ctrl_in.EB = '1' then if c0_ctrl_in.EB = '1' then
if ID_stage.ctrl.word2_en = '0' then if ID_stage.ctrl.word2_en = '0' then
@@ -632,9 +625,9 @@ proc_wptr_mux:
-------------------------------------------------------------------------- --------------------------------------------------------------------------
proc_stage_bcu_op: proc_stage_bcu_op:
process(clk_1) process(clk)
begin begin
if rising_edge(clk_1) then if rising_edge(clk) then
if sdu.EX_stall = '0' then if sdu.EX_stall = '0' then
bcu_op_a <= ID_stage.reg_a; bcu_op_a <= ID_stage.reg_a;
bcu_op_b <= ID_stage.reg_b; bcu_op_b <= ID_stage.reg_b;
@@ -645,11 +638,11 @@ proc_stage_bcu_op:
EX_stage.alu_op1 <= EX_stage.reg_a; EX_stage.alu_op1 <= EX_stage.reg_a;
alu_op2_mux: alu_op2_mux:
process(clk_1) process(clk)
variable data : word_t; variable data : word_t;
begin begin
if rising_edge(clk_1) then if rising_edge(clk) then
if sdu.EX_stall = '0' then if sdu.EX_stall = '0' then
data := ID_stage.reg_b; data := ID_stage.reg_b;
@@ -672,12 +665,12 @@ alu_op2_mux:
end process; end process;
shifter_sa_mux: shifter_sa_mux:
process(clk_1) process(clk)
variable data : shamt_t; variable data : shamt_t;
variable data_inv : shamt_t; variable data_inv : shamt_t;
begin begin
if rising_edge(clk_1) then if rising_edge(clk) then
if sdu.EX_stall = '0' then if sdu.EX_stall = '0' then
data := ID_stage.reg_a(4 downto 0); data := ID_stage.reg_a(4 downto 0);
case ID_stage.ctrl.shamt2_srcsel is case ID_stage.ctrl.shamt2_srcsel is
@@ -749,9 +742,9 @@ inst_bcu: bcu
-- MEM stage -- MEM stage
-------------------------------------------------------------------------- --------------------------------------------------------------------------
proc_stage_MEM_n: proc_stage_MEM_n:
process(clk_1) process(clk)
begin begin
if rising_edge(clk_1) then if rising_edge(clk) then
if stage_rst(2) = '1' then if stage_rst(2) = '1' then
MEM_stage.nop <= '1'; MEM_stage.nop <= '1';
MEM_stage.op <= op_nop; MEM_stage.op <= op_nop;
@@ -846,9 +839,9 @@ proc_stage_MEM_except:
-- WB stage -- WB stage
-------------------------------------------------------------------------- --------------------------------------------------------------------------
proc_stage_WB_p: proc_stage_WB_p:
process(clk_1) process(clk)
begin begin
if rising_edge(clk_1) then if rising_edge(clk) then
if stage_rst(3) = '1' then if stage_rst(3) = '1' then
WB_stage.nop <= '1'; WB_stage.nop <= '1';
WB_stage.op <= op_nop; WB_stage.op <= op_nop;