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- added separate SD-CLK generator

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git-svn-id: http://moon:8086/svn/vhdl/trunk@593 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-03 23:25:29 +00:00
parent a3904fef4c
commit 1843d4de60
2 changed files with 19 additions and 3 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
+9 -1
View File
@@ -36,10 +36,12 @@ architecture struct of tb_sdram_ctrl_frontend64_wb is
-- Number of user data words for simulation -- Number of user data words for simulation
constant CLK_PERIOD : time := 10 ns; constant CLK_PERIOD : time := 10 ns;
constant SDCLK_PERIOD : time := 8 ns;
constant BURST_LEN : natural := 2; constant BURST_LEN : natural := 2;
signal rst : std_logic := '1'; signal rst : std_logic := '1';
signal clk : std_logic := '1'; signal clk : std_logic := '1';
signal sdclk : std_logic := '1';
signal locked : std_logic; signal locked : std_logic;
signal error : std_logic; signal error : std_logic;
signal clk_out : std_logic; signal clk_out : std_logic;
@@ -128,7 +130,7 @@ inst_clockgen : entity work.clockgen
( (
-- Clocks and Reset -- Clocks and Reset
rst => rst, -- external async reset, low active rst => rst, -- external async reset, low active
clk_in => clk, -- system clock (e.g. 100MHz), from board clk_in => sdclk, -- system clock (e.g. 100MHz), from board
clk_fb_in => clk_fb, -- feedback clock clk_fb_in => clk_fb, -- feedback clock
clk0_0_out => CLK0_O, -- System clock #0, dcm#0 output 0° clk0_0_out => CLK0_O, -- System clock #0, dcm#0 output 0°
clk0_270_out => CLK270_O, -- System clock #0, dcm#0 output 270° clk0_270_out => CLK270_O, -- System clock #0, dcm#0 output 270°
@@ -228,6 +230,12 @@ CLK_GEN: process
clk <= not clk; clk <= not clk;
end process; end process;
SDCLK_GEN: process
begin
wait for SDCLK_PERIOD/2;
sdclk <= not sdclk;
end process;
read_register: read_register:
process(CLK_O) process(CLK_O)
begin begin
lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
+10 -2
View File
@@ -36,10 +36,12 @@ architecture struct of tb_sdram_ctrl_frontend_wb is
-- Number of user data words for simulation -- Number of user data words for simulation
constant CLK_PERIOD : time := 10 ns; constant CLK_PERIOD : time := 10 ns;
constant SDCLK_PERIOD : time := 8 ns;
constant BURST_LEN : natural := 2; constant BURST_LEN : natural := 2;
signal rst : std_logic := '1'; signal rst : std_logic := '1';
signal clk : std_logic := '1'; signal clk : std_logic := '1';
signal sdclk : std_logic := '1';
signal locked : std_logic; signal locked : std_logic;
signal error : std_logic; signal error : std_logic;
signal clk_out : std_logic; signal clk_out : std_logic;
@@ -125,7 +127,7 @@ inst_clockgen : entity work.clockgen
( (
-- Clocks and Reset -- Clocks and Reset
rst => rst, -- external async reset, low active rst => rst, -- external async reset, low active
clk_in => clk, -- system clock (e.g. 100MHz), from board clk_in => sdclk, -- system clock (e.g. 100MHz), from board
clk_fb_in => clk_fb, -- feedback clock clk_fb_in => clk_fb, -- feedback clock
clk0_0_out => CLK0_O, -- System clock #0, dcm#0 output 0° clk0_0_out => CLK0_O, -- System clock #0, dcm#0 output 0°
clk0_270_out => CLK270_O, -- System clock #0, dcm#0 output 270° clk0_270_out => CLK270_O, -- System clock #0, dcm#0 output 270°
@@ -145,7 +147,7 @@ inst_clockgen : entity work.clockgen
( (
BL => BURST_LEN, BL => BURST_LEN,
f_sysclk => 100E6, f_sysclk => 100E6,
fifo_depth => 3 fifo_depth => 5
) )
PORT MAP PORT MAP
( (
@@ -224,6 +226,12 @@ CLK_GEN: process
clk <= not clk; clk <= not clk;
end process; end process;
SDCLK_GEN: process
begin
wait for SDCLK_PERIOD/2;
sdclk <= not sdclk;
end process;
read_register: read_register:
process(CLK_O) process(CLK_O)
begin begin