diff --git a/lib/CPUs/MIPS/src/core/mips_cop.vhd b/lib/CPUs/MIPS/src/core/mips_cop.vhd
index c532865..e99025b 100644
--- a/lib/CPUs/MIPS/src/core/mips_cop.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_cop.vhd
@@ -78,7 +78,6 @@ architecture Behavioral of cop is
 	signal dcache_info		: unsigned(7 downto 0);
 	
 	type cop_pipe_t is record
-		din			: word_t;
 		rs			: reg_ptr_t;
 		rd			: reg_ptr_t;
 		func		: func_t;
@@ -109,7 +108,6 @@ begin
 
 	icache_info 					<= "00" & to_unsigned(lg2(icache_line), 3) & to_unsigned(lg2(icache_size)-8, 3);
 	dcache_info 					<= "00" & to_unsigned(lg2(dcache_line), 3) & to_unsigned(lg2(dcache_size)-8, 3);
-	cop_pipe_ID.din					<= din;
 	cop_pipe_ID.cs					<= ir_en;
 	cop_pipe_ID.rs					<= extract_rs(ir);
 	cop_pipe_ID.rd					<= extract_rd(ir);
@@ -287,7 +285,7 @@ cop_ip_reg_write:
 			if rst = '1' then
 				ip(1 downto 0) <= (others => '0');
 			elsif ip_reg_we = '1' then
-				ip(1 downto 0) <= cop_pipe_EX.din(9 downto 8) and im(1 downto 0);
+				ip(1 downto 0) <= din(9 downto 8) and im(1 downto 0);
 			end if;	
 			ip(7 downto 2)	<= ctrl_in.events.Int and im(7 downto 2);
 		end if;
@@ -391,7 +389,7 @@ cop_test_reg_write:
 				test_reg	<= (others => '0');
 			else --if ce = '1' then
 				if test_reg_we = '1' then
-					test_reg	<= cop_pipe_EX.din;
+					test_reg	<= din;
 				end if;
 			end if;
 		end if;
@@ -412,7 +410,7 @@ cop_status_reg_write:
 					status(1 downto 0)	<= status(3 downto 2);
 					status(3 downto 2)	<= status(5 downto 4);
 				elsif stat_reg_we = '1' then
-					status				<= cop_pipe_EX.din;
+					status				<= din;
 				end if;
 			end if;
 		end if;