- refactored

git-svn-id: http://moon:8086/svn/vhdl/trunk@1522 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
2021-03-24 16:42:05 +00:00
parent 89ab6cb56c
commit 1787a89840
9 changed files with 0 additions and 78 deletions
-78
View File
@@ -1,78 +0,0 @@
entity *\(.*\) *is
inst_\1 : work.\1
Generic
GENERIC MAP
Port
PORT MAP
entity busmaster_32_sync is
GENERIC MAP
(
FIFO_DEPTH : natural := 4
);
Port
(
clk : in std_logic;
rst : in std_logic;
cmd_cycle_finished : out std_logic;
cmd_cycle_en : in std_logic;
cmd_rdy : out std_logic;
cmd_we : in std_logic;
cmd_in : in bm_cmd_32_t;
dout : out unsigned(31 downto 0);
dout_vld : out std_logic;
dout_re : in std_logic;
-- J-BUS signals
ACK_I : in std_logic;
SRDY_I : in std_logic;
MDAT_I : in unsigned(31 downto 0);
MDAT_O : out unsigned(31 downto 0);
ADDR_O : out unsigned(31 downto 0);
SEL_O : out unsigned(3 downto 0);
WE_O : out std_logic;
CYC_O : out std_logic;
STB_O : out std_logic;
MRDY_O : out std_logic
);
end busmaster_32_sync;
inst_uut : entity work.busmaster_32_sync
GENERIC MAP
(
FIFO_DEPTH => 4
)
PORT MAP
(
-- System signals
rst => RST_O,
clk => CLK_O,
cmd_cycle_finished => cmd_cycle_finished,
cmd_cycle_en => cmd_cycle_en,
cmd_rdy => cmd_rdy,
cmd_we => cmd_we,
cmd_in => cmd_in,
dout => dout,
dout_vld => dout_vld,
dout_re => dout_re,
-- JBUS Master signals
CYC_O => CYC_O,
STB_O => STB_O,
WE_O => WE_O,
SEL_O => SEL_O,
ACK_I => ACK_I,
SRDY_I => SRDY_I,
MRDY_O => MRDY_O,
ADDR_O => ADDR_O,
MDAT_I => MDAT_I,
MDAT_O => MDAT_O
);