jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- Prepared with FIFO for decimating FIR

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@219 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-10 19:22:15 +00:00
parent 937e129a55
commit 170a65237b
3 changed files with 140 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/radio/ddc/src/ddc.vhd
+120 -5
View File
@@ -170,8 +170,25 @@ ARCHITECTURE behavior OF ddc IS
SIGNAL cfir_vld_q : std_logic;
SIGNAL cfir_ready_i : std_logic;
SIGNAL cfir_ready_q : std_logic;
SIGNAL cfir_start_i : std_logic;
SIGNAL cfir_start_q : std_logic;
SIGNAL cfir_din_vld_i : std_logic;
SIGNAL cfir_din_vld_q : std_logic;
SIGNAL cfir_din_i : sfixed(shi(cfir_nbits_in, cfir_nbits_in_frac) downto slo(cfir_nbits_in, cfir_nbits_in_frac));
SIGNAL cfir_din_q : sfixed(shi(cfir_nbits_in, cfir_nbits_in_frac) downto slo(cfir_nbits_in, cfir_nbits_in_frac));
SIGNAL cfir_write_i : std_logic;
SIGNAL cfir_write_q : std_logic;
SIGNAL fifo_empty_i : std_logic;
SIGNAL fifo_empty_q : std_logic;
SIGNAL fifo_full_i : std_logic;
SIGNAL fifo_full_q : std_logic;
SIGNAL fifo_din_i : unsigned(cfir_nbits_in-1 downto 0);
SIGNAL fifo_din_q : unsigned(cfir_nbits_in-1 downto 0);
SIGNAL fifo_dout_i : unsigned(cfir_nbits_in-1 downto 0);
SIGNAL fifo_dout_q : unsigned(cfir_nbits_in-1 downto 0);
constant cfir_coef : real_array_t(0 to cfir_ntaps-1) := FilterCoef_Lowpass(cfir_ntaps, 0.1, 1.0);
constant cfir_coef : real_array_t(0 to cfir_ntaps-1) := FilterCoef_Lowpass(cfir_ntaps, 0.40, 1.0);
type h_mem_t is array (0 to cfir_ntaps-1) of sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac));
@@ -208,6 +225,8 @@ BEGIN
dout_i <= resize(cfir_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
dout_q <= resize(cfir_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
-- cfir_start <= dec_dout_vld_i and dec_dout_vld_q;
-- Instantiate the Unit Under Test (UUT)
inst_mixer: mix
GENERIC MAP
@@ -297,9 +316,10 @@ BEGIN
h_addr => cfir_h_addr,
h_we => cfir_h_we,
h_in => cfir_h_data,
din_vld => dec_dout_vld_i,
din => dec_dout_i,
din_vld => cfir_din_vld_i,
din => cfir_din_i,
dout_vld => cfir_vld_i,
start => cfir_start_i,
rdy => cfir_ready_i,
dout => cfir_dout_i
);
@@ -324,13 +344,108 @@ BEGIN
h_addr => cfir_h_addr,
h_we => cfir_h_we,
h_in => cfir_h_data,
din_vld => dec_dout_vld_q,
din => dec_dout_q,
din_vld => cfir_din_vld_q,
din => cfir_din_q,
dout_vld => cfir_vld_q,
start => cfir_start_q,
rdy => cfir_ready_q,
dout => cfir_dout_q
);
-- cfir_din_vld_i <= not fifo_empty_i and cfir_ready_i and cfir_write_i;
-- cfir_start_i <= fifo_empty_i and cfir_write_i;
-- fifo_din_i <= to_unsigned(ufixed(dec_dout_i));
-- cfir_din_i <= sfixed(fifo_dout_i);
cfir_din_vld_i <= dec_dout_vld_i;
cfir_start_i <= dec_dout_vld_i;
cfir_din_i <= dec_dout_i;
inst_fifo_sync_i : entity work.fifo_sync
GENERIC MAP
(
addr_width => 1,
data_width => cfir_nbits_in,
almost_full_thresh => 1,
almost_empty_thresh => 1
)
PORT MAP
(
rst => rst,
clk => clk,
we => dec_dout_vld_i,
re => cfir_write_i,
fifo_full => fifo_full_i,
fifo_empty => fifo_empty_i,
fifo_afull => open,
fifo_aempty => open,
data_w => fifo_din_i,
data_r => fifo_dout_i
);
-- cfir_din_vld_q <= not fifo_empty_q and cfir_ready_q and cfir_write_q;
-- cfir_start_q <= fifo_empty_q and cfir_write_q;
-- fifo_din_q <= to_unsigned(ufixed(dec_dout_q));
-- cfir_din_q <= sfixed(fifo_dout_q);
cfir_din_vld_q <= dec_dout_vld_q;
cfir_start_q <= dec_dout_vld_q;
cfir_din_q <= dec_dout_q;
inst_fifo_sync_q : entity work.fifo_sync
GENERIC MAP
(
addr_width => 1,
data_width => cfir_nbits_in,
almost_full_thresh => 1,
almost_empty_thresh => 1
)
PORT MAP
(
rst => rst,
clk => clk,
we => dec_dout_vld_q,
re => cfir_write_q,
fifo_full => fifo_full_q,
fifo_empty => fifo_empty_q,
fifo_afull => open,
fifo_aempty => open,
data_w => fifo_din_q,
data_r => fifo_dout_q
);
cfir_write_logic_i:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
cfir_write_i <= '0';
elsif fifo_full_i = '1' then
cfir_write_i <= '1';
elsif fifo_empty_i = '1' then
cfir_write_i <= '0';
end if;
end if;
end process;
cfir_write_logic_q:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
cfir_write_q <= '0';
elsif fifo_full_q = '1' then
cfir_write_q <= '1';
elsif fifo_empty_q = '1' then
cfir_write_q <= '0';
end if;
end if;
end process;
coef_load_counter:
process(clk)
variable count : natural range 0 to NextPowerOfTwo(cfir_ntaps)-1;