From 165500c7398416ab02474fae48f866665c712d96 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 3 Apr 2021 09:03:19 +0000 Subject: [PATCH] - use single rst signal git-svn-id: http://moon:8086/svn/vhdl/trunk@1623 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/mips_pipeline.vhd | 24 ++++-------------------- 1 file changed, 4 insertions(+), 20 deletions(-) diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd index 92d2860..9935fbe 100644 --- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd +++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd @@ -164,8 +164,6 @@ architecture Behavioral of pipeline is signal bcu_flags : bcu_flags_t; signal vaddr : word_t; signal dmem_src : word_t; - signal stage_rst : unsigned(3 downto 0); - signal pipe_rst : STD_LOGIC; signal pc : pc_t; signal pc_branch : word_t; @@ -254,20 +252,6 @@ inst_muldiv: muldiv -------------------------------------------------------------------------- imem_addr <= pc.curr; - pipe_rst <= stage_rst(0); - -proc_stage_reset: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - stage_rst <= (others => '1'); - else - stage_rst <= stage_rst(stage_rst'left-1 downto 0) & '0'; - end if; - end if; - end process; - proc_stage_pc_next: process(clk) begin @@ -500,7 +484,7 @@ proc_stage_ID_EX_1: process(clk) begin if rising_edge(clk) then - if stage_rst(1) = '1' then + if rst = '1' then EX_stage.nop <= '1'; EX_stage.op <= op_nop; EX_stage.IR <= (others => '0'); @@ -562,7 +546,7 @@ proc_stage_EX_mem_except: process(clk) begin if rising_edge(clk) then - if pipe_rst = '1' then + if rst = '1' then dmem_en <= '0'; elsif sdu.EX_stall = '0' then EX_events_mem <= events_clr; @@ -768,7 +752,7 @@ proc_stage_MEM_n: process(clk) begin if rising_edge(clk) then - if stage_rst(2) = '1' then + if rst = '1' then MEM_stage.nop <= '1'; MEM_stage.op <= op_nop; MEM_stage.va <= (others => '0'); @@ -865,7 +849,7 @@ proc_stage_WB_p: process(clk) begin if rising_edge(clk) then - if stage_rst(3) = '1' then + if rst = '1' then WB_stage.nop <= '1'; WB_stage.op <= op_nop; WB_stage.wreg_we <= '1';