From 14ff542f7ac0ed584f28dfae850c9b4a09889b01 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Mon, 29 Mar 2021 10:48:07 +0000 Subject: [PATCH] - fixed contention cg_draw git-svn-id: http://moon:8086/svn/vhdl/trunk@1568 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/vga_ctrl/src/vga_ctrl_top.vhd | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/projects/vga_ctrl/src/vga_ctrl_top.vhd b/projects/vga_ctrl/src/vga_ctrl_top.vhd index dea8174..24c1baf 100644 --- a/projects/vga_ctrl/src/vga_ctrl_top.vhd +++ b/projects/vga_ctrl/src/vga_ctrl_top.vhd @@ -97,8 +97,6 @@ architecture Behavioral of vga_ctrl_top is signal cg_csr_pos_x : natural range 0 to 80-1; signal cg_csr_pos_y : natural range 0 to 32-1; - signal vga_scan_rdy : std_logic; - -- CPU signals signal cpu_rst : std_logic; signal cpu_ce : std_logic; @@ -171,7 +169,6 @@ inst_vga_backend : entity work.vga_backend color_in(0) <= cpu_color; color_in(1) <= cg_color; --(X"FF", X"FF", X"FF", X"FF"); -- white opaque color_op <= op_over; - vga_scan_rdy <= stat_hready and stat_vready; inst_char_gen : entity work.char_gen GENERIC MAP @@ -239,10 +236,9 @@ inst_vga_backend : entity work.vga_backend rst <= sys_rst_in; clk <= sys_clk_in; - scan_rdy <= stat_vga_rdy; + scan_rdy <= stat_hready and stat_vready; cg_en <= stat_scan; - cg_draw <= stat_scan; cpu_ce <= '1'; --------------------------------------------------------------------------------------------- @@ -343,7 +339,7 @@ cpu_reg_write: if rst = '1' then cpu_rst <= '1'; else - cpu_rst <= not scan_rdy; + cpu_rst <= not stat_vga_rdy; end if; end if; end process;