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Bug fix: Uncached read and buffer write in different state

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git-svn-id: http://moon:8086/svn/vhdl/trunk@48 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-11 20:14:54 +00:00
parent de6bd8f29c
commit 14489d80e9
1 changed files with 31 additions and 23 deletions
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lib/CPUs/MIPS/src/core/mips_bui.vhd
+31 -23
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@@ -112,7 +112,7 @@ architecture behavior of bui is
);
END COMPONENT;
type bus_state_t is (init, ready, i_cache_bus_access, d_cache_bus_access, uncached_bus_read);
type bus_state_t is (init, ready, icache_bus_access, dcache_bus_access, write_bus, read_bus, read_finish);
signal s, sn : bus_state_t;
signal bus_idle : std_logic;
@@ -400,35 +400,43 @@ bus_state:
when ready =>
bus_idle <= '1';
if CYC_O_dmem_wr = '1' then
dmem_mem_wr_gnt <= '1';
sn <= write_bus;
elsif CYC_O_dmem_rd = '1' then
sn <= read_bus;
elsif CYC_O_icache = '1' then
sn <= icache_bus_access;
elsif CYC_O_dcache = '1' then
sn <= dcache_bus_access;
end if;
when icache_bus_access =>
icache_mem_gnt <= '1';
if CYC_O_icache = '0' then
sn <= ready;
end if;
when dcache_bus_access =>
dcache_mem_gnt <= '1';
if CYC_O_dcache = '0' then
sn <= ready;
end if;
when write_bus =>
dmem_mem_wr_gnt <= '1';
if CYC_O_dmem_wr = '1' then
if bout_rdy = '1' then
STB_O_dmem_wr <= '1';
end if;
elsif CYC_O_dmem_rd = '1' then
dmem_mem_rd_gnt <= '1';
if bout_rdy = '1' then
STB_O_dmem_rd <= '1';
sn <= uncached_bus_read;
end if;
elsif CYC_O_icache = '1' then
sn <= i_cache_bus_access;
elsif CYC_O_dcache = '1' then
sn <= d_cache_bus_access;
end if;
when i_cache_bus_access =>
icache_mem_gnt <= '1';
if CYC_O_icache = '0' then
sn <= ready;
else
sn <= ready;
end if;
when d_cache_bus_access =>
dcache_mem_gnt <= '1';
if CYC_O_dcache = '0' then
sn <= ready;
when read_bus =>
dmem_mem_rd_gnt <= '1';
if bout_rdy = '1' then
STB_O_dmem_rd <= '1';
sn <= read_finish;
end if;
when uncached_bus_read =>
when read_finish =>
dmem_mem_rd_gnt <= '1';
if ACK_I = '1' then
sn <= ready;
sn <= ready;
end if;
when others =>
sn <= ready;