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git-svn-id: http://moon:8086/svn/vhdl/trunk@1131 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-20 22:31:20 +00:00
parent 4b9cba542b
commit 1423984428
4 changed files with 96 additions and 7403 deletions
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projects/mips_sys/ise101/mips_sys/mips_sys.par
+96 -94
View File
@@ -1,7 +1,7 @@
Release 10.1.03 par K.39 (lin64)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
callisto:: Wed May 20 23:17:06 2015
callisto:: Thu May 21 00:25:05 2015
par -w -intstyle xflow -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd
mips_sys.pcf
@@ -10,24 +10,11 @@ mips_sys.pcf
Constraints file: mips_sys.pcf.
Loading device for application Rf_Device from file '4vsx35.nph' in environment /home/jens/Xilinx/10.1/ISE.
"mips_sys" is an NCD, version 3.2, device xc4vsx35, package ff668, speed -10
This design is using the default stepping level (major silicon revision) for this device (1). Unless your design is
targeted at devices of this stepping level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any available performance and functional
enhancements for this device. The latest stepping level for this device is '2'. Additional information on "stepping
level" is available at support.xilinx.com.
The STEPPING level for this design is ES.
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
balance between the fastest runtime and best performance, set the effort level to "med".
WARNING:Timing:3262 - Feedback on DCM or PLL inst_clockgen/inst_DCM_SDRCLK_0 forms an incomplete loop. The Tdcmino
calculation will be invalid. If the DCM or PLL uses external feedback, please apply the FEEDBACK constraint to
indicate the external board delay. Consult the Constraints Guide for further information on how to apply the FEEDBACK
constraint.
Device speed data version: "PRODUCTION 1.68 2008-07-25".
@@ -39,51 +26,61 @@ Device Utilization Summary:
Number of BUFGs 14 out of 32 43%
Number of DCM_ADVs 4 out of 8 50%
Number of ILOGICs 93 out of 448 20%
Number of External IOBs 248 out of 448 55%
Number of LOCed IOBs 0 out of 248 0%
Number of External IOBs 255 out of 448 56%
Number of LOCed IOBs 255 out of 255 100%
Number of OLOGICs 192 out of 448 42%
Number of RAMB16s 74 out of 192 38%
Number of Slices 7737 out of 15360 50%
Number of SLICEMs 660 out of 7680 8%
Number of Slices 7873 out of 15360 51%
Number of SLICEMs 668 out of 7680 8%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 10 secs
Finished initial Timing Analysis. REAL time: 10 secs
WARNING:Par:288 - The signal sys_phy_col_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal sys_phy_crs_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal sys_phy_int_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1: 60308 unrouted; REAL time: 10 secs
Phase 1: 60615 unrouted; REAL time: 12 secs
Phase 2: 51172 unrouted; REAL time: 11 secs
Phase 2: 51231 unrouted; REAL time: 12 secs
Phase 3: 18782 unrouted; REAL time: 17 secs
Phase 3: 18749 unrouted; REAL time: 19 secs
Phase 4: 18782 unrouted; (446154) REAL time: 17 secs
Phase 4: 18749 unrouted; (1226606) REAL time: 19 secs
Phase 5: 19345 unrouted; (932) REAL time: 26 secs
Phase 5: 19881 unrouted; (22336) REAL time: 23 secs
Phase 6: 0 unrouted; (8225) REAL time: 48 secs
Phase 6: 19948 unrouted; (3477) REAL time: 24 secs
Phase 7: 0 unrouted; (17354) REAL time: 48 secs
Updating file: mips_sys.ncd with current fully routed design.
Phase 7: 0 unrouted; (96274) REAL time: 2 mins 53 secs
Phase 8: 0 unrouted; (17354) REAL time: 56 secs
Phase 8: 0 unrouted; (20056) REAL time: 3 mins 18 secs
Phase 9: 0 unrouted; (8655) REAL time: 1 mins 13 secs
Phase 9: 0 unrouted; (20056) REAL time: 3 mins 32 secs
Phase 10: 0 unrouted; (8655) REAL time: 1 mins 25 secs
Phase 10: 0 unrouted; (20056) REAL time: 3 mins 32 secs
Updating file: mips_sys.ncd with current fully routed design.
Phase 11: 0 unrouted; (3379) REAL time: 4 mins 19 secs
Phase 11: 0 unrouted; (8655) REAL time: 2 mins 40 secs
Phase 12: 0 unrouted; (3379) REAL time: 4 mins 25 secs
Phase 12: 0 unrouted; (4028) REAL time: 3 mins 32 secs
Phase 13: 0 unrouted; (3379) REAL time: 4 mins 33 secs
Phase 13: 0 unrouted; (4028) REAL time: 3 mins 38 secs
Total REAL time to Router completion: 4 mins 33 secs
Total CPU time to Router completion: 4 mins 32 secs
Phase 14: 0 unrouted; (4028) REAL time: 3 mins 45 secs
Total REAL time to Router completion: 3 mins 49 secs
Total CPU time to Router completion: 3 mins 49 secs
Partition Implementation Status
-------------------------------
@@ -101,34 +98,34 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| CLK_O |BUFGCTRL_X0Y25| No | 2958 | 0.637 | 3.123 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_in_IBUFG |BUFGCTRL_X0Y27| No | 59 | 0.315 | 2.895 |
+---------------------+--------------+------+------+------------+-------------+
| cpu_clk |BUFGCTRL_X0Y22| No | 1778 | 0.512 | 2.999 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk270 |BUFGCTRL_X0Y16| No | 36 | 0.165 | 3.041 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk270var |BUFGCTRL_X0Y20| No | 32 | 0.040 | 3.041 |
+---------------------+--------------+------+------+------------+-------------+
|sys_phy_rx_clk_BUFGP | | | | | |
| |BUFGCTRL_X0Y24| No | 240 | 0.398 | 2.916 |
+---------------------+--------------+------+------+------------+-------------+
| vga_clk |BUFGCTRL_X0Y17| No | 184 | 0.448 | 3.000 |
+---------------------+--------------+------+------+------------+-------------+
|sys_ac97_bit_clk_IBU | | | | | |
| F |BUFGCTRL_X0Y10| No | 245 | 0.401 | 3.040 |
| F | BUFGCTRL_X0Y8| No | 258 | 0.412 | 3.885 |
+---------------------+--------------+------+------+------------+-------------+
|inst_rom_wb/inst_rom | | | | | |
| /bs_clk1 |BUFGCTRL_X0Y31| No | 73 | 0.292 | 2.948 |
| CLK_O | BUFGCTRL_X0Y2| No | 3156 | 0.591 | 3.980 |
+---------------------+--------------+------+------+------------+-------------+
|inst_rom_wb/inst_rom | | | | | |
| /bs_update1 |BUFGCTRL_X0Y30| No | 4 | 0.228 | 2.940 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk0 |BUFGCTRL_X0Y28| No | 231 | 0.508 | 2.994 |
| cpu_clk |BUFGCTRL_X0Y12| No | 1673 | 0.400 | 4.006 |
+---------------------+--------------+------+------+------------+-------------+
|sys_phy_tx_clk_BUFGP | | | | | |
| |BUFGCTRL_X0Y18| No | 218 | 0.526 | 3.014 |
| |BUFGCTRL_X0Y31| No | 240 | 0.358 | 3.792 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk0 |BUFGCTRL_X0Y25| No | 237 | 0.394 | 3.948 |
+---------------------+--------------+------+------+------------+-------------+
|sys_phy_rx_clk_BUFGP | | | | | |
| |BUFGCTRL_X0Y27| No | 277 | 0.256 | 3.849 |
+---------------------+--------------+------+------+------------+-------------+
| vga_clk | BUFGCTRL_X0Y9| No | 176 | 0.431 | 3.881 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_in_IBUFG |BUFGCTRL_X0Y10| No | 70 | 0.324 | 3.796 |
+---------------------+--------------+------+------+------------+-------------+
|inst_rom_wb/inst_rom | | | | | |
| /bs_clk1 |BUFGCTRL_X0Y17| No | 76 | 0.264 | 3.683 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk270 |BUFGCTRL_X0Y22| No | 67 | 0.158 | 3.932 |
+---------------------+--------------+------+------+------------+-------------+
| sdram_clk270var |BUFGCTRL_X0Y28| No | 32 | 0.025 | 3.930 |
+---------------------+--------------+------+------+------------+-------------+
|inst_rom_wb/inst_rom | | | | | |
| /bs_update1 |BUFGCTRL_X0Y19| No | 4 | 0.044 | 3.521 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
@@ -136,7 +133,20 @@ only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 0
Timing Score: 4028
WARNING:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in
your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and select
the "Timing Improvement Wizard" link for suggestions to correct each problem.
Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to
ensure the best options are set in the tools for timing closure.
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
requested value.
@@ -147,48 +157,37 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net CLK | SETUP | N/A| 9.905ns| N/A| 0
_O | HOLD | 0.396ns| | 0| 0
* TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | -0.584ns| 10.484ns| 20| 3603
ns HIGH 50% | HOLD | 0.336ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net sys | SETUP | N/A| 3.644ns| N/A| 0
_clk_in_IBUFG | HOLD | 0.496ns| | 0| 0
* TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | -0.130ns| 10.030ns| 6| 425
HIGH 50% | HOLD | 0.373ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net cpu | SETUP | N/A| 10.524ns| N/A| 0
_clk | HOLD | 0.337ns| | 0| 0
TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.062ns| 7.376ns| 0| 0
7.5 ns HIGH 50% | HOLD | 0.508ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net sys | SETUP | N/A| 6.548ns| N/A| 0
_phy_rx_clk_BUFGP | HOLD | 0.353ns| | 0| 0
TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.494ns| 7.506ns| 0| 0
s HIGH 50% | HOLD | 0.436ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net vga | SETUP | N/A| 8.243ns| N/A| 0
_clk | HOLD | 0.320ns| | 0| 0
TS_phy_tx_clk = PERIOD TIMEGRP "phy_tx_cl | SETUP | 1.474ns| 6.526ns| 0| 0
k" 8 ns HIGH 50% | HOLD | 0.329ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net sys | SETUP | N/A| 5.804ns| N/A| 0
_ac97_bit_clk_IBUF | HOLD | 0.483ns| | 0| 0
TS_phy_rx_clk = PERIOD TIMEGRP "phy_rx_cl | SETUP | 1.534ns| 6.466ns| 0| 0
k" 8 ns HIGH 50% | HOLD | 0.323ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net ins | SETUP | N/A| 1.935ns| N/A| 0
t_rom_wb/inst_rom/bs_clk1 | HOLD | 0.480ns| | 0| 0
NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 37.032ns| 8.893ns| 0| 0
ns HIGH 50% | HOLD | 0.521ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net sdr | SETUP | N/A| 8.766ns| N/A| 0
am_clk0 | HOLD | 0.503ns| | 0| 0
TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 75.276ns| 4.724ns| 0| 0
ns HIGH 50% | HOLD | 0.811ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net sys | SETUP | N/A| 4.574ns| N/A| 0
_phy_tx_clk_BUFGP | HOLD | 0.342ns| | 0| 0
PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.485ns| N/A| 0
------------------------------------------------------------------------------------------------------
PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 7.217ns| N/A| 0
------------------------------------------------------------------------------------------------------
Derived Constraint Report
Derived Constraints for CLK_O
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|CLK_O | 10.895ns| 9.905ns| N/A| 0| 0| 1632145| 0|
| inst_clockgen/sdr0_clk0 | 10.895ns| N/A| N/A| 0| 0| 0| 0|
| inst_clockgen/sdr0_clk270 | 10.895ns| N/A| N/A| 0| 0| 0| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
2 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
@@ -197,17 +196,20 @@ Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 5 mins 50 secs
Total CPU time to PAR completion: 5 mins 49 secs
WARNING:Par:283 - There are 3 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Peak Memory Usage: 898 MB
Total REAL time to PAR completion: 3 mins 55 secs
Total CPU time to PAR completion: 3 mins 55 secs
Peak Memory Usage: 870 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 26 errors found.
Number of error messages: 0
Number of warning messages: 1
Number of info messages: 2
Number of warning messages: 6
Number of info messages: 1
Writing design to file mips_sys.ncd
projects/mips_sys/ise101/mips_sys/mips_sys.syr
-5227
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File diff suppressed because it is too large Load Diff
projects/mips_sys/ise101/mips_sys/mips_sys.twr
-1177
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File diff suppressed because it is too large Load Diff
projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp
-905
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@@ -1,905 +0,0 @@
Release 10.1.03 Map K.39 (lin64)
Xilinx Mapping Report File for Design 'mips_sys'
Design Information
------------------
Command Line : map -intstyle xflow -p xc4vsx35-ff668-10 -timing -logic_opt on
-ol high -xe n -t 1 -register_duplication -global_opt on -retiming on
-equivalent_register_removal on -cm area -pr b -k 4 -power off -o
mips_sys_map.ncd mips_sys.ngd mips_sys.pcf
Target Device : xc4vsx35
Target Package : ff668
Target Speed : -10
Stepping Level : ES
Mapper Version : virtex4 -- $Revision: 1.46.12.2 $
Mapped Date : Wed May 20 23:49:58 2015
Design Summary
--------------
Number of errors : 2
Number of warnings : 74
Section 1 - Errors
------------------
ERROR:Place:539 - The design has objects that are constrained to a set of sites.
The number of objects constrained (3738) of type LUT is too large for the
number of available sites (that are not prohibited and not already taken by
other locked components) of this type in this set (3709) .
The following constraints are causing this issue:
COMPGRP "AG_inst_mips_top.SLICE" LOCATE = SITE "SLICE_X0Y53:SLICE_X39Y0"
LEVEL 4
Encountered an infeasibility when trying to place 7047 components to 8640
sites.
LUTM ( 3) Comps 611 Sites 2160 AvailEmptySites 2160. Reserved 611
sites for LUTM comps.
FFM ( 4) Comps 611 Sites 2160 AvailEmptySites 2160. Reserved 611
sites for FFM comps.
LUT ( 1) Comps 3738 Sites 4320 AvailEmptySites 3709. Reserved 3738
sites for LUT comps.
FF ( 2) Comps 2087 Sites 4320 AvailEmptySites 3709. Reserved 2087
sites for FF comps.
ERROR:Pack:1654 - The timing-driven packing phase encountered an error.
Section 2 - Warnings
--------------------
WARNING:LIT:421 - DIB0 should be connected if WRITE_WIDTH_B is set to 9 (RAMB16
symbol "inst_rom_wb/inst_rom/Mram_word_array3").
WARNING:LIT:243 - Logical network sys_phy_int_IBUF has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 176
more times for the following (max. 5 shown):
sys_phy_col_IBUF,
sys_phy_crs_IBUF,
sys_usb_d_15_IOBUF/N2,
sys_usb_d_15_IOBUF/N3,
sys_usb_d_14_IOBUF/N2
To see the details of these warning messages, please use the -detail switch.
WARNING:Pack:2549 - The register
"inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial" has the property
IOB=TRUE, but was not packed into the OLOGIC component. The output signal for
register symbol inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial requires
general routing.
WARNING:Pack:2549 - The register
"inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial" has the property
IOB=TRUE, but was not packed into the OLOGIC component. The output signal for
register symbol inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial requires
general routing.
WARNING:Pack:2548 - The register
"inst_emac_top_jb/inst_emac_rx/inst_sipo_8bit/shift_cnt_pipe_1" has the
property IOB=TRUE, but was not packed into the ILOGIC component. The ILOGIC
component already contains an IFF1.
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_1" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_703".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_2" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_701".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_3" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_699".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_4" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_697".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_5" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_695".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_6" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_693".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_7" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_691".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_8" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_689".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_9" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_687".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_10" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_685".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_11" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_683".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_12" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_681".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_13" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_679".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_21" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_663".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_14" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_677".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_22" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_661".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_23" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_659".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_15" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_675".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_31" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_643".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_24" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_657".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_16" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_673".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_32" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_641".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_25" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_655".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_17" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_671".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_18" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_669".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_26" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_653".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_19" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_667".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_27" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_651".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_20" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_665".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_28" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_649".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_29" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_647".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_30" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
match the ILOGIC SR signal "N0_645".
WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_data_tx" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "inst_ps2_wb_0/inst_ps2_core/data_tx2" does not match the
ILOGIC SR signal "inst_ps2_phy_0/Inst_debounce_data/output_and0000".
WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_data_tx_1" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "inst_ps2_wb_0/inst_ps2_core/data_tx2" does not match the
ILOGIC SR signal "inst_ps2_phy_0/Inst_debounce_data/output_and0000".
WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_data_tx" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "inst_ps2_wb_1/inst_ps2_core/data_tx2" does not match the
ILOGIC SR signal "inst_ps2_phy_1/Inst_debounce_data/output_and0000".
WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_data_tx_1" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "inst_ps2_wb_1/inst_ps2_core/data_tx2" does not match the
ILOGIC SR signal "inst_ps2_phy_1/Inst_debounce_data/output_and0000".
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_4" has
the property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_4
set/reset disagrees with another register in the OLOGIC component.
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_3" has
the property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_3
set/reset disagrees with another register in the OLOGIC component.
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_2" has
the property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_2
set/reset disagrees with another register in the OLOGIC component.
WARNING:Pack:2549 - The register
"inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_1" has
the property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_1
set/reset disagrees with another register in the OLOGIC component.
WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_30" has the
property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_gpio_wb/gpio_0_dir_reg_30 set/reset disagrees with another register in
the OLOGIC component.
WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_clk_tx" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "N27" does not match the ILOGIC SR signal
"inst_ps2_phy_0/Inst_debounce_clk/output_and0000".
The OLOGIC REV signal "inst_ps2_wb_0/inst_ps2_core/read_cs_FSM_FFd3" does not
match the ILOGIC REV signal
"inst_ps2_phy_0/Inst_debounce_clk/output_and0001".
WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_clk_tx_1" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "N27" does not match the ILOGIC SR signal
"inst_ps2_phy_0/Inst_debounce_clk/output_and0000".
The OLOGIC REV signal "inst_ps2_wb_0/inst_ps2_core/read_cs_FSM_FFd3" does not
match the ILOGIC REV signal
"inst_ps2_phy_0/Inst_debounce_clk/output_and0001".
WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_clk_tx" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "N23" does not match the ILOGIC SR signal
"inst_ps2_phy_1/Inst_debounce_clk/output_and0000".
The OLOGIC REV signal "inst_ps2_wb_1/inst_ps2_core/read_cs_FSM_FFd3" does not
match the ILOGIC REV signal
"inst_ps2_phy_1/Inst_debounce_clk/output_and0001".
WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_clk_tx_1" has
the property IOB=TRUE, but was not packed into the OLOGIC component. The
OLOGIC SR signal "N23" does not match the ILOGIC SR signal
"inst_ps2_phy_1/Inst_debounce_clk/output_and0000".
The OLOGIC REV signal "inst_ps2_wb_1/inst_ps2_core/read_cs_FSM_FFd3" does not
match the ILOGIC REV signal
"inst_ps2_phy_1/Inst_debounce_clk/output_and0001".
WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_0" has the
property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_gpio_wb/gpio_0_dir_reg_0 set/reset disagrees with another register in
the OLOGIC component.
WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_1" has the
property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_gpio_wb/gpio_0_dir_reg_1 set/reset disagrees with another register in
the OLOGIC component.
WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_2" has the
property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_gpio_wb/gpio_0_dir_reg_2 set/reset disagrees with another register in
the OLOGIC component.
WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_3" has the
property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_gpio_wb/gpio_0_dir_reg_3 set/reset disagrees with another register in
the OLOGIC component.
WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_4" has the
property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_gpio_wb/gpio_0_dir_reg_4 set/reset disagrees with another register in
the OLOGIC component.
WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_5" has the
property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_gpio_wb/gpio_0_dir_reg_5 set/reset disagrees with another register in
the OLOGIC component.
WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_6" has the
property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_gpio_wb/gpio_0_dir_reg_6 set/reset disagrees with another register in
the OLOGIC component.
WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_7" has the
property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_gpio_wb/gpio_0_dir_reg_7 set/reset disagrees with another register in
the OLOGIC component.
WARNING:Pack:2549 - The register "inst_gpio_wb/gpio_0_dir_reg_8" has the
property IOB=TRUE, but was not packed into the OLOGIC component. Register
inst_gpio_wb/gpio_0_dir_reg_8 set/reset disagrees with another register in
the OLOGIC component.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000131 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000026_f6/MUXF5.I1
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000112 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000011_f6/MUXF5.I0
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000151 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000024_f6/MUXF5.I1
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000016 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000016_f6/MUXF5.I1
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000071 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00007_f6/MUXF5.I0.
Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000091 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000030_f6/MUXF5.I1
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00004 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000035_f6/MUXF5.I0
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000051 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00005_f6/MUXF5.I0.
Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000012 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000012_f6/MUXF5.I1
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00006 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000033_f6/MUXF5.I0
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000014 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000025_f6/MUXF5.I0
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000031 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00003_f6/MUXF5.I0.
Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00008 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00008_f6/MUXF5.I1.
Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
WARNING:Pack:266 - The function generator
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000010 failed to
merge with F5 multiplexer
inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000010_f6/MUXF5.I1
. Tried to combine two collections of symbols from different layers. The
alignment requirements of the two layers conflict. The design will exhibit
suboptimal timing.
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:159 - Net Timing constraints on signal sys_ac97_bit_clk are pushed
forward through input buffer.
INFO:MapLib:797 - Your design is targeting LX/SX Production Step 0/1/ES devices.
Please note that there are new specifications for the DCMs to guarantee
maximum frequency performance. If the DCM input clock might stop or if the
DCM reset might be asserted for an extended time, then use of the dcm_standby
macro may be required. Please see Answer Record 21127.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
Section 4 - Removed Logic Summary
---------------------------------
174 block(s) removed
4 block(s) optimized away
174 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
The signal "sys_usb_d_15_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_15_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_14_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_14_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_13_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_13_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_12_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_12_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_11_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_11_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_10_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_10_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_9_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_9_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_8_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_8_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_7_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_7_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_6_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_6_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_5_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_5_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_4_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_4_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_3_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_3_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_2_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_2_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_1_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_1_IOBUF/N3" is sourceless and has been removed.
The signal "sys_usb_d_0_IOBUF/N2" is sourceless and has been removed.
The signal "sys_usb_d_0_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_31_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_31_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_30_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_30_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_29_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_29_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_28_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_28_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_27_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_27_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_26_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_26_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_25_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_25_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_24_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_24_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_23_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_23_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_22_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_22_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_21_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_21_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_20_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_20_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_19_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_19_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_18_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_18_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_17_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_17_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_16_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_16_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_15_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_15_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_14_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_14_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_13_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_13_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_12_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_12_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_11_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_11_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_10_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_10_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_9_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_9_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_8_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_8_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_7_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_7_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_6_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_6_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_5_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_5_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_4_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_4_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_3_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_3_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_2_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_2_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_1_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_1_IOBUF/N3" is sourceless and has been removed.
The signal "sys_flash_d_0_IOBUF/N2" is sourceless and has been removed.
The signal "sys_flash_d_0_IOBUF/N3" is sourceless and has been removed.
The signal "sys_phy_tx_clk_BUFGP/N2" is sourceless and has been removed.
The signal "sys_phy_tx_clk_BUFGP/N3" is sourceless and has been removed.
The signal "sys_phy_rx_clk_BUFGP/N2" is sourceless and has been removed.
The signal "sys_phy_rx_clk_BUFGP/N3" is sourceless and has been removed.
The signal "inst_ps2_phy_1/IOBUF_inst_ps2_data/N2" is sourceless and has been
removed.
The signal "inst_ps2_phy_1/IOBUF_inst_ps2_data/N3" is sourceless and has been
removed.
The signal "inst_ps2_phy_1/IOBUF_inst_ps2_clk/N2" is sourceless and has been
removed.
The signal "inst_ps2_phy_1/IOBUF_inst_ps2_clk/N3" is sourceless and has been
removed.
The signal "inst_ps2_phy_0/IOBUF_inst_ps2_data/N2" is sourceless and has been
removed.
The signal "inst_ps2_phy_0/IOBUF_inst_ps2_data/N3" is sourceless and has been
removed.
The signal "inst_ps2_phy_0/IOBUF_inst_ps2_clk/N2" is sourceless and has been
removed.
The signal "inst_ps2_phy_0/IOBUF_inst_ps2_clk/N3" is sourceless and has been
removed.
The signal "sys_phy_mdio_IOBUF/N2" is sourceless and has been removed.
The signal "sys_phy_mdio_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_31_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_31_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_30_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_30_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_29_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_29_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_28_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_28_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_27_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_27_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_26_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_26_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_25_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_25_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_24_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_24_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_23_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_23_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_22_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_22_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_21_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_21_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_20_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_20_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_19_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_19_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_18_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_18_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_17_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_17_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_16_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_16_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_15_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_15_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_14_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_14_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_13_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_13_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_12_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_12_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_11_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_11_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_10_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_10_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_9_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_9_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_8_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_8_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_7_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_7_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_6_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_6_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_5_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_5_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_4_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_4_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_3_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_3_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_2_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_2_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_1_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_1_IOBUF/N3" is sourceless and has been removed.
The signal "sys_sdr_data_0_IOBUF/N2" is sourceless and has been removed.
The signal "sys_sdr_data_0_IOBUF/N3" is sourceless and has been removed.
Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_clk/XST_GND" (ZERO) removed.
Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_clk/XST_VCC" (ONE) removed.
Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_data/XST_GND" (ZERO) removed.
Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_data/XST_VCC" (ONE) removed.
Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_clk/XST_GND" (ZERO) removed.
Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_clk/XST_VCC" (ONE) removed.
Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_data/XST_GND" (ZERO) removed.
Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_data/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_0_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_0_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_10_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_10_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_11_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_11_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_12_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_12_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_13_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_13_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_14_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_14_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_15_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_15_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_16_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_16_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_17_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_17_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_18_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_18_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_19_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_19_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_1_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_1_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_20_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_20_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_21_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_21_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_22_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_22_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_23_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_23_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_24_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_24_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_25_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_25_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_26_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_26_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_27_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_27_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_28_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_28_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_29_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_29_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_2_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_2_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_30_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_30_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_31_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_31_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_3_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_3_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_4_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_4_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_5_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_5_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_6_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_6_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_7_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_7_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_8_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_8_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_flash_d_9_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_flash_d_9_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_phy_mdio_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_phy_mdio_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_phy_rx_clk_BUFGP/XST_GND" (ZERO) removed.
Unused block "sys_phy_rx_clk_BUFGP/XST_VCC" (ONE) removed.
Unused block "sys_phy_tx_clk_BUFGP/XST_GND" (ZERO) removed.
Unused block "sys_phy_tx_clk_BUFGP/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_0_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_0_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_10_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_10_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_11_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_11_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_12_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_12_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_13_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_13_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_14_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_14_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_15_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_15_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_16_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_16_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_17_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_17_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_18_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_18_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_19_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_19_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_1_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_1_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_20_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_20_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_21_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_21_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_22_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_22_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_23_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_23_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_24_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_24_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_25_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_25_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_26_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_26_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_27_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_27_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_28_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_28_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_29_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_29_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_2_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_2_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_30_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_30_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_31_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_31_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_3_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_3_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_4_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_4_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_5_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_5_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_6_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_6_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_7_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_7_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_8_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_8_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_sdr_data_9_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_sdr_data_9_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_0_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_0_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_10_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_10_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_11_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_11_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_12_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_12_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_13_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_13_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_14_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_14_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_15_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_15_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_1_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_1_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_2_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_2_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_3_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_3_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_4_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_4_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_5_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_5_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_6_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_6_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_7_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_7_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_8_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_8_IOBUF/XST_VCC" (ONE) removed.
Unused block "sys_usb_d_9_IOBUF/XST_GND" (ZERO) removed.
Unused block "sys_usb_d_9_IOBUF/XST_VCC" (ONE) removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
GND inst_mips_top/XST_GND
VCC inst_mips_top/XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.