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- bugfix 'x_out' register

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git-svn-id: http://moon:8086/svn/vhdl/trunk@236 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-13 09:55:05 +00:00
parent ef9b538769
commit 1417d6f5cd
1 changed files with 10 additions and 9 deletions
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lib/filter/src/fir_stage_sys.vhd
+8 -7
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@@ -63,12 +63,11 @@ constant min_pipe_lat : integer := 4;
subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
type input_pipe_t is array (min_pipe_lat-2 downto 0) of in_t; type input_pipe_t is array (pipe_latency-2 downto 0) of in_t;
type coef_pipe_t is array (min_pipe_lat-2 downto 0) of in_t; type coef_pipe_t is array (pipe_latency-2 downto 0) of in_t;
signal yin : in_t;
signal yin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); signal prod : out_t;
signal prod : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
------------------------------------------------------------ ------------------------------------------------------------
begin begin
@@ -88,18 +87,20 @@ begin
h_pipe := h_pipe(h_pipe'left-1 downto 0) & resize(h_in, h_pipe(0)); h_pipe := h_pipe(h_pipe'left-1 downto 0) & resize(h_in, h_pipe(0));
prod <= resize(x_pipe(x_pipe'left) * h_pipe(h_pipe'left), prod, fixed_wrap, fixed_truncate); prod <= resize(x_pipe(x_pipe'left) * h_pipe(h_pipe'left), prod, fixed_wrap, fixed_truncate);
end if; end if;
x_out <= resize(x_pipe(x_pipe'left), shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac));
end if; end if;
end process; end process;
------------------------------------------------------------ ------------------------------------------------------------
proc_out_reg: process(clk) proc_out_reg: process(clk)
variable yout : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); variable yout : out_t;
variable xout : in_t;
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if ce = '1' then if ce = '1' then
yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate); yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate);
y_out <= yout; y_out <= yout;
xout := resize(x_in, xout, fixed_wrap, fixed_truncate);
x_out <= xout;
end if; end if;
end if; end if;
end process; end process;