jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[UART]

Browse Source 
- ctrl is input

git-svn-id: http://moon:8086/svn/vhdl/trunk@1241 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-27 15:59:43 +00:00
parent 6588eb752a
commit 13488ae71e
4 changed files with 7 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/uart/uart_jtag.vhd
+2 -2
View File
@@ -23,9 +23,9 @@ ENTITY uart IS
re : in STD_LOGIC; re : in STD_LOGIC;
din : in unsigned(7 downto 0); din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0); dout : out unsigned(7 downto 0);
ser_rx : in std_logic; ser_rx : in std_logic;
ser_tx : out std_logic; ser_tx : out std_logic;
ctrl : out ctrl_t; ctrl : in ctrl_t;
status : out status_t status : out status_t
); );
END uart; END uart;
lib/uart/uart_sim.vhd
+2 -1
View File
@@ -19,7 +19,7 @@ ENTITY uart IS
dout : out unsigned(7 downto 0); dout : out unsigned(7 downto 0);
ser_rx : in std_logic; ser_rx : in std_logic;
ser_tx : out std_logic; ser_tx : out std_logic;
ctrl : out ctrl_t; ctrl : in ctrl_t;
status : out status_t status : out status_t
); );
END uart; END uart;
@@ -35,6 +35,7 @@ status.rx_present <= '0';
ser_tx <= '1'; ser_tx <= '1';
status.tx_complete <= '1'; status.tx_complete <= '1';
status.tx_empty <= '1'; status.tx_empty <= '1';
status.tx_full <= '0';
proc_tx: proc_tx:
process(clk) process(clk)
lib/uart/uart_wb.vhd
+1 -1
View File
@@ -39,7 +39,7 @@ ARCHITECTURE rtl OF uart_wb IS
dout : out unsigned(7 downto 0); dout : out unsigned(7 downto 0);
ser_rx : in std_logic; ser_rx : in std_logic;
ser_tx : out std_logic; ser_tx : out std_logic;
ctrl : out ctrl_t; ctrl : in ctrl_t;
status : out status_t status : out status_t
); );
END COMPONENT; END COMPONENT;
lib/uart/uart_xil.vhd
+2 -2
View File
@@ -15,9 +15,9 @@ ENTITY uart IS
re : in STD_LOGIC; re : in STD_LOGIC;
din : in unsigned(7 downto 0); din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0); dout : out unsigned(7 downto 0);
ser_rx : in std_logic; ser_rx : in std_logic;
ser_tx : out std_logic; ser_tx : out std_logic;
ctrl : out ctrl_t; ctrl : in ctrl_t;
status : out status_t status : out status_t
); );
END uart; END uart;