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- added transmitter part with memory allocation

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git-svn-id: http://moon:8086/svn/vhdl/trunk@805 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-21 14:41:09 +00:00
parent 5f29361ee4
commit 10a5d17015
2 changed files with 785 additions and 95 deletions
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lib/emac/src/tb_emac_jb.vhd
+276 -21
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@@ -32,7 +32,7 @@ END tb_emac_jb;
ARCHITECTURE behavior OF tb_emac_jb IS
constant CLK_PERIOD : time := 10 ns;
constant MII_CLK_PERIOD : time := 40 ns;
constant MII_CLK_PERIOD : time := 8 ns;
signal CLK : std_logic := '1';
signal RST : std_logic := '1';
@@ -48,6 +48,7 @@ ARCHITECTURE behavior OF tb_emac_jb IS
signal ADDR_I : unsigned(31 downto 0) := (others => '-');
signal DAT_I : unsigned(31 downto 0) := (others => '-');
signal DAT_O : unsigned(31 downto 0) := (others => '-');
signal DAT_O_reg : unsigned(31 downto 0) := (others => '-');
-- MII signals
signal mii_rx_clk_board : std_logic := '1';
@@ -64,7 +65,29 @@ ARCHITECTURE behavior OF tb_emac_jb IS
signal mii_col : std_logic := '0';
signal mii_gtx_clk : std_logic;
signal shift_sa : integer := 0;
signal shift_din_vld : std_logic := '0';
signal shift_din : unsigned(31 downto 0) := (others => '-');
signal shift_dout_vld : std_logic;
signal shift_dout : unsigned(31 downto 0);
signal piso_din_vld : std_logic := '0';
signal piso_din_rdy : std_logic;
signal piso_din_be : unsigned(7 downto 0) := (others => '0');
signal piso_din : unsigned(31 downto 0) := (others => '-');
signal piso_dout_en : std_logic;
signal piso_dout : unsigned(3 downto 0);
signal sipo_enable : std_logic := '0';
signal sipo_din_en : std_logic := '0';
signal sipo_din : unsigned(3 downto 0) := (others => '-');
signal sipo_dout_vld : std_logic;
signal sipo_dout_be : unsigned(7 downto 0);
signal sipo_dout : unsigned(31 downto 0);
type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_read);
signal emac_action : emac_action_t;
BEGIN
inst_emac_jb : entity work.emac_jb
@@ -101,6 +124,67 @@ inst_emac_jb : entity work.emac_jb
);
inst_shifter : entity work.shifter
GENERIC MAP
(
data_width => 32,
aggregate_size => 4,
do_pipelined => true
)
PORT MAP
(
rst => RST,
clk => CLK,
sa => shift_sa,
din_vld => shift_din_vld,
din => shift_din,
dout_vld => shift_dout_vld,
dout => shift_dout
);
inst_piso : entity work.piso
GENERIC MAP
(
data_width_in => 32,
data_width_out => 4,
msb_first => true
)
PORT MAP
(
rst => RST,
clk => CLK,
din_vld => piso_din_vld,
din_rdy => piso_din_rdy,
din_be => piso_din_be,
din => piso_din,
dout_en => piso_dout_en,
dout => piso_dout
);
inst_sipo : entity work.sipo
GENERIC MAP
(
data_width_in => 4,
data_width_out => 32,
msb_first => true
)
PORT MAP
(
rst => RST,
clk => CLK,
enable => sipo_enable,
din_en => sipo_din_en,
din => sipo_din,
dout_be => sipo_dout_be,
dout_vld => sipo_dout_vld,
dout => sipo_dout
);
sipo_din <= piso_dout;
sipo_din_en <= piso_dout_en;
CLK_GEN: process
begin
wait for CLK_PERIOD/2;
@@ -110,48 +194,219 @@ CLK_GEN: process
MII_CLK_GEN: process
begin
wait for MII_CLK_PERIOD/2;
mii_rx_clk <= not mii_rx_clk after 3000 ps;
mii_tx_clk <= not mii_tx_clk after 3000 ps;
mii_rx_clk <= not mii_rx_clk;
mii_tx_clk <= not mii_tx_clk;
end process;
mii_rx_clk_board <= mii_rx_clk after 3000 ps;
mii_tx_clk_board <= mii_tx_clk after 3000 ps;
mii_rx_clk_board <= mii_rx_clk;
mii_tx_clk_board <= mii_tx_clk;
DAT_O_register:
process(CLK)
begin
if rising_edge(CLK) then
if ACK_O = '1' then
DAT_O_reg <= DAT_O;
end if;
end if;
end process;
-- Master
STIMULUS: process
procedure emac_alloc (size : natural) is
begin
wait for 6*CLK_PERIOD;
RST <= '0';
wait for 60*CLK_PERIOD;
-- FILL TX data
-- TX-ALLOCATION
-- set TX-size
emac_action <= emac_alloc;
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0000_0001";
ADDR_I <= X"0000_0008";
DAT_I <= to_unsigned(size, 16) & X"55AA";
STB_I <= '1';
WE_I <= '1';
for i in 0 to 240 loop
STB_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= DAT_I + 1;
end loop;
ADDR_I <= X"0000_0004";
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
-- Trigger TX
-- set alloc request
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"0000_0002";
DAT_I <= X"0001_0000";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= X"0000_0000";
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
WE_I <= '0';
-- check alloc busy
check_bsy:
while (true) loop
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '1';
ADDR_I <= X"0000_0000";
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
wait until rising_edge(CLK) and ACK_O = '1';
wait until rising_edge(CLK);
if DAT_O_reg(16) = '0' then
exit check_bsy;
end if;
end loop;
emac_action <= emac_idle;
end procedure emac_alloc;
procedure emac_write (size : natural) is
variable data : unsigned (7 downto 0);
variable num_words : natural;
begin
-- FILL TX data
emac_action <= emac_write;
if (size mod 4) = 0 then
num_words := size/4;
else
num_words := size/4 + 1;
end if;
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
data := X"00";
ADDR_I <= X"0000_0008";
WE_I <= '1';
for i in 1 to num_words loop
STB_I <= '1';
DAT_I(7 downto 0) <= data;
data := data + 1;
DAT_I(15 downto 8) <= data;
data := data + 1;
DAT_I(23 downto 16) <= data;
data := data + 1;
DAT_I(31 downto 24) <= data;
data := data + 1;
wait until rising_edge(CLK) and SRDY_O = '1';
end loop;
STB_I <= '0';
wait until rising_edge(CLK) and SRDY_O = '1';
emac_action <= emac_idle;
end procedure emac_write;
begin
wait for 6*MII_CLK_PERIOD;
RST <= '0';
wait for 60*CLK_PERIOD;
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (1536);
emac_write (1536);
emac_alloc (64);
emac_write (64);
emac_alloc (512);
emac_write (512);
emac_alloc (1536);
emac_write (1536);
emac_alloc (65);
emac_write (65);
emac_alloc (66);
emac_write (66);
emac_alloc (67);
emac_write (67);
emac_alloc (512);
emac_write (512);
wait for 4000*CLK_PERIOD;
wait until rising_edge(CLK);
shift_din <= X"12345678";
shift_sa <= 0;
shift_din_vld <= '1';
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa + 1;
wait until rising_edge(CLK);
shift_sa <= 0;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_sa <= shift_sa - 1;
wait until rising_edge(CLK);
shift_din_vld <= '0';
for i in 1 to 10 loop
wait until rising_edge(CLK);
sipo_enable <= '1';
piso_din_vld <= '1';
piso_din <= X"12345678";
piso_din_be <= "11111111";
wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= piso_din + X"12345678";
piso_din_be <= "11100111";
wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= piso_din + X"12345678";
piso_din_be <= "11111100";
wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= piso_din + X"12345678";
piso_din_be <= "00111111";
wait until rising_edge(CLK) and piso_din_rdy = '1';
piso_din <= (others => '-');
piso_din_vld <= '0';
wait until rising_edge(CLK) and sipo_dout_vld = '1';
wait until rising_edge(CLK);
wait until rising_edge(CLK) and sipo_dout_vld = '1';
sipo_enable <= '0';
wait for 33*CLK_PERIOD;
end loop;
wait;
end process;