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- removed old wave select

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1559 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-28 17:38:25 +00:00
parent d0677069e1
commit 0f7a8fb950
32 changed files with 4 additions and 39 deletions
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Common/sim/ieee_proposed.make
+2 -5
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@@ -1,6 +1,7 @@
# ------------------------------------------------- # -------------------------------------------------
# Compile script for GHDL # Compile script for GHDL
# ------------------------------------------------- # -------------------------------------------------
include ../make/defs.mk
# ------------------------------------------------- # -------------------------------------------------
# Global options # Global options
@@ -8,15 +9,11 @@
LANG_STD := 93c LANG_STD := 93c
IEEE_STD := standard IEEE_STD := standard
WORK_LIB := ieee_proposed WORK_LIB := ieee_proposed
TARGET := ieee_proposed
# ------------------------------------------------- # -------------------------------------------------
# Target options # Target options
# ------------------------------------------------- # -------------------------------------------------
TARGET := ieee_proposed
LIB_PATH := ieee_proposed/modelsim
SRCS := $(LIB_PATH)/standard_additions_c.vhdl SRCS := $(LIB_PATH)/standard_additions_c.vhdl
SRCS += $(LIB_PATH)/standard_textio_additions_c.vhdl SRCS += $(LIB_PATH)/standard_textio_additions_c.vhdl
SRCS += $(LIB_PATH)/env_c.vhdl SRCS += $(LIB_PATH)/env_c.vhdl
Common/sim/unisim.make
+2 -4
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@@ -1,6 +1,7 @@
# ------------------------------------------------- # -------------------------------------------------
# Compile script for GHDL # Compile script for GHDL
# ------------------------------------------------- # -------------------------------------------------
include ../make/defs.mk
# ------------------------------------------------- # -------------------------------------------------
# Global options # Global options
@@ -8,14 +9,11 @@
LANG_STD := 93c LANG_STD := 93c
IEEE_STD := standard IEEE_STD := standard
WORK_LIB := unisim WORK_LIB := unisim
TARGET := unisim
# ------------------------------------------------- # -------------------------------------------------
# Target options # Target options
# ------------------------------------------------- # -------------------------------------------------
TARGET := unisim
LIB_PATH := xilinx/libsrc
SRCS := $(LIB_PATH)/unisims/unisim_VPKG.vhd SRCS := $(LIB_PATH)/unisims/unisim_VPKG.vhd
SRCS += $(LIB_PATH)/unisims/unisim_VCOMP.vhd SRCS += $(LIB_PATH)/unisims/unisim_VCOMP.vhd
SRCS += $(LIB_PATH)/unisims/unisim_SMODEL.vhd SRCS += $(LIB_PATH)/unisims/unisim_SMODEL.vhd
lib/CPUs/MIPS/ghdl/tb_mips_top.make
-1
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@@ -33,7 +33,6 @@ SRCS += ../src/tb_mips_top.vhd
TARGET := tb_mips_top TARGET := tb_mips_top
ENTITY = tb_mips_top ENTITY = tb_mips_top
RUN_TIME := 1500us RUN_TIME := 1500us
WITH_VCD := y
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
lib/FIFO/ghdl/tb_fifo_async.make
-1
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@@ -10,7 +10,6 @@ SRCS += $(LIB_PATH)/FIFO/src/tb_fifo_async.vhd
# Compile # Compile
TARGET := tb_fifo_async TARGET := tb_fifo_async
ENTITY := tb_fifo_async ENTITY := tb_fifo_async
WITH_VCD := y
RUN_TIME := 5us RUN_TIME := 5us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
lib/FIFO/ghdl/tb_fifo_sync.make
-1
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@@ -10,7 +10,6 @@ SRCS += $(LIB_PATH)/FIFO/src/tb_fifo_sync.vhd
# Compile # Compile
TARGET := tb_fifo_sync TARGET := tb_fifo_sync
ENTITY := tb_fifo_sync ENTITY := tb_fifo_sync
WITH_VCD := y
RUN_TIME := 5us RUN_TIME := 5us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
lib/FIFO/ghdl/tb_gray_counter.make
-1
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@@ -7,7 +7,6 @@ SRCS += $(LIB_PATH)/FIFO/src/tb_gray_counter.vhd
# Compile # Compile
TARGET := tb_gray_counter TARGET := tb_gray_counter
ENTITY := tb_gray_counter ENTITY := tb_gray_counter
WITH_VCD := y
RUN_TIME := 1us RUN_TIME := 1us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
lib/JBUS/busmaster/ghdl/tb_busmaster_async.make
-1
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@@ -12,7 +12,6 @@ SRCS += $(MOD_PATH)/src/tb_busmaster_async.vhd
# Compile # Compile
TARGET := tb_busmaster_async TARGET := tb_busmaster_async
ENTITY := tb_busmaster_async ENTITY := tb_busmaster_async
WITH_VCD := y
RUN_TIME := 80us RUN_TIME := 80us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
lib/JBUS/busmaster/ghdl/tb_busmaster_sync.make
-1
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@@ -12,7 +12,6 @@ SRCS += $(MOD_PATH)/src/tb_busmaster_sync.vhd
# Compile # Compile
TARGET := tb_busmaster_sync TARGET := tb_busmaster_sync
ENTITY := tb_busmaster_sync ENTITY := tb_busmaster_sync
WITH_VCD := y
RUN_TIME := 40us RUN_TIME := 40us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
lib/JBUS/dmac/ghdl/tb_dmac_sync.make
-1
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@@ -13,7 +13,6 @@ SRCS += $(MOD_PATH)/dmac/src/tb_dmac.vhd
# Compile # Compile
TARGET := tb_dmac_sync TARGET := tb_dmac_sync
ENTITY := tb_dmac ENTITY := tb_dmac
WITH_VCD := y
RUN_TIME := 6us RUN_TIME := 6us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
lib/JBUS/memory/ghdl/tb_ram_wb.make
-1
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@@ -10,7 +10,6 @@ SRCS += $(MOD_PATH)/src/tb_ram_wb.vhd
# Compile # Compile
TARGET := tb_ram_wb TARGET := tb_ram_wb
ENTITY := tb_ram_wb ENTITY := tb_ram_wb
WITH_VCD := y
RUN_TIME := 1500ns RUN_TIME := 1500ns
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
lib/JBUS/memory/ghdl/tb_rom_wb.make
-1
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@@ -9,7 +9,6 @@ SRCS += $(MOD_PATH)/src/tb_rom_wb.vhd
# Compile # Compile
TARGET := tb_rom_wb TARGET := tb_rom_wb
ENTITY := tb_rom_wb ENTITY := tb_rom_wb
WITH_VCD := y
RUN_TIME := 1500ns RUN_TIME := 1500ns
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.make
-1
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@@ -26,7 +26,6 @@ SRCS += $(MOD_PATH)/src/tb_ctrl_ddr_wb32.vhd
# Compile # Compile
TARGET := tb_ctrl_ddr_wb32 TARGET := tb_ctrl_ddr_wb32
ENTITY := tb_ctrl_ddr_wb32 ENTITY := tb_ctrl_ddr_wb32
WITH_VCD := y
RUN_TIME := 200us RUN_TIME := 200us
GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit
lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.make
-1
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@@ -25,7 +25,6 @@ SRCS += $(MOD_PATH)/src/tb_ctrl_ddr_wb64.vhd
# Compile # Compile
TARGET := tb_ctrl_ddr_wb64 TARGET := tb_ctrl_ddr_wb64
ENTITY := tb_ctrl_ddr_wb64 ENTITY := tb_ctrl_ddr_wb64
WITH_VCD := y
RUN_TIME := 200us RUN_TIME := 200us
GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit GHDL_OPTS := -P$(VHDL_HOME)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit
lib/VGA_ctrl/ghdl/tb_vga_frontend_jb32.make
-1
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@@ -11,7 +11,6 @@ SRCS += ../src/tb_vga_frontend_jb32.vhd
# Compile # Compile
TARGET := tb_vga_frontend_jb32 TARGET := tb_vga_frontend_jb32
ENTITY := tb_vga_frontend_jb32 ENTITY := tb_vga_frontend_jb32
WITH_FST := y
RUN_TIME := 20ms RUN_TIME := 20ms
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
lib/VGA_ctrl/ghdl/tb_vga_frontend_jb64.make
-1
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@@ -11,7 +11,6 @@ SRCS += ../src/tb_vga_frontend_jb64.vhd
# Compile # Compile
TARGET := tb_vga_frontend_jb64 TARGET := tb_vga_frontend_jb64
ENTITY := tb_vga_frontend_jb64 ENTITY := tb_vga_frontend_jb64
WITH_FST := y
RUN_TIME := 2ms RUN_TIME := 2ms
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
lib/emac/ghdl/tb_emac_top_jb.make
-1
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@@ -8,7 +8,6 @@ SRCS += $(LIB_PATH)/emac/src/tb_emac_top_jb.vhd
# Compile # Compile
TARGET := tb_emac_top_jb TARGET := tb_emac_top_jb
ENTITY := tb_emac_top_jb ENTITY := tb_emac_top_jb
WITH_VCD := y
RUN_TIME := 2000us RUN_TIME := 2000us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
lib/filter/ghdl/tb_fir_iterative.make
-1
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@@ -12,7 +12,6 @@ SRCS += $(LIB_PATH)/filter/src/tb_fir_iterative.vhd
# Compile # Compile
TARGET := tb_fir_iterative TARGET := tb_fir_iterative
ENTITY := tb_fir_iterative ENTITY := tb_fir_iterative
WITH_VCD := y
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
RUN_TIME := 6us RUN_TIME := 6us
lib/filter/ghdl/tb_fir_parallel.make
-1
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@@ -12,7 +12,6 @@ SRCS += $(LIB_PATH)/filter/src/tb_fir_parallel.vhd
# Compile # Compile
TARGET := tb_fir_parallel TARGET := tb_fir_parallel
ENTITY := tb_fir_parallel ENTITY := tb_fir_parallel
WITH_VCD := y
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
RUN_TIME := 200us RUN_TIME := 200us
lib/filter/ghdl/tb_fir_semi_parallel.make
-1
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@@ -12,7 +12,6 @@ SRCS += $(LIB_PATH)/filter/src/tb_fir_semi_parallel.vhd
# Compile # Compile
TARGET := tb_fir_semi_parallel TARGET := tb_fir_semi_parallel
ENTITY := tb_fir_semi_parallel ENTITY := tb_fir_semi_parallel
WITH_VCD := y
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
RUN_TIME := 50us RUN_TIME := 50us
lib/filter/ghdl/tb_fir_stage.make
-1
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@@ -12,7 +12,6 @@ SRCS += $(LIB_PATH)/filter/src/tb_fir_stage.vhd
# Compile # Compile
TARGET := tb_fir_stage TARGET := tb_fir_stage
ENTITY := tb_fir_stage ENTITY := tb_fir_stage
WITH_VCD := y
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
RUN_TIME := 2us RUN_TIME := 2us
lib/filter/ghdl/tb_fir_stage_sys.make
-1
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@@ -12,7 +12,6 @@ SRCS += $(LIB_PATH)/filter/src/tb_fir_stage_sys.vhd
# Compile # Compile
TARGET := tb_fir_stage_sys TARGET := tb_fir_stage_sys
ENTITY := tb_fir_stage_sys ENTITY := tb_fir_stage_sys
WITH_VCD := y
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
RUN_TIME := 2us RUN_TIME := 2us
lib/ps2_port/ghdl/tb_ps2_core.make
-1
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@@ -8,7 +8,6 @@ SRCS += $(MOD_PATH)/src/tb_ps2_core.vhd
# Compile # Compile
TARGET := tb_ps2_core TARGET := tb_ps2_core
ENTITY := tb_ps2_core ENTITY := tb_ps2_core
WITH_VCD := y
RUN_TIME := 10ms RUN_TIME := 10ms
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
lib/radio/cordic/ghdl/tb_cordic_iterative_top.make
-1
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@@ -21,7 +21,6 @@ SRCS += $(LIB_PATH)/radio/cordic/src/tb_cordic_top.vhd
# Compile # Compile
TARGET := tb_cordic_iterative_top TARGET := tb_cordic_iterative_top
ENTITY := tb_cordic_top ENTITY := tb_cordic_top
WITH_VCD := y
RUN_TIME := 300us RUN_TIME := 300us
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
lib/radio/cordic/ghdl/tb_cordic_pipe_top.make
-1
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@@ -21,7 +21,6 @@ SRCS += $(LIB_PATH)/radio/cordic/src/tb_cordic_pipe_top.vhd
# Compile # Compile
TARGET := tb_cordic_pipe_top TARGET := tb_cordic_pipe_top
ENTITY := tb_cordic_pipe_top ENTITY := tb_cordic_pipe_top
WITH_VCD := y
RUN_TIME := 150us RUN_TIME := 150us
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
lib/radio/ddc/ghdl/tb_ddc.make
-1
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@@ -17,7 +17,6 @@ SRCS += $(LIB_PATH)/radio/ddc/src/tb_ddc.vhd
# Compile # Compile
TARGET := tb_ddc TARGET := tb_ddc
ENTITY := tb_ddc ENTITY := tb_ddc
WITH_VCD := y
RUN_TIME := 100us RUN_TIME := 100us
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
lib/radio/ddc/ghdl/tb_syn_ddc.make
-1
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@@ -21,7 +21,6 @@ SRCS += $(LIB_PATH)/radio/ddc/src/tb_syn_ddc.vhd
# Compile # Compile
TARGET := tb_syn_ddc TARGET := tb_syn_ddc
ENTITY := tb_syn_ddc ENTITY := tb_syn_ddc
WITH_VCD := y
RUN_TIME := 100us RUN_TIME := 100us
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
lib/radio/decimator/CIC/ghdl/tb_cic_decim_pipe.make
-1
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@@ -9,7 +9,6 @@ SRCS += $(LIB_PATH)/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd
# Compile # Compile
TARGET := tb_cic_decim_pipe TARGET := tb_cic_decim_pipe
ENTITY := tb_cic_decim_pipe ENTITY := tb_cic_decim_pipe
WITH_VCD := y
RUN_TIME := 75us RUN_TIME := 75us
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
lib/radio/nco/ghdl/tb_mix_cordic.make
-1
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@@ -21,7 +21,6 @@ SRCS += $(LIB_PATH)/radio/nco/src/tb_mix_cordic.vhd
# Compile # Compile
TARGET := tb_mix_cordic TARGET := tb_mix_cordic
ENTITY := tb_mix ENTITY := tb_mix
WITH_VCD := y
RUN_TIME := 200us RUN_TIME := 200us
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
lib/radio/nco/ghdl/tb_nco_cordic.make
-1
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@@ -21,7 +21,6 @@ SRCS += $(LIB_PATH)/radio/nco/src/tb_nco_cordic.vhd
# Compile # Compile
TARGET := tb_nco_cordic TARGET := tb_nco_cordic
ENTITY := tb_nco ENTITY := tb_nco
WITH_VCD := y
RUN_TIME := 250us RUN_TIME := 250us
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
lib/radio/nco/ghdl/tb_nco_lut.make
-1
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@@ -21,7 +21,6 @@ SRCS += $(LIB_PATH)/radio/nco/src/tb_nco_lut.vhd
# Compile # Compile
TARGET := tb_nco_lut TARGET := tb_nco_lut
ENTITY := tb_nco ENTITY := tb_nco
WITH_VCD := y
RUN_TIME := 250us RUN_TIME := 250us
GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed GHDL_OPTS := -P$(LIB_PATH)/fixed/ieee_proposed/build/fixed_pkg/ieee_proposed
projects/mips_sys/ghdl/tb_mips_sys.make
-1
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@@ -98,7 +98,6 @@ SRCS += ../src/tb_mips_sys.vhd
TARGET := tb_mips_sys TARGET := tb_mips_sys
ENTITY = tb_mips_sys ENTITY = tb_mips_sys
RUN_TIME := 10ms RUN_TIME := 10ms
WITH_FST := y
GHDL_OPTS := -P$(ROOT_PATH)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit GHDL_OPTS := -P$(ROOT_PATH)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit
projects/vga_ctrl/ghdl/tb_vga_ctrl.make
-1
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@@ -19,7 +19,6 @@ SRCS += ../src/tb_vga_ctrl.vhd
# Compile # Compile
TARGET := tb_vga_ctrl TARGET := tb_vga_ctrl
ENTITY := tb_vga_ctrl ENTITY := tb_vga_ctrl
WITH_VCD := y
RUN_TIME := 1us RUN_TIME := 1us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk