jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- Cleaned up

Browse Source 
git-svn-id: http://moon:8086/svn/vhdl/trunk@209 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-05 10:54:55 +00:00
parent c46a1caaf5
commit 0ed5461442
1 changed files with 27 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/filter/src/delay_line.vhd
+27 -37
View File
@@ -50,38 +50,6 @@ Port
);
end delay_line;
architecture reg_based of delay_line is
-------------------------------------------------------------------------------
subtype word_t is sfixed(shi(nbits, nbits_frac) downto slo(nbits, nbits_frac));
type delay_pipe_t is array (ntaps-1 downto 0) of word_t;
type delay_fix_pipe_t is array (delay_fix downto 0) of word_t;
-------------------------------------------------------------------------------
begin
--- assert delay_fix >= 1 report "fix delay must be greater than 1!" severity failure;
shift_register:
process(clk)
variable delay_pipe : delay_pipe_t;
begin
if rising_edge(clk) then
if ce = '1' then
dout <= delay_pipe(delay);
if shift_en = '1' then
delay_pipe := delay_pipe(delay_pipe'left-1 downto 0) & din;
end if;
end if;
end if;
end process;
----------------------------------------
-- Finished instantiation
----------------------------------------
end reg_based;
architecture ram_based of delay_line is
-------------------------------------------------------------------------------
@@ -136,9 +104,31 @@ counter:
dout_b => ram_r
);
----------------------------------------
-- Finished instantiation
----------------------------------------
end ram_based;
architecture reg_based of delay_line is
-------------------------------------------------------------------------------
subtype word_t is sfixed(shi(nbits, nbits_frac) downto slo(nbits, nbits_frac));
type delay_pipe_t is array (ntaps-1 downto 0) of word_t;
type delay_fix_pipe_t is array (delay_fix downto 0) of word_t;
-------------------------------------------------------------------------------
begin
shift_register:
process(clk)
variable delay_pipe : delay_pipe_t;
begin
if rising_edge(clk) then
if ce = '1' then
dout <= delay_pipe(delay);
if shift_en = '1' then
delay_pipe := delay_pipe(delay_pipe'left-1 downto 0) & din;
end if;
end if;
end if;
end process;
end reg_based;