diff --git a/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf b/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf
index b6a97d9..d40060c 100644
--- a/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf
+++ b/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf
@@ -20,15 +20,15 @@
 CONFIG STEPPING = "ES";
 
 # Bus clock nets
-NET "sys_clk_in" TNM_NET = "sys_clk";
+NET "CLK_O" TNM_NET = "sys_clk";
 TIMESPEC "TS_clk" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
 
 NET "sdram_clk0" TNM_NET = "sdram_clk";
-TIMESPEC "TS_sdram_clk" = PERIOD "sdram_clk" 9.9 ns HIGH 50 %;
+TIMESPEC "TS_sdram_clk" = PERIOD "sdram_clk" 7.5 ns HIGH 50 %;
 TIMESPEC "TS_unrelate_SDRAM" = FROM sys_clk TO sdram_clk TIG;
 
 NET "vga_clk" TNM_NET = "vga_clk";
-#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
+TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
 TIMESPEC "TS_unrelate_VGA" = FROM sys_clk TO vga_clk TIG;
 
 NET "sys_clk_in" LOC = "AE14";
@@ -38,16 +38,16 @@ NET sys_rst_n_in PULLUP;
 NET "sys_rst_n_in" TIG;
 NET "RST_O" TIG;
 
-NET "sys_clk_in" CLOCK_DEDICATED_ROUTE = FALSE;
-PIN "inst_clockgen/inst_DCM_BASE_0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
+#NET "sys_clk_in" CLOCK_DEDICATED_ROUTE = FALSE;
+#PIN "inst_clockgen/inst_DCM_BASE_0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
 
-NET "sys_sdr_clk_fb" CLOCK_DEDICATED_ROUTE = FALSE;
-PIN "inst_clockgen/inst_DCM_BASE_0.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE;
+#NET "sys_sdr_clk_fb" CLOCK_DEDICATED_ROUTE = FALSE;
+#PIN "inst_clockgen/inst_DCM_BASE_0.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE;
 
 # Locate DCM/BUFG - Tools can probably figure them out automatically
 #                   but just LOC them down to be safe
-#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
-#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
+#INST inst_clockgen/inst_DCM_BASE_0 LOC = DCM_ADV_X0Y4;
+#INST inst_clockgen/inst_DCM_BASE_1 LOC = DCM_ADV_X0Y3;
 
 INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
 # GOOD 1