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- working (SDRAM head)

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- use hello_sim for test bench
- changed sys clock gen

git-svn-id: http://moon:8086/svn/vhdl/trunk@1161 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-23 08:02:23 +00:00
parent 7668dd7814
commit 0d68ca00ac
7 changed files with 6794 additions and 400 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_sys/sim/hello_sim.elf.dis
+6583
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projects/mips_sys/sim/hello_sim.elf.flash.bin
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projects/mips_sys/sim/tb_mips_sys.fdo
+10 -5
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@@ -1,6 +1,10 @@
## NOTE: Do not edit this file. ## NOTE: Do not edit this file.
## ##
if {[file exists work]} {vdel -lib work -all}
vlib work vlib work
# Configs # Configs
vcom -explicit -93 "../src/sdram_config_sim.vhd" vcom -explicit -93 "../src/sdram_config_sim.vhd"
@@ -12,6 +16,9 @@ vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd" vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
# Clock Generator
vcom -explicit -93 "../src/sys_clock.vhd"
# RAMs # RAMs
vcom -explicit -93 "../../../lib/rams/dpram_1w1r2c_ro_sim.vhd" vcom -explicit -93 "../../../lib/rams/dpram_1w1r2c_ro_sim.vhd"
vcom -explicit -93 "../../../lib/rams/dpram_2w2r2c_ra_sim.vhd" vcom -explicit -93 "../../../lib/rams/dpram_2w2r2c_ra_sim.vhd"
@@ -37,7 +44,7 @@ vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd" vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd" vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd" vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
vcom -explicit -93 "../src/bootloader.ROM.vhd" vcom -explicit -93 "../src/bootloader_flash.ROM.vhd"
vcom -explicit -93 "../../../lib/misc/rom_wb.vhd" vcom -explicit -93 "../../../lib/misc/rom_wb.vhd"
# VGA # VGA
@@ -78,9 +85,10 @@ vcom -explicit -93 "../../../lib/SSRAM/src/CY7C1354B.vhd"
vcom -explicit -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd" vcom -explicit -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd"
# SDRAM # SDRAM
vcom -explicit -93 "../../../lib/misc/clockgen_virtex4.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
@@ -100,9 +108,6 @@ vcom -explicit -93 "../../../lib/emac/src/emac_rx.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_tx.vhd" vcom -explicit -93 "../../../lib/emac/src/emac_tx.vhd"
vcom -explicit -93 "../../../lib/emac/src/emac_top_jb.vhd" vcom -explicit -93 "../../../lib/emac/src/emac_top_jb.vhd"
# Clock Generator
vcom -explicit -93 "../src/clockgen_virtex4.vhd"
# Top and TB # Top and TB
vcom -explicit -93 "../src/mips_sys_sim.vhd" vcom -explicit -93 "../src/mips_sys_sim.vhd"
vcom -explicit -93 "../src/tb_mips_sys.vhd" vcom -explicit -93 "../src/tb_mips_sys.vhd"
projects/mips_sys/src/clockgen_virtex4.vhd
-363
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@@ -1,363 +0,0 @@
-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: Clock generator (Virtex-4 specific)
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library ieee, work;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE WORK.utils_pkg.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity clockgen is
generic
(
clk_in_freq : real := 100.0;
cpu_clk_out_freq : real := 100.0;
vga_clk_out_freq : real := 100.0;
sdr0_clk_out_phaseshift : integer := 0;
sdr1_clk_out_phaseshift : integer := 0
);
port
(
-- Clocks and Reset
rst_in : in std_logic; -- external async reset, low active
clk_in : in std_logic; -- system clock (e.g. 100MHz), from board
sys_clk_out : out std_logic;
cpu_clk_out : out std_logic;
vga_clk_out : out std_logic;
sdr0_clk_fb_in : in std_logic; -- feedback clock
sdr0_clk0_out : out std_logic; -- System clock #0, dcm#0 output 0°
sdr0_clk270_out : out std_logic; -- System clock #0, dcm#0 output 270°
sdr1_clk0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr1_clk270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
sys_rst_out : out std_logic -- DCM locked status
);
end;
architecture tech of clockgen is
signal dcm_rst : unsigned(2 downto 0);
signal vga_clk0 : std_logic;
signal vga_clkfx : std_logic;
signal vga_clk0_bufg : std_logic;
signal sys_clk0 : std_logic;
signal sys_clk0_bufg : std_logic;
signal cpu_clkfx : std_logic;
signal cpu_clkfx_bufg : std_logic;
signal sdr0_clk0 : std_logic;
signal sdr0_clk270 : std_logic;
signal sdr1_clk0 : std_logic;
signal sdr1_clk270 : std_logic;
signal sdr1_clk0_bufg : std_logic;
signal reset_cnt : unsigned(4 downto 0);
signal reset_pipe0 : unsigned(19 downto 0);
signal reset_pipe1 : unsigned(19 downto 0);
signal reset_pipe2 : unsigned(19 downto 0);
signal vga_fx_lock : std_logic;
signal sys_fx_lock : std_logic;
signal sdr0_lock : std_logic;
signal sdr1_lock : std_logic;
begin
-------------------------------------------------------------------------------------------------------
-- Clock generation
-------------------------------------------------------------------------------------------------------
-- Compnent instantiation
inst_DCM_VGA_FX : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, vga_clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, vga_clk_out_freq), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map
(
CLK0 => vga_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => vga_clkfx, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => vga_fx_lock, -- DCM LOCK status output
CLKFB => vga_clk0_bufg, -- DCM clock feedback
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => dcm_rst(0) -- DCM asynchronous reset input
);
BUFG_vga_clk0 : BUFG
port map
(
O => vga_clk0_bufg, -- Clock buffer output
I => vga_clk0 -- Clock buffer input
);
BUFG_vga_clkfx : BUFG
port map
(
O => vga_clk_out, -- Clock buffer output
I => vga_clkfx -- Clock buffer input
);
-- Compnent instantiation
inst_DCM_CPU_FX : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, cpu_clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, cpu_clk_out_freq), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map
(
CLK0 => sys_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => cpu_clkfx, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => sys_fx_lock, -- DCM LOCK status output
CLKFB => sys_clk0_bufg, -- DCM clock feedback
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => dcm_rst(0) -- DCM asynchronous reset input
);
BUFG_sys_clk0 : BUFG
port map
(
O => sys_clk0_bufg, -- Clock buffer output
I => sys_clk0 -- Clock buffer input
);
BUFG_sys_clkfx : BUFG
port map
(
O => cpu_clkfx_bufg, -- Clock buffer output
I => cpu_clkfx -- Clock buffer input
);
sys_clk_out <= sys_clk0_bufg;
cpu_clk_out <= cpu_clkfx_bufg;
inst_DCM_SDRCLK_0 : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => sdr0_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map
(
CLK0 => sdr0_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => sdr0_clk270, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => sdr0_lock, -- DCM LOCK status output
CLKFB => sdr0_clk_fb_in, -- DCM clock feedback
CLKIN => sys_clk0_bufg, -- Clock input (from IBUFG, BUFG or DCM)
RST => dcm_rst(1) -- DCM asynchronous reset input
);
bufg_sdr0_clk0: bufg
port map
(
o => sdr0_clk0_out,
i => sdr0_clk0
);
bufg_sdr0_clk270: bufg
port map (
o => sdr0_clk270_out,
i => sdr0_clk270
);
inst_DCM_SDRCLK_1 : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => sdr1_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map
(
CLK0 => sdr1_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => sdr1_clk270, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => sdr1_lock, -- DCM LOCK status output
CLKFB => sdr1_clk0_bufg, -- DCM clock feedback
CLKIN => sdr0_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => dcm_rst(2) -- DCM asynchronous reset input
);
sdr1_clk0_out <= sdr1_clk0_bufg;
bufg_sdr1_clk0: bufg
port map
(
o => sdr1_clk0_bufg,
i => sdr1_clk0
);
bufg_sdr1_clk270: bufg
port map (
o => sdr1_clk270_out,
i => sdr1_clk270
);
dcm_rst(0) <= reset_pipe0(reset_pipe0'left);
dcm_reset0:
process(rst_in, clk_in)
begin
if rst_in = '1' then
reset_pipe0 <= (others => '1');
elsif rising_edge(clk_in) then
reset_pipe0 <= reset_pipe0(reset_pipe0'left-1 downto 0) & '0';
end if;
end process;
dcm_rst(1) <= reset_pipe1(reset_pipe1'left);
dcm_reset1:
process(vga_fx_lock, clk_in)
begin
if vga_fx_lock = '0' then
reset_pipe1 <= (others => '1');
elsif rising_edge(clk_in) then
reset_pipe1 <= reset_pipe1(reset_pipe1'left-1 downto 0) & '0';
end if;
end process;
dcm_rst(2) <= reset_pipe2(reset_pipe2'left);
dcm_reset2:
process(sdr0_lock, clk_in)
begin
if sdr0_lock = '0' then
reset_pipe2 <= (others => '1');
elsif rising_edge(clk_in) then
reset_pipe2 <= reset_pipe2(reset_pipe2'left-1 downto 0) & '0';
end if;
end process;
reset_out_logic:
process(rst_in, clk_in, sdr0_lock, sdr1_lock, sys_fx_lock, vga_fx_lock)
begin
if rst_in = '1' or sdr0_lock = '0' or sdr1_lock = '0' or sys_fx_lock = '0' or vga_fx_lock = '0' then
sys_rst_out <= '1';
reset_cnt <= (reset_cnt'left downto reset_cnt'right => '1');
elsif rising_edge(clk_in) then
if reset_cnt /= (reset_cnt'left downto reset_cnt'right => '0') then
reset_cnt <= reset_cnt - 1;
else
sys_rst_out <= '0';
end if;
end if;
end process;
end architecture tech;
projects/mips_sys/src/mips_sys_sim.vhd
+13 -24
View File
@@ -44,7 +44,6 @@ GENERIC
( (
sys_freq_in : real := 100.0; sys_freq_in : real := 100.0;
cpu_freq : real := 100.0; cpu_freq : real := 100.0;
sdram_phaseshift : integer := 0;
tsvga : vga_timespec_t := ts_vga_800_600_72 tsvga : vga_timespec_t := ts_vga_800_600_72
); );
@@ -159,14 +158,12 @@ END mips_sys;
ARCHITECTURE behavior OF mips_sys IS ARCHITECTURE behavior OF mips_sys IS
signal cpu_clk : std_logic;
signal nmi : std_logic; signal nmi : std_logic;
signal eb : std_logic; signal eb : std_logic;
signal sdram_clk0 : std_logic; signal vga_clk : std_logic;
signal sdram_clk270 : std_logic; signal vga_rst : std_logic;
signal sdram_clk270var : std_logic;
signal vga_clk : std_logic; signal vga_ce : std_logic;
signal vga_ce : std_logic;
signal rst_in : std_logic; signal rst_in : std_logic;
signal int_timer : std_logic; signal int_timer : std_logic;
signal int_uart0 : std_logic; signal int_uart0 : std_logic;
@@ -373,7 +370,7 @@ BEGIN
SEL_I_sdram <= "0000" & SEL_O; SEL_I_sdram <= "0000" & SEL_O;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn; sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
vga_ce <= not RST_O; vga_ce <= not vga_rst;
sys_flash_ssram_out: sys_flash_ssram_out:
process(CLK_O) process(CLK_O)
@@ -574,7 +571,7 @@ inst_mips_top: entity work.mips_top
debug => debug, debug => debug,
eb => eb, eb => eb,
nmi => nmi, nmi => nmi,
cpu_clk => cpu_clk, cpu_clk => CLK_O,
RST_I => RST_O, RST_I => RST_O,
CLK_I => CLK_O, CLK_I => CLK_O,
ACK_I => ACK_I_cpu, ACK_I => ACK_I_cpu,
@@ -813,29 +810,22 @@ inst_ssram_port_wb : entity work.ssram_port_wb
ssram_bw_n => sys_ssram_bw_n ssram_bw_n => sys_ssram_bw_n
); );
inst_clockgen : entity work.clockgen inst_sys_clock : entity work.sys_clock
GENERIC MAP GENERIC MAP
( (
clk_in_freq => sys_freq_in, clk_in_freq => sys_freq_in,
cpu_clk_out_freq => cpu_freq, cpu_clk_out_freq => cpu_freq,
vga_clk_out_freq => vga_freq, vga_clk_out_freq => vga_freq
sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0
) )
PORT MAP PORT MAP
( (
-- Clocks and Reset -- Clocks and Reset
rst_in => rst_in, -- external async reset, low active rst_in => rst_in, -- external async reset, low active
clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board
sys_rst_out => RST_O, cpu_clk_out => CLK_O,
sys_clk_out => CLK_O, cpu_rst_out => RST_O,
vga_clk_out => vga_clk, vga_clk_out => vga_clk,
cpu_clk_out => cpu_clk, vga_rst_out => vga_rst
sdr0_clk_fb_in => sys_sdr_clk_fb, -- feedback clock
sdr0_clk0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
sdr0_clk270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
sdr1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr1_clk270_out => sdram_clk270var -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
); );
@@ -852,9 +842,8 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
RST_I => RST_O, RST_I => RST_O,
CLK_I => CLK_O, CLK_I => CLK_O,
SDRAM_CLK0_I => sdram_clk0, SDRAM_CLK_I => sys_clk_in,
SDRAM_CLK270_I => sdram_clk270, SDRAM_CLK_FB_I => sys_sdr_clk_fb,
SDRAM_CLK270VAR_I => sdram_clk270var,
CYC_I => CYC_I_sdram, CYC_I => CYC_I_sdram,
STB_I => STB_O, STB_I => STB_O,
projects/mips_sys/src/sys_clock.vhd
+183
View File
@@ -0,0 +1,183 @@
-------------------------------------------------------------------------
-- Project: SDRAM controller
-- This file: Clock generator (Virtex-4 specific)
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------
library ieee, work;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE WORK.utils_pkg.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity sys_clock is
generic
(
clk_in_freq : real := 100.0;
cpu_clk_out_freq : real := 100.0;
vga_clk_out_freq : real := 100.0
);
port
(
-- Clocks and Reset
rst_in : in std_logic; -- external async reset, low active
clk_in : in std_logic; -- system clock (e.g. 100MHz), from board
cpu_clk_out : out std_logic;
cpu_rst_out : out std_logic;
vga_clk_out : out std_logic;
vga_rst_out : out std_logic
);
end;
architecture tech of sys_clock is
signal vga_clk0 : std_logic;
signal vga_clkfx : std_logic;
signal vga_clk0_bufg : std_logic;
signal cpu_clk0 : std_logic;
signal cpu_clk0_bufg : std_logic;
signal cpu_clkfx : std_logic;
signal vga_fx_lock : std_logic;
signal cpu_fx_lock : std_logic;
begin
-------------------------------------------------------------------------------------------------------
-- Clock generation
-------------------------------------------------------------------------------------------------------
-- Compnent instantiation
inst_DCM_VGA_FX : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, vga_clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, vga_clk_out_freq), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map
(
CLK0 => vga_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => vga_clkfx, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => vga_fx_lock, -- DCM LOCK status output
CLKFB => vga_clk0_bufg, -- DCM clock feedback
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => rst_in -- DCM asynchronous reset input
);
BUFG_vga_clk0 : BUFG
port map
(
O => vga_clk0_bufg, -- Clock buffer output
I => vga_clk0 -- Clock buffer input
);
-- Compnent instantiation
inst_DCM_CPU_FX : DCM_BASE
generic map
(
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, cpu_clk_out_freq), -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, cpu_clk_out_freq), -- Can be any integer from 2 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map
(
CLK0 => cpu_clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => cpu_clkfx, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => cpu_fx_lock, -- DCM LOCK status output
CLKFB => cpu_clk0_bufg, -- DCM clock feedback
CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
RST => rst_in -- DCM asynchronous reset input
);
BUFG_cpu_clk0 : BUFG
port map
(
O => cpu_clk0_bufg, -- Clock buffer output
I => cpu_clk0 -- Clock buffer input
);
vga_clk_out <= vga_clkfx;
cpu_clk_out <= cpu_clkfx;
cpu_rst_out_reg:
process(cpu_clkfx)
begin
if rising_edge(cpu_clkfx) then
cpu_rst_out <= not cpu_fx_lock;
end if;
end process;
vga_rst_out_reg:
process(vga_clkfx)
begin
if rising_edge(vga_clkfx) then
vga_rst_out <= not vga_fx_lock;
end if;
end process;
end architecture tech;
projects/mips_sys/src/tb_mips_sys.vhd
+5 -8
View File
@@ -42,8 +42,6 @@ ARCHITECTURE behavior OF tb_mips_sys IS
constant AC97_CLK_PERIOD : time := 83 ns; constant AC97_CLK_PERIOD : time := 83 ns;
constant ETH_CLK_PERIOD : time := 7.7 ns; constant ETH_CLK_PERIOD : time := 7.7 ns;
constant LOOP_BACK_EN : std_logic := '1'; constant LOOP_BACK_EN : std_logic := '1';
constant WITH_TLB : boolean := true;
constant KSEG_01_TRANSLATED : boolean := true;
signal sys_rst_n_in : std_logic := '0'; signal sys_rst_n_in : std_logic := '0';
signal sys_clk_in : std_logic := '1'; signal sys_clk_in : std_logic := '1';
signal dip : unsigned(7 downto 0) := (others => '0'); signal dip : unsigned(7 downto 0) := (others => '0');
@@ -149,7 +147,6 @@ uut: entity work.mips_sys
( (
sys_freq_in => 100.000, sys_freq_in => 100.000,
cpu_freq => 100.000, cpu_freq => 100.000,
sdram_phaseshift => 0,
tsvga => ts_vga_800_600_72 tsvga => ts_vga_800_600_72
) )
PORT MAP PORT MAP
@@ -271,8 +268,8 @@ inst_ssram : entity work.cy7c1354
-- MICRON DDR SDRAM Simulation Model -- MICRON DDR SDRAM Simulation Model
i_mt46v16m16_0 : entity work.mt46v16m16 i_mt46v16m16_0 : entity work.mt46v16m16
port map ( port map (
dq => std_logic_vector(sys_sdr_data(15 downto 0)), unsigned(dq) => std_logic_vector(sys_sdr_data(15 downto 0)),
dqs => std_logic_vector(sys_sdr_dqs_q(1 downto 0)), unsigned(dqs) => std_logic_vector(sys_sdr_dqs_q(1 downto 0)),
addr => std_logic_vector(sys_sdr_a_q), addr => std_logic_vector(sys_sdr_a_q),
ba => std_logic_vector(sys_sdr_ba_q), ba => std_logic_vector(sys_sdr_ba_q),
clk => sys_sdr_clk_p, clk => sys_sdr_clk_p,
@@ -288,8 +285,8 @@ i_mt46v16m16_0 : entity work.mt46v16m16
-- MICRON DDR SDRAM Simulation Model -- MICRON DDR SDRAM Simulation Model
i_mt46v16m16_1 : entity work.mt46v16m16 i_mt46v16m16_1 : entity work.mt46v16m16
port map ( port map (
dq => std_logic_vector(sys_sdr_data(31 downto 16)), unsigned(dq) => std_logic_vector(sys_sdr_data(31 downto 16)),
dqs => std_logic_vector(sys_sdr_dqs_q(3 downto 2)), unsigned(dqs) => std_logic_vector(sys_sdr_dqs_q(3 downto 2)),
addr => std_logic_vector(sys_sdr_a_q), addr => std_logic_vector(sys_sdr_a_q),
ba => std_logic_vector(sys_sdr_ba_q), ba => std_logic_vector(sys_sdr_ba_q),
clk => sys_sdr_clk_p, clk => sys_sdr_clk_p,
@@ -367,7 +364,7 @@ ac97_clk_gen : PROCESS
FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a) FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a)
type file_t is file of integer; type file_t is file of integer;
file load_flash : file_t open read_mode is "dhry.elf.flash.bin"; file load_flash : file_t open read_mode is "hello_sim.elf.flash.bin";
variable instr : integer; variable instr : integer;
variable index : natural; variable index : natural;
variable temp : signed(31 downto 0); variable temp : signed(31 downto 0);