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- working (SDRAM head)

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- use hello_sim for test bench
- changed sys clock gen

git-svn-id: http://moon:8086/svn/vhdl/trunk@1161 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-23 08:02:23 +00:00
parent 7668dd7814
commit 0d68ca00ac
7 changed files with 6794 additions and 400 deletions
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projects/mips_sys/src/tb_mips_sys.vhd
+5 -8
View File
@@ -42,8 +42,6 @@ ARCHITECTURE behavior OF tb_mips_sys IS
constant AC97_CLK_PERIOD : time := 83 ns;
constant ETH_CLK_PERIOD : time := 7.7 ns;
constant LOOP_BACK_EN : std_logic := '1';
constant WITH_TLB : boolean := true;
constant KSEG_01_TRANSLATED : boolean := true;
signal sys_rst_n_in : std_logic := '0';
signal sys_clk_in : std_logic := '1';
signal dip : unsigned(7 downto 0) := (others => '0');
@@ -149,7 +147,6 @@ uut: entity work.mips_sys
(
sys_freq_in => 100.000,
cpu_freq => 100.000,
sdram_phaseshift => 0,
tsvga => ts_vga_800_600_72
)
PORT MAP
@@ -271,8 +268,8 @@ inst_ssram : entity work.cy7c1354
-- MICRON DDR SDRAM Simulation Model
i_mt46v16m16_0 : entity work.mt46v16m16
port map (
dq => std_logic_vector(sys_sdr_data(15 downto 0)),
dqs => std_logic_vector(sys_sdr_dqs_q(1 downto 0)),
unsigned(dq) => std_logic_vector(sys_sdr_data(15 downto 0)),
unsigned(dqs) => std_logic_vector(sys_sdr_dqs_q(1 downto 0)),
addr => std_logic_vector(sys_sdr_a_q),
ba => std_logic_vector(sys_sdr_ba_q),
clk => sys_sdr_clk_p,
@@ -288,8 +285,8 @@ i_mt46v16m16_0 : entity work.mt46v16m16
-- MICRON DDR SDRAM Simulation Model
i_mt46v16m16_1 : entity work.mt46v16m16
port map (
dq => std_logic_vector(sys_sdr_data(31 downto 16)),
dqs => std_logic_vector(sys_sdr_dqs_q(3 downto 2)),
unsigned(dq) => std_logic_vector(sys_sdr_data(31 downto 16)),
unsigned(dqs) => std_logic_vector(sys_sdr_dqs_q(3 downto 2)),
addr => std_logic_vector(sys_sdr_a_q),
ba => std_logic_vector(sys_sdr_ba_q),
clk => sys_sdr_clk_p,
@@ -367,7 +364,7 @@ ac97_clk_gen : PROCESS
FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a)
type file_t is file of integer;
file load_flash : file_t open read_mode is "dhry.elf.flash.bin";
file load_flash : file_t open read_mode is "hello_sim.elf.flash.bin";
variable instr : integer;
variable index : natural;
variable temp : signed(31 downto 0);