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- working (SDRAM head)

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- use hello_sim for test bench
- changed sys clock gen

git-svn-id: http://moon:8086/svn/vhdl/trunk@1161 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-23 08:02:23 +00:00
parent 7668dd7814
commit 0d68ca00ac
7 changed files with 6794 additions and 400 deletions
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projects/mips_sys/src/mips_sys_sim.vhd
+13 -24
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@@ -44,7 +44,6 @@ GENERIC
(
sys_freq_in : real := 100.0;
cpu_freq : real := 100.0;
sdram_phaseshift : integer := 0;
tsvga : vga_timespec_t := ts_vga_800_600_72
);
@@ -159,14 +158,12 @@ END mips_sys;
ARCHITECTURE behavior OF mips_sys IS
signal cpu_clk : std_logic;
signal nmi : std_logic;
signal eb : std_logic;
signal sdram_clk0 : std_logic;
signal sdram_clk270 : std_logic;
signal sdram_clk270var : std_logic;
signal vga_clk : std_logic;
signal vga_ce : std_logic;
signal vga_clk : std_logic;
signal vga_rst : std_logic;
signal vga_ce : std_logic;
signal rst_in : std_logic;
signal int_timer : std_logic;
signal int_uart0 : std_logic;
@@ -373,7 +370,7 @@ BEGIN
SEL_I_sdram <= "0000" & SEL_O;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
vga_ce <= not RST_O;
vga_ce <= not vga_rst;
sys_flash_ssram_out:
process(CLK_O)
@@ -574,7 +571,7 @@ inst_mips_top: entity work.mips_top
debug => debug,
eb => eb,
nmi => nmi,
cpu_clk => cpu_clk,
cpu_clk => CLK_O,
RST_I => RST_O,
CLK_I => CLK_O,
ACK_I => ACK_I_cpu,
@@ -813,29 +810,22 @@ inst_ssram_port_wb : entity work.ssram_port_wb
ssram_bw_n => sys_ssram_bw_n
);
inst_clockgen : entity work.clockgen
inst_sys_clock : entity work.sys_clock
GENERIC MAP
(
clk_in_freq => sys_freq_in,
cpu_clk_out_freq => cpu_freq,
vga_clk_out_freq => vga_freq,
sdr0_clk_out_phaseshift => 0,
sdr1_clk_out_phaseshift => 0
vga_clk_out_freq => vga_freq
)
PORT MAP
(
-- Clocks and Reset
rst_in => rst_in, -- external async reset, low active
clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board
sys_rst_out => RST_O,
sys_clk_out => CLK_O,
cpu_clk_out => CLK_O,
cpu_rst_out => RST_O,
vga_clk_out => vga_clk,
cpu_clk_out => cpu_clk,
sdr0_clk_fb_in => sys_sdr_clk_fb, -- feedback clock
sdr0_clk0_out => sdram_clk0, -- System clock #0, dcm#0 output 0°
sdr0_clk270_out => sdram_clk270, -- System clock #0, dcm#0 output 270°
sdr1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sdr1_clk270_out => sdram_clk270var -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
vga_rst_out => vga_rst
);
@@ -852,9 +842,8 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
RST_I => RST_O,
CLK_I => CLK_O,
SDRAM_CLK0_I => sdram_clk0,
SDRAM_CLK270_I => sdram_clk270,
SDRAM_CLK270VAR_I => sdram_clk270var,
SDRAM_CLK_I => sys_clk_in,
SDRAM_CLK_FB_I => sys_sdr_clk_fb,
CYC_I => CYC_I_sdram,
STB_I => STB_O,