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git-svn-id: http://moon:8086/svn/vhdl/trunk@938 cc03376c-175c-47c8-b038-4cd826a8556b

lib/FIFO/sim/tb_fifo_async.fdo

@@ -0,0 +1,16 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../src/gray_counter.vhd"
+vcom -explicit  -93 "../src/dpram_1w1r.vhd"
+vcom -explicit  -93 "../src/fifo_async_ctrl.vhd"
+vcom -explicit  -93 "../src/fifo_async.vhd"
+vcom -explicit  -93 "../src/tb_fifo_async.vhd"
+vsim -t 1ps   -lib work tb_fifo_async
+view wave
+do {tb_fifo_async.wdo}
+view structure
+view signals
+
+run 5us

lib/FIFO/sim/tb_fifo_async.wdo

@@ -0,0 +1,39 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_fifo_async/rst
+add wave -noupdate -format Logic /tb_fifo_async/clk_w
+add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_async/din
+add wave -noupdate -format Logic /tb_fifo_async/fifo_full
+add wave -noupdate -format Logic /tb_fifo_async/we
+add wave -noupdate -format Logic /tb_fifo_async/write_en
+add wave -noupdate -format Logic /tb_fifo_async/clk_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_async/dout
+add wave -noupdate -format Logic /tb_fifo_async/fifo_empty
+add wave -noupdate -format Logic /tb_fifo_async/re
+add wave -noupdate -format Logic /tb_fifo_async/read_en
+add wave -noupdate -format Logic /tb_fifo_async/fifo_almost_full
+add wave -noupdate -format Logic /tb_fifo_async/fifo_almost_empty
+add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_async/ref_r
+add wave -noupdate -format Logic /tb_fifo_async/uut/inst_fifo_async_ctrl/empty
+add wave -noupdate -format Logic /tb_fifo_async/uut/inst_fifo_async_ctrl/full
+add wave -noupdate -format Logic /tb_fifo_async/uut/pre_full
+add wave -noupdate -format Logic /tb_fifo_async/uut/pre_empty
+add wave -noupdate -format Literal /tb_fifo_async/uut/ptr_w
+add wave -noupdate -format Literal /tb_fifo_async/uut/ptr_r
+add wave -noupdate -format Logic /tb_fifo_async/uut/inst_fifo_async_ctrl/rinc
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {155864 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {112771 ps} {210880 ps}

lib/FIFO/sim/tb_fifo_sync.fdo

@@ -0,0 +1,15 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../src/dpram_1w1r.vhd"
+vcom -explicit  -93 "../src/fifo_sync_ctrl.vhd"
+vcom -explicit  -93 "../src/fifo_sync.vhd"
+vcom -explicit  -93 "../src/tb_fifo_sync.vhd"
+vsim -t 1ps   -lib work tb_fifo_sync
+view wave
+do {tb_fifo_sync.wdo}
+view structure
+view signals
+
+run 5us

lib/FIFO/sim/tb_fifo_sync.wdo

@@ -0,0 +1,31 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_fifo_sync/rst
+add wave -noupdate -format Logic /tb_fifo_sync/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_sync/din
+add wave -noupdate -format Logic /tb_fifo_sync/fifo_full
+add wave -noupdate -format Logic /tb_fifo_sync/fifo_almost_full
+add wave -noupdate -format Logic /tb_fifo_sync/we
+add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_sync/dout
+add wave -noupdate -format Logic /tb_fifo_sync/fifo_empty
+add wave -noupdate -format Logic /tb_fifo_sync/fifo_almost_empty
+add wave -noupdate -format Logic /tb_fifo_sync/re
+add wave -noupdate -format Logic /tb_fifo_sync/write_en
+add wave -noupdate -format Logic /tb_fifo_sync/read_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_sync/ref_r
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1360023 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {4760828 ps} {5012588 ps}

lib/misc/dpram_1w1r1c_sim.vhd

@@ -0,0 +1,77 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r1c_sim.vhd,v 1.1 2013-02-07 14:15:37 jens Exp $
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram_1w1r1c is
+	Generic
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clk			: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_1w1r1c;
+
+architecture Behavioral of dpram_1w1r1c is
+
+	signal addr_b_r : unsigned (addr_width-1 downto 0);
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	
+begin
+
+process (clk)
+begin
+if clk'event and clk = '1' then
+	if en_a = '1' then
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) <= din_a;
+		end if;	
+	end if;	
+	if en_b = '1' then
+		addr_b_r	<= addr_b;
+	end if;
+end if;
+end process;
+
+dout_b <= RAM(to_integer(addr_b_r));
+
+
+end Behavioral;
+

lib/misc/dpram_1w1r1c_xil.vhd

@@ -0,0 +1,77 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r1c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram_1w1r1c is
+	Generic
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clk			: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_1w1r1c;
+
+architecture Behavioral of dpram_1w1r1c is
+
+	signal addr_b_r : unsigned (addr_width-1 downto 0);
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	
+begin
+
+process (clk)
+begin
+if clk'event and clk = '1' then
+	if en_a = '1' then
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) <= din_a;
+		end if;	
+	end if;	
+	if en_b = '1' then
+		addr_b_r	<= addr_b;
+	end if;
+end if;
+end process;
+
+dout_b <= RAM(to_integer(addr_b_r));
+
+
+end Behavioral;
+

lib/misc/dpram_1w1r2c_sim.vhd

@@ -0,0 +1,82 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r2c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram_1w1r2c is
+	Generic (
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port (
+		clk_a		: in  STD_LOGIC;
+		clk_b		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_1w1r2c;
+
+architecture Behavioral of dpram_1w1r2c is
+
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	signal addr_b_r : unsigned (addr_width-1 downto 0);
+	
+begin
+
+	dout_b <= RAM(to_integer(addr_b_r));
+
+process (clk_a)
+begin
+if clk_a'event and clk_a = '1' then
+	if en_a = '1' then
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) <= din_a;
+		end if;
+	end if;
+end if;
+end process;
+
+process (clk_b)
+begin
+if clk_b'event and clk_b = '1' then
+	if en_b = '1' then
+		addr_b_r	<= addr_b;
+	end if;
+end if;
+end process;
+
+
+end Behavioral;
+

lib/misc/dpram_1w1r2c_xil.vhd

@@ -0,0 +1,82 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r2c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram_1w1r2c is
+	Generic (
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port (
+		clk_a		: in  STD_LOGIC;
+		clk_b		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_1w1r2c;
+
+architecture Behavioral of dpram_1w1r2c is
+
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	signal addr_b_r : unsigned (addr_width-1 downto 0);
+	
+begin
+
+	dout_b <= RAM(to_integer(addr_b_r));
+
+process (clk_a)
+begin
+if clk_a'event and clk_a = '1' then
+	if en_a = '1' then
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) <= din_a;
+		end if;
+	end if;
+end if;
+end process;
+
+process (clk_b)
+begin
+if clk_b'event and clk_b = '1' then
+	if en_b = '1' then
+		addr_b_r	<= addr_b;
+	end if;
+end if;
+end process;
+
+
+end Behavioral;
+

lib/misc/dpram_1w2r1c_sim.vhd

@@ -0,0 +1,86 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w2r1c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity dpram_1w2r1c is
+	Generic 
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clk			: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_1w2r1c;
+
+architecture Behavioral of dpram_1w2r1c is
+
+	constant depth : integer := 2**addr_width;
+	signal addr_a_r : unsigned (addr_width-1 downto 0);
+	signal addr_b_r : unsigned (addr_width-1 downto 0);
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	
+begin
+
+	dout_a <= RAM(to_integer(addr_a_r));
+	dout_b <= RAM(to_integer(addr_b_r));
+
+process (clk)
+begin
+if clk'event and clk = '1' then
+	if en_a = '1' then
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) <= din_a;
+		end if;
+		addr_a_r	<= addr_a;
+	end if;
+end if;
+end process;
+
+process (clk)
+begin
+if clk'event and clk = '1' then
+	if en_b = '1' then
+		addr_b_r	<= addr_b;
+	end if;
+end if;
+end process;
+
+end Behavioral;
+

lib/misc/dpram_1w2r1c_xil.vhd

@@ -0,0 +1,80 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w2r1c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity dpram_1w2r1c is
+	Generic 
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clk			: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_1w2r1c;
+
+architecture Behavioral of dpram_1w2r1c is
+
+
+begin
+
+inst_dpram: entity work.dpram_2w2r2c
+	GENERIC MAP 
+	(
+		addr_width	=> addr_width,
+		data_width	=> data_width
+	)
+	PORT MAP
+	(
+		clk_a	=> clk,
+		clk_b	=> clk,
+		en_a	=> en_a,
+		en_b	=> en_b,
+		we_a	=> we_a,
+		we_b	=> '0',
+		addr_a	=> addr_a,
+		addr_b	=> addr_b,
+		din_a	=> din_a,
+		din_b	=> din_a,
+		dout_a	=> dout_a,
+		dout_b	=> dout_b
+	);
+
+
+end Behavioral;
+

lib/misc/dpram_2w2r1c_sim.vhd

@@ -0,0 +1,88 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r1c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity dpram_2w2r1c is
+	Generic 
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clk			: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_2w2r1c;
+
+architecture Behavioral of dpram_2w2r1c is
+
+	constant depth : integer := 2**addr_width;
+	signal addr_a_r : unsigned (addr_width-1 downto 0);
+	signal addr_b_r : unsigned (addr_width-1 downto 0);
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	signal contention : std_logic;	
+begin
+
+	dout_a <= RAM(to_integer(addr_a_r));
+	dout_b <= RAM(to_integer(addr_b_r));
+
+	contention	<= en_a and we_a and en_b and we_b;
+	
+process (clk)
+begin
+if clk'event and clk = '1' then
+	assert contention = '0' report "dpram_2w2r1c: Simultaneous write on Port A and Port B!" severity warning;
+	if en_a = '1' then
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) <= din_a;
+		end if;
+		addr_a_r	<= addr_a;
+	end if;
+	if en_b = '1' then
+		if we_b = '1' then
+			RAM(to_integer(addr_b)) <= din_b;
+		end if;
+		addr_b_r	<= addr_b;
+	end if;
+end if;
+end process;
+
+end Behavioral;
+

lib/misc/dpram_2w2r1c_xil.vhd

@@ -0,0 +1,82 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r1c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity dpram_2w2r1c is
+	Generic 
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clk			: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_2w2r1c;
+
+architecture Behavioral of dpram_2w2r1c is
+
+
+begin
+
+inst_dpram: entity work.dpram_2w2r2c
+	GENERIC MAP 
+	(
+		addr_width	=> addr_width,
+		data_width	=> data_width
+	)
+	PORT MAP
+	(
+		clk_a	=> clk,
+		clk_b	=> clk,
+		en_a	=> en_a,
+		en_b	=> en_b,
+		we_a	=> we_a,
+		we_b	=> we_b,
+		addr_a	=> addr_a,
+		addr_b	=> addr_b,
+		din_a	=> din_a,
+		din_b	=> din_a,
+		dout_a	=> dout_a,
+		dout_b	=> dout_b
+	);
+
+
+end Behavioral;
+

lib/misc/dpram_2w2r2c_sim.vhd

@@ -0,0 +1,95 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r2c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity dpram_2w2r2c is
+	Generic 
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clk_a		: in  STD_LOGIC;
+		clk_b		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_2w2r2c;
+
+architecture Behavioral of dpram_2w2r2c is
+
+	constant depth : integer := 2**addr_width;
+	signal addr_a_r : unsigned (addr_width-1 downto 0);
+	signal addr_b_r : unsigned (addr_width-1 downto 0);
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	
+begin
+
+	dout_a <= RAM(to_integer(addr_a_r));
+	dout_b <= RAM(to_integer(addr_b_r));
+
+process (clk_a, clk_b)
+begin
+	if clk_a'event and clk_a = '1' and en_a = '1' and we_a = '1' then
+		RAM(to_integer(addr_a)) <= din_a;
+	elsif clk_b'event and clk_b = '1' and en_b = '1' and we_b = '1' then
+		RAM(to_integer(addr_b)) <= din_b;
+	end if;
+end process;
+
+process (clk_a)
+begin
+	if clk_a'event and clk_a = '1' then
+		if en_a = '1' then
+			addr_a_r	<= addr_a;
+		end if;
+	end if;
+end process;
+
+process (clk_b)
+begin
+	if clk_b'event and clk_b = '1' then
+		if en_b = '1' then
+			addr_b_r	<= addr_b;
+		end if;
+	end if;
+end process;
+
+end Behavioral;
+

lib/misc/dpram_2w2r2c_xil.vhd

@@ -0,0 +1,93 @@
+-------------------------------------------------------------------------
+-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
+-- This file: Dual-ported register file with asynchrous read
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r2c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
+-----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+entity dpram_2w2r2c is
+	Generic 
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port
+	(
+		clk_a		: in  STD_LOGIC;
+		clk_b		: in  STD_LOGIC;
+		en_a		: in  STD_LOGIC;
+		en_b		: in  STD_LOGIC;
+		we_a		: in  STD_LOGIC;
+		we_b		: in  STD_LOGIC;
+		addr_a		: in  unsigned (addr_width-1 downto 0);
+		addr_b		: in  unsigned (addr_width-1 downto 0);
+		din_a		: in  unsigned (data_width-1 downto 0);
+		din_b		: in  unsigned (data_width-1 downto 0);
+		dout_a		: out unsigned (data_width-1 downto 0);
+		dout_b		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_2w2r2c;
+
+architecture Behavioral of dpram_2w2r2c is
+
+	constant depth : integer := 2**addr_width;
+	signal addr_a_r : unsigned (addr_width-1 downto 0);
+	signal addr_b_r : unsigned (addr_width-1 downto 0);
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	shared variable RAM : RAMtype;
+	
+begin
+
+	dout_a <= RAM(to_integer(addr_a_r));
+	dout_b <= RAM(to_integer(addr_b_r));
+
+process (clk_a)
+begin
+if clk_a'event and clk_a = '1' then
+	if en_a = '1' then
+		if we_a = '1' then
+			RAM(to_integer(addr_a)) := din_a;
+		end if;
+		addr_a_r	<= addr_a;
+	end if;
+end if;
+end process;
+
+
+process (clk_b)
+begin
+if clk_b'event and clk_b = '1' then
+	if en_b = '1' then
+		if we_b = '1' then
+			RAM(to_integer(addr_b)) := din_b;
+		end if;
+		addr_b_r	<= addr_b;
+	end if;
+end if;
+end process;
+
+end Behavioral;
+

lib/misc/wire_delay.vhd

@@ -0,0 +1,42 @@
+library IEEE;  
+  use IEEE.Std_Logic_1164.all;
+
+entity wire_delay is
+  generic(a_to_b_loss : time := 1 ns;
+          b_to_a_loss : time := 2 ns);
+  port
+    (A : inout Std_Logic;
+     B : inout Std_Logic
+     );
+end wire_delay;
+
+architecture behave of wire_delay is
+begin
+
+  ABC0_Lbl: process
+    variable ThenTime_v : time := 0 ns;
+
+    function max(t1,t2 : time) return time is
+    begin
+        if (t1 > t2) then
+          return t1;
+        else
+          return t2;
+        end if;
+    end;
+
+  begin
+    wait on A'transaction, B'transaction
+                      until ThenTime_v + max(a_to_b_loss, b_to_a_loss) < now;
+    -- Break
+    ThenTime_v := now;
+    A <= 'Z';
+    B <= 'Z';
+    wait for 0 ns;
+
+    -- Make
+    A <= transport B after b_to_a_loss;
+    B <= transport A after a_to_b_loss;
+
+  end process ABC0_Lbl;
+end behave;